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更新初版工程
2024-01-14 19:28:00 +08:00
/***********************************************
<EFBFBD><EFBFBD>˾<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȥ<EFBFBD>Ƽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>޹<EFBFBD>˾
Ʒ<EFBFBD>ƣ<EFBFBD>WHEELTEC
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>wheeltec.net
<EFBFBD>Ա<EFBFBD><EFBFBD><EFBFBD><EFBFBD>̣<EFBFBD>shop114407458.taobao.com
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ: https://minibalance.aliexpress.com/store/4455017
<EFBFBD>汾<EFBFBD><EFBFBD>5.7
<EFBFBD>޸<EFBFBD>ʱ<EFBFBD>䣺2021-04-29
Brand: WHEELTEC
Website: wheeltec.net
Taobao shop: shop114407458.taobao.com
Aliexpress: https://minibalance.aliexpress.com/store/4455017
Version:5.7
Update<EFBFBD><EFBFBD>2021-04-29
All rights reserved
***********************************************/
#include "sys.h"
/**************************************************************************
Function: Set the vector table offset address
Input : Base site Offsets
Output : none
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD>Ƶ<EFBFBD>ַ
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>NVIC_VectTab:<EFBFBD><EFBFBD>ַ Offset:ƫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
**************************************************************************/
void MY_NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
{
SCB->VTOR = NVIC_VectTab|(Offset & (u32)0x1FFFFF80);//<2F><><EFBFBD><EFBFBD>NVIC<49><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƫ<EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
//<2F><><EFBFBD>ڱ<EFBFBD>ʶ<EFBFBD><CAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CODE<44><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM<41><4D>
}
/**************************************************************************
Function: Set NVIC group
Input : NVIC_Group
Output : none
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϷ<EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>NVIC_Group:NVIC<EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0~4 <EFBFBD>ܹ<EFBFBD>5<EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
**************************************************************************/
void MY_NVIC_PriorityGroupConfig(u8 NVIC_Group)
{
u32 temp,temp1;
temp1=(~NVIC_Group)&0x07;//ȡ<><C8A1><EFBFBD><EFBFBD>λ
temp1<<=8;
temp=SCB->AIRCR; //<2F><>ȡ<EFBFBD><C8A1>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
temp&=0X0000F8FF; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD>
temp|=0X05FA0000; //д<><D0B4>Կ<EFBFBD><D4BF>
temp|=temp1;
SCB->AIRCR=temp; //<2F><><EFBFBD>÷<EFBFBD><C3B7><EFBFBD>
}
/**************************************************************************
Function: Set NVIC group
Input : NVIC_PreemptionPriority NVIC_SubPriority NVIC_Channel NVIC_Group
Output : none
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϷ<EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD> <EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD> <EFBFBD>жϱ<EFBFBD><EFBFBD><EFBFBD> <EFBFBD>жϷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD>жϷ<EFBFBD><EFBFBD><EFBFBD> | <EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* --------+--------------------------------------
* <EFBFBD><EFBFBD>0 | 0λ<EFBFBD><EFBFBD>ռ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>,4λ<EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>
* <EFBFBD><EFBFBD>1 | 1λ<EFBFBD><EFBFBD>ռ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>,3λ<EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>
* <EFBFBD><EFBFBD>2 | 2λ<EFBFBD><EFBFBD>ռ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>,2λ<EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>
* <EFBFBD><EFBFBD>3 | 3λ<EFBFBD><EFBFBD>ռ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>,1λ<EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>
* <EFBFBD><EFBFBD>4 | 4λ<EFBFBD><EFBFBD>ռ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>,0λ<EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>
*NVIC_SubPriority<EFBFBD><EFBFBD>NVIC_PreemptionPriority<EFBFBD><EFBFBD>ԭ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<EFBFBD><EFBFBD>ֵԽС,Խ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
**************************************************************************/
void MY_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group)
{ //ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD><C8BC><EFBFBD><EFBFBD>ܳ<EFBFBD><DCB3><EFBFBD><EFBFBD>趨<EFBFBD><E8B6A8><EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>Χ!<21><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>벻<EFBFBD><EBB2BB><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
u32 temp;
MY_NVIC_PriorityGroupConfig(NVIC_Group); //<2F><><EFBFBD>÷<EFBFBD><C3B7><EFBFBD>
temp=NVIC_PreemptionPriority<<(4-NVIC_Group);
temp|=NVIC_SubPriority&(0x0f>>NVIC_Group);
temp&=0xf;//ȡ<><C8A1><EFBFBD><EFBFBD>λ
NVIC->ISER[NVIC_Channel/32]|=(1<<NVIC_Channel%32);//ʹ<><CAB9><EFBFBD>ж<EFBFBD>λ(Ҫ<><D2AA><EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD>,<2C>෴<EFBFBD><E0B7B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>OK)
NVIC->IP[NVIC_Channel]|=temp<<4; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD>ȼ<EFBFBD><C8BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȼ<EFBFBD>
}
/**************************************************************************
Function: External interrupt function configuration
Input : GPIOx<EFBFBD><EFBFBD>General-purpose input/output BITx<EFBFBD><EFBFBD>The port needed enable
TRIM<EFBFBD><EFBFBD>Trigger mode
Output : none
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><EFBFBD>ⲿ<EFBFBD>жϺ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>GPIOx:0~6,<EFBFBD><EFBFBD><EFBFBD><EFBFBD>GPIOA~G<EFBFBD><EFBFBD>
BITx:<EFBFBD><EFBFBD>Ҫʹ<EFBFBD>ܵ<EFBFBD>λ; TRIM:<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ,1,<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>;2,<EFBFBD>Ͻ<EFBFBD><EFBFBD><EFBFBD>;3<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
**************************************************************************/
//<2F>ú<EFBFBD><C3BA><EFBFBD>һ<EFBFBD><D2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31>IO<49><4F>,<2C><><EFBFBD><EFBFBD>IO<49><4F>,<2C><><EFBFBD><EFBFBD><EFBFBD>ε<EFBFBD><CEB5><EFBFBD>
//<2F>ú<EFBFBD><C3BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>ж<EFBFBD>,<2C>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM)
{
u8 EXTADDR;
u8 EXTOFFSET;
EXTADDR=BITx/4;//<2F>õ<EFBFBD><C3B5>жϼĴ<CFBC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ı<EFBFBD><C4B1><EFBFBD>
EXTOFFSET=(BITx%4)*4;
RCC->APB2ENR|=0x01;//ʹ<><CAB9>io<69><6F><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
AFIO->EXTICR[EXTADDR]&=~(0x000F<<EXTOFFSET);//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD>
AFIO->EXTICR[EXTADDR]|=GPIOx<<EXTOFFSET;//EXTI.BITxӳ<78>䵽GPIOx.BITx
//<2F>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>
EXTI->IMR|=1<<BITx;// <20><><EFBFBD><EFBFBD>line BITx<54>ϵ<EFBFBD><CFB5>ж<EFBFBD>
//EXTI->EMR|=1<<BITx;//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>line BITx<54>ϵ<EFBFBD><CFB5>¼<EFBFBD> (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD>ǿ<EFBFBD><C7BF>Ե<EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>޷<EFBFBD><DEB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>!)
if(TRIM&0x01)EXTI->FTSR|=1<<BITx;//line BITx<54><78><EFBFBD>¼<EFBFBD><C2BC>½<EFBFBD><C2BD>ش<EFBFBD><D8B4><EFBFBD>
if(TRIM&0x02)EXTI->RTSR|=1<<BITx;//line BITx<54><78><EFBFBD>¼<EFBFBD><C2BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD>
}
/**************************************************************************
Function: Reset all clock registers
Input : none
Output : none
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӼĴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
**************************************************************************/
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>踴λ!<21><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>𴮿ڲ<F0B4AEBF><DAB2><EFBFBD><EFBFBD><EFBFBD>.
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ӼĴ<D3BC><C4B4><EFBFBD><EFBFBD><EFBFBD>λ
void MYRCC_DeInit(void)
{
RCC->APB1RSTR = 0x00000000;//<2F><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>
RCC->APB2RSTR = 0x00000000;
RCC->AHBENR = 0x00000014; //˯<><CBAF>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SRAMʱ<4D><CAB1>ʹ<EFBFBD><CAB9>.<2E><><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD>.
RCC->APB2ENR = 0x00000000; //<2F><><EFBFBD><EFBFBD>ʱ<EFBFBD>ӹر<D3B9>.
RCC->APB1ENR = 0x00000000;
RCC->CR |= 0x00000001; //ʹ<><CAB9><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>HSION
RCC->CFGR &= 0xF8FF0000; //<2F><>λSW[1:0],HPRE[3:0],PPRE1[2:0],PPRE2[2:0],ADCPRE[1:0],MCO[2:0]
RCC->CR &= 0xFEF6FFFF; //<2F><>λHSEON,CSSON,PLLON
RCC->CR &= 0xFFFBFFFF; //<2F><>λHSEBYP
RCC->CFGR &= 0xFF80FFFF; //<2F><>λPLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE
RCC->CIR = 0x00000000; //<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#ifdef VECT_TAB_RAM
MY_NVIC_SetVectorTable(0x20000000, 0x0);
#else
MY_NVIC_SetVectorTable(0x08000000,0x0);
#endif
}
//THUMBָ<42>֧<EEB2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD>ʵ<EFBFBD><CAB5>ִ<EFBFBD>л<EFBFBD><D0BB><EFBFBD>ָ<EFBFBD><D6B8>WFI
__asm void WFI_SET(void)
{
WFI;
}
//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
__asm void INTX_DISABLE(void)
{
CPSID I;
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
__asm void INTX_ENABLE(void)
{
CPSIE I;
}
//<2F><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ
//addr:ջ<><D5BB><EFBFBD><EFBFBD>ַ
__asm void MSR_MSP(u32 addr)
{
MSR MSP, r0 //set Main Stack value
BX r14
}
/**************************************************************************
Function: Go to standby mode
Input : none
Output : none
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
**************************************************************************/
void Sys_Standby(void)
{
SCB->SCR|=1<<2; //ʹ<><CAB9>SLEEPDEEPλ (SYS->CTRL)
RCC->APB1ENR|=1<<28; //ʹ<>ܵ<EFBFBD>Դʱ<D4B4><CAB1>
PWR->CSR|=1<<8; //<2F><><EFBFBD><EFBFBD>WKUP<55><50><EFBFBD>ڻ<EFBFBD><DABB><EFBFBD>
PWR->CR|=1<<2; //<2F><><EFBFBD><EFBFBD>Wake-up <20><>־
PWR->CR|=1<<1; //PDDS<44><53>λ
WFI_SET(); //ִ<><D6B4>WFIָ<49><D6B8>
}
/**************************************************************************
Function: System soft reset
Input : none
Output : none
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD>ϵͳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
**************************************************************************/
void Sys_Soft_Reset(void)
{
SCB->AIRCR =0X05FA0000|(u32)0x04;
}
/**************************************************************************
Function: Set JTAG mode
Input : mode:JTAG, swd mode settings<EFBFBD><EFBFBD>00<EFBFBD><EFBFBD>all enable<EFBFBD><EFBFBD>01<EFBFBD><EFBFBD>enable SWD<EFBFBD><EFBFBD>10<EFBFBD><EFBFBD>Full shutdown
Output : none
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>JTAGģʽ
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>mode:jtag,swdģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>;00,ȫʹ<EFBFBD><EFBFBD>;01,ʹ<EFBFBD><EFBFBD>SWD;10,ȫ<EFBFBD>ر<EFBFBD>;
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
**************************************************************************/
//#define JTAG_SWD_DISABLE 0X02
//#define SWD_ENABLE 0X01
//#define JTAG_SWD_ENABLE 0X00
void JTAG_Set(u8 mode)
{
u32 temp;
temp=mode;
temp<<=25;
RCC->APB2ENR|=1<<0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
AFIO->MAPR&=0XF8FFFFFF; //<2F><><EFBFBD><EFBFBD>MAPR<50><52>[26:24]
AFIO->MAPR|=temp; //<2F><><EFBFBD><EFBFBD>jtagģʽ
}
/**************************************************************************
Function: System clock initialization function
Input : pll<EFBFBD><EFBFBD>Selected frequency multiplication<EFBFBD><EFBFBD>Starting at 2, the maximum value is 16
Output : none
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ܣ<EFBFBD>ϵͳʱ<EFBFBD>ӳ<EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
<EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>pll:ѡ<EFBFBD><EFBFBD><EFBFBD>ı<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵΪ16
<EFBFBD><EFBFBD><EFBFBD><EFBFBD> ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
**************************************************************************/
void Stm32_Clock_Init(u8 PLL)
{
unsigned char temp=0;
MYRCC_DeInit(); //<2F><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
RCC->CR|=0x00010000; //<2F>ⲿ<EFBFBD><E2B2BF><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ʹ<EFBFBD><CAB9>HSEON
while(!(RCC->CR>>17)); //<2F>ȴ<EFBFBD><C8B4>ⲿʱ<E2B2BF>Ӿ<EFBFBD><D3BE><EFBFBD>
RCC->CFGR=0X00000400; //APB1=DIV2;APB2=DIV1;AHB=DIV1;
PLL-=2; //<2F><><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD>λ
RCC->CFGR|=PLL<<18; //<2F><><EFBFBD><EFBFBD>PLLֵ 2~16
RCC->CFGR|=1<<16; //PLLSRC ON
FLASH->ACR|=0x32; //FLASH 2<><32><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
RCC->CR|=0x01000000; //PLLON
while(!(RCC->CR>>25)); //<2F>ȴ<EFBFBD>PLL<4C><4C><EFBFBD><EFBFBD>
RCC->CFGR|=0x00000002; //PLL<4C><4C>Ϊϵͳʱ<CDB3><CAB1>
while(temp!=0x02) //<2F>ȴ<EFBFBD>PLL<4C><4C>Ϊϵͳʱ<CDB3><CAB1><EFBFBD><EFBFBD><EFBFBD>óɹ<C3B3>
{
temp=RCC->CFGR>>2;
temp&=0x03;
}
}