更新初版工程
parent
2ed0f6787a
commit
f10257b47b
|
|
@ -1,34 +1,14 @@
|
||||||
# ---> C++
|
# ---> C++
|
||||||
# Prerequisites
|
# Prerequisites
|
||||||
*.d
|
*.d
|
||||||
|
|
||||||
# Compiled Object files
|
|
||||||
*.slo
|
|
||||||
*.lo
|
|
||||||
*.o
|
*.o
|
||||||
*.obj
|
*.obj
|
||||||
|
*.crf
|
||||||
# Precompiled Headers
|
*.sct
|
||||||
*.gch
|
*.axf
|
||||||
*.pch
|
*.htm
|
||||||
|
*.dep
|
||||||
# Compiled Dynamic libraries
|
|
||||||
*.so
|
|
||||||
*.dylib
|
|
||||||
*.dll
|
|
||||||
|
|
||||||
# Fortran module files
|
|
||||||
*.mod
|
|
||||||
*.smod
|
|
||||||
|
|
||||||
# Compiled Static libraries
|
|
||||||
*.lai
|
|
||||||
*.la
|
|
||||||
*.a
|
*.a
|
||||||
*.lib
|
*.lib
|
||||||
|
|
||||||
# Executables
|
|
||||||
*.exe
|
|
||||||
*.out
|
|
||||||
*.app
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,5 @@
|
||||||
|
{
|
||||||
|
"files.associations": {
|
||||||
|
"limits": "c"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,220 @@
|
||||||
|
/******************** (C) COPYRIGHT 2024 GeekRebot *****************************
|
||||||
|
* File Name : control.c
|
||||||
|
* Current Version : V1.0 & ST 3.5.0
|
||||||
|
* Author : zhanli 719901725@qq.com
|
||||||
|
* Date of Issued : 2024.01.06 zhanli: Create
|
||||||
|
* Comments : 平衡车控制代码
|
||||||
|
********************************************************************************/
|
||||||
|
#include "control.h"
|
||||||
|
|
||||||
|
/**----------------------------------------------------------------------
|
||||||
|
* Function : EXTI15_10_IRQHandler
|
||||||
|
* Description : 所有的控制代码都在这里面, 5ms定时中断由MPU6050的INT引脚触发
|
||||||
|
严格保证采样和数据处理的时间同步
|
||||||
|
* Author : zhanli&719901725@qq.com
|
||||||
|
* Date : 2023/05/20 zhanli
|
||||||
|
*---------------------------------------------------------------------**/
|
||||||
|
int EXTI15_10_IRQHandler(void)
|
||||||
|
{
|
||||||
|
static u8 Flag_Target; // 控制函数相关变量，提供10ms基准
|
||||||
|
int Balance_Pwm, Velocity_Pwm; // 平衡环PWM变量，速度环PWM变量
|
||||||
|
int Motor_Left, Motor_Right; // 电机PWM变量 应是Motor的 向Moto致敬
|
||||||
|
if (INT == 0)
|
||||||
|
{
|
||||||
|
EXTI->PR = 1 << 12; // 清除中断标志位
|
||||||
|
Flag_Target = !Flag_Target;
|
||||||
|
IMU_GetAngle(); // 更新姿态 5ms读取一次
|
||||||
|
Encoder_Left = -Read_Encoder(2); // 读取左轮编码器的值，前进为正，后退为负
|
||||||
|
Encoder_Right = -Read_Encoder(4); // 读取右轮编码器的值，前进为正，后退为负
|
||||||
|
// 左轮A相接TIM2_CH1,右轮A相接TIM4_CH2,故这里两个编码器的极性相同
|
||||||
|
if (Flag_Target == 1) // 实际上10ms控制一次
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
// 扫描按键状态 单击可启停电机
|
||||||
|
Key();
|
||||||
|
|
||||||
|
// 平衡PID控制,Gyro_Balance平衡角速度极性：前倾为正，后倾为负
|
||||||
|
Balance_Pwm = Balance(Angle_Balance, Gyro_Balance);
|
||||||
|
// 速度环PID控制,记住，速度反馈是正反馈，就是小车快的时候要慢下来就需要再跑快一点
|
||||||
|
Velocity_Pwm = Velocity(Encoder_Left, Encoder_Right);
|
||||||
|
|
||||||
|
Motor_Left = Balance_Pwm + Velocity_Pwm; // 计算左轮电机最终PWM
|
||||||
|
Motor_Right = Balance_Pwm + Velocity_Pwm; // 计算右轮电机最终PWM
|
||||||
|
|
||||||
|
Motor_Left = Motor_PWMLimit(Motor_Left, 6900, -6900);
|
||||||
|
Motor_Right = Motor_PWMLimit(Motor_Right, 6900, -6900); // PWM限幅
|
||||||
|
|
||||||
|
if (Turn_Off(Angle_Balance) == 0) // 如果不存在异常
|
||||||
|
Motor_PWMSet(Motor_Left, Motor_Right); // 赋值给PWM寄存器
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**----------------------------------------------------------------------
|
||||||
|
* Function : Balance
|
||||||
|
* Description : 直立PD控制
|
||||||
|
* Input : Angle:角度, Gyro:角速度
|
||||||
|
* Author : zhanli&719901725@qq.com
|
||||||
|
* Date : 2023/05/20 zhanli
|
||||||
|
*---------------------------------------------------------------------**/
|
||||||
|
int Balance(float Angle, float Gyro)
|
||||||
|
{
|
||||||
|
// 直立环PD参数
|
||||||
|
float Balance_Kp = 225, Balance_Kd = 1.08;
|
||||||
|
float Angle_bias, Gyro_bias;
|
||||||
|
int balance;
|
||||||
|
// 求出平衡的角度中值 和机械相关
|
||||||
|
Angle_bias = Middle_angle - Angle;
|
||||||
|
Gyro_bias = 0 - Gyro;
|
||||||
|
// 计算平衡控制的电机PWM PD控制 kp是P系数 kd是D系数
|
||||||
|
balance = -Balance_Kp * Angle_bias - Gyro_bias * Balance_Kd;
|
||||||
|
return balance;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Speed PI control
|
||||||
|
Input : encoder_left：Left wheel encoder reading；encoder_right：Right wheel encoder reading
|
||||||
|
Output : Speed control PWM
|
||||||
|
函数功能：速度控制PWM
|
||||||
|
入口参数：encoder_left：左轮编码器读数；encoder_right：右轮编码器读数
|
||||||
|
返回 值：速度控制PWM
|
||||||
|
**************************************************************************/
|
||||||
|
int Velocity(int encoder_left, int encoder_right)
|
||||||
|
{
|
||||||
|
float Velocity_Kp = 160, Velocity_Ki = 0.8; // 速度环PI参数
|
||||||
|
static float velocity, Encoder_Least, Encoder_bias;
|
||||||
|
static float Encoder_Integral;
|
||||||
|
// 速度PI控制器
|
||||||
|
Encoder_Least = 0 - (encoder_left + encoder_right); // 获取最新速度偏差==测量速度（左右编码器之和）-目标速度（此处为零）
|
||||||
|
Encoder_bias *= 0.8; // 一阶低通滤波器
|
||||||
|
Encoder_bias += Encoder_Least * 0.2; // 一阶低通滤波器
|
||||||
|
// 相当于上次偏差的0.8 + 本次偏差的0.2，减缓速度差值，减少对直立的干扰
|
||||||
|
Encoder_Integral += Encoder_bias; // 积分出位移 积分时间：10ms
|
||||||
|
if (Encoder_Integral > 10000)
|
||||||
|
Encoder_Integral = 10000; // 积分限幅
|
||||||
|
if (Encoder_Integral < -10000)
|
||||||
|
Encoder_Integral = -10000; // 积分限幅
|
||||||
|
|
||||||
|
// 速度控制
|
||||||
|
velocity = -Encoder_bias * Velocity_Kp - Encoder_Integral * Velocity_Ki;
|
||||||
|
|
||||||
|
// 电机关闭后清除积分
|
||||||
|
if (Turn_Off(Angle_Balance) == 1 || Flag_Stop == 1)
|
||||||
|
Encoder_Integral = 0;
|
||||||
|
return velocity;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Assign to PWM register
|
||||||
|
Input : motor_left：Left wheel PWM；motor_right：Right wheel PWM
|
||||||
|
Output : none
|
||||||
|
函数功能：赋值给PWM寄存器
|
||||||
|
入口参数：左轮PWM、右轮PWM
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void Motor_PWMSet(int motor_left, int motor_right)
|
||||||
|
{
|
||||||
|
if (motor_left > 0)
|
||||||
|
BIN1 = 1, BIN2 = 0; // 前进
|
||||||
|
else
|
||||||
|
BIN1 = 0, BIN2 = 1; // 后退
|
||||||
|
PWMB = myabs(motor_left);
|
||||||
|
if (motor_right > 0)
|
||||||
|
AIN2 = 1, AIN1 = 0; // 前进
|
||||||
|
else
|
||||||
|
AIN2 = 0, AIN1 = 1; // 后退
|
||||||
|
PWMA = myabs(motor_right);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: PWM limiting range
|
||||||
|
Input : IN：Input max：Maximum value min：Minimum value
|
||||||
|
Output : Output
|
||||||
|
函数功能：限制PWM赋值
|
||||||
|
入口参数：IN：输入参数 max：限幅最大值 min：限幅最小值
|
||||||
|
返回 值：限幅后的值
|
||||||
|
**************************************************************************/
|
||||||
|
int Motor_PWMLimit(int IN, int max, int min)
|
||||||
|
{
|
||||||
|
int OUT = IN;
|
||||||
|
if (OUT > max){
|
||||||
|
OUT = max;
|
||||||
|
}
|
||||||
|
if (OUT < min){
|
||||||
|
OUT = min;
|
||||||
|
}
|
||||||
|
return OUT;
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Press the key to modify the car running state
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：按键修改小车运行状态
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void Key(void)
|
||||||
|
{
|
||||||
|
u8 tmp;
|
||||||
|
tmp = click();
|
||||||
|
if (tmp == 1){
|
||||||
|
Flag_Stop = !Flag_Stop; // 单击控制小车的启停
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: If abnormal, turn off the motor
|
||||||
|
Input : angle：Car inclination；voltage：Voltage
|
||||||
|
Output : 1：abnormal；0：normal
|
||||||
|
函数功能：异常关闭电机
|
||||||
|
入口参数：angle：小车倾角
|
||||||
|
返回 值：1：异常 0：正常
|
||||||
|
**************************************************************************/
|
||||||
|
u8 Turn_Off(float angle)
|
||||||
|
{
|
||||||
|
u8 temp;
|
||||||
|
if (angle < -40 || angle > 40 || 1 == Flag_Stop) // 倾角大于40度关闭电机
|
||||||
|
{ // Flag_Stop置1关闭电机
|
||||||
|
temp = 1;
|
||||||
|
AIN1 = 0;
|
||||||
|
AIN2 = 0;
|
||||||
|
BIN1 = 0;
|
||||||
|
BIN2 = 0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
temp = 0;
|
||||||
|
return temp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Get angle
|
||||||
|
Input : way：The algorithm of getting angle 1：DMP 2：kalman 3：Complementary filtering
|
||||||
|
Output : none
|
||||||
|
函数功能：获取角度
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void IMU_GetAngle(void)
|
||||||
|
{
|
||||||
|
Read_DMP(); // 读取加速度、角速度、倾角
|
||||||
|
Angle_Balance = Pitch; // 更新平衡倾角,前倾为正，后倾为负
|
||||||
|
Gyro_Balance = gyro[0]; // 更新平衡角速度,前倾为正，后倾为负
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Absolute value function
|
||||||
|
Input : a：Number to be converted
|
||||||
|
Output : unsigned int
|
||||||
|
函数功能：绝对值函数
|
||||||
|
入口参数：a：需要计算绝对值的数
|
||||||
|
返回 值：无符号整型
|
||||||
|
**************************************************************************/
|
||||||
|
int myabs(int a)
|
||||||
|
{
|
||||||
|
int temp;
|
||||||
|
if (a < 0)
|
||||||
|
temp = -a;
|
||||||
|
else
|
||||||
|
temp = a;
|
||||||
|
return temp;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
#ifndef __CONTROL_H__
|
||||||
|
#define __CONTROL_H__
|
||||||
|
#include "sys.h"
|
||||||
|
|
||||||
|
#define Middle_angle 0 // 定义平衡角度为0
|
||||||
|
|
||||||
|
int EXTI15_10_IRQHandler(void);
|
||||||
|
int Balance(float angle,float gyro);
|
||||||
|
int Velocity(int encoder_left,int encoder_right);
|
||||||
|
void Motor_PWMSet(int motor_left,int motor_right);
|
||||||
|
int Motor_PWMLimit(int IN,int max,int min);
|
||||||
|
void Key(void);
|
||||||
|
u8 Turn_Off(float angle);
|
||||||
|
void IMU_GetAngle(void);
|
||||||
|
int myabs(int a);
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,494 @@
|
||||||
|
/*
|
||||||
|
$License:
|
||||||
|
Copyright (C) 2011 InvenSense Corporation, All Rights Reserved.
|
||||||
|
$
|
||||||
|
*/
|
||||||
|
#ifndef DMPKEY_H__
|
||||||
|
#define DMPKEY_H__
|
||||||
|
|
||||||
|
#define KEY_CFG_25 (0)
|
||||||
|
#define KEY_CFG_24 (KEY_CFG_25 + 1)
|
||||||
|
#define KEY_CFG_26 (KEY_CFG_24 + 1)
|
||||||
|
#define KEY_CFG_27 (KEY_CFG_26 + 1)
|
||||||
|
#define KEY_CFG_21 (KEY_CFG_27 + 1)
|
||||||
|
#define KEY_CFG_20 (KEY_CFG_21 + 1)
|
||||||
|
#define KEY_CFG_TAP4 (KEY_CFG_20 + 1)
|
||||||
|
#define KEY_CFG_TAP5 (KEY_CFG_TAP4 + 1)
|
||||||
|
#define KEY_CFG_TAP6 (KEY_CFG_TAP5 + 1)
|
||||||
|
#define KEY_CFG_TAP7 (KEY_CFG_TAP6 + 1)
|
||||||
|
#define KEY_CFG_TAP0 (KEY_CFG_TAP7 + 1)
|
||||||
|
#define KEY_CFG_TAP1 (KEY_CFG_TAP0 + 1)
|
||||||
|
#define KEY_CFG_TAP2 (KEY_CFG_TAP1 + 1)
|
||||||
|
#define KEY_CFG_TAP3 (KEY_CFG_TAP2 + 1)
|
||||||
|
#define KEY_CFG_TAP_QUANTIZE (KEY_CFG_TAP3 + 1)
|
||||||
|
#define KEY_CFG_TAP_JERK (KEY_CFG_TAP_QUANTIZE + 1)
|
||||||
|
#define KEY_CFG_DR_INT (KEY_CFG_TAP_JERK + 1)
|
||||||
|
#define KEY_CFG_AUTH (KEY_CFG_DR_INT + 1)
|
||||||
|
#define KEY_CFG_TAP_SAVE_ACCB (KEY_CFG_AUTH + 1)
|
||||||
|
#define KEY_CFG_TAP_CLEAR_STICKY (KEY_CFG_TAP_SAVE_ACCB + 1)
|
||||||
|
#define KEY_CFG_FIFO_ON_EVENT (KEY_CFG_TAP_CLEAR_STICKY + 1)
|
||||||
|
#define KEY_FCFG_ACCEL_INPUT (KEY_CFG_FIFO_ON_EVENT + 1)
|
||||||
|
#define KEY_FCFG_ACCEL_INIT (KEY_FCFG_ACCEL_INPUT + 1)
|
||||||
|
#define KEY_CFG_23 (KEY_FCFG_ACCEL_INIT + 1)
|
||||||
|
#define KEY_FCFG_1 (KEY_CFG_23 + 1)
|
||||||
|
#define KEY_FCFG_3 (KEY_FCFG_1 + 1)
|
||||||
|
#define KEY_FCFG_2 (KEY_FCFG_3 + 1)
|
||||||
|
#define KEY_CFG_3D (KEY_FCFG_2 + 1)
|
||||||
|
#define KEY_CFG_3B (KEY_CFG_3D + 1)
|
||||||
|
#define KEY_CFG_3C (KEY_CFG_3B + 1)
|
||||||
|
#define KEY_FCFG_5 (KEY_CFG_3C + 1)
|
||||||
|
#define KEY_FCFG_4 (KEY_FCFG_5 + 1)
|
||||||
|
#define KEY_FCFG_7 (KEY_FCFG_4 + 1)
|
||||||
|
#define KEY_FCFG_FSCALE (KEY_FCFG_7 + 1)
|
||||||
|
#define KEY_FCFG_AZ (KEY_FCFG_FSCALE + 1)
|
||||||
|
#define KEY_FCFG_6 (KEY_FCFG_AZ + 1)
|
||||||
|
#define KEY_FCFG_LSB4 (KEY_FCFG_6 + 1)
|
||||||
|
#define KEY_CFG_12 (KEY_FCFG_LSB4 + 1)
|
||||||
|
#define KEY_CFG_14 (KEY_CFG_12 + 1)
|
||||||
|
#define KEY_CFG_15 (KEY_CFG_14 + 1)
|
||||||
|
#define KEY_CFG_16 (KEY_CFG_15 + 1)
|
||||||
|
#define KEY_CFG_18 (KEY_CFG_16 + 1)
|
||||||
|
#define KEY_CFG_6 (KEY_CFG_18 + 1)
|
||||||
|
#define KEY_CFG_7 (KEY_CFG_6 + 1)
|
||||||
|
#define KEY_CFG_4 (KEY_CFG_7 + 1)
|
||||||
|
#define KEY_CFG_5 (KEY_CFG_4 + 1)
|
||||||
|
#define KEY_CFG_2 (KEY_CFG_5 + 1)
|
||||||
|
#define KEY_CFG_3 (KEY_CFG_2 + 1)
|
||||||
|
#define KEY_CFG_1 (KEY_CFG_3 + 1)
|
||||||
|
#define KEY_CFG_EXTERNAL (KEY_CFG_1 + 1)
|
||||||
|
#define KEY_CFG_8 (KEY_CFG_EXTERNAL + 1)
|
||||||
|
#define KEY_CFG_9 (KEY_CFG_8 + 1)
|
||||||
|
#define KEY_CFG_ORIENT_3 (KEY_CFG_9 + 1)
|
||||||
|
#define KEY_CFG_ORIENT_2 (KEY_CFG_ORIENT_3 + 1)
|
||||||
|
#define KEY_CFG_ORIENT_1 (KEY_CFG_ORIENT_2 + 1)
|
||||||
|
#define KEY_CFG_GYRO_SOURCE (KEY_CFG_ORIENT_1 + 1)
|
||||||
|
#define KEY_CFG_ORIENT_IRQ_1 (KEY_CFG_GYRO_SOURCE + 1)
|
||||||
|
#define KEY_CFG_ORIENT_IRQ_2 (KEY_CFG_ORIENT_IRQ_1 + 1)
|
||||||
|
#define KEY_CFG_ORIENT_IRQ_3 (KEY_CFG_ORIENT_IRQ_2 + 1)
|
||||||
|
#define KEY_FCFG_MAG_VAL (KEY_CFG_ORIENT_IRQ_3 + 1)
|
||||||
|
#define KEY_FCFG_MAG_MOV (KEY_FCFG_MAG_VAL + 1)
|
||||||
|
#define KEY_CFG_LP_QUAT (KEY_FCFG_MAG_MOV + 1)
|
||||||
|
|
||||||
|
/* MPU6050 keys */
|
||||||
|
#define KEY_CFG_ACCEL_FILTER (KEY_CFG_LP_QUAT + 1)
|
||||||
|
#define KEY_CFG_MOTION_BIAS (KEY_CFG_ACCEL_FILTER + 1)
|
||||||
|
#define KEY_TEMPLABEL (KEY_CFG_MOTION_BIAS + 1)
|
||||||
|
|
||||||
|
#define KEY_D_0_22 (KEY_TEMPLABEL + 1)
|
||||||
|
#define KEY_D_0_24 (KEY_D_0_22 + 1)
|
||||||
|
#define KEY_D_0_36 (KEY_D_0_24 + 1)
|
||||||
|
#define KEY_D_0_52 (KEY_D_0_36 + 1)
|
||||||
|
#define KEY_D_0_96 (KEY_D_0_52 + 1)
|
||||||
|
#define KEY_D_0_104 (KEY_D_0_96 + 1)
|
||||||
|
#define KEY_D_0_108 (KEY_D_0_104 + 1)
|
||||||
|
#define KEY_D_0_163 (KEY_D_0_108 + 1)
|
||||||
|
#define KEY_D_0_188 (KEY_D_0_163 + 1)
|
||||||
|
#define KEY_D_0_192 (KEY_D_0_188 + 1)
|
||||||
|
#define KEY_D_0_224 (KEY_D_0_192 + 1)
|
||||||
|
#define KEY_D_0_228 (KEY_D_0_224 + 1)
|
||||||
|
#define KEY_D_0_232 (KEY_D_0_228 + 1)
|
||||||
|
#define KEY_D_0_236 (KEY_D_0_232 + 1)
|
||||||
|
|
||||||
|
#define KEY_DMP_PREVPTAT (KEY_D_0_236 + 1)
|
||||||
|
#define KEY_D_1_2 (KEY_DMP_PREVPTAT + 1)
|
||||||
|
#define KEY_D_1_4 (KEY_D_1_2 + 1)
|
||||||
|
#define KEY_D_1_8 (KEY_D_1_4 + 1)
|
||||||
|
#define KEY_D_1_10 (KEY_D_1_8 + 1)
|
||||||
|
#define KEY_D_1_24 (KEY_D_1_10 + 1)
|
||||||
|
#define KEY_D_1_28 (KEY_D_1_24 + 1)
|
||||||
|
#define KEY_D_1_36 (KEY_D_1_28 + 1)
|
||||||
|
#define KEY_D_1_40 (KEY_D_1_36 + 1)
|
||||||
|
#define KEY_D_1_44 (KEY_D_1_40 + 1)
|
||||||
|
#define KEY_D_1_72 (KEY_D_1_44 + 1)
|
||||||
|
#define KEY_D_1_74 (KEY_D_1_72 + 1)
|
||||||
|
#define KEY_D_1_79 (KEY_D_1_74 + 1)
|
||||||
|
#define KEY_D_1_88 (KEY_D_1_79 + 1)
|
||||||
|
#define KEY_D_1_90 (KEY_D_1_88 + 1)
|
||||||
|
#define KEY_D_1_92 (KEY_D_1_90 + 1)
|
||||||
|
#define KEY_D_1_96 (KEY_D_1_92 + 1)
|
||||||
|
#define KEY_D_1_98 (KEY_D_1_96 + 1)
|
||||||
|
#define KEY_D_1_100 (KEY_D_1_98 + 1)
|
||||||
|
#define KEY_D_1_106 (KEY_D_1_100 + 1)
|
||||||
|
#define KEY_D_1_108 (KEY_D_1_106 + 1)
|
||||||
|
#define KEY_D_1_112 (KEY_D_1_108 + 1)
|
||||||
|
#define KEY_D_1_128 (KEY_D_1_112 + 1)
|
||||||
|
#define KEY_D_1_152 (KEY_D_1_128 + 1)
|
||||||
|
#define KEY_D_1_160 (KEY_D_1_152 + 1)
|
||||||
|
#define KEY_D_1_168 (KEY_D_1_160 + 1)
|
||||||
|
#define KEY_D_1_175 (KEY_D_1_168 + 1)
|
||||||
|
#define KEY_D_1_176 (KEY_D_1_175 + 1)
|
||||||
|
#define KEY_D_1_178 (KEY_D_1_176 + 1)
|
||||||
|
#define KEY_D_1_179 (KEY_D_1_178 + 1)
|
||||||
|
#define KEY_D_1_218 (KEY_D_1_179 + 1)
|
||||||
|
#define KEY_D_1_232 (KEY_D_1_218 + 1)
|
||||||
|
#define KEY_D_1_236 (KEY_D_1_232 + 1)
|
||||||
|
#define KEY_D_1_240 (KEY_D_1_236 + 1)
|
||||||
|
#define KEY_D_1_244 (KEY_D_1_240 + 1)
|
||||||
|
#define KEY_D_1_250 (KEY_D_1_244 + 1)
|
||||||
|
#define KEY_D_1_252 (KEY_D_1_250 + 1)
|
||||||
|
#define KEY_D_2_12 (KEY_D_1_252 + 1)
|
||||||
|
#define KEY_D_2_96 (KEY_D_2_12 + 1)
|
||||||
|
#define KEY_D_2_108 (KEY_D_2_96 + 1)
|
||||||
|
#define KEY_D_2_208 (KEY_D_2_108 + 1)
|
||||||
|
#define KEY_FLICK_MSG (KEY_D_2_208 + 1)
|
||||||
|
#define KEY_FLICK_COUNTER (KEY_FLICK_MSG + 1)
|
||||||
|
#define KEY_FLICK_LOWER (KEY_FLICK_COUNTER + 1)
|
||||||
|
#define KEY_CFG_FLICK_IN (KEY_FLICK_LOWER + 1)
|
||||||
|
#define KEY_FLICK_UPPER (KEY_CFG_FLICK_IN + 1)
|
||||||
|
#define KEY_CGNOTICE_INTR (KEY_FLICK_UPPER + 1)
|
||||||
|
#define KEY_D_2_224 (KEY_CGNOTICE_INTR + 1)
|
||||||
|
#define KEY_D_2_244 (KEY_D_2_224 + 1)
|
||||||
|
#define KEY_D_2_248 (KEY_D_2_244 + 1)
|
||||||
|
#define KEY_D_2_252 (KEY_D_2_248 + 1)
|
||||||
|
|
||||||
|
#define KEY_D_GYRO_BIAS_X (KEY_D_2_252 + 1)
|
||||||
|
#define KEY_D_GYRO_BIAS_Y (KEY_D_GYRO_BIAS_X + 1)
|
||||||
|
#define KEY_D_GYRO_BIAS_Z (KEY_D_GYRO_BIAS_Y + 1)
|
||||||
|
#define KEY_D_ACC_BIAS_X (KEY_D_GYRO_BIAS_Z + 1)
|
||||||
|
#define KEY_D_ACC_BIAS_Y (KEY_D_ACC_BIAS_X + 1)
|
||||||
|
#define KEY_D_ACC_BIAS_Z (KEY_D_ACC_BIAS_Y + 1)
|
||||||
|
#define KEY_D_GYRO_ENABLE (KEY_D_ACC_BIAS_Z + 1)
|
||||||
|
#define KEY_D_ACCEL_ENABLE (KEY_D_GYRO_ENABLE + 1)
|
||||||
|
#define KEY_D_QUAT_ENABLE (KEY_D_ACCEL_ENABLE +1)
|
||||||
|
#define KEY_D_OUTPUT_ENABLE (KEY_D_QUAT_ENABLE + 1)
|
||||||
|
#define KEY_D_CR_TIME_G (KEY_D_OUTPUT_ENABLE + 1)
|
||||||
|
#define KEY_D_CR_TIME_A (KEY_D_CR_TIME_G + 1)
|
||||||
|
#define KEY_D_CR_TIME_Q (KEY_D_CR_TIME_A + 1)
|
||||||
|
#define KEY_D_CS_TAX (KEY_D_CR_TIME_Q + 1)
|
||||||
|
#define KEY_D_CS_TAY (KEY_D_CS_TAX + 1)
|
||||||
|
#define KEY_D_CS_TAZ (KEY_D_CS_TAY + 1)
|
||||||
|
#define KEY_D_CS_TGX (KEY_D_CS_TAZ + 1)
|
||||||
|
#define KEY_D_CS_TGY (KEY_D_CS_TGX + 1)
|
||||||
|
#define KEY_D_CS_TGZ (KEY_D_CS_TGY + 1)
|
||||||
|
#define KEY_D_CS_TQ0 (KEY_D_CS_TGZ + 1)
|
||||||
|
#define KEY_D_CS_TQ1 (KEY_D_CS_TQ0 + 1)
|
||||||
|
#define KEY_D_CS_TQ2 (KEY_D_CS_TQ1 + 1)
|
||||||
|
#define KEY_D_CS_TQ3 (KEY_D_CS_TQ2 + 1)
|
||||||
|
|
||||||
|
/* Compass keys */
|
||||||
|
#define KEY_CPASS_BIAS_X (KEY_D_CS_TQ3 + 1)
|
||||||
|
#define KEY_CPASS_BIAS_Y (KEY_CPASS_BIAS_X + 1)
|
||||||
|
#define KEY_CPASS_BIAS_Z (KEY_CPASS_BIAS_Y + 1)
|
||||||
|
#define KEY_CPASS_MTX_00 (KEY_CPASS_BIAS_Z + 1)
|
||||||
|
#define KEY_CPASS_MTX_01 (KEY_CPASS_MTX_00 + 1)
|
||||||
|
#define KEY_CPASS_MTX_02 (KEY_CPASS_MTX_01 + 1)
|
||||||
|
#define KEY_CPASS_MTX_10 (KEY_CPASS_MTX_02 + 1)
|
||||||
|
#define KEY_CPASS_MTX_11 (KEY_CPASS_MTX_10 + 1)
|
||||||
|
#define KEY_CPASS_MTX_12 (KEY_CPASS_MTX_11 + 1)
|
||||||
|
#define KEY_CPASS_MTX_20 (KEY_CPASS_MTX_12 + 1)
|
||||||
|
#define KEY_CPASS_MTX_21 (KEY_CPASS_MTX_20 + 1)
|
||||||
|
#define KEY_CPASS_MTX_22 (KEY_CPASS_MTX_21 + 1)
|
||||||
|
|
||||||
|
/* Gesture Keys */
|
||||||
|
#define KEY_DMP_TAPW_MIN (KEY_CPASS_MTX_22 + 1)
|
||||||
|
#define KEY_DMP_TAP_THR_X (KEY_DMP_TAPW_MIN + 1)
|
||||||
|
#define KEY_DMP_TAP_THR_Y (KEY_DMP_TAP_THR_X + 1)
|
||||||
|
#define KEY_DMP_TAP_THR_Z (KEY_DMP_TAP_THR_Y + 1)
|
||||||
|
#define KEY_DMP_SH_TH_Y (KEY_DMP_TAP_THR_Z + 1)
|
||||||
|
#define KEY_DMP_SH_TH_X (KEY_DMP_SH_TH_Y + 1)
|
||||||
|
#define KEY_DMP_SH_TH_Z (KEY_DMP_SH_TH_X + 1)
|
||||||
|
#define KEY_DMP_ORIENT (KEY_DMP_SH_TH_Z + 1)
|
||||||
|
#define KEY_D_ACT0 (KEY_DMP_ORIENT + 1)
|
||||||
|
#define KEY_D_ACSX (KEY_D_ACT0 + 1)
|
||||||
|
#define KEY_D_ACSY (KEY_D_ACSX + 1)
|
||||||
|
#define KEY_D_ACSZ (KEY_D_ACSY + 1)
|
||||||
|
|
||||||
|
#define KEY_X_GRT_Y_TMP (KEY_D_ACSZ + 1)
|
||||||
|
#define KEY_SKIP_X_GRT_Y_TMP (KEY_X_GRT_Y_TMP + 1)
|
||||||
|
#define KEY_SKIP_END_COMPARE (KEY_SKIP_X_GRT_Y_TMP + 1)
|
||||||
|
#define KEY_END_COMPARE_Y_X_TMP2 (KEY_SKIP_END_COMPARE + 1)
|
||||||
|
#define KEY_CFG_ANDROID_ORIENT_INT (KEY_END_COMPARE_Y_X_TMP2 + 1)
|
||||||
|
#define KEY_NO_ORIENT_INTERRUPT (KEY_CFG_ANDROID_ORIENT_INT + 1)
|
||||||
|
#define KEY_END_COMPARE_Y_X_TMP (KEY_NO_ORIENT_INTERRUPT + 1)
|
||||||
|
#define KEY_END_ORIENT_1 (KEY_END_COMPARE_Y_X_TMP + 1)
|
||||||
|
#define KEY_END_COMPARE_Y_X (KEY_END_ORIENT_1 + 1)
|
||||||
|
#define KEY_END_ORIENT (KEY_END_COMPARE_Y_X + 1)
|
||||||
|
#define KEY_X_GRT_Y (KEY_END_ORIENT + 1)
|
||||||
|
#define KEY_NOT_TIME_MINUS_1 (KEY_X_GRT_Y + 1)
|
||||||
|
#define KEY_END_COMPARE_Y_X_TMP3 (KEY_NOT_TIME_MINUS_1 + 1)
|
||||||
|
#define KEY_X_GRT_Y_TMP2 (KEY_END_COMPARE_Y_X_TMP3 + 1)
|
||||||
|
|
||||||
|
/* Authenticate Keys */
|
||||||
|
#define KEY_D_AUTH_OUT (KEY_X_GRT_Y_TMP2 + 1)
|
||||||
|
#define KEY_D_AUTH_IN (KEY_D_AUTH_OUT + 1)
|
||||||
|
#define KEY_D_AUTH_A (KEY_D_AUTH_IN + 1)
|
||||||
|
#define KEY_D_AUTH_B (KEY_D_AUTH_A + 1)
|
||||||
|
|
||||||
|
/* Pedometer standalone only keys */
|
||||||
|
#define KEY_D_PEDSTD_BP_B (KEY_D_AUTH_B + 1)
|
||||||
|
#define KEY_D_PEDSTD_HP_A (KEY_D_PEDSTD_BP_B + 1)
|
||||||
|
#define KEY_D_PEDSTD_HP_B (KEY_D_PEDSTD_HP_A + 1)
|
||||||
|
#define KEY_D_PEDSTD_BP_A4 (KEY_D_PEDSTD_HP_B + 1)
|
||||||
|
#define KEY_D_PEDSTD_BP_A3 (KEY_D_PEDSTD_BP_A4 + 1)
|
||||||
|
#define KEY_D_PEDSTD_BP_A2 (KEY_D_PEDSTD_BP_A3 + 1)
|
||||||
|
#define KEY_D_PEDSTD_BP_A1 (KEY_D_PEDSTD_BP_A2 + 1)
|
||||||
|
#define KEY_D_PEDSTD_INT_THRSH (KEY_D_PEDSTD_BP_A1 + 1)
|
||||||
|
#define KEY_D_PEDSTD_CLIP (KEY_D_PEDSTD_INT_THRSH + 1)
|
||||||
|
#define KEY_D_PEDSTD_SB (KEY_D_PEDSTD_CLIP + 1)
|
||||||
|
#define KEY_D_PEDSTD_SB_TIME (KEY_D_PEDSTD_SB + 1)
|
||||||
|
#define KEY_D_PEDSTD_PEAKTHRSH (KEY_D_PEDSTD_SB_TIME + 1)
|
||||||
|
#define KEY_D_PEDSTD_TIML (KEY_D_PEDSTD_PEAKTHRSH + 1)
|
||||||
|
#define KEY_D_PEDSTD_TIMH (KEY_D_PEDSTD_TIML + 1)
|
||||||
|
#define KEY_D_PEDSTD_PEAK (KEY_D_PEDSTD_TIMH + 1)
|
||||||
|
#define KEY_D_PEDSTD_TIMECTR (KEY_D_PEDSTD_PEAK + 1)
|
||||||
|
#define KEY_D_PEDSTD_STEPCTR (KEY_D_PEDSTD_TIMECTR + 1)
|
||||||
|
#define KEY_D_PEDSTD_WALKTIME (KEY_D_PEDSTD_STEPCTR + 1)
|
||||||
|
#define KEY_D_PEDSTD_DECI (KEY_D_PEDSTD_WALKTIME + 1)
|
||||||
|
|
||||||
|
/*Host Based No Motion*/
|
||||||
|
#define KEY_D_HOST_NO_MOT (KEY_D_PEDSTD_DECI + 1)
|
||||||
|
|
||||||
|
/* EIS keys */
|
||||||
|
#define KEY_P_EIS_FIFO_FOOTER (KEY_D_HOST_NO_MOT + 1)
|
||||||
|
#define KEY_P_EIS_FIFO_YSHIFT (KEY_P_EIS_FIFO_FOOTER + 1)
|
||||||
|
#define KEY_P_EIS_DATA_RATE (KEY_P_EIS_FIFO_YSHIFT + 1)
|
||||||
|
#define KEY_P_EIS_FIFO_XSHIFT (KEY_P_EIS_DATA_RATE + 1)
|
||||||
|
#define KEY_P_EIS_FIFO_SYNC (KEY_P_EIS_FIFO_XSHIFT + 1)
|
||||||
|
#define KEY_P_EIS_FIFO_ZSHIFT (KEY_P_EIS_FIFO_SYNC + 1)
|
||||||
|
#define KEY_P_EIS_FIFO_READY (KEY_P_EIS_FIFO_ZSHIFT + 1)
|
||||||
|
#define KEY_DMP_FOOTER (KEY_P_EIS_FIFO_READY + 1)
|
||||||
|
#define KEY_DMP_INTX_HC (KEY_DMP_FOOTER + 1)
|
||||||
|
#define KEY_DMP_INTX_PH (KEY_DMP_INTX_HC + 1)
|
||||||
|
#define KEY_DMP_INTX_SH (KEY_DMP_INTX_PH + 1)
|
||||||
|
#define KEY_DMP_AINV_SH (KEY_DMP_INTX_SH + 1)
|
||||||
|
#define KEY_DMP_A_INV_XH (KEY_DMP_AINV_SH + 1)
|
||||||
|
#define KEY_DMP_AINV_PH (KEY_DMP_A_INV_XH + 1)
|
||||||
|
#define KEY_DMP_CTHX_H (KEY_DMP_AINV_PH + 1)
|
||||||
|
#define KEY_DMP_CTHY_H (KEY_DMP_CTHX_H + 1)
|
||||||
|
#define KEY_DMP_CTHZ_H (KEY_DMP_CTHY_H + 1)
|
||||||
|
#define KEY_DMP_NCTHX_H (KEY_DMP_CTHZ_H + 1)
|
||||||
|
#define KEY_DMP_NCTHY_H (KEY_DMP_NCTHX_H + 1)
|
||||||
|
#define KEY_DMP_NCTHZ_H (KEY_DMP_NCTHY_H + 1)
|
||||||
|
#define KEY_DMP_CTSQ_XH (KEY_DMP_NCTHZ_H + 1)
|
||||||
|
#define KEY_DMP_CTSQ_YH (KEY_DMP_CTSQ_XH + 1)
|
||||||
|
#define KEY_DMP_CTSQ_ZH (KEY_DMP_CTSQ_YH + 1)
|
||||||
|
#define KEY_DMP_INTX_H (KEY_DMP_CTSQ_ZH + 1)
|
||||||
|
#define KEY_DMP_INTY_H (KEY_DMP_INTX_H + 1)
|
||||||
|
#define KEY_DMP_INTZ_H (KEY_DMP_INTY_H + 1)
|
||||||
|
//#define KEY_DMP_HPX_H (KEY_DMP_INTZ_H + 1)
|
||||||
|
//#define KEY_DMP_HPY_H (KEY_DMP_HPX_H + 1)
|
||||||
|
//#define KEY_DMP_HPZ_H (KEY_DMP_HPY_H + 1)
|
||||||
|
|
||||||
|
/* Stream keys */
|
||||||
|
#define KEY_STREAM_P_GYRO_Z (KEY_DMP_INTZ_H + 1)
|
||||||
|
#define KEY_STREAM_P_GYRO_Y (KEY_STREAM_P_GYRO_Z + 1)
|
||||||
|
#define KEY_STREAM_P_GYRO_X (KEY_STREAM_P_GYRO_Y + 1)
|
||||||
|
#define KEY_STREAM_P_TEMP (KEY_STREAM_P_GYRO_X + 1)
|
||||||
|
#define KEY_STREAM_P_AUX_Y (KEY_STREAM_P_TEMP + 1)
|
||||||
|
#define KEY_STREAM_P_AUX_X (KEY_STREAM_P_AUX_Y + 1)
|
||||||
|
#define KEY_STREAM_P_AUX_Z (KEY_STREAM_P_AUX_X + 1)
|
||||||
|
#define KEY_STREAM_P_ACCEL_Y (KEY_STREAM_P_AUX_Z + 1)
|
||||||
|
#define KEY_STREAM_P_ACCEL_X (KEY_STREAM_P_ACCEL_Y + 1)
|
||||||
|
#define KEY_STREAM_P_FOOTER (KEY_STREAM_P_ACCEL_X + 1)
|
||||||
|
#define KEY_STREAM_P_ACCEL_Z (KEY_STREAM_P_FOOTER + 1)
|
||||||
|
|
||||||
|
#define NUM_KEYS (KEY_STREAM_P_ACCEL_Z + 1)
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
unsigned short key;
|
||||||
|
unsigned short addr;
|
||||||
|
} tKeyLabel;
|
||||||
|
|
||||||
|
#define DINA0A 0x0a
|
||||||
|
#define DINA22 0x22
|
||||||
|
#define DINA42 0x42
|
||||||
|
#define DINA5A 0x5a
|
||||||
|
|
||||||
|
#define DINA06 0x06
|
||||||
|
#define DINA0E 0x0e
|
||||||
|
#define DINA16 0x16
|
||||||
|
#define DINA1E 0x1e
|
||||||
|
#define DINA26 0x26
|
||||||
|
#define DINA2E 0x2e
|
||||||
|
#define DINA36 0x36
|
||||||
|
#define DINA3E 0x3e
|
||||||
|
#define DINA46 0x46
|
||||||
|
#define DINA4E 0x4e
|
||||||
|
#define DINA56 0x56
|
||||||
|
#define DINA5E 0x5e
|
||||||
|
#define DINA66 0x66
|
||||||
|
#define DINA6E 0x6e
|
||||||
|
#define DINA76 0x76
|
||||||
|
#define DINA7E 0x7e
|
||||||
|
|
||||||
|
#define DINA00 0x00
|
||||||
|
#define DINA08 0x08
|
||||||
|
#define DINA10 0x10
|
||||||
|
#define DINA18 0x18
|
||||||
|
#define DINA20 0x20
|
||||||
|
#define DINA28 0x28
|
||||||
|
#define DINA30 0x30
|
||||||
|
#define DINA38 0x38
|
||||||
|
#define DINA40 0x40
|
||||||
|
#define DINA48 0x48
|
||||||
|
#define DINA50 0x50
|
||||||
|
#define DINA58 0x58
|
||||||
|
#define DINA60 0x60
|
||||||
|
#define DINA68 0x68
|
||||||
|
#define DINA70 0x70
|
||||||
|
#define DINA78 0x78
|
||||||
|
|
||||||
|
#define DINA04 0x04
|
||||||
|
#define DINA0C 0x0c
|
||||||
|
#define DINA14 0x14
|
||||||
|
#define DINA1C 0x1C
|
||||||
|
#define DINA24 0x24
|
||||||
|
#define DINA2C 0x2c
|
||||||
|
#define DINA34 0x34
|
||||||
|
#define DINA3C 0x3c
|
||||||
|
#define DINA44 0x44
|
||||||
|
#define DINA4C 0x4c
|
||||||
|
#define DINA54 0x54
|
||||||
|
#define DINA5C 0x5c
|
||||||
|
#define DINA64 0x64
|
||||||
|
#define DINA6C 0x6c
|
||||||
|
#define DINA74 0x74
|
||||||
|
#define DINA7C 0x7c
|
||||||
|
|
||||||
|
#define DINA01 0x01
|
||||||
|
#define DINA09 0x09
|
||||||
|
#define DINA11 0x11
|
||||||
|
#define DINA19 0x19
|
||||||
|
#define DINA21 0x21
|
||||||
|
#define DINA29 0x29
|
||||||
|
#define DINA31 0x31
|
||||||
|
#define DINA39 0x39
|
||||||
|
#define DINA41 0x41
|
||||||
|
#define DINA49 0x49
|
||||||
|
#define DINA51 0x51
|
||||||
|
#define DINA59 0x59
|
||||||
|
#define DINA61 0x61
|
||||||
|
#define DINA69 0x69
|
||||||
|
#define DINA71 0x71
|
||||||
|
#define DINA79 0x79
|
||||||
|
|
||||||
|
#define DINA25 0x25
|
||||||
|
#define DINA2D 0x2d
|
||||||
|
#define DINA35 0x35
|
||||||
|
#define DINA3D 0x3d
|
||||||
|
#define DINA4D 0x4d
|
||||||
|
#define DINA55 0x55
|
||||||
|
#define DINA5D 0x5D
|
||||||
|
#define DINA6D 0x6d
|
||||||
|
#define DINA75 0x75
|
||||||
|
#define DINA7D 0x7d
|
||||||
|
|
||||||
|
#define DINADC 0xdc
|
||||||
|
#define DINAF2 0xf2
|
||||||
|
#define DINAAB 0xab
|
||||||
|
#define DINAAA 0xaa
|
||||||
|
#define DINAF1 0xf1
|
||||||
|
#define DINADF 0xdf
|
||||||
|
#define DINADA 0xda
|
||||||
|
#define DINAB1 0xb1
|
||||||
|
#define DINAB9 0xb9
|
||||||
|
#define DINAF3 0xf3
|
||||||
|
#define DINA8B 0x8b
|
||||||
|
#define DINAA3 0xa3
|
||||||
|
#define DINA91 0x91
|
||||||
|
#define DINAB6 0xb6
|
||||||
|
#define DINAB4 0xb4
|
||||||
|
|
||||||
|
|
||||||
|
#define DINC00 0x00
|
||||||
|
#define DINC01 0x01
|
||||||
|
#define DINC02 0x02
|
||||||
|
#define DINC03 0x03
|
||||||
|
#define DINC08 0x08
|
||||||
|
#define DINC09 0x09
|
||||||
|
#define DINC0A 0x0a
|
||||||
|
#define DINC0B 0x0b
|
||||||
|
#define DINC10 0x10
|
||||||
|
#define DINC11 0x11
|
||||||
|
#define DINC12 0x12
|
||||||
|
#define DINC13 0x13
|
||||||
|
#define DINC18 0x18
|
||||||
|
#define DINC19 0x19
|
||||||
|
#define DINC1A 0x1a
|
||||||
|
#define DINC1B 0x1b
|
||||||
|
|
||||||
|
#define DINC20 0x20
|
||||||
|
#define DINC21 0x21
|
||||||
|
#define DINC22 0x22
|
||||||
|
#define DINC23 0x23
|
||||||
|
#define DINC28 0x28
|
||||||
|
#define DINC29 0x29
|
||||||
|
#define DINC2A 0x2a
|
||||||
|
#define DINC2B 0x2b
|
||||||
|
#define DINC30 0x30
|
||||||
|
#define DINC31 0x31
|
||||||
|
#define DINC32 0x32
|
||||||
|
#define DINC33 0x33
|
||||||
|
#define DINC38 0x38
|
||||||
|
#define DINC39 0x39
|
||||||
|
#define DINC3A 0x3a
|
||||||
|
#define DINC3B 0x3b
|
||||||
|
|
||||||
|
#define DINC40 0x40
|
||||||
|
#define DINC41 0x41
|
||||||
|
#define DINC42 0x42
|
||||||
|
#define DINC43 0x43
|
||||||
|
#define DINC48 0x48
|
||||||
|
#define DINC49 0x49
|
||||||
|
#define DINC4A 0x4a
|
||||||
|
#define DINC4B 0x4b
|
||||||
|
#define DINC50 0x50
|
||||||
|
#define DINC51 0x51
|
||||||
|
#define DINC52 0x52
|
||||||
|
#define DINC53 0x53
|
||||||
|
#define DINC58 0x58
|
||||||
|
#define DINC59 0x59
|
||||||
|
#define DINC5A 0x5a
|
||||||
|
#define DINC5B 0x5b
|
||||||
|
|
||||||
|
#define DINC60 0x60
|
||||||
|
#define DINC61 0x61
|
||||||
|
#define DINC62 0x62
|
||||||
|
#define DINC63 0x63
|
||||||
|
#define DINC68 0x68
|
||||||
|
#define DINC69 0x69
|
||||||
|
#define DINC6A 0x6a
|
||||||
|
#define DINC6B 0x6b
|
||||||
|
#define DINC70 0x70
|
||||||
|
#define DINC71 0x71
|
||||||
|
#define DINC72 0x72
|
||||||
|
#define DINC73 0x73
|
||||||
|
#define DINC78 0x78
|
||||||
|
#define DINC79 0x79
|
||||||
|
#define DINC7A 0x7a
|
||||||
|
#define DINC7B 0x7b
|
||||||
|
|
||||||
|
#define DIND40 0x40
|
||||||
|
|
||||||
|
|
||||||
|
#define DINA80 0x80
|
||||||
|
#define DINA90 0x90
|
||||||
|
#define DINAA0 0xa0
|
||||||
|
#define DINAC9 0xc9
|
||||||
|
#define DINACB 0xcb
|
||||||
|
#define DINACD 0xcd
|
||||||
|
#define DINACF 0xcf
|
||||||
|
#define DINAC8 0xc8
|
||||||
|
#define DINACA 0xca
|
||||||
|
#define DINACC 0xcc
|
||||||
|
#define DINACE 0xce
|
||||||
|
#define DINAD8 0xd8
|
||||||
|
#define DINADD 0xdd
|
||||||
|
#define DINAF8 0xf0
|
||||||
|
#define DINAFE 0xfe
|
||||||
|
|
||||||
|
#define DINBF8 0xf8
|
||||||
|
#define DINAC0 0xb0
|
||||||
|
#define DINAC1 0xb1
|
||||||
|
#define DINAC2 0xb4
|
||||||
|
#define DINAC3 0xb5
|
||||||
|
#define DINAC4 0xb8
|
||||||
|
#define DINAC5 0xb9
|
||||||
|
#define DINBC0 0xc0
|
||||||
|
#define DINBC2 0xc2
|
||||||
|
#define DINBC4 0xc4
|
||||||
|
#define DINBC6 0xc6
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif // DMPKEY_H__
|
||||||
|
|
@ -0,0 +1,264 @@
|
||||||
|
/*
|
||||||
|
$License:
|
||||||
|
Copyright (C) 2011 InvenSense Corporation, All Rights Reserved.
|
||||||
|
$
|
||||||
|
*/
|
||||||
|
#ifndef DMPMAP_H
|
||||||
|
#define DMPMAP_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define DMP_PTAT 0
|
||||||
|
#define DMP_XGYR 2
|
||||||
|
#define DMP_YGYR 4
|
||||||
|
#define DMP_ZGYR 6
|
||||||
|
#define DMP_XACC 8
|
||||||
|
#define DMP_YACC 10
|
||||||
|
#define DMP_ZACC 12
|
||||||
|
#define DMP_ADC1 14
|
||||||
|
#define DMP_ADC2 16
|
||||||
|
#define DMP_ADC3 18
|
||||||
|
#define DMP_BIASUNC 20
|
||||||
|
#define DMP_FIFORT 22
|
||||||
|
#define DMP_INVGSFH 24
|
||||||
|
#define DMP_INVGSFL 26
|
||||||
|
#define DMP_1H 28
|
||||||
|
#define DMP_1L 30
|
||||||
|
#define DMP_BLPFSTCH 32
|
||||||
|
#define DMP_BLPFSTCL 34
|
||||||
|
#define DMP_BLPFSXH 36
|
||||||
|
#define DMP_BLPFSXL 38
|
||||||
|
#define DMP_BLPFSYH 40
|
||||||
|
#define DMP_BLPFSYL 42
|
||||||
|
#define DMP_BLPFSZH 44
|
||||||
|
#define DMP_BLPFSZL 46
|
||||||
|
#define DMP_BLPFMTC 48
|
||||||
|
#define DMP_SMC 50
|
||||||
|
#define DMP_BLPFMXH 52
|
||||||
|
#define DMP_BLPFMXL 54
|
||||||
|
#define DMP_BLPFMYH 56
|
||||||
|
#define DMP_BLPFMYL 58
|
||||||
|
#define DMP_BLPFMZH 60
|
||||||
|
#define DMP_BLPFMZL 62
|
||||||
|
#define DMP_BLPFC 64
|
||||||
|
#define DMP_SMCTH 66
|
||||||
|
#define DMP_0H2 68
|
||||||
|
#define DMP_0L2 70
|
||||||
|
#define DMP_BERR2H 72
|
||||||
|
#define DMP_BERR2L 74
|
||||||
|
#define DMP_BERR2NH 76
|
||||||
|
#define DMP_SMCINC 78
|
||||||
|
#define DMP_ANGVBXH 80
|
||||||
|
#define DMP_ANGVBXL 82
|
||||||
|
#define DMP_ANGVBYH 84
|
||||||
|
#define DMP_ANGVBYL 86
|
||||||
|
#define DMP_ANGVBZH 88
|
||||||
|
#define DMP_ANGVBZL 90
|
||||||
|
#define DMP_BERR1H 92
|
||||||
|
#define DMP_BERR1L 94
|
||||||
|
#define DMP_ATCH 96
|
||||||
|
#define DMP_BIASUNCSF 98
|
||||||
|
#define DMP_ACT2H 100
|
||||||
|
#define DMP_ACT2L 102
|
||||||
|
#define DMP_GSFH 104
|
||||||
|
#define DMP_GSFL 106
|
||||||
|
#define DMP_GH 108
|
||||||
|
#define DMP_GL 110
|
||||||
|
#define DMP_0_5H 112
|
||||||
|
#define DMP_0_5L 114
|
||||||
|
#define DMP_0_0H 116
|
||||||
|
#define DMP_0_0L 118
|
||||||
|
#define DMP_1_0H 120
|
||||||
|
#define DMP_1_0L 122
|
||||||
|
#define DMP_1_5H 124
|
||||||
|
#define DMP_1_5L 126
|
||||||
|
#define DMP_TMP1AH 128
|
||||||
|
#define DMP_TMP1AL 130
|
||||||
|
#define DMP_TMP2AH 132
|
||||||
|
#define DMP_TMP2AL 134
|
||||||
|
#define DMP_TMP3AH 136
|
||||||
|
#define DMP_TMP3AL 138
|
||||||
|
#define DMP_TMP4AH 140
|
||||||
|
#define DMP_TMP4AL 142
|
||||||
|
#define DMP_XACCW 144
|
||||||
|
#define DMP_TMP5 146
|
||||||
|
#define DMP_XACCB 148
|
||||||
|
#define DMP_TMP8 150
|
||||||
|
#define DMP_YACCB 152
|
||||||
|
#define DMP_TMP9 154
|
||||||
|
#define DMP_ZACCB 156
|
||||||
|
#define DMP_TMP10 158
|
||||||
|
#define DMP_DZH 160
|
||||||
|
#define DMP_DZL 162
|
||||||
|
#define DMP_XGCH 164
|
||||||
|
#define DMP_XGCL 166
|
||||||
|
#define DMP_YGCH 168
|
||||||
|
#define DMP_YGCL 170
|
||||||
|
#define DMP_ZGCH 172
|
||||||
|
#define DMP_ZGCL 174
|
||||||
|
#define DMP_YACCW 176
|
||||||
|
#define DMP_TMP7 178
|
||||||
|
#define DMP_AFB1H 180
|
||||||
|
#define DMP_AFB1L 182
|
||||||
|
#define DMP_AFB2H 184
|
||||||
|
#define DMP_AFB2L 186
|
||||||
|
#define DMP_MAGFBH 188
|
||||||
|
#define DMP_MAGFBL 190
|
||||||
|
#define DMP_QT1H 192
|
||||||
|
#define DMP_QT1L 194
|
||||||
|
#define DMP_QT2H 196
|
||||||
|
#define DMP_QT2L 198
|
||||||
|
#define DMP_QT3H 200
|
||||||
|
#define DMP_QT3L 202
|
||||||
|
#define DMP_QT4H 204
|
||||||
|
#define DMP_QT4L 206
|
||||||
|
#define DMP_CTRL1H 208
|
||||||
|
#define DMP_CTRL1L 210
|
||||||
|
#define DMP_CTRL2H 212
|
||||||
|
#define DMP_CTRL2L 214
|
||||||
|
#define DMP_CTRL3H 216
|
||||||
|
#define DMP_CTRL3L 218
|
||||||
|
#define DMP_CTRL4H 220
|
||||||
|
#define DMP_CTRL4L 222
|
||||||
|
#define DMP_CTRLS1 224
|
||||||
|
#define DMP_CTRLSF1 226
|
||||||
|
#define DMP_CTRLS2 228
|
||||||
|
#define DMP_CTRLSF2 230
|
||||||
|
#define DMP_CTRLS3 232
|
||||||
|
#define DMP_CTRLSFNLL 234
|
||||||
|
#define DMP_CTRLS4 236
|
||||||
|
#define DMP_CTRLSFNL2 238
|
||||||
|
#define DMP_CTRLSFNL 240
|
||||||
|
#define DMP_TMP30 242
|
||||||
|
#define DMP_CTRLSFJT 244
|
||||||
|
#define DMP_TMP31 246
|
||||||
|
#define DMP_TMP11 248
|
||||||
|
#define DMP_CTRLSF2_2 250
|
||||||
|
#define DMP_TMP12 252
|
||||||
|
#define DMP_CTRLSF1_2 254
|
||||||
|
#define DMP_PREVPTAT 256
|
||||||
|
#define DMP_ACCZB 258
|
||||||
|
#define DMP_ACCXB 264
|
||||||
|
#define DMP_ACCYB 266
|
||||||
|
#define DMP_1HB 272
|
||||||
|
#define DMP_1LB 274
|
||||||
|
#define DMP_0H 276
|
||||||
|
#define DMP_0L 278
|
||||||
|
#define DMP_ASR22H 280
|
||||||
|
#define DMP_ASR22L 282
|
||||||
|
#define DMP_ASR6H 284
|
||||||
|
#define DMP_ASR6L 286
|
||||||
|
#define DMP_TMP13 288
|
||||||
|
#define DMP_TMP14 290
|
||||||
|
#define DMP_FINTXH 292
|
||||||
|
#define DMP_FINTXL 294
|
||||||
|
#define DMP_FINTYH 296
|
||||||
|
#define DMP_FINTYL 298
|
||||||
|
#define DMP_FINTZH 300
|
||||||
|
#define DMP_FINTZL 302
|
||||||
|
#define DMP_TMP1BH 304
|
||||||
|
#define DMP_TMP1BL 306
|
||||||
|
#define DMP_TMP2BH 308
|
||||||
|
#define DMP_TMP2BL 310
|
||||||
|
#define DMP_TMP3BH 312
|
||||||
|
#define DMP_TMP3BL 314
|
||||||
|
#define DMP_TMP4BH 316
|
||||||
|
#define DMP_TMP4BL 318
|
||||||
|
#define DMP_STXG 320
|
||||||
|
#define DMP_ZCTXG 322
|
||||||
|
#define DMP_STYG 324
|
||||||
|
#define DMP_ZCTYG 326
|
||||||
|
#define DMP_STZG 328
|
||||||
|
#define DMP_ZCTZG 330
|
||||||
|
#define DMP_CTRLSFJT2 332
|
||||||
|
#define DMP_CTRLSFJTCNT 334
|
||||||
|
#define DMP_PVXG 336
|
||||||
|
#define DMP_TMP15 338
|
||||||
|
#define DMP_PVYG 340
|
||||||
|
#define DMP_TMP16 342
|
||||||
|
#define DMP_PVZG 344
|
||||||
|
#define DMP_TMP17 346
|
||||||
|
#define DMP_MNMFLAGH 352
|
||||||
|
#define DMP_MNMFLAGL 354
|
||||||
|
#define DMP_MNMTMH 356
|
||||||
|
#define DMP_MNMTML 358
|
||||||
|
#define DMP_MNMTMTHRH 360
|
||||||
|
#define DMP_MNMTMTHRL 362
|
||||||
|
#define DMP_MNMTHRH 364
|
||||||
|
#define DMP_MNMTHRL 366
|
||||||
|
#define DMP_ACCQD4H 368
|
||||||
|
#define DMP_ACCQD4L 370
|
||||||
|
#define DMP_ACCQD5H 372
|
||||||
|
#define DMP_ACCQD5L 374
|
||||||
|
#define DMP_ACCQD6H 376
|
||||||
|
#define DMP_ACCQD6L 378
|
||||||
|
#define DMP_ACCQD7H 380
|
||||||
|
#define DMP_ACCQD7L 382
|
||||||
|
#define DMP_ACCQD0H 384
|
||||||
|
#define DMP_ACCQD0L 386
|
||||||
|
#define DMP_ACCQD1H 388
|
||||||
|
#define DMP_ACCQD1L 390
|
||||||
|
#define DMP_ACCQD2H 392
|
||||||
|
#define DMP_ACCQD2L 394
|
||||||
|
#define DMP_ACCQD3H 396
|
||||||
|
#define DMP_ACCQD3L 398
|
||||||
|
#define DMP_XN2H 400
|
||||||
|
#define DMP_XN2L 402
|
||||||
|
#define DMP_XN1H 404
|
||||||
|
#define DMP_XN1L 406
|
||||||
|
#define DMP_YN2H 408
|
||||||
|
#define DMP_YN2L 410
|
||||||
|
#define DMP_YN1H 412
|
||||||
|
#define DMP_YN1L 414
|
||||||
|
#define DMP_YH 416
|
||||||
|
#define DMP_YL 418
|
||||||
|
#define DMP_B0H 420
|
||||||
|
#define DMP_B0L 422
|
||||||
|
#define DMP_A1H 424
|
||||||
|
#define DMP_A1L 426
|
||||||
|
#define DMP_A2H 428
|
||||||
|
#define DMP_A2L 430
|
||||||
|
#define DMP_SEM1 432
|
||||||
|
#define DMP_FIFOCNT 434
|
||||||
|
#define DMP_SH_TH_X 436
|
||||||
|
#define DMP_PACKET 438
|
||||||
|
#define DMP_SH_TH_Y 440
|
||||||
|
#define DMP_FOOTER 442
|
||||||
|
#define DMP_SH_TH_Z 444
|
||||||
|
#define DMP_TEMP29 448
|
||||||
|
#define DMP_TEMP30 450
|
||||||
|
#define DMP_XACCB_PRE 452
|
||||||
|
#define DMP_XACCB_PREL 454
|
||||||
|
#define DMP_YACCB_PRE 456
|
||||||
|
#define DMP_YACCB_PREL 458
|
||||||
|
#define DMP_ZACCB_PRE 460
|
||||||
|
#define DMP_ZACCB_PREL 462
|
||||||
|
#define DMP_TMP22 464
|
||||||
|
#define DMP_TAP_TIMER 466
|
||||||
|
#define DMP_TAP_THX 468
|
||||||
|
#define DMP_TAP_THY 472
|
||||||
|
#define DMP_TAP_THZ 476
|
||||||
|
#define DMP_TAPW_MIN 478
|
||||||
|
#define DMP_TMP25 480
|
||||||
|
#define DMP_TMP26 482
|
||||||
|
#define DMP_TMP27 484
|
||||||
|
#define DMP_TMP28 486
|
||||||
|
#define DMP_ORIENT 488
|
||||||
|
#define DMP_THRSH 490
|
||||||
|
#define DMP_ENDIANH 492
|
||||||
|
#define DMP_ENDIANL 494
|
||||||
|
#define DMP_BLPFNMTCH 496
|
||||||
|
#define DMP_BLPFNMTCL 498
|
||||||
|
#define DMP_BLPFNMXH 500
|
||||||
|
#define DMP_BLPFNMXL 502
|
||||||
|
#define DMP_BLPFNMYH 504
|
||||||
|
#define DMP_BLPFNMYL 506
|
||||||
|
#define DMP_BLPFNMZH 508
|
||||||
|
#define DMP_BLPFNMZL 510
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif // DMPMAP_H
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,122 @@
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup DRIVERS Sensor Driver Layer
|
||||||
|
* @brief Hardware drivers to communicate with sensors via I2C.
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
* @file inv_mpu.h
|
||||||
|
* @brief An I2C-based driver for Invensense gyroscopes.
|
||||||
|
* @details This driver currently works for the following devices:
|
||||||
|
* MPU6050
|
||||||
|
* MPU6500
|
||||||
|
* MPU9150 (or MPU6050 w/ AK8975 on the auxiliary bus)
|
||||||
|
* MPU9250 (or MPU6500 w/ AK8963 on the auxiliary bus)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _INV_MPU_H_
|
||||||
|
#define _INV_MPU_H_
|
||||||
|
|
||||||
|
#define INV_X_GYRO (0x40)
|
||||||
|
#define INV_Y_GYRO (0x20)
|
||||||
|
#define INV_Z_GYRO (0x10)
|
||||||
|
#define INV_XYZ_GYRO (INV_X_GYRO | INV_Y_GYRO | INV_Z_GYRO)
|
||||||
|
#define INV_XYZ_ACCEL (0x08)
|
||||||
|
#define INV_XYZ_COMPASS (0x01)
|
||||||
|
|
||||||
|
struct int_param_s {
|
||||||
|
//#if defined EMPL_TARGET_MSP430 || defined MOTION_DRIVER_TARGET_MSP430
|
||||||
|
void (*cb)(void);
|
||||||
|
unsigned short pin;
|
||||||
|
unsigned char lp_exit;
|
||||||
|
unsigned char active_low;
|
||||||
|
/*#elif defined EMPL_TARGET_UC3L0
|
||||||
|
unsigned long pin;
|
||||||
|
void (*cb)(volatile void*);
|
||||||
|
void *arg;
|
||||||
|
#endif */
|
||||||
|
};
|
||||||
|
|
||||||
|
#define MPU_INT_STATUS_DATA_READY (0x0001)
|
||||||
|
#define MPU_INT_STATUS_DMP (0x0002)
|
||||||
|
#define MPU_INT_STATUS_PLL_READY (0x0004)
|
||||||
|
#define MPU_INT_STATUS_I2C_MST (0x0008)
|
||||||
|
#define MPU_INT_STATUS_FIFO_OVERFLOW (0x0010)
|
||||||
|
#define MPU_INT_STATUS_ZMOT (0x0020)
|
||||||
|
#define MPU_INT_STATUS_MOT (0x0040)
|
||||||
|
#define MPU_INT_STATUS_FREE_FALL (0x0080)
|
||||||
|
#define MPU_INT_STATUS_DMP_0 (0x0100)
|
||||||
|
#define MPU_INT_STATUS_DMP_1 (0x0200)
|
||||||
|
#define MPU_INT_STATUS_DMP_2 (0x0400)
|
||||||
|
#define MPU_INT_STATUS_DMP_3 (0x0800)
|
||||||
|
#define MPU_INT_STATUS_DMP_4 (0x1000)
|
||||||
|
#define MPU_INT_STATUS_DMP_5 (0x2000)
|
||||||
|
|
||||||
|
/* Set up APIs */
|
||||||
|
int mpu_init(void);
|
||||||
|
int mpu_init_slave(void);
|
||||||
|
int mpu_set_bypass(unsigned char bypass_on);
|
||||||
|
|
||||||
|
/* Configuration APIs */
|
||||||
|
int mpu_lp_accel_mode(unsigned char rate);
|
||||||
|
int mpu_lp_motion_interrupt(unsigned short thresh, unsigned char time,
|
||||||
|
unsigned char lpa_freq);
|
||||||
|
int mpu_set_int_level(unsigned char active_low);
|
||||||
|
int mpu_set_int_latched(unsigned char enable);
|
||||||
|
|
||||||
|
int mpu_set_dmp_state(unsigned char enable);
|
||||||
|
int mpu_get_dmp_state(unsigned char *enabled);
|
||||||
|
|
||||||
|
int mpu_get_lpf(unsigned short *lpf);
|
||||||
|
int mpu_set_lpf(unsigned short lpf);
|
||||||
|
|
||||||
|
int mpu_get_gyro_fsr(unsigned short *fsr);
|
||||||
|
int mpu_set_gyro_fsr(unsigned short fsr);
|
||||||
|
|
||||||
|
int mpu_get_accel_fsr(unsigned char *fsr);
|
||||||
|
int mpu_set_accel_fsr(unsigned char fsr);
|
||||||
|
|
||||||
|
int mpu_get_compass_fsr(unsigned short *fsr);
|
||||||
|
|
||||||
|
int mpu_get_gyro_sens(float *sens);
|
||||||
|
int mpu_get_accel_sens(unsigned short *sens);
|
||||||
|
|
||||||
|
int mpu_get_sample_rate(unsigned short *rate);
|
||||||
|
int mpu_set_sample_rate(unsigned short rate);
|
||||||
|
int mpu_get_compass_sample_rate(unsigned short *rate);
|
||||||
|
int mpu_set_compass_sample_rate(unsigned short rate);
|
||||||
|
|
||||||
|
int mpu_get_fifo_config(unsigned char *sensors);
|
||||||
|
int mpu_configure_fifo(unsigned char sensors);
|
||||||
|
|
||||||
|
int mpu_get_power_state(unsigned char *power_on);
|
||||||
|
int mpu_set_sensors(unsigned char sensors);
|
||||||
|
|
||||||
|
int mpu_set_accel_bias(const long *accel_bias);
|
||||||
|
|
||||||
|
/* Data getter/setter APIs */
|
||||||
|
int mpu_get_gyro_reg(short *data, unsigned long *timestamp);
|
||||||
|
int mpu_get_accel_reg(short *data, unsigned long *timestamp);
|
||||||
|
int mpu_get_compass_reg(short *data, unsigned long *timestamp);
|
||||||
|
int mpu_get_temperature(long *data, unsigned long *timestamp);
|
||||||
|
|
||||||
|
int mpu_get_int_status(short *status);
|
||||||
|
int mpu_read_fifo(short *gyro, short *accel, unsigned long *timestamp,
|
||||||
|
unsigned char *sensors, unsigned char *more);
|
||||||
|
int mpu_read_fifo_stream(unsigned short length, unsigned char *data,
|
||||||
|
unsigned char *more);
|
||||||
|
int mpu_reset_fifo(void);
|
||||||
|
|
||||||
|
int mpu_write_mem(unsigned short mem_addr, unsigned short length,
|
||||||
|
unsigned char *data);
|
||||||
|
int mpu_read_mem(unsigned short mem_addr, unsigned short length,
|
||||||
|
unsigned char *data);
|
||||||
|
int mpu_load_firmware(unsigned short length, const unsigned char *firmware,
|
||||||
|
unsigned short start_addr, unsigned short sample_rate);
|
||||||
|
|
||||||
|
int mpu_reg_dump(void);
|
||||||
|
int mpu_read_reg(unsigned char reg, unsigned char *data);
|
||||||
|
int mpu_run_self_test(long *gyro, long *accel);
|
||||||
|
int mpu_register_tap_cb(void (*func)(unsigned char, unsigned char));
|
||||||
|
void myget_ms(unsigned long *time);
|
||||||
|
#endif /* #ifndef _INV_MPU_H_ */
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,92 @@
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup DRIVERS Sensor Driver Layer
|
||||||
|
* @brief Hardware drivers to communicate with sensors via I2C.
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
* @file inv_mpu_dmp_motion_driver.h
|
||||||
|
* @brief DMP image and interface functions.
|
||||||
|
* @details All functions are preceded by the dmp_ prefix to
|
||||||
|
* differentiate among MPL and general driver function calls.
|
||||||
|
*/
|
||||||
|
#ifndef _INV_MPU_DMP_MOTION_DRIVER_H_
|
||||||
|
#define _INV_MPU_DMP_MOTION_DRIVER_H_
|
||||||
|
|
||||||
|
#define TAP_X (0x01)
|
||||||
|
#define TAP_Y (0x02)
|
||||||
|
#define TAP_Z (0x04)
|
||||||
|
#define TAP_XYZ (0x07)
|
||||||
|
|
||||||
|
#define TAP_X_UP (0x01)
|
||||||
|
#define TAP_X_DOWN (0x02)
|
||||||
|
#define TAP_Y_UP (0x03)
|
||||||
|
#define TAP_Y_DOWN (0x04)
|
||||||
|
#define TAP_Z_UP (0x05)
|
||||||
|
#define TAP_Z_DOWN (0x06)
|
||||||
|
|
||||||
|
#define ANDROID_ORIENT_PORTRAIT (0x00)
|
||||||
|
#define ANDROID_ORIENT_LANDSCAPE (0x01)
|
||||||
|
#define ANDROID_ORIENT_REVERSE_PORTRAIT (0x02)
|
||||||
|
#define ANDROID_ORIENT_REVERSE_LANDSCAPE (0x03)
|
||||||
|
|
||||||
|
#define DMP_INT_GESTURE (0x01)
|
||||||
|
#define DMP_INT_CONTINUOUS (0x02)
|
||||||
|
|
||||||
|
#define DMP_FEATURE_TAP (0x001)
|
||||||
|
#define DMP_FEATURE_ANDROID_ORIENT (0x002)
|
||||||
|
#define DMP_FEATURE_LP_QUAT (0x004)
|
||||||
|
#define DMP_FEATURE_PEDOMETER (0x008)
|
||||||
|
#define DMP_FEATURE_6X_LP_QUAT (0x010)
|
||||||
|
#define DMP_FEATURE_GYRO_CAL (0x020)
|
||||||
|
#define DMP_FEATURE_SEND_RAW_ACCEL (0x040)
|
||||||
|
#define DMP_FEATURE_SEND_RAW_GYRO (0x080)
|
||||||
|
#define DMP_FEATURE_SEND_CAL_GYRO (0x100)
|
||||||
|
|
||||||
|
#define INV_WXYZ_QUAT (0x100)
|
||||||
|
|
||||||
|
/* Set up functions. */
|
||||||
|
int dmp_load_motion_driver_firmware(void);
|
||||||
|
int dmp_set_fifo_rate(unsigned short rate);
|
||||||
|
int dmp_get_fifo_rate(unsigned short *rate);
|
||||||
|
int dmp_enable_feature(unsigned short mask);
|
||||||
|
int dmp_get_enabled_features(unsigned short *mask);
|
||||||
|
int dmp_set_interrupt_mode(unsigned char mode);
|
||||||
|
int dmp_set_orientation(unsigned short orient);
|
||||||
|
int dmp_set_gyro_bias(long *bias);
|
||||||
|
int dmp_set_accel_bias(long *bias);
|
||||||
|
|
||||||
|
/* Tap functions. */
|
||||||
|
int dmp_register_tap_cb(void (*func)(unsigned char, unsigned char));
|
||||||
|
int dmp_set_tap_thresh(unsigned char axis, unsigned short thresh);
|
||||||
|
int dmp_set_tap_axes(unsigned char axis);
|
||||||
|
int dmp_set_tap_count(unsigned char min_taps);
|
||||||
|
int dmp_set_tap_time(unsigned short time);
|
||||||
|
int dmp_set_tap_time_multi(unsigned short time);
|
||||||
|
int dmp_set_shake_reject_thresh(long sf, unsigned short thresh);
|
||||||
|
int dmp_set_shake_reject_time(unsigned short time);
|
||||||
|
int dmp_set_shake_reject_timeout(unsigned short time);
|
||||||
|
|
||||||
|
/* Android orientation functions. */
|
||||||
|
int dmp_register_android_orient_cb(void (*func)(unsigned char));
|
||||||
|
|
||||||
|
/* LP quaternion functions. */
|
||||||
|
int dmp_enable_lp_quat(unsigned char enable);
|
||||||
|
int dmp_enable_6x_lp_quat(unsigned char enable);
|
||||||
|
|
||||||
|
/* Pedometer functions. */
|
||||||
|
int dmp_get_pedometer_step_count(unsigned long *count);
|
||||||
|
int dmp_set_pedometer_step_count(unsigned long count);
|
||||||
|
int dmp_get_pedometer_walk_time(unsigned long *time);
|
||||||
|
int dmp_set_pedometer_walk_time(unsigned long time);
|
||||||
|
|
||||||
|
/* DMP gyro calibration functions. */
|
||||||
|
int dmp_enable_gyro_cal(unsigned char enable);
|
||||||
|
|
||||||
|
/* Read function. This function should be called whenever the MPU interrupt is
|
||||||
|
* detected.
|
||||||
|
*/
|
||||||
|
int dmp_read_fifo(short *gyro, short *accel, long *quat,
|
||||||
|
unsigned long *timestamp, short *sensors, unsigned char *more);
|
||||||
|
|
||||||
|
#endif /* #ifndef _INV_MPU_DMP_MOTION_DRIVER_H_ */
|
||||||
|
|
||||||
|
|
@ -0,0 +1,90 @@
|
||||||
|
|
||||||
|
#include "DataScope_DP.h"
|
||||||
|
/**************************************************************************
|
||||||
|
作者：平衡小车之家
|
||||||
|
我的淘宝小店：http://shop114407458.taobao.com/
|
||||||
|
**************************************************************************/
|
||||||
|
unsigned char DataScope_OutPut_Buffer[42] = {0}; //串口发送缓冲区
|
||||||
|
|
||||||
|
|
||||||
|
//函数说明：将单精度浮点数据转成4字节数据并存入指定地址
|
||||||
|
//附加说明：用户无需直接操作此函数
|
||||||
|
//target:目标单精度数据
|
||||||
|
//buf:待写入数组
|
||||||
|
//beg:指定从数组第几个元素开始写入
|
||||||
|
//函数无返回
|
||||||
|
void Float2Byte(float *target,unsigned char *buf,unsigned char beg)
|
||||||
|
{
|
||||||
|
unsigned char *point;
|
||||||
|
point = (unsigned char*)target; //得到float的地址
|
||||||
|
buf[beg] = point[0];
|
||||||
|
buf[beg+1] = point[1];
|
||||||
|
buf[beg+2] = point[2];
|
||||||
|
buf[beg+3] = point[3];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
//函数说明：将待发送通道的单精度浮点数据写入发送缓冲区
|
||||||
|
//Data：通道数据
|
||||||
|
//Channel：选择通道（1-10）
|
||||||
|
//函数无返回
|
||||||
|
void DataScope_Get_Channel_Data(float Data,unsigned char Channel)
|
||||||
|
{
|
||||||
|
if ( (Channel > 10) || (Channel == 0) ) return; //通道个数大于10或等于0，直接跳出，不执行函数
|
||||||
|
else
|
||||||
|
{
|
||||||
|
switch (Channel)
|
||||||
|
{
|
||||||
|
case 1: Float2Byte(&Data,DataScope_OutPut_Buffer,1); break;
|
||||||
|
case 2: Float2Byte(&Data,DataScope_OutPut_Buffer,5); break;
|
||||||
|
case 3: Float2Byte(&Data,DataScope_OutPut_Buffer,9); break;
|
||||||
|
case 4: Float2Byte(&Data,DataScope_OutPut_Buffer,13); break;
|
||||||
|
case 5: Float2Byte(&Data,DataScope_OutPut_Buffer,17); break;
|
||||||
|
case 6: Float2Byte(&Data,DataScope_OutPut_Buffer,21); break;
|
||||||
|
case 7: Float2Byte(&Data,DataScope_OutPut_Buffer,25); break;
|
||||||
|
case 8: Float2Byte(&Data,DataScope_OutPut_Buffer,29); break;
|
||||||
|
case 9: Float2Byte(&Data,DataScope_OutPut_Buffer,33); break;
|
||||||
|
case 10: Float2Byte(&Data,DataScope_OutPut_Buffer,37); break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
//函数说明：生成 DataScopeV1.0 能正确识别的帧格式
|
||||||
|
//Channel_Number，需要发送的通道个数
|
||||||
|
//返回发送缓冲区数据个数
|
||||||
|
//返回0表示帧格式生成失败
|
||||||
|
unsigned char DataScope_Data_Generate(unsigned char Channel_Number)
|
||||||
|
{
|
||||||
|
if ( (Channel_Number > 10) || (Channel_Number == 0) ) { return 0; } //通道个数大于10或等于0，直接跳出，不执行函数
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DataScope_OutPut_Buffer[0] = '$'; //帧头
|
||||||
|
|
||||||
|
switch(Channel_Number)
|
||||||
|
{
|
||||||
|
case 1: DataScope_OutPut_Buffer[5] = 5; return 6;
|
||||||
|
case 2: DataScope_OutPut_Buffer[9] = 9; return 10;
|
||||||
|
case 3: DataScope_OutPut_Buffer[13] = 13; return 14;
|
||||||
|
case 4: DataScope_OutPut_Buffer[17] = 17; return 18;
|
||||||
|
case 5: DataScope_OutPut_Buffer[21] = 21; return 22;
|
||||||
|
case 6: DataScope_OutPut_Buffer[25] = 25; return 26;
|
||||||
|
case 7: DataScope_OutPut_Buffer[29] = 29; return 30;
|
||||||
|
case 8: DataScope_OutPut_Buffer[33] = 33; return 34;
|
||||||
|
case 9: DataScope_OutPut_Buffer[37] = 37; return 38;
|
||||||
|
case 10: DataScope_OutPut_Buffer[41] = 41; return 42;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,21 @@
|
||||||
|
/**************************************************************************
|
||||||
|
作者：平衡小车之家
|
||||||
|
我的淘宝小店：http://shop114407458.taobao.com/
|
||||||
|
**************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __DATA_PRTOCOL_H
|
||||||
|
#define __DATA_PRTOCOL_H
|
||||||
|
|
||||||
|
|
||||||
|
extern unsigned char DataScope_OutPut_Buffer[42]; //待发送帧数据缓存区
|
||||||
|
|
||||||
|
|
||||||
|
void DataScope_Get_Channel_Data(float Data,unsigned char Channel); // 写通道数据至 待发送帧数据缓存区
|
||||||
|
|
||||||
|
unsigned char DataScope_Data_Generate(unsigned char Channel_Number); // 发送帧数据生成函数
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,692 @@
|
||||||
|
//#include "MPU6050.h"
|
||||||
|
//#include "IOI2C.h"
|
||||||
|
//#include "usart.h"
|
||||||
|
//#define PRINT_ACCEL (0x01)
|
||||||
|
//#define PRINT_GYRO (0x02)
|
||||||
|
//#define PRINT_QUAT (0x04)
|
||||||
|
//#define ACCEL_ON (0x01)
|
||||||
|
//#define GYRO_ON (0x02)
|
||||||
|
//#define MOTION (0)
|
||||||
|
//#define NO_MOTION (1)
|
||||||
|
//#define DEFAULT_MPU_HZ (200)
|
||||||
|
//#define FLASH_SIZE (512)
|
||||||
|
//#define FLASH_MEM_START ((void*)0x1800)
|
||||||
|
//#define q30 1073741824.0f
|
||||||
|
//short gyro[3], accel[3], sensors;
|
||||||
|
//float Pitch,Roll;
|
||||||
|
//float q0=1.0f,q1=0.0f,q2=0.0f,q3=0.0f;
|
||||||
|
//static signed char gyro_orientation[9] = {-1, 0, 0,
|
||||||
|
// 0,-1, 0,
|
||||||
|
// 0, 0, 1};
|
||||||
|
|
||||||
|
//static unsigned short inv_row_2_scale(const signed char *row)
|
||||||
|
//{
|
||||||
|
// unsigned short b;
|
||||||
|
|
||||||
|
// if (row[0] > 0)
|
||||||
|
// b = 0;
|
||||||
|
// else if (row[0] < 0)
|
||||||
|
// b = 4;
|
||||||
|
// else if (row[1] > 0)
|
||||||
|
// b = 1;
|
||||||
|
// else if (row[1] < 0)
|
||||||
|
// b = 5;
|
||||||
|
// else if (row[2] > 0)
|
||||||
|
// b = 2;
|
||||||
|
// else if (row[2] < 0)
|
||||||
|
// b = 6;
|
||||||
|
// else
|
||||||
|
// b = 7; // error
|
||||||
|
// return b;
|
||||||
|
//}
|
||||||
|
|
||||||
|
|
||||||
|
//static unsigned short inv_orientation_matrix_to_scalar(
|
||||||
|
// const signed char *mtx)
|
||||||
|
//{
|
||||||
|
// unsigned short scalar;
|
||||||
|
// scalar = inv_row_2_scale(mtx);
|
||||||
|
// scalar |= inv_row_2_scale(mtx + 3) << 3;
|
||||||
|
// scalar |= inv_row_2_scale(mtx + 6) << 6;
|
||||||
|
|
||||||
|
|
||||||
|
// return scalar;
|
||||||
|
//}
|
||||||
|
|
||||||
|
//static void run_self_test(void)
|
||||||
|
//{
|
||||||
|
// int result;
|
||||||
|
// long gyro[3], accel[3];
|
||||||
|
|
||||||
|
// result = mpu_run_self_test(gyro, accel);
|
||||||
|
// if (result == 0x7) {
|
||||||
|
// /* Test passed. We can trust the gyro data here, so let's push it down
|
||||||
|
// * to the DMP.
|
||||||
|
// */
|
||||||
|
// float sens;
|
||||||
|
// unsigned short accel_sens;
|
||||||
|
// mpu_get_gyro_sens(&sens);
|
||||||
|
// gyro[0] = (long)(gyro[0] * sens);
|
||||||
|
// gyro[1] = (long)(gyro[1] * sens);
|
||||||
|
// gyro[2] = (long)(gyro[2] * sens);
|
||||||
|
// dmp_set_gyro_bias(gyro);
|
||||||
|
// mpu_get_accel_sens(&accel_sens);
|
||||||
|
// accel[0] *= accel_sens;
|
||||||
|
// accel[1] *= accel_sens;
|
||||||
|
// accel[2] *= accel_sens;
|
||||||
|
// dmp_set_accel_bias(accel);
|
||||||
|
// printf("setting bias succesfully ......\r\n");
|
||||||
|
// }
|
||||||
|
//}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
//uint8_t buffer[14];
|
||||||
|
|
||||||
|
//int16_t MPU6050_FIFO[6][11];
|
||||||
|
//int16_t Gx_offset=0,Gy_offset=0,Gz_offset=0;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: The new ADC data is updated to FIFO array for filtering
|
||||||
|
//Input : ax，ay，az：x，y, z-axis acceleration data；gx，gy，gz：x. Y, z-axis angular acceleration data
|
||||||
|
//Output : none
|
||||||
|
//函数功能：将新的ADC数据更新到 FIFO数组，进行滤波处理
|
||||||
|
//入口参数：ax，ay，az：x，y，z轴加速度数据；gx，gy，gz：x，y，z轴角加速度数据
|
||||||
|
//返回 值：无
|
||||||
|
//**************************************************************************/
|
||||||
|
|
||||||
|
//void MPU6050_newValues(int16_t ax,int16_t ay,int16_t az,int16_t gx,int16_t gy,int16_t gz)
|
||||||
|
//{
|
||||||
|
//unsigned char i ;
|
||||||
|
//int32_t sum=0;
|
||||||
|
//for(i=1;i<10;i++){ //FIFO 操作
|
||||||
|
//MPU6050_FIFO[0][i-1]=MPU6050_FIFO[0][i];
|
||||||
|
//MPU6050_FIFO[1][i-1]=MPU6050_FIFO[1][i];
|
||||||
|
//MPU6050_FIFO[2][i-1]=MPU6050_FIFO[2][i];
|
||||||
|
//MPU6050_FIFO[3][i-1]=MPU6050_FIFO[3][i];
|
||||||
|
//MPU6050_FIFO[4][i-1]=MPU6050_FIFO[4][i];
|
||||||
|
//MPU6050_FIFO[5][i-1]=MPU6050_FIFO[5][i];
|
||||||
|
//}
|
||||||
|
//MPU6050_FIFO[0][9]=ax;//将新的数据放置到 数据的最后面
|
||||||
|
//MPU6050_FIFO[1][9]=ay;
|
||||||
|
//MPU6050_FIFO[2][9]=az;
|
||||||
|
//MPU6050_FIFO[3][9]=gx;
|
||||||
|
//MPU6050_FIFO[4][9]=gy;
|
||||||
|
//MPU6050_FIFO[5][9]=gz;
|
||||||
|
|
||||||
|
//sum=0;
|
||||||
|
//for(i=0;i<10;i++){ //求当前数组的合，再取平均值
|
||||||
|
// sum+=MPU6050_FIFO[0][i];
|
||||||
|
//}
|
||||||
|
//MPU6050_FIFO[0][10]=sum/10;
|
||||||
|
|
||||||
|
//sum=0;
|
||||||
|
//for(i=0;i<10;i++){
|
||||||
|
// sum+=MPU6050_FIFO[1][i];
|
||||||
|
//}
|
||||||
|
//MPU6050_FIFO[1][10]=sum/10;
|
||||||
|
|
||||||
|
//sum=0;
|
||||||
|
//for(i=0;i<10;i++){
|
||||||
|
// sum+=MPU6050_FIFO[2][i];
|
||||||
|
//}
|
||||||
|
//MPU6050_FIFO[2][10]=sum/10;
|
||||||
|
|
||||||
|
//sum=0;
|
||||||
|
//for(i=0;i<10;i++){
|
||||||
|
// sum+=MPU6050_FIFO[3][i];
|
||||||
|
//}
|
||||||
|
//MPU6050_FIFO[3][10]=sum/10;
|
||||||
|
|
||||||
|
//sum=0;
|
||||||
|
//for(i=0;i<10;i++){
|
||||||
|
// sum+=MPU6050_FIFO[4][i];
|
||||||
|
//}
|
||||||
|
//MPU6050_FIFO[4][10]=sum/10;
|
||||||
|
|
||||||
|
//sum=0;
|
||||||
|
//for(i=0;i<10;i++){
|
||||||
|
// sum+=MPU6050_FIFO[5][i];
|
||||||
|
//}
|
||||||
|
//MPU6050_FIFO[5][10]=sum/10;
|
||||||
|
//}
|
||||||
|
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: Setting the clock source of mpu6050
|
||||||
|
//Input : source：Clock source number
|
||||||
|
//Output : none
|
||||||
|
//函数功能：设置 MPU6050 的时钟源
|
||||||
|
//入口参数：source：时钟源编号
|
||||||
|
//返回 值：无
|
||||||
|
// * CLK_SEL | Clock Source
|
||||||
|
// * --------+--------------------------------------
|
||||||
|
// * 0 | Internal oscillator
|
||||||
|
// * 1 | PLL with X Gyro reference
|
||||||
|
// * 2 | PLL with Y Gyro reference
|
||||||
|
// * 3 | PLL with Z Gyro reference
|
||||||
|
// * 4 | PLL with external 32.768kHz reference
|
||||||
|
// * 5 | PLL with external 19.2MHz reference
|
||||||
|
// * 6 | Reserved
|
||||||
|
// * 7 | Stops the clock and keeps the timing generator in reset
|
||||||
|
//**************************************************************************/
|
||||||
|
//void MPU6050_setClockSource(uint8_t source){
|
||||||
|
// IICwriteBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, source);
|
||||||
|
|
||||||
|
//}
|
||||||
|
|
||||||
|
///** Set full-scale gyroscope range.
|
||||||
|
// * @param range New full-scale gyroscope range value
|
||||||
|
// * @see getFullScaleRange()
|
||||||
|
// * @see MPU6050_GYRO_FS_250
|
||||||
|
// * @see MPU6050_RA_GYRO_CONFIG
|
||||||
|
// * @see MPU6050_GCONFIG_FS_SEL_BIT
|
||||||
|
// * @see MPU6050_GCONFIG_FS_SEL_LENGTH
|
||||||
|
// */
|
||||||
|
//void MPU6050_setFullScaleGyroRange(uint8_t range) {
|
||||||
|
// IICwriteBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH, range);
|
||||||
|
//}
|
||||||
|
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: Setting the maximum range of mpu6050 accelerometer
|
||||||
|
//Input : range：Acceleration maximum range number
|
||||||
|
//Output : none
|
||||||
|
//函数功能：设置 MPU6050 加速度计的最大量程
|
||||||
|
//入口参数：range：加速度最大量程编号
|
||||||
|
//返回 值：无
|
||||||
|
//**************************************************************************/
|
||||||
|
////#define MPU6050_ACCEL_FS_2 0x00 //===最大量程+-2G
|
||||||
|
////#define MPU6050_ACCEL_FS_4 0x01 //===最大量程+-4G
|
||||||
|
////#define MPU6050_ACCEL_FS_8 0x02 //===最大量程+-8G
|
||||||
|
////#define MPU6050_ACCEL_FS_16 0x03 //===最大量程+-16G
|
||||||
|
//void MPU6050_setFullScaleAccelRange(uint8_t range) {
|
||||||
|
// IICwriteBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH, range);
|
||||||
|
//}
|
||||||
|
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: Set mpu6050 to sleep mode or not
|
||||||
|
//Input : enable：1，sleep；0，work；
|
||||||
|
//Output : none
|
||||||
|
//函数功能：设置 MPU6050 是否进入睡眠模式
|
||||||
|
//入口参数：enable：1，睡觉；0，工作；
|
||||||
|
//返回 值：无
|
||||||
|
//**************************************************************************/
|
||||||
|
//void MPU6050_setSleepEnabled(uint8_t enabled) {
|
||||||
|
// IICwriteBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, enabled);
|
||||||
|
//}
|
||||||
|
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: Read identity
|
||||||
|
//Input : none
|
||||||
|
//Output : 0x68
|
||||||
|
//函数功能：读取 MPU6050 WHO_AM_I 标识
|
||||||
|
//入口参数：无
|
||||||
|
//返回 值：0x68
|
||||||
|
//**************************************************************************/
|
||||||
|
//uint8_t MPU6050_getDeviceID(void) {
|
||||||
|
|
||||||
|
// IICreadBytes(devAddr, MPU6050_RA_WHO_AM_I, 1, buffer);
|
||||||
|
// return buffer[0];
|
||||||
|
//}
|
||||||
|
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: Check whether mpu6050 is connected
|
||||||
|
//Input : none
|
||||||
|
//Output : 1：Connected；0：Not connected
|
||||||
|
//函数功能：检测MPU6050 是否已经连接
|
||||||
|
//入口参数：无
|
||||||
|
//返回 值：1：已连接；0：未连接
|
||||||
|
//**************************************************************************/
|
||||||
|
//uint8_t MPU6050_testConnection(void) {
|
||||||
|
// if(MPU6050_getDeviceID() == 0x68) //0b01101000;
|
||||||
|
// return 1;
|
||||||
|
// else return 0;
|
||||||
|
//}
|
||||||
|
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: Setting whether mpu6050 is the host of aux I2C cable
|
||||||
|
//Input : enable：1，yes；0;not
|
||||||
|
//Output : none
|
||||||
|
//函数功能：设置 MPU6050 是否为AUX I2C线的主机
|
||||||
|
//入口参数：enable：1，是；0：否
|
||||||
|
//返回 值：无
|
||||||
|
//**************************************************************************/
|
||||||
|
//void MPU6050_setI2CMasterModeEnabled(uint8_t enabled) {
|
||||||
|
// IICwriteBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, enabled);
|
||||||
|
//}
|
||||||
|
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: Setting whether mpu6050 is the host of aux I2C cable
|
||||||
|
//Input : enable：1，yes；0;not
|
||||||
|
//Output : none
|
||||||
|
//函数功能：设置 MPU6050 是否为AUX I2C线的主机
|
||||||
|
//入口参数：enable：1，是；0：否
|
||||||
|
//返回 值：无
|
||||||
|
//**************************************************************************/
|
||||||
|
//void MPU6050_setI2CBypassEnabled(uint8_t enabled) {
|
||||||
|
// IICwriteBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, enabled);
|
||||||
|
//}
|
||||||
|
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: initialization Mpu6050 to enter the available state
|
||||||
|
//Input : none
|
||||||
|
//Output : none
|
||||||
|
//函数功能：初始化 MPU6050 以进入可用状态
|
||||||
|
//入口参数：无
|
||||||
|
//返回 值：无
|
||||||
|
//**************************************************************************/
|
||||||
|
//void MPU6050_initialize(void) {
|
||||||
|
// MPU6050_setClockSource(MPU6050_CLOCK_PLL_YGYRO); //设置时钟
|
||||||
|
// MPU6050_setFullScaleGyroRange(MPU6050_GYRO_FS_2000);//陀螺仪量程设置
|
||||||
|
// MPU6050_setFullScaleAccelRange(MPU6050_ACCEL_FS_2); //加速度度最大量程 +-2G
|
||||||
|
// MPU6050_setSleepEnabled(0); //进入工作状态
|
||||||
|
// MPU6050_setI2CMasterModeEnabled(0); //不让MPU6050 控制AUXI2C
|
||||||
|
// MPU6050_setI2CBypassEnabled(0); //主控制器的I2C与 MPU6050的AUXI2C 直通关闭
|
||||||
|
//}
|
||||||
|
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: Initialization of DMP in mpu6050
|
||||||
|
//Input : none
|
||||||
|
//Output : none
|
||||||
|
//函数功能：MPU6050内置DMP的初始化
|
||||||
|
//入口参数：无
|
||||||
|
//返回 值：无
|
||||||
|
//**************************************************************************/
|
||||||
|
//void DMP_Init(void)
|
||||||
|
//{
|
||||||
|
// u8 temp[1]={0};
|
||||||
|
// i2cRead(0x68,0x75,1,temp);
|
||||||
|
// printf("mpu_set_sensor complete ......\r\n");
|
||||||
|
// if(temp[0]!=0x68)NVIC_SystemReset();
|
||||||
|
// if(!mpu_init())
|
||||||
|
// {
|
||||||
|
// if(!mpu_set_sensors(INV_XYZ_GYRO | INV_XYZ_ACCEL))
|
||||||
|
// printf("mpu_set_sensor complete ......\r\n");
|
||||||
|
// if(!mpu_configure_fifo(INV_XYZ_GYRO | INV_XYZ_ACCEL))
|
||||||
|
// printf("mpu_configure_fifo complete ......\r\n");
|
||||||
|
// if(!mpu_set_sample_rate(DEFAULT_MPU_HZ))
|
||||||
|
// printf("mpu_set_sample_rate complete ......\r\n");
|
||||||
|
// if(!dmp_load_motion_driver_firmware())
|
||||||
|
// printf("dmp_load_motion_driver_firmware complete ......\r\n");
|
||||||
|
// if(!dmp_set_orientation(inv_orientation_matrix_to_scalar(gyro_orientation)))
|
||||||
|
// printf("dmp_set_orientation complete ......\r\n");
|
||||||
|
// if(!dmp_enable_feature(DMP_FEATURE_6X_LP_QUAT | DMP_FEATURE_TAP |
|
||||||
|
// DMP_FEATURE_ANDROID_ORIENT | DMP_FEATURE_SEND_RAW_ACCEL | DMP_FEATURE_SEND_CAL_GYRO |
|
||||||
|
// DMP_FEATURE_GYRO_CAL))
|
||||||
|
// printf("dmp_enable_feature complete ......\r\n");
|
||||||
|
// if(!dmp_set_fifo_rate(DEFAULT_MPU_HZ))
|
||||||
|
// printf("dmp_set_fifo_rate complete ......\r\n");
|
||||||
|
// run_self_test();
|
||||||
|
// if(!mpu_set_dmp_state(1))
|
||||||
|
// printf("mpu_set_dmp_state complete ......\r\n");
|
||||||
|
// }
|
||||||
|
//}
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: Read the attitude information of DMP in mpu6050
|
||||||
|
//Input : none
|
||||||
|
//Output : none
|
||||||
|
//函数功能：读取MPU6050内置DMP的姿态信息
|
||||||
|
//入口参数：无
|
||||||
|
//返回 值：无
|
||||||
|
//**************************************************************************/
|
||||||
|
//void Read_DMP(void)
|
||||||
|
//{
|
||||||
|
// unsigned long sensor_timestamp;
|
||||||
|
// unsigned char more;
|
||||||
|
// long quat[4];
|
||||||
|
|
||||||
|
// dmp_read_fifo(gyro, accel, quat, &sensor_timestamp, &sensors, &more); //读取DMP数据
|
||||||
|
// if (sensors & INV_WXYZ_QUAT )
|
||||||
|
// {
|
||||||
|
// q0=quat[0] / q30;
|
||||||
|
// q1=quat[1] / q30;
|
||||||
|
// q2=quat[2] / q30;
|
||||||
|
// q3=quat[3] / q30; //四元数
|
||||||
|
// Pitch = asin(-2 * q1 * q3 + 2 * q0* q2)* 57.3; //计算出俯仰角
|
||||||
|
// Roll = atan2(2 * q2 * q3 + 2 * q0 * q1, -2 * q1 * q1 - 2 * q2* q2 + 1)* 57.3; // 计算出横滚角
|
||||||
|
// }
|
||||||
|
|
||||||
|
//}
|
||||||
|
///**************************************************************************
|
||||||
|
//Function: Read mpu6050 built-in temperature sensor data
|
||||||
|
//Input : none
|
||||||
|
//Output : Centigrade temperature
|
||||||
|
//函数功能：读取MPU6050内置温度传感器数据
|
||||||
|
//入口参数：无
|
||||||
|
//返回 值：摄氏温度
|
||||||
|
//**************************************************************************/
|
||||||
|
//int Read_Temperature(void)
|
||||||
|
//{
|
||||||
|
// float Temp;
|
||||||
|
// Temp=(I2C_ReadOneByte(devAddr,MPU6050_RA_TEMP_OUT_H)<<8)+I2C_ReadOneByte(devAddr,MPU6050_RA_TEMP_OUT_L);
|
||||||
|
// if(Temp>32768) Temp-=65536;
|
||||||
|
// Temp=(36.53+Temp/340)*10; //温度放大十倍存放
|
||||||
|
// return (int)Temp;
|
||||||
|
//}
|
||||||
|
////------------------End of File----------------------------
|
||||||
|
#include "MPU6050.h"
|
||||||
|
#include "IOI2C.h"
|
||||||
|
#include "usart.h"
|
||||||
|
#define PRINT_ACCEL (0x01)
|
||||||
|
#define PRINT_GYRO (0x02)
|
||||||
|
#define PRINT_QUAT (0x04)
|
||||||
|
#define ACCEL_ON (0x01)
|
||||||
|
#define GYRO_ON (0x02)
|
||||||
|
#define MOTION (0)
|
||||||
|
#define NO_MOTION (1)
|
||||||
|
#define DEFAULT_MPU_HZ (200)
|
||||||
|
#define FLASH_SIZE (512)
|
||||||
|
#define FLASH_MEM_START ((void*)0x1800)
|
||||||
|
#define q30 1073741824.0f
|
||||||
|
short gyro[3], accel[3], sensors;
|
||||||
|
float Pitch,Roll;
|
||||||
|
float q0=1.0f,q1=0.0f,q2=0.0f,q3=0.0f;
|
||||||
|
static signed char gyro_orientation[9] = {-1, 0, 0,
|
||||||
|
0,-1, 0,
|
||||||
|
0, 0, 1};
|
||||||
|
|
||||||
|
static unsigned short inv_row_2_scale(const signed char *row)
|
||||||
|
{
|
||||||
|
unsigned short b;
|
||||||
|
|
||||||
|
if (row[0] > 0)
|
||||||
|
b = 0;
|
||||||
|
else if (row[0] < 0)
|
||||||
|
b = 4;
|
||||||
|
else if (row[1] > 0)
|
||||||
|
b = 1;
|
||||||
|
else if (row[1] < 0)
|
||||||
|
b = 5;
|
||||||
|
else if (row[2] > 0)
|
||||||
|
b = 2;
|
||||||
|
else if (row[2] < 0)
|
||||||
|
b = 6;
|
||||||
|
else
|
||||||
|
b = 7; // error
|
||||||
|
return b;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static unsigned short inv_orientation_matrix_to_scalar(
|
||||||
|
const signed char *mtx)
|
||||||
|
{
|
||||||
|
unsigned short scalar;
|
||||||
|
scalar = inv_row_2_scale(mtx);
|
||||||
|
scalar |= inv_row_2_scale(mtx + 3) << 3;
|
||||||
|
scalar |= inv_row_2_scale(mtx + 6) << 6;
|
||||||
|
|
||||||
|
|
||||||
|
return scalar;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void run_self_test(void)
|
||||||
|
{
|
||||||
|
int result;
|
||||||
|
long gyro[3], accel[3];
|
||||||
|
|
||||||
|
result = mpu_run_self_test(gyro, accel);
|
||||||
|
if (result == 0x7) {
|
||||||
|
/* Test passed. We can trust the gyro data here, so let's push it down
|
||||||
|
* to the DMP.
|
||||||
|
*/
|
||||||
|
float sens;
|
||||||
|
unsigned short accel_sens;
|
||||||
|
mpu_get_gyro_sens(&sens);
|
||||||
|
gyro[0] = (long)(gyro[0] * sens);
|
||||||
|
gyro[1] = (long)(gyro[1] * sens);
|
||||||
|
gyro[2] = (long)(gyro[2] * sens);
|
||||||
|
dmp_set_gyro_bias(gyro);
|
||||||
|
mpu_get_accel_sens(&accel_sens);
|
||||||
|
accel[0] *= accel_sens;
|
||||||
|
accel[1] *= accel_sens;
|
||||||
|
accel[2] *= accel_sens;
|
||||||
|
dmp_set_accel_bias(accel);
|
||||||
|
printf("setting bias succesfully ......\r\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
uint8_t buffer[14];
|
||||||
|
|
||||||
|
int16_t MPU6050_FIFO[6][11];
|
||||||
|
int16_t Gx_offset=0,Gy_offset=0,Gz_offset=0;
|
||||||
|
|
||||||
|
|
||||||
|
/**************************实现函数********************************************
|
||||||
|
*函数原型: void MPU6050_newValues(int16_t ax,int16_t ay,int16_t az,int16_t gx,int16_t gy,int16_t gz)
|
||||||
|
*功 能: 将新的ADC数据更新到 FIFO数组，进行滤波处理
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
void MPU6050_newValues(int16_t ax,int16_t ay,int16_t az,int16_t gx,int16_t gy,int16_t gz)
|
||||||
|
{
|
||||||
|
unsigned char i ;
|
||||||
|
int32_t sum=0;
|
||||||
|
for(i=1;i<10;i++){ //FIFO 操作
|
||||||
|
MPU6050_FIFO[0][i-1]=MPU6050_FIFO[0][i];
|
||||||
|
MPU6050_FIFO[1][i-1]=MPU6050_FIFO[1][i];
|
||||||
|
MPU6050_FIFO[2][i-1]=MPU6050_FIFO[2][i];
|
||||||
|
MPU6050_FIFO[3][i-1]=MPU6050_FIFO[3][i];
|
||||||
|
MPU6050_FIFO[4][i-1]=MPU6050_FIFO[4][i];
|
||||||
|
MPU6050_FIFO[5][i-1]=MPU6050_FIFO[5][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[0][9]=ax;//将新的数据放置到 数据的最后面
|
||||||
|
MPU6050_FIFO[1][9]=ay;
|
||||||
|
MPU6050_FIFO[2][9]=az;
|
||||||
|
MPU6050_FIFO[3][9]=gx;
|
||||||
|
MPU6050_FIFO[4][9]=gy;
|
||||||
|
MPU6050_FIFO[5][9]=gz;
|
||||||
|
|
||||||
|
sum=0;
|
||||||
|
for(i=0;i<10;i++){ //求当前数组的合，再取平均值
|
||||||
|
sum+=MPU6050_FIFO[0][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[0][10]=sum/10;
|
||||||
|
|
||||||
|
sum=0;
|
||||||
|
for(i=0;i<10;i++){
|
||||||
|
sum+=MPU6050_FIFO[1][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[1][10]=sum/10;
|
||||||
|
|
||||||
|
sum=0;
|
||||||
|
for(i=0;i<10;i++){
|
||||||
|
sum+=MPU6050_FIFO[2][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[2][10]=sum/10;
|
||||||
|
|
||||||
|
sum=0;
|
||||||
|
for(i=0;i<10;i++){
|
||||||
|
sum+=MPU6050_FIFO[3][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[3][10]=sum/10;
|
||||||
|
|
||||||
|
sum=0;
|
||||||
|
for(i=0;i<10;i++){
|
||||||
|
sum+=MPU6050_FIFO[4][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[4][10]=sum/10;
|
||||||
|
|
||||||
|
sum=0;
|
||||||
|
for(i=0;i<10;i++){
|
||||||
|
sum+=MPU6050_FIFO[5][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[5][10]=sum/10;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************实现函数********************************************
|
||||||
|
*函数原型: void MPU6050_setClockSource(uint8_t source)
|
||||||
|
*功 能: 设置 MPU6050 的时钟源
|
||||||
|
* CLK_SEL | Clock Source
|
||||||
|
* --------+--------------------------------------
|
||||||
|
* 0 | Internal oscillator
|
||||||
|
* 1 | PLL with X Gyro reference
|
||||||
|
* 2 | PLL with Y Gyro reference
|
||||||
|
* 3 | PLL with Z Gyro reference
|
||||||
|
* 4 | PLL with external 32.768kHz reference
|
||||||
|
* 5 | PLL with external 19.2MHz reference
|
||||||
|
* 6 | Reserved
|
||||||
|
* 7 | Stops the clock and keeps the timing generator in reset
|
||||||
|
*******************************************************************************/
|
||||||
|
void MPU6050_setClockSource(uint8_t source){
|
||||||
|
IICwriteBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, source);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Set full-scale gyroscope range.
|
||||||
|
* @param range New full-scale gyroscope range value
|
||||||
|
* @see getFullScaleRange()
|
||||||
|
* @see MPU6050_GYRO_FS_250
|
||||||
|
* @see MPU6050_RA_GYRO_CONFIG
|
||||||
|
* @see MPU6050_GCONFIG_FS_SEL_BIT
|
||||||
|
* @see MPU6050_GCONFIG_FS_SEL_LENGTH
|
||||||
|
*/
|
||||||
|
void MPU6050_setFullScaleGyroRange(uint8_t range) {
|
||||||
|
IICwriteBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH, range);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************实现函数********************************************
|
||||||
|
*函数原型: void MPU6050_setFullScaleAccelRange(uint8_t range)
|
||||||
|
*功 能: 设置 MPU6050 加速度计的最大量程
|
||||||
|
*******************************************************************************/
|
||||||
|
void MPU6050_setFullScaleAccelRange(uint8_t range) {
|
||||||
|
IICwriteBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH, range);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************实现函数********************************************
|
||||||
|
*函数原型: void MPU6050_setSleepEnabled(uint8_t enabled)
|
||||||
|
*功 能: 设置 MPU6050 是否进入睡眠模式
|
||||||
|
enabled =1 睡觉
|
||||||
|
enabled =0 工作
|
||||||
|
*******************************************************************************/
|
||||||
|
void MPU6050_setSleepEnabled(uint8_t enabled) {
|
||||||
|
IICwriteBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, enabled);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************实现函数********************************************
|
||||||
|
*函数原型: uint8_t MPU6050_getDeviceID(void)
|
||||||
|
*功 能: 读取 MPU6050 WHO_AM_I 标识 将返回 0x68
|
||||||
|
*******************************************************************************/
|
||||||
|
uint8_t MPU6050_getDeviceID(void) {
|
||||||
|
|
||||||
|
IICreadBytes(devAddr, MPU6050_RA_WHO_AM_I, 1, buffer);
|
||||||
|
return buffer[0];
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************实现函数********************************************
|
||||||
|
*函数原型: uint8_t MPU6050_testConnection(void)
|
||||||
|
*功 能: 检测MPU6050 是否已经连接
|
||||||
|
*******************************************************************************/
|
||||||
|
uint8_t MPU6050_testConnection(void) {
|
||||||
|
if(MPU6050_getDeviceID() == 0x68) //0b01101000;
|
||||||
|
return 1;
|
||||||
|
else return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************实现函数********************************************
|
||||||
|
*函数原型: void MPU6050_setI2CMasterModeEnabled(uint8_t enabled)
|
||||||
|
*功 能: 设置 MPU6050 是否为AUX I2C线的主机
|
||||||
|
*******************************************************************************/
|
||||||
|
void MPU6050_setI2CMasterModeEnabled(uint8_t enabled) {
|
||||||
|
IICwriteBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, enabled);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************实现函数********************************************
|
||||||
|
*函数原型: void MPU6050_setI2CBypassEnabled(uint8_t enabled)
|
||||||
|
*功 能: 设置 MPU6050 是否为AUX I2C线的主机
|
||||||
|
*******************************************************************************/
|
||||||
|
void MPU6050_setI2CBypassEnabled(uint8_t enabled) {
|
||||||
|
IICwriteBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, enabled);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************实现函数********************************************
|
||||||
|
*函数原型: void MPU6050_initialize(void)
|
||||||
|
*功 能: 初始化 MPU6050 以进入可用状态。
|
||||||
|
*******************************************************************************/
|
||||||
|
void MPU6050_initialize(void) {
|
||||||
|
MPU6050_setClockSource(MPU6050_CLOCK_PLL_YGYRO); //设置时钟
|
||||||
|
MPU6050_setFullScaleGyroRange(MPU6050_GYRO_FS_2000);//陀螺仪量程设置
|
||||||
|
MPU6050_setFullScaleAccelRange(MPU6050_ACCEL_FS_2); //加速度度最大量程 +-2G
|
||||||
|
MPU6050_setSleepEnabled(0); //进入工作状态
|
||||||
|
MPU6050_setI2CMasterModeEnabled(0); //不让MPU6050 控制AUXI2C
|
||||||
|
MPU6050_setI2CBypassEnabled(0); //主控制器的I2C与 MPU6050的AUXI2C 直通关闭
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
函数功能：MPU6050内置DMP的初始化
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
作 者：平衡小车之家
|
||||||
|
**************************************************************************/
|
||||||
|
void DMP_Init(void)
|
||||||
|
{
|
||||||
|
u8 temp[1]={0};
|
||||||
|
i2cRead(0x68,0x75,1,temp);
|
||||||
|
Flag_Show=1;
|
||||||
|
printf("mpu_set_sensor complete ......\r\n");
|
||||||
|
if(temp[0]!=0x68)NVIC_SystemReset();
|
||||||
|
if(!mpu_init())
|
||||||
|
{
|
||||||
|
if(!mpu_set_sensors(INV_XYZ_GYRO | INV_XYZ_ACCEL))
|
||||||
|
printf("mpu_set_sensor complete ......\r\n");
|
||||||
|
if(!mpu_configure_fifo(INV_XYZ_GYRO | INV_XYZ_ACCEL))
|
||||||
|
printf("mpu_configure_fifo complete ......\r\n");
|
||||||
|
if(!mpu_set_sample_rate(DEFAULT_MPU_HZ))
|
||||||
|
printf("mpu_set_sample_rate complete ......\r\n");
|
||||||
|
if(!dmp_load_motion_driver_firmware())
|
||||||
|
printf("dmp_load_motion_driver_firmware complete ......\r\n");
|
||||||
|
if(!dmp_set_orientation(inv_orientation_matrix_to_scalar(gyro_orientation)))
|
||||||
|
printf("dmp_set_orientation complete ......\r\n");
|
||||||
|
if(!dmp_enable_feature(DMP_FEATURE_6X_LP_QUAT | DMP_FEATURE_TAP |
|
||||||
|
DMP_FEATURE_ANDROID_ORIENT | DMP_FEATURE_SEND_RAW_ACCEL | DMP_FEATURE_SEND_CAL_GYRO |
|
||||||
|
DMP_FEATURE_GYRO_CAL))
|
||||||
|
printf("dmp_enable_feature complete ......\r\n");
|
||||||
|
if(!dmp_set_fifo_rate(DEFAULT_MPU_HZ))
|
||||||
|
printf("dmp_set_fifo_rate complete ......\r\n");
|
||||||
|
run_self_test();
|
||||||
|
if(!mpu_set_dmp_state(1))
|
||||||
|
printf("mpu_set_dmp_state complete ......\r\n");
|
||||||
|
}
|
||||||
|
Flag_Show=0;
|
||||||
|
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
函数功能：读取MPU6050内置DMP的姿态信息
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
作 者：平衡小车之家
|
||||||
|
**************************************************************************/
|
||||||
|
void Read_DMP(void)
|
||||||
|
{
|
||||||
|
unsigned long sensor_timestamp;
|
||||||
|
unsigned char more;
|
||||||
|
long quat[4];
|
||||||
|
|
||||||
|
dmp_read_fifo(gyro, accel, quat, &sensor_timestamp, &sensors, &more);
|
||||||
|
if (sensors & INV_WXYZ_QUAT )
|
||||||
|
{
|
||||||
|
q0=quat[0] / q30;
|
||||||
|
q1=quat[1] / q30;
|
||||||
|
q2=quat[2] / q30;
|
||||||
|
q3=quat[3] / q30;
|
||||||
|
Pitch = asin(-2 * q1 * q3 + 2 * q0* q2)* 57.3;
|
||||||
|
Roll = atan2(2 * q2 * q3 + 2 * q0 * q1, -2 * q1 * q1 - 2 * q2* q2 + 1)* 57.3; // roll
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
函数功能：读取MPU6050内置温度传感器数据
|
||||||
|
入口参数：无
|
||||||
|
返回 值：摄氏温度
|
||||||
|
作 者：平衡小车之家
|
||||||
|
**************************************************************************/
|
||||||
|
int Read_Temperature(void)
|
||||||
|
{
|
||||||
|
float Temp;
|
||||||
|
Temp=(I2C_ReadOneByte(devAddr,MPU6050_RA_TEMP_OUT_H)<<8)+I2C_ReadOneByte(devAddr,MPU6050_RA_TEMP_OUT_L);
|
||||||
|
if(Temp>32768) Temp-=65536;
|
||||||
|
Temp=(36.53+Temp/340)*10;
|
||||||
|
return (int)Temp;
|
||||||
|
}
|
||||||
|
//------------------End of File----------------------------
|
||||||
|
|
@ -0,0 +1,375 @@
|
||||||
|
#ifndef __MPU6050_H
|
||||||
|
#define __MPU6050_H
|
||||||
|
/**************************************************************************
|
||||||
|
作者：平衡小车之家
|
||||||
|
我的淘宝小店：http://shop114407458.taobao.com/
|
||||||
|
**************************************************************************/
|
||||||
|
#include "sys.h"
|
||||||
|
#define devAddr 0xD0
|
||||||
|
|
||||||
|
#define MPU6050_ADDRESS_AD0_LOW 0x68 // address pin low (GND), default for InvenSense evaluation board
|
||||||
|
#define MPU6050_ADDRESS_AD0_HIGH 0x69 // address pin high (VCC)
|
||||||
|
#define MPU6050_DEFAULT_ADDRESS MPU6050_ADDRESS_AD0_LOW
|
||||||
|
|
||||||
|
#define MPU6050_RA_XG_OFFS_TC 0x00 //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD
|
||||||
|
#define MPU6050_RA_YG_OFFS_TC 0x01 //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD
|
||||||
|
#define MPU6050_RA_ZG_OFFS_TC 0x02 //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD
|
||||||
|
#define MPU6050_RA_X_FINE_GAIN 0x03 //[7:0] X_FINE_GAIN
|
||||||
|
#define MPU6050_RA_Y_FINE_GAIN 0x04 //[7:0] Y_FINE_GAIN
|
||||||
|
#define MPU6050_RA_Z_FINE_GAIN 0x05 //[7:0] Z_FINE_GAIN
|
||||||
|
#define MPU6050_RA_XA_OFFS_H 0x06 //[15:0] XA_OFFS
|
||||||
|
#define MPU6050_RA_XA_OFFS_L_TC 0x07
|
||||||
|
#define MPU6050_RA_YA_OFFS_H 0x08 //[15:0] YA_OFFS
|
||||||
|
#define MPU6050_RA_YA_OFFS_L_TC 0x09
|
||||||
|
#define MPU6050_RA_ZA_OFFS_H 0x0A //[15:0] ZA_OFFS
|
||||||
|
#define MPU6050_RA_ZA_OFFS_L_TC 0x0B
|
||||||
|
#define MPU6050_RA_XG_OFFS_USRH 0x13 //[15:0] XG_OFFS_USR
|
||||||
|
#define MPU6050_RA_XG_OFFS_USRL 0x14
|
||||||
|
#define MPU6050_RA_YG_OFFS_USRH 0x15 //[15:0] YG_OFFS_USR
|
||||||
|
#define MPU6050_RA_YG_OFFS_USRL 0x16
|
||||||
|
#define MPU6050_RA_ZG_OFFS_USRH 0x17 //[15:0] ZG_OFFS_USR
|
||||||
|
#define MPU6050_RA_ZG_OFFS_USRL 0x18
|
||||||
|
#define MPU6050_RA_SMPLRT_DIV 0x19
|
||||||
|
#define MPU6050_RA_CONFIG 0x1A
|
||||||
|
#define MPU6050_RA_GYRO_CONFIG 0x1B
|
||||||
|
#define MPU6050_RA_ACCEL_CONFIG 0x1C
|
||||||
|
#define MPU6050_RA_FF_THR 0x1D
|
||||||
|
#define MPU6050_RA_FF_DUR 0x1E
|
||||||
|
#define MPU6050_RA_MOT_THR 0x1F
|
||||||
|
#define MPU6050_RA_MOT_DUR 0x20
|
||||||
|
#define MPU6050_RA_ZRMOT_THR 0x21
|
||||||
|
#define MPU6050_RA_ZRMOT_DUR 0x22
|
||||||
|
#define MPU6050_RA_FIFO_EN 0x23
|
||||||
|
#define MPU6050_RA_I2C_MST_CTRL 0x24
|
||||||
|
#define MPU6050_RA_I2C_SLV0_ADDR 0x25
|
||||||
|
#define MPU6050_RA_I2C_SLV0_REG 0x26
|
||||||
|
# define MPU6050_RA_I2C_SLV0_CTRL 0x27
|
||||||
|
#define MPU6050_RA_I2C_SLV1_ADDR 0x28
|
||||||
|
#define MPU6050_RA_I2C_SLV1_REG 0x29
|
||||||
|
#define MPU6050_RA_I2C_SLV1_CTRL 0x2A
|
||||||
|
#define MPU6050_RA_I2C_SLV2_ADDR 0x2B
|
||||||
|
#define MPU6050_RA_I2C_SLV2_REG 0x2C
|
||||||
|
#define MPU6050_RA_I2C_SLV2_CTRL 0x2D
|
||||||
|
#define MPU6050_RA_I2C_SLV3_ADDR 0x2E
|
||||||
|
#define MPU6050_RA_I2C_SLV3_REG 0x2F
|
||||||
|
#define MPU6050_RA_I2C_SLV3_CTRL 0x30
|
||||||
|
#define MPU6050_RA_I2C_SLV4_ADDR 0x31
|
||||||
|
#define MPU6050_RA_I2C_SLV4_REG 0x32
|
||||||
|
#define MPU6050_RA_I2C_SLV4_DO 0x33
|
||||||
|
#define MPU6050_RA_I2C_SLV4_CTRL 0x34
|
||||||
|
#define MPU6050_RA_I2C_SLV4_DI 0x35
|
||||||
|
#define MPU6050_RA_I2C_MST_STATUS 0x36
|
||||||
|
#define MPU6050_RA_INT_PIN_CFG 0x37
|
||||||
|
#define MPU6050_RA_INT_ENABLE 0x38
|
||||||
|
#define MPU6050_RA_DMP_INT_STATUS 0x39
|
||||||
|
#define MPU6050_RA_INT_STATUS 0x3A
|
||||||
|
#define MPU6050_RA_ACCEL_XOUT_H 0x3B
|
||||||
|
#define MPU6050_RA_ACCEL_XOUT_L 0x3C
|
||||||
|
#define MPU6050_RA_ACCEL_YOUT_H 0x3D
|
||||||
|
#define MPU6050_RA_ACCEL_YOUT_L 0x3E
|
||||||
|
#define MPU6050_RA_ACCEL_ZOUT_H 0x3F
|
||||||
|
#define MPU6050_RA_ACCEL_ZOUT_L 0x40
|
||||||
|
#define MPU6050_RA_TEMP_OUT_H 0x41
|
||||||
|
#define MPU6050_RA_TEMP_OUT_L 0x42
|
||||||
|
#define MPU6050_RA_GYRO_XOUT_H 0x43
|
||||||
|
#define MPU6050_RA_GYRO_XOUT_L 0x44
|
||||||
|
#define MPU6050_RA_GYRO_YOUT_H 0x45
|
||||||
|
#define MPU6050_RA_GYRO_YOUT_L 0x46
|
||||||
|
#define MPU6050_RA_GYRO_ZOUT_H 0x47
|
||||||
|
#define MPU6050_RA_GYRO_ZOUT_L 0x48
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_00 0x49
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_01 0x4A
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_02 0x4B
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_03 0x4C
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_04 0x4D
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_05 0x4E
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_06 0x4F
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_07 0x50
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_08 0x51
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_09 0x52
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_10 0x53
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_11 0x54
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_12 0x55
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_13 0x56
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_14 0x57
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_15 0x58
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_16 0x59
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_17 0x5A
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_18 0x5B
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_19 0x5C
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_20 0x5D
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_21 0x5E
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_22 0x5F
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_23 0x60
|
||||||
|
#define MPU6050_RA_MOT_DETECT_STATUS 0x61
|
||||||
|
#define MPU6050_RA_I2C_SLV0_DO 0x63
|
||||||
|
#define MPU6050_RA_I2C_SLV1_DO 0x64
|
||||||
|
#define MPU6050_RA_I2C_SLV2_DO 0x65
|
||||||
|
#define MPU6050_RA_I2C_SLV3_DO 0x66
|
||||||
|
#define MPU6050_RA_I2C_MST_DELAY_CTRL 0x67
|
||||||
|
#define MPU6050_RA_SIGNAL_PATH_RESET 0x68
|
||||||
|
#define MPU6050_RA_MOT_DETECT_CTRL 0x69
|
||||||
|
#define MPU6050_RA_USER_CTRL 0x6A
|
||||||
|
#define MPU6050_RA_PWR_MGMT_1 0x6B
|
||||||
|
#define MPU6050_RA_PWR_MGMT_2 0x6C
|
||||||
|
#define MPU6050_RA_BANK_SEL 0x6D
|
||||||
|
#define MPU6050_RA_MEM_START_ADDR 0x6E
|
||||||
|
#define MPU6050_RA_MEM_R_W 0x6F
|
||||||
|
#define MPU6050_RA_DMP_CFG_1 0x70
|
||||||
|
#define MPU6050_RA_DMP_CFG_2 0x71
|
||||||
|
#define MPU6050_RA_FIFO_COUNTH 0x72
|
||||||
|
#define MPU6050_RA_FIFO_COUNTL 0x73
|
||||||
|
#define MPU6050_RA_FIFO_R_W 0x74
|
||||||
|
#define MPU6050_RA_WHO_AM_I 0x75
|
||||||
|
|
||||||
|
#define MPU6050_TC_PWR_MODE_BIT 7
|
||||||
|
#define MPU6050_TC_OFFSET_BIT 6
|
||||||
|
#define MPU6050_TC_OFFSET_LENGTH 6
|
||||||
|
#define MPU6050_TC_OTP_BNK_VLD_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_VDDIO_LEVEL_VLOGIC 0
|
||||||
|
#define MPU6050_VDDIO_LEVEL_VDD 1
|
||||||
|
|
||||||
|
#define MPU6050_CFG_EXT_SYNC_SET_BIT 5
|
||||||
|
#define MPU6050_CFG_EXT_SYNC_SET_LENGTH 3
|
||||||
|
#define MPU6050_CFG_DLPF_CFG_BIT 2
|
||||||
|
#define MPU6050_CFG_DLPF_CFG_LENGTH 3
|
||||||
|
|
||||||
|
#define MPU6050_EXT_SYNC_DISABLED 0x0
|
||||||
|
#define MPU6050_EXT_SYNC_TEMP_OUT_L 0x1
|
||||||
|
#define MPU6050_EXT_SYNC_GYRO_XOUT_L 0x2
|
||||||
|
#define MPU6050_EXT_SYNC_GYRO_YOUT_L 0x3
|
||||||
|
#define MPU6050_EXT_SYNC_GYRO_ZOUT_L 0x4
|
||||||
|
#define MPU6050_EXT_SYNC_ACCEL_XOUT_L 0x5
|
||||||
|
#define MPU6050_EXT_SYNC_ACCEL_YOUT_L 0x6
|
||||||
|
#define MPU6050_EXT_SYNC_ACCEL_ZOUT_L 0x7
|
||||||
|
|
||||||
|
#define MPU6050_DLPF_BW_256 0x00
|
||||||
|
#define MPU6050_DLPF_BW_188 0x01
|
||||||
|
#define MPU6050_DLPF_BW_98 0x02
|
||||||
|
#define MPU6050_DLPF_BW_42 0x03
|
||||||
|
#define MPU6050_DLPF_BW_20 0x04
|
||||||
|
#define MPU6050_DLPF_BW_10 0x05
|
||||||
|
#define MPU6050_DLPF_BW_5 0x06
|
||||||
|
|
||||||
|
#define MPU6050_GCONFIG_FS_SEL_BIT 4
|
||||||
|
#define MPU6050_GCONFIG_FS_SEL_LENGTH 2
|
||||||
|
|
||||||
|
#define MPU6050_GYRO_FS_250 0x00
|
||||||
|
#define MPU6050_GYRO_FS_500 0x01
|
||||||
|
#define MPU6050_GYRO_FS_1000 0x02
|
||||||
|
#define MPU6050_GYRO_FS_2000 0x03
|
||||||
|
|
||||||
|
#define MPU6050_ACONFIG_XA_ST_BIT 7
|
||||||
|
#define MPU6050_ACONFIG_YA_ST_BIT 6
|
||||||
|
#define MPU6050_ACONFIG_ZA_ST_BIT 5
|
||||||
|
#define MPU6050_ACONFIG_AFS_SEL_BIT 4
|
||||||
|
#define MPU6050_ACONFIG_AFS_SEL_LENGTH 2
|
||||||
|
#define MPU6050_ACONFIG_ACCEL_HPF_BIT 2
|
||||||
|
#define MPU6050_ACONFIG_ACCEL_HPF_LENGTH 3
|
||||||
|
|
||||||
|
#define MPU6050_ACCEL_FS_2 0x00
|
||||||
|
#define MPU6050_ACCEL_FS_4 0x01
|
||||||
|
#define MPU6050_ACCEL_FS_8 0x02
|
||||||
|
#define MPU6050_ACCEL_FS_16 0x03
|
||||||
|
|
||||||
|
#define MPU6050_DHPF_RESET 0x00
|
||||||
|
#define MPU6050_DHPF_5 0x01
|
||||||
|
#define MPU6050_DHPF_2P5 0x02
|
||||||
|
#define MPU6050_DHPF_1P25 0x03
|
||||||
|
#define MPU6050_DHPF_0P63 0x04
|
||||||
|
#define MPU6050_DHPF_HOLD 0x07
|
||||||
|
|
||||||
|
#define MPU6050_TEMP_FIFO_EN_BIT 7
|
||||||
|
#define MPU6050_XG_FIFO_EN_BIT 6
|
||||||
|
#define MPU6050_YG_FIFO_EN_BIT 5
|
||||||
|
#define MPU6050_ZG_FIFO_EN_BIT 4
|
||||||
|
#define MPU6050_ACCEL_FIFO_EN_BIT 3
|
||||||
|
#define MPU6050_SLV2_FIFO_EN_BIT 2
|
||||||
|
#define MPU6050_SLV1_FIFO_EN_BIT 1
|
||||||
|
#define MPU6050_SLV0_FIFO_EN_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_MULT_MST_EN_BIT 7
|
||||||
|
#define MPU6050_WAIT_FOR_ES_BIT 6
|
||||||
|
#define MPU6050_SLV_3_FIFO_EN_BIT 5
|
||||||
|
#define MPU6050_I2C_MST_P_NSR_BIT 4
|
||||||
|
#define MPU6050_I2C_MST_CLK_BIT 3
|
||||||
|
#define MPU6050_I2C_MST_CLK_LENGTH 4
|
||||||
|
|
||||||
|
#define MPU6050_CLOCK_DIV_348 0x0
|
||||||
|
#define MPU6050_CLOCK_DIV_333 0x1
|
||||||
|
#define MPU6050_CLOCK_DIV_320 0x2
|
||||||
|
#define MPU6050_CLOCK_DIV_308 0x3
|
||||||
|
#define MPU6050_CLOCK_DIV_296 0x4
|
||||||
|
#define MPU6050_CLOCK_DIV_286 0x5
|
||||||
|
#define MPU6050_CLOCK_DIV_276 0x6
|
||||||
|
#define MPU6050_CLOCK_DIV_267 0x7
|
||||||
|
#define MPU6050_CLOCK_DIV_258 0x8
|
||||||
|
#define MPU6050_CLOCK_DIV_500 0x9
|
||||||
|
#define MPU6050_CLOCK_DIV_471 0xA
|
||||||
|
#define MPU6050_CLOCK_DIV_444 0xB
|
||||||
|
#define MPU6050_CLOCK_DIV_421 0xC
|
||||||
|
#define MPU6050_CLOCK_DIV_400 0xD
|
||||||
|
#define MPU6050_CLOCK_DIV_381 0xE
|
||||||
|
#define MPU6050_CLOCK_DIV_364 0xF
|
||||||
|
|
||||||
|
#define MPU6050_I2C_SLV_RW_BIT 7
|
||||||
|
#define MPU6050_I2C_SLV_ADDR_BIT 6
|
||||||
|
#define MPU6050_I2C_SLV_ADDR_LENGTH 7
|
||||||
|
#define MPU6050_I2C_SLV_EN_BIT 7
|
||||||
|
#define MPU6050_I2C_SLV_BYTE_SW_BIT 6
|
||||||
|
#define MPU6050_I2C_SLV_REG_DIS_BIT 5
|
||||||
|
#define MPU6050_I2C_SLV_GRP_BIT 4
|
||||||
|
#define MPU6050_I2C_SLV_LEN_BIT 3
|
||||||
|
#define MPU6050_I2C_SLV_LEN_LENGTH 4
|
||||||
|
|
||||||
|
#define MPU6050_I2C_SLV4_RW_BIT 7
|
||||||
|
#define MPU6050_I2C_SLV4_ADDR_BIT 6
|
||||||
|
#define MPU6050_I2C_SLV4_ADDR_LENGTH 7
|
||||||
|
#define MPU6050_I2C_SLV4_EN_BIT 7
|
||||||
|
#define MPU6050_I2C_SLV4_INT_EN_BIT 6
|
||||||
|
#define MPU6050_I2C_SLV4_REG_DIS_BIT 5
|
||||||
|
#define MPU6050_I2C_SLV4_MST_DLY_BIT 4
|
||||||
|
#define MPU6050_I2C_SLV4_MST_DLY_LENGTH 5
|
||||||
|
|
||||||
|
#define MPU6050_MST_PASS_THROUGH_BIT 7
|
||||||
|
#define MPU6050_MST_I2C_SLV4_DONE_BIT 6
|
||||||
|
#define MPU6050_MST_I2C_LOST_ARB_BIT 5
|
||||||
|
#define MPU6050_MST_I2C_SLV4_NACK_BIT 4
|
||||||
|
#define MPU6050_MST_I2C_SLV3_NACK_BIT 3
|
||||||
|
#define MPU6050_MST_I2C_SLV2_NACK_BIT 2
|
||||||
|
#define MPU6050_MST_I2C_SLV1_NACK_BIT 1
|
||||||
|
#define MPU6050_MST_I2C_SLV0_NACK_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_INTCFG_INT_LEVEL_BIT 7
|
||||||
|
#define MPU6050_INTCFG_INT_OPEN_BIT 6
|
||||||
|
#define MPU6050_INTCFG_LATCH_INT_EN_BIT 5
|
||||||
|
#define MPU6050_INTCFG_INT_RD_CLEAR_BIT 4
|
||||||
|
#define MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT 3
|
||||||
|
#define MPU6050_INTCFG_FSYNC_INT_EN_BIT 2
|
||||||
|
#define MPU6050_INTCFG_I2C_BYPASS_EN_BIT 1
|
||||||
|
#define MPU6050_INTCFG_CLKOUT_EN_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_INTMODE_ACTIVEHIGH 0x00
|
||||||
|
#define MPU6050_INTMODE_ACTIVELOW 0x01
|
||||||
|
|
||||||
|
#define MPU6050_INTDRV_PUSHPULL 0x00
|
||||||
|
#define MPU6050_INTDRV_OPENDRAIN 0x01
|
||||||
|
|
||||||
|
#define MPU6050_INTLATCH_50USPULSE 0x00
|
||||||
|
#define MPU6050_INTLATCH_WAITCLEAR 0x01
|
||||||
|
|
||||||
|
#define MPU6050_INTCLEAR_STATUSREAD 0x00
|
||||||
|
#define MPU6050_INTCLEAR_ANYREAD 0x01
|
||||||
|
|
||||||
|
#define MPU6050_INTERRUPT_FF_BIT 7
|
||||||
|
#define MPU6050_INTERRUPT_MOT_BIT 6
|
||||||
|
#define MPU6050_INTERRUPT_ZMOT_BIT 5
|
||||||
|
#define MPU6050_INTERRUPT_FIFO_OFLOW_BIT 4
|
||||||
|
#define MPU6050_INTERRUPT_I2C_MST_INT_BIT 3
|
||||||
|
#define MPU6050_INTERRUPT_PLL_RDY_INT_BIT 2
|
||||||
|
#define MPU6050_INTERRUPT_DMP_INT_BIT 1
|
||||||
|
#define MPU6050_INTERRUPT_DATA_RDY_BIT 0
|
||||||
|
|
||||||
|
// TODO: figure out what these actually do
|
||||||
|
// UMPL source code is not very obivous
|
||||||
|
#define MPU6050_DMPINT_5_BIT 5
|
||||||
|
#define MPU6050_DMPINT_4_BIT 4
|
||||||
|
#define MPU6050_DMPINT_3_BIT 3
|
||||||
|
#define MPU6050_DMPINT_2_BIT 2
|
||||||
|
#define MPU6050_DMPINT_1_BIT 1
|
||||||
|
#define MPU6050_DMPINT_0_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_MOTION_MOT_XNEG_BIT 7
|
||||||
|
#define MPU6050_MOTION_MOT_XPOS_BIT 6
|
||||||
|
#define MPU6050_MOTION_MOT_YNEG_BIT 5
|
||||||
|
#define MPU6050_MOTION_MOT_YPOS_BIT 4
|
||||||
|
#define MPU6050_MOTION_MOT_ZNEG_BIT 3
|
||||||
|
#define MPU6050_MOTION_MOT_ZPOS_BIT 2
|
||||||
|
#define MPU6050_MOTION_MOT_ZRMOT_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT 7
|
||||||
|
#define MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT 4
|
||||||
|
#define MPU6050_DELAYCTRL_I2C_SLV3_DLY_EN_BIT 3
|
||||||
|
#define MPU6050_DELAYCTRL_I2C_SLV2_DLY_EN_BIT 2
|
||||||
|
#define MPU6050_DELAYCTRL_I2C_SLV1_DLY_EN_BIT 1
|
||||||
|
#define MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_PATHRESET_GYRO_RESET_BIT 2
|
||||||
|
#define MPU6050_PATHRESET_ACCEL_RESET_BIT 1
|
||||||
|
#define MPU6050_PATHRESET_TEMP_RESET_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_DETECT_ACCEL_ON_DELAY_BIT 5
|
||||||
|
#define MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH 2
|
||||||
|
#define MPU6050_DETECT_FF_COUNT_BIT 3
|
||||||
|
#define MPU6050_DETECT_FF_COUNT_LENGTH 2
|
||||||
|
#define MPU6050_DETECT_MOT_COUNT_BIT 1
|
||||||
|
#define MPU6050_DETECT_MOT_COUNT_LENGTH 2
|
||||||
|
|
||||||
|
#define MPU6050_DETECT_DECREMENT_RESET 0x0
|
||||||
|
#define MPU6050_DETECT_DECREMENT_1 0x1
|
||||||
|
#define MPU6050_DETECT_DECREMENT_2 0x2
|
||||||
|
#define MPU6050_DETECT_DECREMENT_4 0x3
|
||||||
|
|
||||||
|
#define MPU6050_USERCTRL_DMP_EN_BIT 7
|
||||||
|
#define MPU6050_USERCTRL_FIFO_EN_BIT 6
|
||||||
|
#define MPU6050_USERCTRL_I2C_MST_EN_BIT 5
|
||||||
|
#define MPU6050_USERCTRL_I2C_IF_DIS_BIT 4
|
||||||
|
#define MPU6050_USERCTRL_DMP_RESET_BIT 3
|
||||||
|
#define MPU6050_USERCTRL_FIFO_RESET_BIT 2
|
||||||
|
#define MPU6050_USERCTRL_I2C_MST_RESET_BIT 1
|
||||||
|
#define MPU6050_USERCTRL_SIG_COND_RESET_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_PWR1_DEVICE_RESET_BIT 7
|
||||||
|
#define MPU6050_PWR1_SLEEP_BIT 6
|
||||||
|
#define MPU6050_PWR1_CYCLE_BIT 5
|
||||||
|
#define MPU6050_PWR1_TEMP_DIS_BIT 3
|
||||||
|
#define MPU6050_PWR1_CLKSEL_BIT 2
|
||||||
|
#define MPU6050_PWR1_CLKSEL_LENGTH 3
|
||||||
|
|
||||||
|
#define MPU6050_CLOCK_INTERNAL 0x00
|
||||||
|
#define MPU6050_CLOCK_PLL_XGYRO 0x01
|
||||||
|
#define MPU6050_CLOCK_PLL_YGYRO 0x02
|
||||||
|
#define MPU6050_CLOCK_PLL_ZGYRO 0x03
|
||||||
|
#define MPU6050_CLOCK_PLL_EXT32K 0x04
|
||||||
|
#define MPU6050_CLOCK_PLL_EXT19M 0x05
|
||||||
|
#define MPU6050_CLOCK_KEEP_RESET 0x07
|
||||||
|
|
||||||
|
#define MPU6050_PWR2_LP_WAKE_CTRL_BIT 7
|
||||||
|
#define MPU6050_PWR2_LP_WAKE_CTRL_LENGTH 2
|
||||||
|
#define MPU6050_PWR2_STBY_XA_BIT 5
|
||||||
|
#define MPU6050_PWR2_STBY_YA_BIT 4
|
||||||
|
#define MPU6050_PWR2_STBY_ZA_BIT 3
|
||||||
|
#define MPU6050_PWR2_STBY_XG_BIT 2
|
||||||
|
#define MPU6050_PWR2_STBY_YG_BIT 1
|
||||||
|
#define MPU6050_PWR2_STBY_ZG_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_WAKE_FREQ_1P25 0x0
|
||||||
|
#define MPU6050_WAKE_FREQ_2P5 0x1
|
||||||
|
#define MPU6050_WAKE_FREQ_5 0x2
|
||||||
|
#define MPU6050_WAKE_FREQ_10 0x3
|
||||||
|
|
||||||
|
#define MPU6050_BANKSEL_PRFTCH_EN_BIT 6
|
||||||
|
#define MPU6050_BANKSEL_CFG_USER_BANK_BIT 5
|
||||||
|
#define MPU6050_BANKSEL_MEM_SEL_BIT 4
|
||||||
|
#define MPU6050_BANKSEL_MEM_SEL_LENGTH 5
|
||||||
|
|
||||||
|
#define MPU6050_WHO_AM_I_BIT 6
|
||||||
|
#define MPU6050_WHO_AM_I_LENGTH 6
|
||||||
|
extern short gyro[3], accel[3];
|
||||||
|
extern int16_t Gx_offset,Gy_offset,Gz_offset;
|
||||||
|
extern float Acc1G_Values;
|
||||||
|
extern float Pitch,Roll;
|
||||||
|
//供外部调用的API
|
||||||
|
void MPU6050_initialize(void); //初始化
|
||||||
|
uint8_t MPU6050_testConnection(void); //检测MPU6050是否存在
|
||||||
|
//读取ADC值
|
||||||
|
void MPU6050_getMotion6(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz);
|
||||||
|
void MPU6050_getlastMotion6(int16_t* ax, int16_t* ay,
|
||||||
|
int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz);
|
||||||
|
uint8_t MPU6050_getDeviceID(void); //读取MPU6050的ID
|
||||||
|
void MPU6050_InitGyro_Offset(void);//初始化陀螺仪偏置
|
||||||
|
void DMP_Init(void);
|
||||||
|
void Read_DMP(void);
|
||||||
|
int Read_Temperature(void);
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,93 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：东莞市微宏智能科技有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
Company: WeiHong Co.Ltd
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#include "filter.h"
|
||||||
|
float K1 =0.02;
|
||||||
|
float angle,angle_dot;
|
||||||
|
float Q_angle=0.001;// 过程噪声的协方差
|
||||||
|
float Q_gyro=0.003;//0.003 过程噪声的协方差 过程噪声的协方差为一个一行两列矩阵
|
||||||
|
float R_angle=0.5;// 测量噪声的协方差 既测量偏差
|
||||||
|
float dt=0.005;//
|
||||||
|
char C_0 = 1;
|
||||||
|
float Q_bias, AngleErr;
|
||||||
|
float PCt_0, PCt_1, E;
|
||||||
|
float K_0, K_1, t_0, t_1;
|
||||||
|
float Pdot[4] ={0,0,0,0};
|
||||||
|
float PP[2][2] = { { 1, 0 },{ 0, 1 } };
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Simple Kalman filter
|
||||||
|
Input : acceleration、angular velocity
|
||||||
|
Output : none
|
||||||
|
函数功能：简易卡尔曼滤波
|
||||||
|
入口参数：加速度、角速度
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void Kalman_Filter(float Accel, float Gyro)
|
||||||
|
{
|
||||||
|
// 状态预测方程 Xt+1 = F*Xt
|
||||||
|
angle += (Gyro - Q_bias) * dt;
|
||||||
|
// Pk-先验估计误差协方差的微分
|
||||||
|
Pdot[0] = Q_angle - PP[0][1] - PP[1][0];
|
||||||
|
|
||||||
|
// P = FPF + Q
|
||||||
|
Pdot[1]=-PP[1][1];
|
||||||
|
Pdot[2]=-PP[1][1];
|
||||||
|
Pdot[3]=Q_gyro;
|
||||||
|
|
||||||
|
PP[0][0] += Pdot[0] * dt; // Pk-先验估计误差协方差微分的积分
|
||||||
|
PP[0][1] += Pdot[1] * dt; // =先验估计误差协方差
|
||||||
|
PP[1][0] += Pdot[2] * dt;
|
||||||
|
PP[1][1] += Pdot[3] * dt;
|
||||||
|
|
||||||
|
AngleErr = Accel - angle; //zk-先验估计
|
||||||
|
|
||||||
|
PCt_0 = C_0 * PP[0][0];
|
||||||
|
PCt_1 = C_0 * PP[1][0];
|
||||||
|
|
||||||
|
E = R_angle + C_0 * PCt_0;
|
||||||
|
|
||||||
|
K_0 = PCt_0 / E;
|
||||||
|
K_1 = PCt_1 / E;
|
||||||
|
|
||||||
|
t_0 = PCt_0;
|
||||||
|
t_1 = C_0 * PP[0][1];
|
||||||
|
|
||||||
|
PP[0][0] -= K_0 * t_0; // 后验估计误差协方差
|
||||||
|
PP[0][1] -= K_0 * t_1;
|
||||||
|
PP[1][0] -= K_1 * t_0;
|
||||||
|
PP[1][1] -= K_1 * t_1;
|
||||||
|
|
||||||
|
angle += K_0 * AngleErr; // 后验估计
|
||||||
|
Q_bias += K_1 * AngleErr; // 后验估计
|
||||||
|
angle_dot = Gyro - Q_bias; // 输出值(后验估计)的微分=角速度
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: First order complementary filtering
|
||||||
|
Input : acceleration、angular velocity
|
||||||
|
Output : none
|
||||||
|
函数功能：一阶互补滤波
|
||||||
|
入口参数：加速度、角速度
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void First_order_filter(float angle_m, float gyro_m)
|
||||||
|
{
|
||||||
|
angle = K1 * angle_m+ (1-K1) * (angle + gyro_m * 0.005);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：东莞市微宏智能科技有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
Company: WeiHong Co.Ltd
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#ifndef __FILTER_H
|
||||||
|
#define __FILTER_H
|
||||||
|
extern float angle, angle_dot;
|
||||||
|
void Kalman_Filter(float Accel,float Gyro);
|
||||||
|
void First_order_filter(float angle_m, float gyro_m);
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,55 @@
|
||||||
|
#include "show.h"
|
||||||
|
/**************************************************************************
|
||||||
|
Function: OLED display
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：OLED显示
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void oled_show(void)
|
||||||
|
{
|
||||||
|
// 显示屏打开
|
||||||
|
OLED_Display_On();
|
||||||
|
// 第一行显示小车模式
|
||||||
|
OLED_ShowString(0,0,"DMP");
|
||||||
|
OLED_ShowString(60,0,"Normal");
|
||||||
|
// 第三行显示编码器1
|
||||||
|
OLED_ShowString(00,20,"EncoLEFT");
|
||||||
|
if( Encoder_Left<0){
|
||||||
|
OLED_ShowString(80,20,"-");
|
||||||
|
OLED_ShowNumber(95,20,-Encoder_Left,3,12);
|
||||||
|
}else{
|
||||||
|
OLED_ShowString(80,20,"+");
|
||||||
|
OLED_ShowNumber(95,20, Encoder_Left,3,12);
|
||||||
|
}
|
||||||
|
|
||||||
|
// 第四行显示编码器2
|
||||||
|
OLED_ShowString(00,30,"EncoRIGHT");
|
||||||
|
if(Encoder_Right<0){
|
||||||
|
OLED_ShowString(80,30,"-");
|
||||||
|
OLED_ShowNumber(95,30,-Encoder_Right,3,12);
|
||||||
|
}else{
|
||||||
|
OLED_ShowString(80,30,"+");
|
||||||
|
OLED_ShowNumber(95,30, Encoder_Right,3,12);
|
||||||
|
}
|
||||||
|
|
||||||
|
// 第六行显示角度
|
||||||
|
OLED_ShowString(0,50,"Angle");
|
||||||
|
if(Angle_Balance < 0){
|
||||||
|
OLED_ShowString(48,50,"-");
|
||||||
|
}
|
||||||
|
if(Angle_Balance>=0){
|
||||||
|
OLED_ShowString(48,50,"+");
|
||||||
|
}
|
||||||
|
OLED_ShowNumber(53,50,myabs((int)Angle_Balance),3,12);
|
||||||
|
|
||||||
|
if(Flag_Stop){
|
||||||
|
OLED_ShowString(90,50,"OFF");
|
||||||
|
}
|
||||||
|
if(!Flag_Stop){
|
||||||
|
OLED_ShowString(90,50,"ON ");
|
||||||
|
}
|
||||||
|
// 刷新
|
||||||
|
OLED_Refresh_Gram();
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#ifndef __SHOW_H
|
||||||
|
#define __SHOW_H
|
||||||
|
#include "sys.h"
|
||||||
|
void oled_show(void);
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,784 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm3.c
|
||||||
|
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
|
||||||
|
* @version V1.30
|
||||||
|
* @date 30. October 2009
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
* processor based microcontrollers. This file can be freely distributed
|
||||||
|
* within development tools that are supporting such ARM based processors.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/* define compiler specific symbols */
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||||
|
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* ################### Compiler specific Intrinsics ########################### */
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||||
|
/* ARM armcc specific functions */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @return ProcessStackPointer
|
||||||
|
*
|
||||||
|
* Return the actual process stack pointer
|
||||||
|
*/
|
||||||
|
__ASM uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
mrs r0, psp
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfProcStack Process Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value ProcessStackPointer to the MSP
|
||||||
|
* (process stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
__ASM void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
msr psp, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @return Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Return the current value of the MSP (main stack pointer)
|
||||||
|
* Cortex processor register
|
||||||
|
*/
|
||||||
|
__ASM uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
mrs r0, msp
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfMainStack Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value mainStackPointer to the MSP
|
||||||
|
* (main stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
__ASM void __set_MSP(uint32_t mainStackPointer)
|
||||||
|
{
|
||||||
|
msr msp, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order in unsigned short value
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in unsigned short value
|
||||||
|
*/
|
||||||
|
__ASM uint32_t __REV16(uint16_t value)
|
||||||
|
{
|
||||||
|
rev16 r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order in signed short value with sign extension to integer
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in signed short value with sign extension to integer
|
||||||
|
*/
|
||||||
|
__ASM int32_t __REVSH(int16_t value)
|
||||||
|
{
|
||||||
|
revsh r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if (__ARMCC_VERSION < 400000)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Remove the exclusive lock created by ldrex
|
||||||
|
*
|
||||||
|
* Removes the exclusive lock which is created by ldrex.
|
||||||
|
*/
|
||||||
|
__ASM void __CLREX(void)
|
||||||
|
{
|
||||||
|
clrex
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Base Priority value
|
||||||
|
*
|
||||||
|
* @return BasePriority
|
||||||
|
*
|
||||||
|
* Return the content of the base priority register
|
||||||
|
*/
|
||||||
|
__ASM uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
mrs r0, basepri
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Base Priority value
|
||||||
|
*
|
||||||
|
* @param basePri BasePriority
|
||||||
|
*
|
||||||
|
* Set the base priority register
|
||||||
|
*/
|
||||||
|
__ASM void __set_BASEPRI(uint32_t basePri)
|
||||||
|
{
|
||||||
|
msr basepri, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Priority Mask value
|
||||||
|
*
|
||||||
|
* @return PriMask
|
||||||
|
*
|
||||||
|
* Return state of the priority mask bit from the priority mask register
|
||||||
|
*/
|
||||||
|
__ASM uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
mrs r0, primask
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Priority Mask value
|
||||||
|
*
|
||||||
|
* @param priMask PriMask
|
||||||
|
*
|
||||||
|
* Set the priority mask bit in the priority mask register
|
||||||
|
*/
|
||||||
|
__ASM void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
msr primask, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Fault Mask value
|
||||||
|
*
|
||||||
|
* @return FaultMask
|
||||||
|
*
|
||||||
|
* Return the content of the fault mask register
|
||||||
|
*/
|
||||||
|
__ASM uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
mrs r0, faultmask
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Fault Mask value
|
||||||
|
*
|
||||||
|
* @param faultMask faultMask value
|
||||||
|
*
|
||||||
|
* Set the fault mask register
|
||||||
|
*/
|
||||||
|
__ASM void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
msr faultmask, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Control Register value
|
||||||
|
*
|
||||||
|
* @return Control value
|
||||||
|
*
|
||||||
|
* Return the content of the control register
|
||||||
|
*/
|
||||||
|
__ASM uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
mrs r0, control
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Control Register value
|
||||||
|
*
|
||||||
|
* @param control Control value
|
||||||
|
*
|
||||||
|
* Set the control register
|
||||||
|
*/
|
||||||
|
__ASM void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
msr control, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARMCC_VERSION */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
#pragma diag_suppress=Pe940
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @return ProcessStackPointer
|
||||||
|
*
|
||||||
|
* Return the actual process stack pointer
|
||||||
|
*/
|
||||||
|
uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
__ASM("mrs r0, psp");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfProcStack Process Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value ProcessStackPointer to the MSP
|
||||||
|
* (process stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
__ASM("msr psp, r0");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @return Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Return the current value of the MSP (main stack pointer)
|
||||||
|
* Cortex processor register
|
||||||
|
*/
|
||||||
|
uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
__ASM("mrs r0, msp");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfMainStack Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value mainStackPointer to the MSP
|
||||||
|
* (main stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
__ASM("msr msp, r0");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order in unsigned short value
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in unsigned short value
|
||||||
|
*/
|
||||||
|
uint32_t __REV16(uint16_t value)
|
||||||
|
{
|
||||||
|
__ASM("rev16 r0, r0");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse bit order of value
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse bit order of value
|
||||||
|
*/
|
||||||
|
uint32_t __RBIT(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM("rbit r0, r0");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (8 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 8 bit values)
|
||||||
|
*/
|
||||||
|
uint8_t __LDREXB(uint8_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("ldrexb r0, [r0]");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (16 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 16 bit values
|
||||||
|
*/
|
||||||
|
uint16_t __LDREXH(uint16_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("ldrexh r0, [r0]");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (32 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 32 bit values
|
||||||
|
*/
|
||||||
|
uint32_t __LDREXW(uint32_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("ldrex r0, [r0]");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (8 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 8 bit values
|
||||||
|
*/
|
||||||
|
uint32_t __STREXB(uint8_t value, uint8_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("strexb r0, r0, [r1]");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (16 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 16 bit values
|
||||||
|
*/
|
||||||
|
uint32_t __STREXH(uint16_t value, uint16_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("strexh r0, r0, [r1]");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (32 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 32 bit values
|
||||||
|
*/
|
||||||
|
uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("strex r0, r0, [r1]");
|
||||||
|
__ASM("bx lr");
|
||||||
|
}
|
||||||
|
|
||||||
|
#pragma diag_default=Pe940
|
||||||
|
|
||||||
|
|
||||||
|
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
||||||
|
/* GNU gcc specific functions */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @return ProcessStackPointer
|
||||||
|
*
|
||||||
|
* Return the actual process stack pointer
|
||||||
|
*/
|
||||||
|
uint32_t __get_PSP(void) __attribute__( ( naked ) );
|
||||||
|
uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, psp\n\t"
|
||||||
|
"MOV r0, %0 \n\t"
|
||||||
|
"BX lr \n\t" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Process Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfProcStack Process Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value ProcessStackPointer to the MSP
|
||||||
|
* (process stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
|
||||||
|
void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR psp, %0\n\t"
|
||||||
|
"BX lr \n\t" : : "r" (topOfProcStack) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @return Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Return the current value of the MSP (main stack pointer)
|
||||||
|
* Cortex processor register
|
||||||
|
*/
|
||||||
|
uint32_t __get_MSP(void) __attribute__( ( naked ) );
|
||||||
|
uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, msp\n\t"
|
||||||
|
"MOV r0, %0 \n\t"
|
||||||
|
"BX lr \n\t" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Main Stack Pointer
|
||||||
|
*
|
||||||
|
* @param topOfMainStack Main Stack Pointer
|
||||||
|
*
|
||||||
|
* Assign the value mainStackPointer to the MSP
|
||||||
|
* (main stack pointer) Cortex processor register
|
||||||
|
*/
|
||||||
|
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
|
||||||
|
void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR msp, %0\n\t"
|
||||||
|
"BX lr \n\t" : : "r" (topOfMainStack) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Base Priority value
|
||||||
|
*
|
||||||
|
* @return BasePriority
|
||||||
|
*
|
||||||
|
* Return the content of the base priority register
|
||||||
|
*/
|
||||||
|
uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Base Priority value
|
||||||
|
*
|
||||||
|
* @param basePri BasePriority
|
||||||
|
*
|
||||||
|
* Set the base priority register
|
||||||
|
*/
|
||||||
|
void __set_BASEPRI(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Priority Mask value
|
||||||
|
*
|
||||||
|
* @return PriMask
|
||||||
|
*
|
||||||
|
* Return state of the priority mask bit from the priority mask register
|
||||||
|
*/
|
||||||
|
uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Priority Mask value
|
||||||
|
*
|
||||||
|
* @param priMask PriMask
|
||||||
|
*
|
||||||
|
* Set the priority mask bit in the priority mask register
|
||||||
|
*/
|
||||||
|
void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Fault Mask value
|
||||||
|
*
|
||||||
|
* @return FaultMask
|
||||||
|
*
|
||||||
|
* Return the content of the fault mask register
|
||||||
|
*/
|
||||||
|
uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Fault Mask value
|
||||||
|
*
|
||||||
|
* @param faultMask faultMask value
|
||||||
|
*
|
||||||
|
* Set the fault mask register
|
||||||
|
*/
|
||||||
|
void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the Control Register value
|
||||||
|
*
|
||||||
|
* @return Control value
|
||||||
|
*
|
||||||
|
* Return the content of the control register
|
||||||
|
*/
|
||||||
|
uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the Control Register value
|
||||||
|
*
|
||||||
|
* @param control Control value
|
||||||
|
*
|
||||||
|
* Set the control register
|
||||||
|
*/
|
||||||
|
void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order in integer value
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in integer value
|
||||||
|
*/
|
||||||
|
uint32_t __REV(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order in unsigned short value
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in unsigned short value
|
||||||
|
*/
|
||||||
|
uint32_t __REV16(uint16_t value)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse byte order in signed short value with sign extension to integer
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse byte order in signed short value with sign extension to integer
|
||||||
|
*/
|
||||||
|
int32_t __REVSH(int16_t value)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reverse bit order of value
|
||||||
|
*
|
||||||
|
* @param value value to reverse
|
||||||
|
* @return reversed value
|
||||||
|
*
|
||||||
|
* Reverse bit order of value
|
||||||
|
*/
|
||||||
|
uint32_t __RBIT(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (8 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 8 bit value
|
||||||
|
*/
|
||||||
|
uint8_t __LDREXB(uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint8_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (16 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 16 bit values
|
||||||
|
*/
|
||||||
|
uint16_t __LDREXH(uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint16_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief LDR Exclusive (32 bit)
|
||||||
|
*
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return value of (*address)
|
||||||
|
*
|
||||||
|
* Exclusive LDR command for 32 bit values
|
||||||
|
*/
|
||||||
|
uint32_t __LDREXW(uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (8 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 8 bit values
|
||||||
|
*/
|
||||||
|
uint32_t __STREXB(uint8_t value, uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (16 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 16 bit values
|
||||||
|
*/
|
||||||
|
uint32_t __STREXH(uint16_t value, uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STR Exclusive (32 bit)
|
||||||
|
*
|
||||||
|
* @param value value to store
|
||||||
|
* @param *addr address pointer
|
||||||
|
* @return successful / failed
|
||||||
|
*
|
||||||
|
* Exclusive STR command for 32 bit values
|
||||||
|
*/
|
||||||
|
uint32_t __STREXW(uint32_t value, uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result=0;
|
||||||
|
|
||||||
|
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
|
||||||
|
/* TASKING carm specific functions */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,307 @@
|
||||||
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
|
||||||
|
;* File Name : startup_stm32f10x_md.s
|
||||||
|
;* Author : MCD Application Team
|
||||||
|
;* Version : V3.5.0
|
||||||
|
;* Date : 11-March-2011
|
||||||
|
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
|
||||||
|
;* toolchain.
|
||||||
|
;* This module performs:
|
||||||
|
;* - Set the initial SP
|
||||||
|
;* - Set the initial PC == Reset_Handler
|
||||||
|
;* - Set the vector table entries with the exceptions ISR address
|
||||||
|
;* - Configure the clock system
|
||||||
|
;* - Branches to __main in the C library (which eventually
|
||||||
|
;* calls main()).
|
||||||
|
;* After Reset the CortexM3 processor is in Thread mode,
|
||||||
|
;* priority is Privileged, and the Stack is set to Main.
|
||||||
|
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||||
|
;*******************************************************************************
|
||||||
|
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
|
||||||
|
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
|
||||||
|
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||||
|
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
|
||||||
|
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
;*******************************************************************************
|
||||||
|
|
||||||
|
; Amount of memory (in bytes) allocated for Stack
|
||||||
|
; Tailor this value to your application needs
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000200
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDG_IRQHandler ; Window Watchdog
|
||||||
|
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||||
|
DCD TAMPER_IRQHandler ; Tamper
|
||||||
|
DCD RTC_IRQHandler ; RTC
|
||||||
|
DCD FLASH_IRQHandler ; Flash
|
||||||
|
DCD RCC_IRQHandler ; RCC
|
||||||
|
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||||
|
DCD ADC1_2_IRQHandler ; ADC1_2
|
||||||
|
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||||
|
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||||
|
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||||
|
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||||
|
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||||
|
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||||
|
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||||
|
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||||
|
DCD TIM2_IRQHandler ; TIM2
|
||||||
|
DCD TIM3_IRQHandler ; TIM3
|
||||||
|
DCD TIM4_IRQHandler ; TIM4
|
||||||
|
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||||
|
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||||
|
DCD SPI1_IRQHandler ; SPI1
|
||||||
|
DCD SPI2_IRQHandler ; SPI2
|
||||||
|
DCD USART1_IRQHandler ; USART1
|
||||||
|
DCD USART2_IRQHandler ; USART2
|
||||||
|
DCD USART3_IRQHandler ; USART3
|
||||||
|
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||||
|
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||||
|
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
; Reset handler
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT __main
|
||||||
|
IMPORT SystemInit
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
|
||||||
|
EXPORT WWDG_IRQHandler [WEAK]
|
||||||
|
EXPORT PVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_IRQHandler [WEAK]
|
||||||
|
EXPORT FLASH_IRQHandler [WEAK]
|
||||||
|
EXPORT RCC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM3_IRQHandler [WEAK]
|
||||||
|
EXPORT TIM4_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT USART3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||||
|
EXPORT RTCAlarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
WWDG_IRQHandler
|
||||||
|
PVD_IRQHandler
|
||||||
|
TAMPER_IRQHandler
|
||||||
|
RTC_IRQHandler
|
||||||
|
FLASH_IRQHandler
|
||||||
|
RCC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
ADC1_2_IRQHandler
|
||||||
|
USB_HP_CAN1_TX_IRQHandler
|
||||||
|
USB_LP_CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_SCE_IRQHandler
|
||||||
|
EXTI9_5_IRQHandler
|
||||||
|
TIM1_BRK_IRQHandler
|
||||||
|
TIM1_UP_IRQHandler
|
||||||
|
TIM1_TRG_COM_IRQHandler
|
||||||
|
TIM1_CC_IRQHandler
|
||||||
|
TIM2_IRQHandler
|
||||||
|
TIM3_IRQHandler
|
||||||
|
TIM4_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
USART3_IRQHandler
|
||||||
|
EXTI15_10_IRQHandler
|
||||||
|
RTCAlarm_IRQHandler
|
||||||
|
USBWakeUp_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
;*******************************************************************************
|
||||||
|
; User Stack and Heap initialization
|
||||||
|
;*******************************************************************************
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap
|
||||||
|
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
|
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
||||||
|
|
@ -0,0 +1,494 @@
|
||||||
|
/*
|
||||||
|
$License:
|
||||||
|
Copyright (C) 2011 InvenSense Corporation, All Rights Reserved.
|
||||||
|
$
|
||||||
|
*/
|
||||||
|
#ifndef DMPKEY_H__
|
||||||
|
#define DMPKEY_H__
|
||||||
|
|
||||||
|
#define KEY_CFG_25 (0)
|
||||||
|
#define KEY_CFG_24 (KEY_CFG_25 + 1)
|
||||||
|
#define KEY_CFG_26 (KEY_CFG_24 + 1)
|
||||||
|
#define KEY_CFG_27 (KEY_CFG_26 + 1)
|
||||||
|
#define KEY_CFG_21 (KEY_CFG_27 + 1)
|
||||||
|
#define KEY_CFG_20 (KEY_CFG_21 + 1)
|
||||||
|
#define KEY_CFG_TAP4 (KEY_CFG_20 + 1)
|
||||||
|
#define KEY_CFG_TAP5 (KEY_CFG_TAP4 + 1)
|
||||||
|
#define KEY_CFG_TAP6 (KEY_CFG_TAP5 + 1)
|
||||||
|
#define KEY_CFG_TAP7 (KEY_CFG_TAP6 + 1)
|
||||||
|
#define KEY_CFG_TAP0 (KEY_CFG_TAP7 + 1)
|
||||||
|
#define KEY_CFG_TAP1 (KEY_CFG_TAP0 + 1)
|
||||||
|
#define KEY_CFG_TAP2 (KEY_CFG_TAP1 + 1)
|
||||||
|
#define KEY_CFG_TAP3 (KEY_CFG_TAP2 + 1)
|
||||||
|
#define KEY_CFG_TAP_QUANTIZE (KEY_CFG_TAP3 + 1)
|
||||||
|
#define KEY_CFG_TAP_JERK (KEY_CFG_TAP_QUANTIZE + 1)
|
||||||
|
#define KEY_CFG_DR_INT (KEY_CFG_TAP_JERK + 1)
|
||||||
|
#define KEY_CFG_AUTH (KEY_CFG_DR_INT + 1)
|
||||||
|
#define KEY_CFG_TAP_SAVE_ACCB (KEY_CFG_AUTH + 1)
|
||||||
|
#define KEY_CFG_TAP_CLEAR_STICKY (KEY_CFG_TAP_SAVE_ACCB + 1)
|
||||||
|
#define KEY_CFG_FIFO_ON_EVENT (KEY_CFG_TAP_CLEAR_STICKY + 1)
|
||||||
|
#define KEY_FCFG_ACCEL_INPUT (KEY_CFG_FIFO_ON_EVENT + 1)
|
||||||
|
#define KEY_FCFG_ACCEL_INIT (KEY_FCFG_ACCEL_INPUT + 1)
|
||||||
|
#define KEY_CFG_23 (KEY_FCFG_ACCEL_INIT + 1)
|
||||||
|
#define KEY_FCFG_1 (KEY_CFG_23 + 1)
|
||||||
|
#define KEY_FCFG_3 (KEY_FCFG_1 + 1)
|
||||||
|
#define KEY_FCFG_2 (KEY_FCFG_3 + 1)
|
||||||
|
#define KEY_CFG_3D (KEY_FCFG_2 + 1)
|
||||||
|
#define KEY_CFG_3B (KEY_CFG_3D + 1)
|
||||||
|
#define KEY_CFG_3C (KEY_CFG_3B + 1)
|
||||||
|
#define KEY_FCFG_5 (KEY_CFG_3C + 1)
|
||||||
|
#define KEY_FCFG_4 (KEY_FCFG_5 + 1)
|
||||||
|
#define KEY_FCFG_7 (KEY_FCFG_4 + 1)
|
||||||
|
#define KEY_FCFG_FSCALE (KEY_FCFG_7 + 1)
|
||||||
|
#define KEY_FCFG_AZ (KEY_FCFG_FSCALE + 1)
|
||||||
|
#define KEY_FCFG_6 (KEY_FCFG_AZ + 1)
|
||||||
|
#define KEY_FCFG_LSB4 (KEY_FCFG_6 + 1)
|
||||||
|
#define KEY_CFG_12 (KEY_FCFG_LSB4 + 1)
|
||||||
|
#define KEY_CFG_14 (KEY_CFG_12 + 1)
|
||||||
|
#define KEY_CFG_15 (KEY_CFG_14 + 1)
|
||||||
|
#define KEY_CFG_16 (KEY_CFG_15 + 1)
|
||||||
|
#define KEY_CFG_18 (KEY_CFG_16 + 1)
|
||||||
|
#define KEY_CFG_6 (KEY_CFG_18 + 1)
|
||||||
|
#define KEY_CFG_7 (KEY_CFG_6 + 1)
|
||||||
|
#define KEY_CFG_4 (KEY_CFG_7 + 1)
|
||||||
|
#define KEY_CFG_5 (KEY_CFG_4 + 1)
|
||||||
|
#define KEY_CFG_2 (KEY_CFG_5 + 1)
|
||||||
|
#define KEY_CFG_3 (KEY_CFG_2 + 1)
|
||||||
|
#define KEY_CFG_1 (KEY_CFG_3 + 1)
|
||||||
|
#define KEY_CFG_EXTERNAL (KEY_CFG_1 + 1)
|
||||||
|
#define KEY_CFG_8 (KEY_CFG_EXTERNAL + 1)
|
||||||
|
#define KEY_CFG_9 (KEY_CFG_8 + 1)
|
||||||
|
#define KEY_CFG_ORIENT_3 (KEY_CFG_9 + 1)
|
||||||
|
#define KEY_CFG_ORIENT_2 (KEY_CFG_ORIENT_3 + 1)
|
||||||
|
#define KEY_CFG_ORIENT_1 (KEY_CFG_ORIENT_2 + 1)
|
||||||
|
#define KEY_CFG_GYRO_SOURCE (KEY_CFG_ORIENT_1 + 1)
|
||||||
|
#define KEY_CFG_ORIENT_IRQ_1 (KEY_CFG_GYRO_SOURCE + 1)
|
||||||
|
#define KEY_CFG_ORIENT_IRQ_2 (KEY_CFG_ORIENT_IRQ_1 + 1)
|
||||||
|
#define KEY_CFG_ORIENT_IRQ_3 (KEY_CFG_ORIENT_IRQ_2 + 1)
|
||||||
|
#define KEY_FCFG_MAG_VAL (KEY_CFG_ORIENT_IRQ_3 + 1)
|
||||||
|
#define KEY_FCFG_MAG_MOV (KEY_FCFG_MAG_VAL + 1)
|
||||||
|
#define KEY_CFG_LP_QUAT (KEY_FCFG_MAG_MOV + 1)
|
||||||
|
|
||||||
|
/* MPU6050 keys */
|
||||||
|
#define KEY_CFG_ACCEL_FILTER (KEY_CFG_LP_QUAT + 1)
|
||||||
|
#define KEY_CFG_MOTION_BIAS (KEY_CFG_ACCEL_FILTER + 1)
|
||||||
|
#define KEY_TEMPLABEL (KEY_CFG_MOTION_BIAS + 1)
|
||||||
|
|
||||||
|
#define KEY_D_0_22 (KEY_TEMPLABEL + 1)
|
||||||
|
#define KEY_D_0_24 (KEY_D_0_22 + 1)
|
||||||
|
#define KEY_D_0_36 (KEY_D_0_24 + 1)
|
||||||
|
#define KEY_D_0_52 (KEY_D_0_36 + 1)
|
||||||
|
#define KEY_D_0_96 (KEY_D_0_52 + 1)
|
||||||
|
#define KEY_D_0_104 (KEY_D_0_96 + 1)
|
||||||
|
#define KEY_D_0_108 (KEY_D_0_104 + 1)
|
||||||
|
#define KEY_D_0_163 (KEY_D_0_108 + 1)
|
||||||
|
#define KEY_D_0_188 (KEY_D_0_163 + 1)
|
||||||
|
#define KEY_D_0_192 (KEY_D_0_188 + 1)
|
||||||
|
#define KEY_D_0_224 (KEY_D_0_192 + 1)
|
||||||
|
#define KEY_D_0_228 (KEY_D_0_224 + 1)
|
||||||
|
#define KEY_D_0_232 (KEY_D_0_228 + 1)
|
||||||
|
#define KEY_D_0_236 (KEY_D_0_232 + 1)
|
||||||
|
|
||||||
|
#define KEY_DMP_PREVPTAT (KEY_D_0_236 + 1)
|
||||||
|
#define KEY_D_1_2 (KEY_DMP_PREVPTAT + 1)
|
||||||
|
#define KEY_D_1_4 (KEY_D_1_2 + 1)
|
||||||
|
#define KEY_D_1_8 (KEY_D_1_4 + 1)
|
||||||
|
#define KEY_D_1_10 (KEY_D_1_8 + 1)
|
||||||
|
#define KEY_D_1_24 (KEY_D_1_10 + 1)
|
||||||
|
#define KEY_D_1_28 (KEY_D_1_24 + 1)
|
||||||
|
#define KEY_D_1_36 (KEY_D_1_28 + 1)
|
||||||
|
#define KEY_D_1_40 (KEY_D_1_36 + 1)
|
||||||
|
#define KEY_D_1_44 (KEY_D_1_40 + 1)
|
||||||
|
#define KEY_D_1_72 (KEY_D_1_44 + 1)
|
||||||
|
#define KEY_D_1_74 (KEY_D_1_72 + 1)
|
||||||
|
#define KEY_D_1_79 (KEY_D_1_74 + 1)
|
||||||
|
#define KEY_D_1_88 (KEY_D_1_79 + 1)
|
||||||
|
#define KEY_D_1_90 (KEY_D_1_88 + 1)
|
||||||
|
#define KEY_D_1_92 (KEY_D_1_90 + 1)
|
||||||
|
#define KEY_D_1_96 (KEY_D_1_92 + 1)
|
||||||
|
#define KEY_D_1_98 (KEY_D_1_96 + 1)
|
||||||
|
#define KEY_D_1_100 (KEY_D_1_98 + 1)
|
||||||
|
#define KEY_D_1_106 (KEY_D_1_100 + 1)
|
||||||
|
#define KEY_D_1_108 (KEY_D_1_106 + 1)
|
||||||
|
#define KEY_D_1_112 (KEY_D_1_108 + 1)
|
||||||
|
#define KEY_D_1_128 (KEY_D_1_112 + 1)
|
||||||
|
#define KEY_D_1_152 (KEY_D_1_128 + 1)
|
||||||
|
#define KEY_D_1_160 (KEY_D_1_152 + 1)
|
||||||
|
#define KEY_D_1_168 (KEY_D_1_160 + 1)
|
||||||
|
#define KEY_D_1_175 (KEY_D_1_168 + 1)
|
||||||
|
#define KEY_D_1_176 (KEY_D_1_175 + 1)
|
||||||
|
#define KEY_D_1_178 (KEY_D_1_176 + 1)
|
||||||
|
#define KEY_D_1_179 (KEY_D_1_178 + 1)
|
||||||
|
#define KEY_D_1_218 (KEY_D_1_179 + 1)
|
||||||
|
#define KEY_D_1_232 (KEY_D_1_218 + 1)
|
||||||
|
#define KEY_D_1_236 (KEY_D_1_232 + 1)
|
||||||
|
#define KEY_D_1_240 (KEY_D_1_236 + 1)
|
||||||
|
#define KEY_D_1_244 (KEY_D_1_240 + 1)
|
||||||
|
#define KEY_D_1_250 (KEY_D_1_244 + 1)
|
||||||
|
#define KEY_D_1_252 (KEY_D_1_250 + 1)
|
||||||
|
#define KEY_D_2_12 (KEY_D_1_252 + 1)
|
||||||
|
#define KEY_D_2_96 (KEY_D_2_12 + 1)
|
||||||
|
#define KEY_D_2_108 (KEY_D_2_96 + 1)
|
||||||
|
#define KEY_D_2_208 (KEY_D_2_108 + 1)
|
||||||
|
#define KEY_FLICK_MSG (KEY_D_2_208 + 1)
|
||||||
|
#define KEY_FLICK_COUNTER (KEY_FLICK_MSG + 1)
|
||||||
|
#define KEY_FLICK_LOWER (KEY_FLICK_COUNTER + 1)
|
||||||
|
#define KEY_CFG_FLICK_IN (KEY_FLICK_LOWER + 1)
|
||||||
|
#define KEY_FLICK_UPPER (KEY_CFG_FLICK_IN + 1)
|
||||||
|
#define KEY_CGNOTICE_INTR (KEY_FLICK_UPPER + 1)
|
||||||
|
#define KEY_D_2_224 (KEY_CGNOTICE_INTR + 1)
|
||||||
|
#define KEY_D_2_244 (KEY_D_2_224 + 1)
|
||||||
|
#define KEY_D_2_248 (KEY_D_2_244 + 1)
|
||||||
|
#define KEY_D_2_252 (KEY_D_2_248 + 1)
|
||||||
|
|
||||||
|
#define KEY_D_GYRO_BIAS_X (KEY_D_2_252 + 1)
|
||||||
|
#define KEY_D_GYRO_BIAS_Y (KEY_D_GYRO_BIAS_X + 1)
|
||||||
|
#define KEY_D_GYRO_BIAS_Z (KEY_D_GYRO_BIAS_Y + 1)
|
||||||
|
#define KEY_D_ACC_BIAS_X (KEY_D_GYRO_BIAS_Z + 1)
|
||||||
|
#define KEY_D_ACC_BIAS_Y (KEY_D_ACC_BIAS_X + 1)
|
||||||
|
#define KEY_D_ACC_BIAS_Z (KEY_D_ACC_BIAS_Y + 1)
|
||||||
|
#define KEY_D_GYRO_ENABLE (KEY_D_ACC_BIAS_Z + 1)
|
||||||
|
#define KEY_D_ACCEL_ENABLE (KEY_D_GYRO_ENABLE + 1)
|
||||||
|
#define KEY_D_QUAT_ENABLE (KEY_D_ACCEL_ENABLE +1)
|
||||||
|
#define KEY_D_OUTPUT_ENABLE (KEY_D_QUAT_ENABLE + 1)
|
||||||
|
#define KEY_D_CR_TIME_G (KEY_D_OUTPUT_ENABLE + 1)
|
||||||
|
#define KEY_D_CR_TIME_A (KEY_D_CR_TIME_G + 1)
|
||||||
|
#define KEY_D_CR_TIME_Q (KEY_D_CR_TIME_A + 1)
|
||||||
|
#define KEY_D_CS_TAX (KEY_D_CR_TIME_Q + 1)
|
||||||
|
#define KEY_D_CS_TAY (KEY_D_CS_TAX + 1)
|
||||||
|
#define KEY_D_CS_TAZ (KEY_D_CS_TAY + 1)
|
||||||
|
#define KEY_D_CS_TGX (KEY_D_CS_TAZ + 1)
|
||||||
|
#define KEY_D_CS_TGY (KEY_D_CS_TGX + 1)
|
||||||
|
#define KEY_D_CS_TGZ (KEY_D_CS_TGY + 1)
|
||||||
|
#define KEY_D_CS_TQ0 (KEY_D_CS_TGZ + 1)
|
||||||
|
#define KEY_D_CS_TQ1 (KEY_D_CS_TQ0 + 1)
|
||||||
|
#define KEY_D_CS_TQ2 (KEY_D_CS_TQ1 + 1)
|
||||||
|
#define KEY_D_CS_TQ3 (KEY_D_CS_TQ2 + 1)
|
||||||
|
|
||||||
|
/* Compass keys */
|
||||||
|
#define KEY_CPASS_BIAS_X (KEY_D_CS_TQ3 + 1)
|
||||||
|
#define KEY_CPASS_BIAS_Y (KEY_CPASS_BIAS_X + 1)
|
||||||
|
#define KEY_CPASS_BIAS_Z (KEY_CPASS_BIAS_Y + 1)
|
||||||
|
#define KEY_CPASS_MTX_00 (KEY_CPASS_BIAS_Z + 1)
|
||||||
|
#define KEY_CPASS_MTX_01 (KEY_CPASS_MTX_00 + 1)
|
||||||
|
#define KEY_CPASS_MTX_02 (KEY_CPASS_MTX_01 + 1)
|
||||||
|
#define KEY_CPASS_MTX_10 (KEY_CPASS_MTX_02 + 1)
|
||||||
|
#define KEY_CPASS_MTX_11 (KEY_CPASS_MTX_10 + 1)
|
||||||
|
#define KEY_CPASS_MTX_12 (KEY_CPASS_MTX_11 + 1)
|
||||||
|
#define KEY_CPASS_MTX_20 (KEY_CPASS_MTX_12 + 1)
|
||||||
|
#define KEY_CPASS_MTX_21 (KEY_CPASS_MTX_20 + 1)
|
||||||
|
#define KEY_CPASS_MTX_22 (KEY_CPASS_MTX_21 + 1)
|
||||||
|
|
||||||
|
/* Gesture Keys */
|
||||||
|
#define KEY_DMP_TAPW_MIN (KEY_CPASS_MTX_22 + 1)
|
||||||
|
#define KEY_DMP_TAP_THR_X (KEY_DMP_TAPW_MIN + 1)
|
||||||
|
#define KEY_DMP_TAP_THR_Y (KEY_DMP_TAP_THR_X + 1)
|
||||||
|
#define KEY_DMP_TAP_THR_Z (KEY_DMP_TAP_THR_Y + 1)
|
||||||
|
#define KEY_DMP_SH_TH_Y (KEY_DMP_TAP_THR_Z + 1)
|
||||||
|
#define KEY_DMP_SH_TH_X (KEY_DMP_SH_TH_Y + 1)
|
||||||
|
#define KEY_DMP_SH_TH_Z (KEY_DMP_SH_TH_X + 1)
|
||||||
|
#define KEY_DMP_ORIENT (KEY_DMP_SH_TH_Z + 1)
|
||||||
|
#define KEY_D_ACT0 (KEY_DMP_ORIENT + 1)
|
||||||
|
#define KEY_D_ACSX (KEY_D_ACT0 + 1)
|
||||||
|
#define KEY_D_ACSY (KEY_D_ACSX + 1)
|
||||||
|
#define KEY_D_ACSZ (KEY_D_ACSY + 1)
|
||||||
|
|
||||||
|
#define KEY_X_GRT_Y_TMP (KEY_D_ACSZ + 1)
|
||||||
|
#define KEY_SKIP_X_GRT_Y_TMP (KEY_X_GRT_Y_TMP + 1)
|
||||||
|
#define KEY_SKIP_END_COMPARE (KEY_SKIP_X_GRT_Y_TMP + 1)
|
||||||
|
#define KEY_END_COMPARE_Y_X_TMP2 (KEY_SKIP_END_COMPARE + 1)
|
||||||
|
#define KEY_CFG_ANDROID_ORIENT_INT (KEY_END_COMPARE_Y_X_TMP2 + 1)
|
||||||
|
#define KEY_NO_ORIENT_INTERRUPT (KEY_CFG_ANDROID_ORIENT_INT + 1)
|
||||||
|
#define KEY_END_COMPARE_Y_X_TMP (KEY_NO_ORIENT_INTERRUPT + 1)
|
||||||
|
#define KEY_END_ORIENT_1 (KEY_END_COMPARE_Y_X_TMP + 1)
|
||||||
|
#define KEY_END_COMPARE_Y_X (KEY_END_ORIENT_1 + 1)
|
||||||
|
#define KEY_END_ORIENT (KEY_END_COMPARE_Y_X + 1)
|
||||||
|
#define KEY_X_GRT_Y (KEY_END_ORIENT + 1)
|
||||||
|
#define KEY_NOT_TIME_MINUS_1 (KEY_X_GRT_Y + 1)
|
||||||
|
#define KEY_END_COMPARE_Y_X_TMP3 (KEY_NOT_TIME_MINUS_1 + 1)
|
||||||
|
#define KEY_X_GRT_Y_TMP2 (KEY_END_COMPARE_Y_X_TMP3 + 1)
|
||||||
|
|
||||||
|
/* Authenticate Keys */
|
||||||
|
#define KEY_D_AUTH_OUT (KEY_X_GRT_Y_TMP2 + 1)
|
||||||
|
#define KEY_D_AUTH_IN (KEY_D_AUTH_OUT + 1)
|
||||||
|
#define KEY_D_AUTH_A (KEY_D_AUTH_IN + 1)
|
||||||
|
#define KEY_D_AUTH_B (KEY_D_AUTH_A + 1)
|
||||||
|
|
||||||
|
/* Pedometer standalone only keys */
|
||||||
|
#define KEY_D_PEDSTD_BP_B (KEY_D_AUTH_B + 1)
|
||||||
|
#define KEY_D_PEDSTD_HP_A (KEY_D_PEDSTD_BP_B + 1)
|
||||||
|
#define KEY_D_PEDSTD_HP_B (KEY_D_PEDSTD_HP_A + 1)
|
||||||
|
#define KEY_D_PEDSTD_BP_A4 (KEY_D_PEDSTD_HP_B + 1)
|
||||||
|
#define KEY_D_PEDSTD_BP_A3 (KEY_D_PEDSTD_BP_A4 + 1)
|
||||||
|
#define KEY_D_PEDSTD_BP_A2 (KEY_D_PEDSTD_BP_A3 + 1)
|
||||||
|
#define KEY_D_PEDSTD_BP_A1 (KEY_D_PEDSTD_BP_A2 + 1)
|
||||||
|
#define KEY_D_PEDSTD_INT_THRSH (KEY_D_PEDSTD_BP_A1 + 1)
|
||||||
|
#define KEY_D_PEDSTD_CLIP (KEY_D_PEDSTD_INT_THRSH + 1)
|
||||||
|
#define KEY_D_PEDSTD_SB (KEY_D_PEDSTD_CLIP + 1)
|
||||||
|
#define KEY_D_PEDSTD_SB_TIME (KEY_D_PEDSTD_SB + 1)
|
||||||
|
#define KEY_D_PEDSTD_PEAKTHRSH (KEY_D_PEDSTD_SB_TIME + 1)
|
||||||
|
#define KEY_D_PEDSTD_TIML (KEY_D_PEDSTD_PEAKTHRSH + 1)
|
||||||
|
#define KEY_D_PEDSTD_TIMH (KEY_D_PEDSTD_TIML + 1)
|
||||||
|
#define KEY_D_PEDSTD_PEAK (KEY_D_PEDSTD_TIMH + 1)
|
||||||
|
#define KEY_D_PEDSTD_TIMECTR (KEY_D_PEDSTD_PEAK + 1)
|
||||||
|
#define KEY_D_PEDSTD_STEPCTR (KEY_D_PEDSTD_TIMECTR + 1)
|
||||||
|
#define KEY_D_PEDSTD_WALKTIME (KEY_D_PEDSTD_STEPCTR + 1)
|
||||||
|
#define KEY_D_PEDSTD_DECI (KEY_D_PEDSTD_WALKTIME + 1)
|
||||||
|
|
||||||
|
/*Host Based No Motion*/
|
||||||
|
#define KEY_D_HOST_NO_MOT (KEY_D_PEDSTD_DECI + 1)
|
||||||
|
|
||||||
|
/* EIS keys */
|
||||||
|
#define KEY_P_EIS_FIFO_FOOTER (KEY_D_HOST_NO_MOT + 1)
|
||||||
|
#define KEY_P_EIS_FIFO_YSHIFT (KEY_P_EIS_FIFO_FOOTER + 1)
|
||||||
|
#define KEY_P_EIS_DATA_RATE (KEY_P_EIS_FIFO_YSHIFT + 1)
|
||||||
|
#define KEY_P_EIS_FIFO_XSHIFT (KEY_P_EIS_DATA_RATE + 1)
|
||||||
|
#define KEY_P_EIS_FIFO_SYNC (KEY_P_EIS_FIFO_XSHIFT + 1)
|
||||||
|
#define KEY_P_EIS_FIFO_ZSHIFT (KEY_P_EIS_FIFO_SYNC + 1)
|
||||||
|
#define KEY_P_EIS_FIFO_READY (KEY_P_EIS_FIFO_ZSHIFT + 1)
|
||||||
|
#define KEY_DMP_FOOTER (KEY_P_EIS_FIFO_READY + 1)
|
||||||
|
#define KEY_DMP_INTX_HC (KEY_DMP_FOOTER + 1)
|
||||||
|
#define KEY_DMP_INTX_PH (KEY_DMP_INTX_HC + 1)
|
||||||
|
#define KEY_DMP_INTX_SH (KEY_DMP_INTX_PH + 1)
|
||||||
|
#define KEY_DMP_AINV_SH (KEY_DMP_INTX_SH + 1)
|
||||||
|
#define KEY_DMP_A_INV_XH (KEY_DMP_AINV_SH + 1)
|
||||||
|
#define KEY_DMP_AINV_PH (KEY_DMP_A_INV_XH + 1)
|
||||||
|
#define KEY_DMP_CTHX_H (KEY_DMP_AINV_PH + 1)
|
||||||
|
#define KEY_DMP_CTHY_H (KEY_DMP_CTHX_H + 1)
|
||||||
|
#define KEY_DMP_CTHZ_H (KEY_DMP_CTHY_H + 1)
|
||||||
|
#define KEY_DMP_NCTHX_H (KEY_DMP_CTHZ_H + 1)
|
||||||
|
#define KEY_DMP_NCTHY_H (KEY_DMP_NCTHX_H + 1)
|
||||||
|
#define KEY_DMP_NCTHZ_H (KEY_DMP_NCTHY_H + 1)
|
||||||
|
#define KEY_DMP_CTSQ_XH (KEY_DMP_NCTHZ_H + 1)
|
||||||
|
#define KEY_DMP_CTSQ_YH (KEY_DMP_CTSQ_XH + 1)
|
||||||
|
#define KEY_DMP_CTSQ_ZH (KEY_DMP_CTSQ_YH + 1)
|
||||||
|
#define KEY_DMP_INTX_H (KEY_DMP_CTSQ_ZH + 1)
|
||||||
|
#define KEY_DMP_INTY_H (KEY_DMP_INTX_H + 1)
|
||||||
|
#define KEY_DMP_INTZ_H (KEY_DMP_INTY_H + 1)
|
||||||
|
//#define KEY_DMP_HPX_H (KEY_DMP_INTZ_H + 1)
|
||||||
|
//#define KEY_DMP_HPY_H (KEY_DMP_HPX_H + 1)
|
||||||
|
//#define KEY_DMP_HPZ_H (KEY_DMP_HPY_H + 1)
|
||||||
|
|
||||||
|
/* Stream keys */
|
||||||
|
#define KEY_STREAM_P_GYRO_Z (KEY_DMP_INTZ_H + 1)
|
||||||
|
#define KEY_STREAM_P_GYRO_Y (KEY_STREAM_P_GYRO_Z + 1)
|
||||||
|
#define KEY_STREAM_P_GYRO_X (KEY_STREAM_P_GYRO_Y + 1)
|
||||||
|
#define KEY_STREAM_P_TEMP (KEY_STREAM_P_GYRO_X + 1)
|
||||||
|
#define KEY_STREAM_P_AUX_Y (KEY_STREAM_P_TEMP + 1)
|
||||||
|
#define KEY_STREAM_P_AUX_X (KEY_STREAM_P_AUX_Y + 1)
|
||||||
|
#define KEY_STREAM_P_AUX_Z (KEY_STREAM_P_AUX_X + 1)
|
||||||
|
#define KEY_STREAM_P_ACCEL_Y (KEY_STREAM_P_AUX_Z + 1)
|
||||||
|
#define KEY_STREAM_P_ACCEL_X (KEY_STREAM_P_ACCEL_Y + 1)
|
||||||
|
#define KEY_STREAM_P_FOOTER (KEY_STREAM_P_ACCEL_X + 1)
|
||||||
|
#define KEY_STREAM_P_ACCEL_Z (KEY_STREAM_P_FOOTER + 1)
|
||||||
|
|
||||||
|
#define NUM_KEYS (KEY_STREAM_P_ACCEL_Z + 1)
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
unsigned short key;
|
||||||
|
unsigned short addr;
|
||||||
|
} tKeyLabel;
|
||||||
|
|
||||||
|
#define DINA0A 0x0a
|
||||||
|
#define DINA22 0x22
|
||||||
|
#define DINA42 0x42
|
||||||
|
#define DINA5A 0x5a
|
||||||
|
|
||||||
|
#define DINA06 0x06
|
||||||
|
#define DINA0E 0x0e
|
||||||
|
#define DINA16 0x16
|
||||||
|
#define DINA1E 0x1e
|
||||||
|
#define DINA26 0x26
|
||||||
|
#define DINA2E 0x2e
|
||||||
|
#define DINA36 0x36
|
||||||
|
#define DINA3E 0x3e
|
||||||
|
#define DINA46 0x46
|
||||||
|
#define DINA4E 0x4e
|
||||||
|
#define DINA56 0x56
|
||||||
|
#define DINA5E 0x5e
|
||||||
|
#define DINA66 0x66
|
||||||
|
#define DINA6E 0x6e
|
||||||
|
#define DINA76 0x76
|
||||||
|
#define DINA7E 0x7e
|
||||||
|
|
||||||
|
#define DINA00 0x00
|
||||||
|
#define DINA08 0x08
|
||||||
|
#define DINA10 0x10
|
||||||
|
#define DINA18 0x18
|
||||||
|
#define DINA20 0x20
|
||||||
|
#define DINA28 0x28
|
||||||
|
#define DINA30 0x30
|
||||||
|
#define DINA38 0x38
|
||||||
|
#define DINA40 0x40
|
||||||
|
#define DINA48 0x48
|
||||||
|
#define DINA50 0x50
|
||||||
|
#define DINA58 0x58
|
||||||
|
#define DINA60 0x60
|
||||||
|
#define DINA68 0x68
|
||||||
|
#define DINA70 0x70
|
||||||
|
#define DINA78 0x78
|
||||||
|
|
||||||
|
#define DINA04 0x04
|
||||||
|
#define DINA0C 0x0c
|
||||||
|
#define DINA14 0x14
|
||||||
|
#define DINA1C 0x1C
|
||||||
|
#define DINA24 0x24
|
||||||
|
#define DINA2C 0x2c
|
||||||
|
#define DINA34 0x34
|
||||||
|
#define DINA3C 0x3c
|
||||||
|
#define DINA44 0x44
|
||||||
|
#define DINA4C 0x4c
|
||||||
|
#define DINA54 0x54
|
||||||
|
#define DINA5C 0x5c
|
||||||
|
#define DINA64 0x64
|
||||||
|
#define DINA6C 0x6c
|
||||||
|
#define DINA74 0x74
|
||||||
|
#define DINA7C 0x7c
|
||||||
|
|
||||||
|
#define DINA01 0x01
|
||||||
|
#define DINA09 0x09
|
||||||
|
#define DINA11 0x11
|
||||||
|
#define DINA19 0x19
|
||||||
|
#define DINA21 0x21
|
||||||
|
#define DINA29 0x29
|
||||||
|
#define DINA31 0x31
|
||||||
|
#define DINA39 0x39
|
||||||
|
#define DINA41 0x41
|
||||||
|
#define DINA49 0x49
|
||||||
|
#define DINA51 0x51
|
||||||
|
#define DINA59 0x59
|
||||||
|
#define DINA61 0x61
|
||||||
|
#define DINA69 0x69
|
||||||
|
#define DINA71 0x71
|
||||||
|
#define DINA79 0x79
|
||||||
|
|
||||||
|
#define DINA25 0x25
|
||||||
|
#define DINA2D 0x2d
|
||||||
|
#define DINA35 0x35
|
||||||
|
#define DINA3D 0x3d
|
||||||
|
#define DINA4D 0x4d
|
||||||
|
#define DINA55 0x55
|
||||||
|
#define DINA5D 0x5D
|
||||||
|
#define DINA6D 0x6d
|
||||||
|
#define DINA75 0x75
|
||||||
|
#define DINA7D 0x7d
|
||||||
|
|
||||||
|
#define DINADC 0xdc
|
||||||
|
#define DINAF2 0xf2
|
||||||
|
#define DINAAB 0xab
|
||||||
|
#define DINAAA 0xaa
|
||||||
|
#define DINAF1 0xf1
|
||||||
|
#define DINADF 0xdf
|
||||||
|
#define DINADA 0xda
|
||||||
|
#define DINAB1 0xb1
|
||||||
|
#define DINAB9 0xb9
|
||||||
|
#define DINAF3 0xf3
|
||||||
|
#define DINA8B 0x8b
|
||||||
|
#define DINAA3 0xa3
|
||||||
|
#define DINA91 0x91
|
||||||
|
#define DINAB6 0xb6
|
||||||
|
#define DINAB4 0xb4
|
||||||
|
|
||||||
|
|
||||||
|
#define DINC00 0x00
|
||||||
|
#define DINC01 0x01
|
||||||
|
#define DINC02 0x02
|
||||||
|
#define DINC03 0x03
|
||||||
|
#define DINC08 0x08
|
||||||
|
#define DINC09 0x09
|
||||||
|
#define DINC0A 0x0a
|
||||||
|
#define DINC0B 0x0b
|
||||||
|
#define DINC10 0x10
|
||||||
|
#define DINC11 0x11
|
||||||
|
#define DINC12 0x12
|
||||||
|
#define DINC13 0x13
|
||||||
|
#define DINC18 0x18
|
||||||
|
#define DINC19 0x19
|
||||||
|
#define DINC1A 0x1a
|
||||||
|
#define DINC1B 0x1b
|
||||||
|
|
||||||
|
#define DINC20 0x20
|
||||||
|
#define DINC21 0x21
|
||||||
|
#define DINC22 0x22
|
||||||
|
#define DINC23 0x23
|
||||||
|
#define DINC28 0x28
|
||||||
|
#define DINC29 0x29
|
||||||
|
#define DINC2A 0x2a
|
||||||
|
#define DINC2B 0x2b
|
||||||
|
#define DINC30 0x30
|
||||||
|
#define DINC31 0x31
|
||||||
|
#define DINC32 0x32
|
||||||
|
#define DINC33 0x33
|
||||||
|
#define DINC38 0x38
|
||||||
|
#define DINC39 0x39
|
||||||
|
#define DINC3A 0x3a
|
||||||
|
#define DINC3B 0x3b
|
||||||
|
|
||||||
|
#define DINC40 0x40
|
||||||
|
#define DINC41 0x41
|
||||||
|
#define DINC42 0x42
|
||||||
|
#define DINC43 0x43
|
||||||
|
#define DINC48 0x48
|
||||||
|
#define DINC49 0x49
|
||||||
|
#define DINC4A 0x4a
|
||||||
|
#define DINC4B 0x4b
|
||||||
|
#define DINC50 0x50
|
||||||
|
#define DINC51 0x51
|
||||||
|
#define DINC52 0x52
|
||||||
|
#define DINC53 0x53
|
||||||
|
#define DINC58 0x58
|
||||||
|
#define DINC59 0x59
|
||||||
|
#define DINC5A 0x5a
|
||||||
|
#define DINC5B 0x5b
|
||||||
|
|
||||||
|
#define DINC60 0x60
|
||||||
|
#define DINC61 0x61
|
||||||
|
#define DINC62 0x62
|
||||||
|
#define DINC63 0x63
|
||||||
|
#define DINC68 0x68
|
||||||
|
#define DINC69 0x69
|
||||||
|
#define DINC6A 0x6a
|
||||||
|
#define DINC6B 0x6b
|
||||||
|
#define DINC70 0x70
|
||||||
|
#define DINC71 0x71
|
||||||
|
#define DINC72 0x72
|
||||||
|
#define DINC73 0x73
|
||||||
|
#define DINC78 0x78
|
||||||
|
#define DINC79 0x79
|
||||||
|
#define DINC7A 0x7a
|
||||||
|
#define DINC7B 0x7b
|
||||||
|
|
||||||
|
#define DIND40 0x40
|
||||||
|
|
||||||
|
|
||||||
|
#define DINA80 0x80
|
||||||
|
#define DINA90 0x90
|
||||||
|
#define DINAA0 0xa0
|
||||||
|
#define DINAC9 0xc9
|
||||||
|
#define DINACB 0xcb
|
||||||
|
#define DINACD 0xcd
|
||||||
|
#define DINACF 0xcf
|
||||||
|
#define DINAC8 0xc8
|
||||||
|
#define DINACA 0xca
|
||||||
|
#define DINACC 0xcc
|
||||||
|
#define DINACE 0xce
|
||||||
|
#define DINAD8 0xd8
|
||||||
|
#define DINADD 0xdd
|
||||||
|
#define DINAF8 0xf0
|
||||||
|
#define DINAFE 0xfe
|
||||||
|
|
||||||
|
#define DINBF8 0xf8
|
||||||
|
#define DINAC0 0xb0
|
||||||
|
#define DINAC1 0xb1
|
||||||
|
#define DINAC2 0xb4
|
||||||
|
#define DINAC3 0xb5
|
||||||
|
#define DINAC4 0xb8
|
||||||
|
#define DINAC5 0xb9
|
||||||
|
#define DINBC0 0xc0
|
||||||
|
#define DINBC2 0xc2
|
||||||
|
#define DINBC4 0xc4
|
||||||
|
#define DINBC6 0xc6
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif // DMPKEY_H__
|
||||||
|
|
@ -0,0 +1,264 @@
|
||||||
|
/*
|
||||||
|
$License:
|
||||||
|
Copyright (C) 2011 InvenSense Corporation, All Rights Reserved.
|
||||||
|
$
|
||||||
|
*/
|
||||||
|
#ifndef DMPMAP_H
|
||||||
|
#define DMPMAP_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define DMP_PTAT 0
|
||||||
|
#define DMP_XGYR 2
|
||||||
|
#define DMP_YGYR 4
|
||||||
|
#define DMP_ZGYR 6
|
||||||
|
#define DMP_XACC 8
|
||||||
|
#define DMP_YACC 10
|
||||||
|
#define DMP_ZACC 12
|
||||||
|
#define DMP_ADC1 14
|
||||||
|
#define DMP_ADC2 16
|
||||||
|
#define DMP_ADC3 18
|
||||||
|
#define DMP_BIASUNC 20
|
||||||
|
#define DMP_FIFORT 22
|
||||||
|
#define DMP_INVGSFH 24
|
||||||
|
#define DMP_INVGSFL 26
|
||||||
|
#define DMP_1H 28
|
||||||
|
#define DMP_1L 30
|
||||||
|
#define DMP_BLPFSTCH 32
|
||||||
|
#define DMP_BLPFSTCL 34
|
||||||
|
#define DMP_BLPFSXH 36
|
||||||
|
#define DMP_BLPFSXL 38
|
||||||
|
#define DMP_BLPFSYH 40
|
||||||
|
#define DMP_BLPFSYL 42
|
||||||
|
#define DMP_BLPFSZH 44
|
||||||
|
#define DMP_BLPFSZL 46
|
||||||
|
#define DMP_BLPFMTC 48
|
||||||
|
#define DMP_SMC 50
|
||||||
|
#define DMP_BLPFMXH 52
|
||||||
|
#define DMP_BLPFMXL 54
|
||||||
|
#define DMP_BLPFMYH 56
|
||||||
|
#define DMP_BLPFMYL 58
|
||||||
|
#define DMP_BLPFMZH 60
|
||||||
|
#define DMP_BLPFMZL 62
|
||||||
|
#define DMP_BLPFC 64
|
||||||
|
#define DMP_SMCTH 66
|
||||||
|
#define DMP_0H2 68
|
||||||
|
#define DMP_0L2 70
|
||||||
|
#define DMP_BERR2H 72
|
||||||
|
#define DMP_BERR2L 74
|
||||||
|
#define DMP_BERR2NH 76
|
||||||
|
#define DMP_SMCINC 78
|
||||||
|
#define DMP_ANGVBXH 80
|
||||||
|
#define DMP_ANGVBXL 82
|
||||||
|
#define DMP_ANGVBYH 84
|
||||||
|
#define DMP_ANGVBYL 86
|
||||||
|
#define DMP_ANGVBZH 88
|
||||||
|
#define DMP_ANGVBZL 90
|
||||||
|
#define DMP_BERR1H 92
|
||||||
|
#define DMP_BERR1L 94
|
||||||
|
#define DMP_ATCH 96
|
||||||
|
#define DMP_BIASUNCSF 98
|
||||||
|
#define DMP_ACT2H 100
|
||||||
|
#define DMP_ACT2L 102
|
||||||
|
#define DMP_GSFH 104
|
||||||
|
#define DMP_GSFL 106
|
||||||
|
#define DMP_GH 108
|
||||||
|
#define DMP_GL 110
|
||||||
|
#define DMP_0_5H 112
|
||||||
|
#define DMP_0_5L 114
|
||||||
|
#define DMP_0_0H 116
|
||||||
|
#define DMP_0_0L 118
|
||||||
|
#define DMP_1_0H 120
|
||||||
|
#define DMP_1_0L 122
|
||||||
|
#define DMP_1_5H 124
|
||||||
|
#define DMP_1_5L 126
|
||||||
|
#define DMP_TMP1AH 128
|
||||||
|
#define DMP_TMP1AL 130
|
||||||
|
#define DMP_TMP2AH 132
|
||||||
|
#define DMP_TMP2AL 134
|
||||||
|
#define DMP_TMP3AH 136
|
||||||
|
#define DMP_TMP3AL 138
|
||||||
|
#define DMP_TMP4AH 140
|
||||||
|
#define DMP_TMP4AL 142
|
||||||
|
#define DMP_XACCW 144
|
||||||
|
#define DMP_TMP5 146
|
||||||
|
#define DMP_XACCB 148
|
||||||
|
#define DMP_TMP8 150
|
||||||
|
#define DMP_YACCB 152
|
||||||
|
#define DMP_TMP9 154
|
||||||
|
#define DMP_ZACCB 156
|
||||||
|
#define DMP_TMP10 158
|
||||||
|
#define DMP_DZH 160
|
||||||
|
#define DMP_DZL 162
|
||||||
|
#define DMP_XGCH 164
|
||||||
|
#define DMP_XGCL 166
|
||||||
|
#define DMP_YGCH 168
|
||||||
|
#define DMP_YGCL 170
|
||||||
|
#define DMP_ZGCH 172
|
||||||
|
#define DMP_ZGCL 174
|
||||||
|
#define DMP_YACCW 176
|
||||||
|
#define DMP_TMP7 178
|
||||||
|
#define DMP_AFB1H 180
|
||||||
|
#define DMP_AFB1L 182
|
||||||
|
#define DMP_AFB2H 184
|
||||||
|
#define DMP_AFB2L 186
|
||||||
|
#define DMP_MAGFBH 188
|
||||||
|
#define DMP_MAGFBL 190
|
||||||
|
#define DMP_QT1H 192
|
||||||
|
#define DMP_QT1L 194
|
||||||
|
#define DMP_QT2H 196
|
||||||
|
#define DMP_QT2L 198
|
||||||
|
#define DMP_QT3H 200
|
||||||
|
#define DMP_QT3L 202
|
||||||
|
#define DMP_QT4H 204
|
||||||
|
#define DMP_QT4L 206
|
||||||
|
#define DMP_CTRL1H 208
|
||||||
|
#define DMP_CTRL1L 210
|
||||||
|
#define DMP_CTRL2H 212
|
||||||
|
#define DMP_CTRL2L 214
|
||||||
|
#define DMP_CTRL3H 216
|
||||||
|
#define DMP_CTRL3L 218
|
||||||
|
#define DMP_CTRL4H 220
|
||||||
|
#define DMP_CTRL4L 222
|
||||||
|
#define DMP_CTRLS1 224
|
||||||
|
#define DMP_CTRLSF1 226
|
||||||
|
#define DMP_CTRLS2 228
|
||||||
|
#define DMP_CTRLSF2 230
|
||||||
|
#define DMP_CTRLS3 232
|
||||||
|
#define DMP_CTRLSFNLL 234
|
||||||
|
#define DMP_CTRLS4 236
|
||||||
|
#define DMP_CTRLSFNL2 238
|
||||||
|
#define DMP_CTRLSFNL 240
|
||||||
|
#define DMP_TMP30 242
|
||||||
|
#define DMP_CTRLSFJT 244
|
||||||
|
#define DMP_TMP31 246
|
||||||
|
#define DMP_TMP11 248
|
||||||
|
#define DMP_CTRLSF2_2 250
|
||||||
|
#define DMP_TMP12 252
|
||||||
|
#define DMP_CTRLSF1_2 254
|
||||||
|
#define DMP_PREVPTAT 256
|
||||||
|
#define DMP_ACCZB 258
|
||||||
|
#define DMP_ACCXB 264
|
||||||
|
#define DMP_ACCYB 266
|
||||||
|
#define DMP_1HB 272
|
||||||
|
#define DMP_1LB 274
|
||||||
|
#define DMP_0H 276
|
||||||
|
#define DMP_0L 278
|
||||||
|
#define DMP_ASR22H 280
|
||||||
|
#define DMP_ASR22L 282
|
||||||
|
#define DMP_ASR6H 284
|
||||||
|
#define DMP_ASR6L 286
|
||||||
|
#define DMP_TMP13 288
|
||||||
|
#define DMP_TMP14 290
|
||||||
|
#define DMP_FINTXH 292
|
||||||
|
#define DMP_FINTXL 294
|
||||||
|
#define DMP_FINTYH 296
|
||||||
|
#define DMP_FINTYL 298
|
||||||
|
#define DMP_FINTZH 300
|
||||||
|
#define DMP_FINTZL 302
|
||||||
|
#define DMP_TMP1BH 304
|
||||||
|
#define DMP_TMP1BL 306
|
||||||
|
#define DMP_TMP2BH 308
|
||||||
|
#define DMP_TMP2BL 310
|
||||||
|
#define DMP_TMP3BH 312
|
||||||
|
#define DMP_TMP3BL 314
|
||||||
|
#define DMP_TMP4BH 316
|
||||||
|
#define DMP_TMP4BL 318
|
||||||
|
#define DMP_STXG 320
|
||||||
|
#define DMP_ZCTXG 322
|
||||||
|
#define DMP_STYG 324
|
||||||
|
#define DMP_ZCTYG 326
|
||||||
|
#define DMP_STZG 328
|
||||||
|
#define DMP_ZCTZG 330
|
||||||
|
#define DMP_CTRLSFJT2 332
|
||||||
|
#define DMP_CTRLSFJTCNT 334
|
||||||
|
#define DMP_PVXG 336
|
||||||
|
#define DMP_TMP15 338
|
||||||
|
#define DMP_PVYG 340
|
||||||
|
#define DMP_TMP16 342
|
||||||
|
#define DMP_PVZG 344
|
||||||
|
#define DMP_TMP17 346
|
||||||
|
#define DMP_MNMFLAGH 352
|
||||||
|
#define DMP_MNMFLAGL 354
|
||||||
|
#define DMP_MNMTMH 356
|
||||||
|
#define DMP_MNMTML 358
|
||||||
|
#define DMP_MNMTMTHRH 360
|
||||||
|
#define DMP_MNMTMTHRL 362
|
||||||
|
#define DMP_MNMTHRH 364
|
||||||
|
#define DMP_MNMTHRL 366
|
||||||
|
#define DMP_ACCQD4H 368
|
||||||
|
#define DMP_ACCQD4L 370
|
||||||
|
#define DMP_ACCQD5H 372
|
||||||
|
#define DMP_ACCQD5L 374
|
||||||
|
#define DMP_ACCQD6H 376
|
||||||
|
#define DMP_ACCQD6L 378
|
||||||
|
#define DMP_ACCQD7H 380
|
||||||
|
#define DMP_ACCQD7L 382
|
||||||
|
#define DMP_ACCQD0H 384
|
||||||
|
#define DMP_ACCQD0L 386
|
||||||
|
#define DMP_ACCQD1H 388
|
||||||
|
#define DMP_ACCQD1L 390
|
||||||
|
#define DMP_ACCQD2H 392
|
||||||
|
#define DMP_ACCQD2L 394
|
||||||
|
#define DMP_ACCQD3H 396
|
||||||
|
#define DMP_ACCQD3L 398
|
||||||
|
#define DMP_XN2H 400
|
||||||
|
#define DMP_XN2L 402
|
||||||
|
#define DMP_XN1H 404
|
||||||
|
#define DMP_XN1L 406
|
||||||
|
#define DMP_YN2H 408
|
||||||
|
#define DMP_YN2L 410
|
||||||
|
#define DMP_YN1H 412
|
||||||
|
#define DMP_YN1L 414
|
||||||
|
#define DMP_YH 416
|
||||||
|
#define DMP_YL 418
|
||||||
|
#define DMP_B0H 420
|
||||||
|
#define DMP_B0L 422
|
||||||
|
#define DMP_A1H 424
|
||||||
|
#define DMP_A1L 426
|
||||||
|
#define DMP_A2H 428
|
||||||
|
#define DMP_A2L 430
|
||||||
|
#define DMP_SEM1 432
|
||||||
|
#define DMP_FIFOCNT 434
|
||||||
|
#define DMP_SH_TH_X 436
|
||||||
|
#define DMP_PACKET 438
|
||||||
|
#define DMP_SH_TH_Y 440
|
||||||
|
#define DMP_FOOTER 442
|
||||||
|
#define DMP_SH_TH_Z 444
|
||||||
|
#define DMP_TEMP29 448
|
||||||
|
#define DMP_TEMP30 450
|
||||||
|
#define DMP_XACCB_PRE 452
|
||||||
|
#define DMP_XACCB_PREL 454
|
||||||
|
#define DMP_YACCB_PRE 456
|
||||||
|
#define DMP_YACCB_PREL 458
|
||||||
|
#define DMP_ZACCB_PRE 460
|
||||||
|
#define DMP_ZACCB_PREL 462
|
||||||
|
#define DMP_TMP22 464
|
||||||
|
#define DMP_TAP_TIMER 466
|
||||||
|
#define DMP_TAP_THX 468
|
||||||
|
#define DMP_TAP_THY 472
|
||||||
|
#define DMP_TAP_THZ 476
|
||||||
|
#define DMP_TAPW_MIN 478
|
||||||
|
#define DMP_TMP25 480
|
||||||
|
#define DMP_TMP26 482
|
||||||
|
#define DMP_TMP27 484
|
||||||
|
#define DMP_TMP28 486
|
||||||
|
#define DMP_ORIENT 488
|
||||||
|
#define DMP_THRSH 490
|
||||||
|
#define DMP_ENDIANH 492
|
||||||
|
#define DMP_ENDIANL 494
|
||||||
|
#define DMP_BLPFNMTCH 496
|
||||||
|
#define DMP_BLPFNMTCL 498
|
||||||
|
#define DMP_BLPFNMXH 500
|
||||||
|
#define DMP_BLPFNMXL 502
|
||||||
|
#define DMP_BLPFNMYH 504
|
||||||
|
#define DMP_BLPFNMYL 506
|
||||||
|
#define DMP_BLPFNMZH 508
|
||||||
|
#define DMP_BLPFNMZL 510
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif // DMPMAP_H
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,122 @@
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup DRIVERS Sensor Driver Layer
|
||||||
|
* @brief Hardware drivers to communicate with sensors via I2C.
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
* @file inv_mpu.h
|
||||||
|
* @brief An I2C-based driver for Invensense gyroscopes.
|
||||||
|
* @details This driver currently works for the following devices:
|
||||||
|
* MPU6050
|
||||||
|
* MPU6500
|
||||||
|
* MPU9150 (or MPU6050 w/ AK8975 on the auxiliary bus)
|
||||||
|
* MPU9250 (or MPU6500 w/ AK8963 on the auxiliary bus)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _INV_MPU_H_
|
||||||
|
#define _INV_MPU_H_
|
||||||
|
|
||||||
|
#define INV_X_GYRO (0x40)
|
||||||
|
#define INV_Y_GYRO (0x20)
|
||||||
|
#define INV_Z_GYRO (0x10)
|
||||||
|
#define INV_XYZ_GYRO (INV_X_GYRO | INV_Y_GYRO | INV_Z_GYRO)
|
||||||
|
#define INV_XYZ_ACCEL (0x08)
|
||||||
|
#define INV_XYZ_COMPASS (0x01)
|
||||||
|
|
||||||
|
struct int_param_s {
|
||||||
|
//#if defined EMPL_TARGET_MSP430 || defined MOTION_DRIVER_TARGET_MSP430
|
||||||
|
void (*cb)(void);
|
||||||
|
unsigned short pin;
|
||||||
|
unsigned char lp_exit;
|
||||||
|
unsigned char active_low;
|
||||||
|
/*#elif defined EMPL_TARGET_UC3L0
|
||||||
|
unsigned long pin;
|
||||||
|
void (*cb)(volatile void*);
|
||||||
|
void *arg;
|
||||||
|
#endif */
|
||||||
|
};
|
||||||
|
|
||||||
|
#define MPU_INT_STATUS_DATA_READY (0x0001)
|
||||||
|
#define MPU_INT_STATUS_DMP (0x0002)
|
||||||
|
#define MPU_INT_STATUS_PLL_READY (0x0004)
|
||||||
|
#define MPU_INT_STATUS_I2C_MST (0x0008)
|
||||||
|
#define MPU_INT_STATUS_FIFO_OVERFLOW (0x0010)
|
||||||
|
#define MPU_INT_STATUS_ZMOT (0x0020)
|
||||||
|
#define MPU_INT_STATUS_MOT (0x0040)
|
||||||
|
#define MPU_INT_STATUS_FREE_FALL (0x0080)
|
||||||
|
#define MPU_INT_STATUS_DMP_0 (0x0100)
|
||||||
|
#define MPU_INT_STATUS_DMP_1 (0x0200)
|
||||||
|
#define MPU_INT_STATUS_DMP_2 (0x0400)
|
||||||
|
#define MPU_INT_STATUS_DMP_3 (0x0800)
|
||||||
|
#define MPU_INT_STATUS_DMP_4 (0x1000)
|
||||||
|
#define MPU_INT_STATUS_DMP_5 (0x2000)
|
||||||
|
|
||||||
|
/* Set up APIs */
|
||||||
|
int mpu_init(void);
|
||||||
|
int mpu_init_slave(void);
|
||||||
|
int mpu_set_bypass(unsigned char bypass_on);
|
||||||
|
|
||||||
|
/* Configuration APIs */
|
||||||
|
int mpu_lp_accel_mode(unsigned char rate);
|
||||||
|
int mpu_lp_motion_interrupt(unsigned short thresh, unsigned char time,
|
||||||
|
unsigned char lpa_freq);
|
||||||
|
int mpu_set_int_level(unsigned char active_low);
|
||||||
|
int mpu_set_int_latched(unsigned char enable);
|
||||||
|
|
||||||
|
int mpu_set_dmp_state(unsigned char enable);
|
||||||
|
int mpu_get_dmp_state(unsigned char *enabled);
|
||||||
|
|
||||||
|
int mpu_get_lpf(unsigned short *lpf);
|
||||||
|
int mpu_set_lpf(unsigned short lpf);
|
||||||
|
|
||||||
|
int mpu_get_gyro_fsr(unsigned short *fsr);
|
||||||
|
int mpu_set_gyro_fsr(unsigned short fsr);
|
||||||
|
|
||||||
|
int mpu_get_accel_fsr(unsigned char *fsr);
|
||||||
|
int mpu_set_accel_fsr(unsigned char fsr);
|
||||||
|
|
||||||
|
int mpu_get_compass_fsr(unsigned short *fsr);
|
||||||
|
|
||||||
|
int mpu_get_gyro_sens(float *sens);
|
||||||
|
int mpu_get_accel_sens(unsigned short *sens);
|
||||||
|
|
||||||
|
int mpu_get_sample_rate(unsigned short *rate);
|
||||||
|
int mpu_set_sample_rate(unsigned short rate);
|
||||||
|
int mpu_get_compass_sample_rate(unsigned short *rate);
|
||||||
|
int mpu_set_compass_sample_rate(unsigned short rate);
|
||||||
|
|
||||||
|
int mpu_get_fifo_config(unsigned char *sensors);
|
||||||
|
int mpu_configure_fifo(unsigned char sensors);
|
||||||
|
|
||||||
|
int mpu_get_power_state(unsigned char *power_on);
|
||||||
|
int mpu_set_sensors(unsigned char sensors);
|
||||||
|
|
||||||
|
int mpu_set_accel_bias(const long *accel_bias);
|
||||||
|
|
||||||
|
/* Data getter/setter APIs */
|
||||||
|
int mpu_get_gyro_reg(short *data, unsigned long *timestamp);
|
||||||
|
int mpu_get_accel_reg(short *data, unsigned long *timestamp);
|
||||||
|
int mpu_get_compass_reg(short *data, unsigned long *timestamp);
|
||||||
|
int mpu_get_temperature(long *data, unsigned long *timestamp);
|
||||||
|
|
||||||
|
int mpu_get_int_status(short *status);
|
||||||
|
int mpu_read_fifo(short *gyro, short *accel, unsigned long *timestamp,
|
||||||
|
unsigned char *sensors, unsigned char *more);
|
||||||
|
int mpu_read_fifo_stream(unsigned short length, unsigned char *data,
|
||||||
|
unsigned char *more);
|
||||||
|
int mpu_reset_fifo(void);
|
||||||
|
|
||||||
|
int mpu_write_mem(unsigned short mem_addr, unsigned short length,
|
||||||
|
unsigned char *data);
|
||||||
|
int mpu_read_mem(unsigned short mem_addr, unsigned short length,
|
||||||
|
unsigned char *data);
|
||||||
|
int mpu_load_firmware(unsigned short length, const unsigned char *firmware,
|
||||||
|
unsigned short start_addr, unsigned short sample_rate);
|
||||||
|
|
||||||
|
int mpu_reg_dump(void);
|
||||||
|
int mpu_read_reg(unsigned char reg, unsigned char *data);
|
||||||
|
int mpu_run_self_test(long *gyro, long *accel);
|
||||||
|
int mpu_register_tap_cb(void (*func)(unsigned char, unsigned char));
|
||||||
|
void myget_ms(unsigned long *time);
|
||||||
|
#endif /* #ifndef _INV_MPU_H_ */
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,92 @@
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @addtogroup DRIVERS Sensor Driver Layer
|
||||||
|
* @brief Hardware drivers to communicate with sensors via I2C.
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
* @file inv_mpu_dmp_motion_driver.h
|
||||||
|
* @brief DMP image and interface functions.
|
||||||
|
* @details All functions are preceded by the dmp_ prefix to
|
||||||
|
* differentiate among MPL and general driver function calls.
|
||||||
|
*/
|
||||||
|
#ifndef _INV_MPU_DMP_MOTION_DRIVER_H_
|
||||||
|
#define _INV_MPU_DMP_MOTION_DRIVER_H_
|
||||||
|
|
||||||
|
#define TAP_X (0x01)
|
||||||
|
#define TAP_Y (0x02)
|
||||||
|
#define TAP_Z (0x04)
|
||||||
|
#define TAP_XYZ (0x07)
|
||||||
|
|
||||||
|
#define TAP_X_UP (0x01)
|
||||||
|
#define TAP_X_DOWN (0x02)
|
||||||
|
#define TAP_Y_UP (0x03)
|
||||||
|
#define TAP_Y_DOWN (0x04)
|
||||||
|
#define TAP_Z_UP (0x05)
|
||||||
|
#define TAP_Z_DOWN (0x06)
|
||||||
|
|
||||||
|
#define ANDROID_ORIENT_PORTRAIT (0x00)
|
||||||
|
#define ANDROID_ORIENT_LANDSCAPE (0x01)
|
||||||
|
#define ANDROID_ORIENT_REVERSE_PORTRAIT (0x02)
|
||||||
|
#define ANDROID_ORIENT_REVERSE_LANDSCAPE (0x03)
|
||||||
|
|
||||||
|
#define DMP_INT_GESTURE (0x01)
|
||||||
|
#define DMP_INT_CONTINUOUS (0x02)
|
||||||
|
|
||||||
|
#define DMP_FEATURE_TAP (0x001)
|
||||||
|
#define DMP_FEATURE_ANDROID_ORIENT (0x002)
|
||||||
|
#define DMP_FEATURE_LP_QUAT (0x004)
|
||||||
|
#define DMP_FEATURE_PEDOMETER (0x008)
|
||||||
|
#define DMP_FEATURE_6X_LP_QUAT (0x010)
|
||||||
|
#define DMP_FEATURE_GYRO_CAL (0x020)
|
||||||
|
#define DMP_FEATURE_SEND_RAW_ACCEL (0x040)
|
||||||
|
#define DMP_FEATURE_SEND_RAW_GYRO (0x080)
|
||||||
|
#define DMP_FEATURE_SEND_CAL_GYRO (0x100)
|
||||||
|
|
||||||
|
#define INV_WXYZ_QUAT (0x100)
|
||||||
|
|
||||||
|
/* Set up functions. */
|
||||||
|
int dmp_load_motion_driver_firmware(void);
|
||||||
|
int dmp_set_fifo_rate(unsigned short rate);
|
||||||
|
int dmp_get_fifo_rate(unsigned short *rate);
|
||||||
|
int dmp_enable_feature(unsigned short mask);
|
||||||
|
int dmp_get_enabled_features(unsigned short *mask);
|
||||||
|
int dmp_set_interrupt_mode(unsigned char mode);
|
||||||
|
int dmp_set_orientation(unsigned short orient);
|
||||||
|
int dmp_set_gyro_bias(long *bias);
|
||||||
|
int dmp_set_accel_bias(long *bias);
|
||||||
|
|
||||||
|
/* Tap functions. */
|
||||||
|
int dmp_register_tap_cb(void (*func)(unsigned char, unsigned char));
|
||||||
|
int dmp_set_tap_thresh(unsigned char axis, unsigned short thresh);
|
||||||
|
int dmp_set_tap_axes(unsigned char axis);
|
||||||
|
int dmp_set_tap_count(unsigned char min_taps);
|
||||||
|
int dmp_set_tap_time(unsigned short time);
|
||||||
|
int dmp_set_tap_time_multi(unsigned short time);
|
||||||
|
int dmp_set_shake_reject_thresh(long sf, unsigned short thresh);
|
||||||
|
int dmp_set_shake_reject_time(unsigned short time);
|
||||||
|
int dmp_set_shake_reject_timeout(unsigned short time);
|
||||||
|
|
||||||
|
/* Android orientation functions. */
|
||||||
|
int dmp_register_android_orient_cb(void (*func)(unsigned char));
|
||||||
|
|
||||||
|
/* LP quaternion functions. */
|
||||||
|
int dmp_enable_lp_quat(unsigned char enable);
|
||||||
|
int dmp_enable_6x_lp_quat(unsigned char enable);
|
||||||
|
|
||||||
|
/* Pedometer functions. */
|
||||||
|
int dmp_get_pedometer_step_count(unsigned long *count);
|
||||||
|
int dmp_set_pedometer_step_count(unsigned long count);
|
||||||
|
int dmp_get_pedometer_walk_time(unsigned long *time);
|
||||||
|
int dmp_set_pedometer_walk_time(unsigned long time);
|
||||||
|
|
||||||
|
/* DMP gyro calibration functions. */
|
||||||
|
int dmp_enable_gyro_cal(unsigned char enable);
|
||||||
|
|
||||||
|
/* Read function. This function should be called whenever the MPU interrupt is
|
||||||
|
* detected.
|
||||||
|
*/
|
||||||
|
int dmp_read_fifo(short *gyro, short *accel, long *quat,
|
||||||
|
unsigned long *timestamp, short *sensors, unsigned char *more);
|
||||||
|
|
||||||
|
#endif /* #ifndef _INV_MPU_DMP_MOTION_DRIVER_H_ */
|
||||||
|
|
||||||
|
|
@ -0,0 +1,147 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#include "encoder.h"
|
||||||
|
#include "stm32f10x_gpio.h"
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Initialize TIM2 to encoder interface mode
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：把TIM2初始化为编码器接口模式
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void Encoder_Init_TIM2(void)
|
||||||
|
{
|
||||||
|
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
|
||||||
|
TIM_ICInitTypeDef TIM_ICInitStructure;
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);//使能定时器4的时钟
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);//使能PB端口时钟
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1; //端口配置
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; //浮空输入
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure); //根据设定参数初始化GPIOB
|
||||||
|
|
||||||
|
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
|
||||||
|
TIM_TimeBaseStructure.TIM_Prescaler = 0x0; // 预分频器
|
||||||
|
TIM_TimeBaseStructure.TIM_Period = ENCODER_TIM_PERIOD; //设定计数器自动重装值
|
||||||
|
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;//选择时钟分频：不分频
|
||||||
|
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;////TIM向上计数
|
||||||
|
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
|
||||||
|
TIM_EncoderInterfaceConfig(TIM2, TIM_EncoderMode_TI12, TIM_ICPolarity_Rising, TIM_ICPolarity_Rising);//使用编码器模式3
|
||||||
|
TIM_ICStructInit(&TIM_ICInitStructure);
|
||||||
|
TIM_ICInitStructure.TIM_ICFilter = 10; //滤波10
|
||||||
|
TIM_ICInit(TIM2, &TIM_ICInitStructure);
|
||||||
|
TIM_ClearFlag(TIM2, TIM_FLAG_Update);//清除TIM的更新标志位
|
||||||
|
TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
|
||||||
|
//Reset counter
|
||||||
|
TIM_SetCounter(TIM2,0);
|
||||||
|
TIM_Cmd(TIM2, ENABLE);
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Initialize TIM4 to encoder interface mode
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：把TIM4初始化为编码器接口模式
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void Encoder_Init_TIM4(void)
|
||||||
|
{
|
||||||
|
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
|
||||||
|
TIM_ICInitTypeDef TIM_ICInitStructure;
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);//使能定时器4的时钟
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);//使能PB端口时钟
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6|GPIO_Pin_7; //端口配置
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; //浮空输入
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure); //根据设定参数初始化GPIOB
|
||||||
|
|
||||||
|
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
|
||||||
|
TIM_TimeBaseStructure.TIM_Prescaler = 0x0; // 预分频器
|
||||||
|
TIM_TimeBaseStructure.TIM_Period = ENCODER_TIM_PERIOD; //设定计数器自动重装值
|
||||||
|
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;//选择时钟分频：不分频
|
||||||
|
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;////TIM向上计数
|
||||||
|
TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
|
||||||
|
TIM_EncoderInterfaceConfig(TIM4, TIM_EncoderMode_TI12, TIM_ICPolarity_Rising, TIM_ICPolarity_Rising);//使用编码器模式3
|
||||||
|
TIM_ICStructInit(&TIM_ICInitStructure);
|
||||||
|
TIM_ICInitStructure.TIM_ICFilter = 10;
|
||||||
|
TIM_ICInit(TIM4, &TIM_ICInitStructure);
|
||||||
|
TIM_ClearFlag(TIM4, TIM_FLAG_Update);//清除TIM的更新标志位
|
||||||
|
TIM_ITConfig(TIM4, TIM_IT_Update, ENABLE);
|
||||||
|
//Reset counter
|
||||||
|
TIM_SetCounter(TIM4,0);
|
||||||
|
TIM_Cmd(TIM4, ENABLE);
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Read encoder count per unit time
|
||||||
|
Input : TIMX：Timer
|
||||||
|
Output : none
|
||||||
|
函数功能：单位时间读取编码器计数
|
||||||
|
入口参数：TIMX：定时器
|
||||||
|
返回 值：速度值
|
||||||
|
**************************************************************************/
|
||||||
|
int Read_Encoder(u8 TIMX)
|
||||||
|
{
|
||||||
|
int Encoder_TIM;
|
||||||
|
switch(TIMX)
|
||||||
|
{
|
||||||
|
case 2: Encoder_TIM= (short)TIM2 -> CNT; TIM2 -> CNT=0;break;
|
||||||
|
case 3: Encoder_TIM= (short)TIM3 -> CNT; TIM3 -> CNT=0;break;
|
||||||
|
case 4: Encoder_TIM= (short)TIM4 -> CNT; TIM4 -> CNT=0;break;
|
||||||
|
default: Encoder_TIM=0;
|
||||||
|
}
|
||||||
|
return Encoder_TIM;
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: TIM4 interrupt service function
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：TIM4中断服务函数
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void TIM4_IRQHandler(void)
|
||||||
|
{
|
||||||
|
if(TIM4->SR&0X0001)//溢出中断
|
||||||
|
{
|
||||||
|
}
|
||||||
|
TIM4->SR&=~(1<<0);//清除中断标志位
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: TIM2 interrupt service function
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：TIM2中断服务函数
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void TIM2_IRQHandler(void)
|
||||||
|
{
|
||||||
|
if(TIM2->SR&0X0001)//溢出中断
|
||||||
|
{
|
||||||
|
}
|
||||||
|
TIM2->SR&=~(1<<0);//清除中断标志位
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,29 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#ifndef __ENCODER_H
|
||||||
|
#define __ENCODER_H
|
||||||
|
#include <sys.h>
|
||||||
|
#define ENCODER_TIM_PERIOD (u16)(65535) //不可大于65535 因为F103的定时器是16位的。
|
||||||
|
void Encoder_Init_TIM2(void);
|
||||||
|
void Encoder_Init_TIM4(void);
|
||||||
|
int Read_Encoder(u8 TIMX);
|
||||||
|
void TIM4_IRQHandler(void);
|
||||||
|
void TIM2_IRQHandler(void);
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,52 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#include "exti.h"
|
||||||
|
/**************************************************************************
|
||||||
|
Function: External interrupt initialization
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：外部中断初始化
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void MiniBalance_EXTI_Init(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
EXTI_InitTypeDef EXTI_InitStructure;
|
||||||
|
NVIC_InitTypeDef NVIC_InitStructure;
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO,ENABLE); //外部中断，需要使能AFIO时钟
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); //使能GPIO端口时钟
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; //端口配置
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; //上拉输入
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure); //根据设定参数初始化GPIO
|
||||||
|
GPIO_EXTILineConfig(GPIO_PortSourceGPIOA,GPIO_PinSource12);
|
||||||
|
EXTI_InitStructure.EXTI_Line=EXTI_Line12;
|
||||||
|
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||||||
|
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;//下降沿触发
|
||||||
|
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
|
||||||
|
EXTI_Init(&EXTI_InitStructure); //根据EXTI_InitStruct中指定的参数初始化外设EXTI寄存器
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannel = EXTI15_10_IRQn; //使能按键所在的外部中断通道
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x02; //抢占优先级2，
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x01; //子优先级1
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //使能外部中断通道
|
||||||
|
NVIC_Init(&NVIC_InitStructure);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#ifndef __EXTI_H
|
||||||
|
#define __EXIT_H
|
||||||
|
#include "sys.h"
|
||||||
|
#define INT PAin(12) //PA12连接到MPU6050的中断引脚
|
||||||
|
void MiniBalance_EXTI_Init(void); //外部中断初始化
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,441 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#include "ioi2c.h"
|
||||||
|
#include "sys.h"
|
||||||
|
#include "delay.h"
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: IIC pin initialization
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：IIC引脚初始化
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void IIC_Init(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); // 使能PB端口时钟
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9; // 端口配置
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; // 推挽输出
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; // 50M
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure); // 根据设定参数初始化GPIOB
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Simulate IIC start signal
|
||||||
|
Input : none
|
||||||
|
Output : 1
|
||||||
|
函数功能：模拟IIC起始信号
|
||||||
|
入口参数：无
|
||||||
|
返回 值：1
|
||||||
|
**************************************************************************/
|
||||||
|
int IIC_Start(void)
|
||||||
|
{
|
||||||
|
SDA_OUT(); // sda线输出
|
||||||
|
IIC_SDA = 1;
|
||||||
|
if (!READ_SDA)
|
||||||
|
return 0;
|
||||||
|
IIC_SCL = 1;
|
||||||
|
delay_us(1);
|
||||||
|
IIC_SDA = 0; // START:when CLK is high,DATA change form high to low
|
||||||
|
if (READ_SDA)
|
||||||
|
return 0;
|
||||||
|
delay_us(1);
|
||||||
|
IIC_SCL = 0; // 钳住I2C总线，准备发送或接收数据
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Analog IIC end signal
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：模拟IIC结束信号
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void IIC_Stop(void)
|
||||||
|
{
|
||||||
|
SDA_OUT(); // sda线输出
|
||||||
|
IIC_SCL = 0;
|
||||||
|
IIC_SDA = 0; // STOP:when CLK is high DATA change form low to high
|
||||||
|
delay_us(1);
|
||||||
|
IIC_SCL = 1;
|
||||||
|
IIC_SDA = 1; // 发送I2C总线结束信号
|
||||||
|
delay_us(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: IIC wait the response signal
|
||||||
|
Input : none
|
||||||
|
Output : 0：No response received；1：Response received
|
||||||
|
函数功能：IIC等待应答信号
|
||||||
|
入口参数：无
|
||||||
|
返回 值：0：没有收到应答；1：收到应答
|
||||||
|
**************************************************************************/
|
||||||
|
int IIC_Wait_Ack(void)
|
||||||
|
{
|
||||||
|
u8 ucErrTime = 0;
|
||||||
|
SDA_IN(); // SDA设置为输入
|
||||||
|
IIC_SDA = 1;
|
||||||
|
delay_us(1);
|
||||||
|
IIC_SCL = 1;
|
||||||
|
delay_us(1);
|
||||||
|
while (READ_SDA)
|
||||||
|
{
|
||||||
|
ucErrTime++;
|
||||||
|
if (ucErrTime > 50)
|
||||||
|
{
|
||||||
|
IIC_Stop();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
delay_us(1);
|
||||||
|
}
|
||||||
|
IIC_SCL = 0; // 时钟输出0
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: IIC response
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：IIC应答
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void IIC_Ack(void)
|
||||||
|
{
|
||||||
|
IIC_SCL = 0;
|
||||||
|
SDA_OUT();
|
||||||
|
IIC_SDA = 0;
|
||||||
|
delay_us(1);
|
||||||
|
IIC_SCL = 1;
|
||||||
|
delay_us(1);
|
||||||
|
IIC_SCL = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: IIC don't reply
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：IIC不应答
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void IIC_NAck(void)
|
||||||
|
{
|
||||||
|
IIC_SCL = 0;
|
||||||
|
SDA_OUT();
|
||||||
|
IIC_SDA = 1;
|
||||||
|
delay_us(1);
|
||||||
|
IIC_SCL = 1;
|
||||||
|
delay_us(1);
|
||||||
|
IIC_SCL = 0;
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: IIC sends a byte
|
||||||
|
Input : txd：Byte data sent
|
||||||
|
Output : none
|
||||||
|
函数功能：IIC发送一个字节
|
||||||
|
入口参数：txd：发送的字节数据
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void IIC_Send_Byte(u8 txd)
|
||||||
|
{
|
||||||
|
u8 t;
|
||||||
|
SDA_OUT();
|
||||||
|
IIC_SCL = 0; // 拉低时钟开始数据传输
|
||||||
|
for (t = 0; t < 8; t++)
|
||||||
|
{
|
||||||
|
IIC_SDA = (txd & 0x80) >> 7;
|
||||||
|
txd <<= 1;
|
||||||
|
delay_us(1);
|
||||||
|
IIC_SCL = 1;
|
||||||
|
delay_us(1);
|
||||||
|
IIC_SCL = 0;
|
||||||
|
delay_us(1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: IIC write data to register
|
||||||
|
Input : addr：Device address；reg：Register address；len;Number of bytes；data：Data
|
||||||
|
Output : 0：Write successfully；1：Failed to write
|
||||||
|
函数功能：IIC写数据到寄存器
|
||||||
|
入口参数：addr：设备地址；reg：寄存器地址；len;字节数；data：数据
|
||||||
|
返回 值：0：成功写入；1：没有成功写入
|
||||||
|
**************************************************************************/
|
||||||
|
int i2cWrite(uint8_t addr, uint8_t reg, uint8_t len, uint8_t *data)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
if (!IIC_Start())
|
||||||
|
return 1;
|
||||||
|
IIC_Send_Byte(addr << 1);
|
||||||
|
if (!IIC_Wait_Ack())
|
||||||
|
{
|
||||||
|
IIC_Stop();
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
IIC_Send_Byte(reg);
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
for (i = 0; i < len; i++)
|
||||||
|
{
|
||||||
|
IIC_Send_Byte(data[i]);
|
||||||
|
if (!IIC_Wait_Ack())
|
||||||
|
{
|
||||||
|
IIC_Stop();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
IIC_Stop();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: IIC read register data
|
||||||
|
Input : addr：Device address；reg：Register address；len;Number of bytes；*buf：Data read out
|
||||||
|
Output : 0：Read successfully；1：Failed to read
|
||||||
|
函数功能：IIC读寄存器的数据
|
||||||
|
入口参数：addr：设备地址；reg：寄存器地址；len;字节数；*buf：读出数据缓存
|
||||||
|
返回 值：0：成功读出；1：没有成功读出
|
||||||
|
**************************************************************************/
|
||||||
|
|
||||||
|
int i2cRead(uint8_t addr, uint8_t reg, uint8_t len, uint8_t *buf)
|
||||||
|
{
|
||||||
|
if (!IIC_Start())
|
||||||
|
return 1;
|
||||||
|
IIC_Send_Byte(addr << 1);
|
||||||
|
if (!IIC_Wait_Ack())
|
||||||
|
{
|
||||||
|
IIC_Stop();
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
IIC_Send_Byte(reg);
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
IIC_Start();
|
||||||
|
IIC_Send_Byte((addr << 1) + 1);
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
while (len)
|
||||||
|
{
|
||||||
|
if (len == 1)
|
||||||
|
*buf = IIC_Read_Byte(0);
|
||||||
|
else
|
||||||
|
*buf = IIC_Read_Byte(1);
|
||||||
|
buf++;
|
||||||
|
len--;
|
||||||
|
}
|
||||||
|
IIC_Stop();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: IIC reads a byte
|
||||||
|
Input : ack：Send response signal or not；1：Send；0：Do not send
|
||||||
|
Output : receive：Data read
|
||||||
|
函数功能：IIC读取一个位
|
||||||
|
入口参数：ack：是否发送应答信号；1：发送；0：不发送
|
||||||
|
返回 值：receive：读取的数据
|
||||||
|
**************************************************************************/
|
||||||
|
u8 IIC_Read_Byte(unsigned char ack)
|
||||||
|
{
|
||||||
|
unsigned char i, receive = 0;
|
||||||
|
SDA_IN(); // SDA设置为输入
|
||||||
|
for (i = 0; i < 8; i++)
|
||||||
|
{
|
||||||
|
IIC_SCL = 0;
|
||||||
|
delay_us(2);
|
||||||
|
IIC_SCL = 1;
|
||||||
|
receive <<= 1;
|
||||||
|
if (READ_SDA)
|
||||||
|
receive++;
|
||||||
|
delay_us(2);
|
||||||
|
}
|
||||||
|
if (ack)
|
||||||
|
IIC_Ack(); // 发送ACK
|
||||||
|
else
|
||||||
|
IIC_NAck(); // 发送nACK
|
||||||
|
return receive;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: IIC reads a byte
|
||||||
|
Input : I2C_Addr：Device IIC address；addr:Register address
|
||||||
|
Output : res：Data read
|
||||||
|
函数功能：读取指定设备指定寄存器的一个值
|
||||||
|
入口参数：I2C_Addr：设备IIC地址；addr:寄存器地址
|
||||||
|
返回 值：res：读取的数据
|
||||||
|
**************************************************************************/
|
||||||
|
unsigned char I2C_ReadOneByte(unsigned char I2C_Addr, unsigned char addr)
|
||||||
|
{
|
||||||
|
unsigned char res = 0;
|
||||||
|
|
||||||
|
IIC_Start();
|
||||||
|
IIC_Send_Byte(I2C_Addr); // 发送写命令
|
||||||
|
res++;
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
IIC_Send_Byte(addr);
|
||||||
|
res++; // 发送地址
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
// IIC_Stop();//产生一个停止条件
|
||||||
|
IIC_Start();
|
||||||
|
IIC_Send_Byte(I2C_Addr + 1);
|
||||||
|
res++; // 进入接收模式
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
res = IIC_Read_Byte(0);
|
||||||
|
IIC_Stop(); // 产生一个停止条件
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: IIC continuous reading data
|
||||||
|
Input : dev：Target device IIC address；reg:Register address；
|
||||||
|
length：Number of bytes；*data:The pointer where the read data will be stored
|
||||||
|
Output : count：Number of bytes read out-1
|
||||||
|
函数功能：IIC连续读数据
|
||||||
|
入口参数：dev：目标设备IIC地址；reg:寄存器地址；length：字节数；
|
||||||
|
*data:读出的数据将要存放的指针
|
||||||
|
返回 值：count：读出来的字节数量-1
|
||||||
|
**************************************************************************/
|
||||||
|
u8 IICreadBytes(u8 dev, u8 reg, u8 length, u8 *data)
|
||||||
|
{
|
||||||
|
u8 count = 0;
|
||||||
|
|
||||||
|
IIC_Start();
|
||||||
|
IIC_Send_Byte(dev); // 发送写命令
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
IIC_Send_Byte(reg); // 发送地址
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
IIC_Start();
|
||||||
|
IIC_Send_Byte(dev + 1); // 进入接收模式
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
|
||||||
|
for (count = 0; count < length; count++)
|
||||||
|
{
|
||||||
|
|
||||||
|
if (count != length - 1)
|
||||||
|
data[count] = IIC_Read_Byte(1); // 带ACK的读数据
|
||||||
|
else
|
||||||
|
data[count] = IIC_Read_Byte(0); // 最后一个字节NACK
|
||||||
|
}
|
||||||
|
IIC_Stop(); // 产生一个停止条件
|
||||||
|
return count;
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Writes multiple bytes to the specified register of the specified device
|
||||||
|
Input : dev：Target device IIC address；reg：Register address；length：Number of bytes；
|
||||||
|
*data：The pointer where the read data will be stored
|
||||||
|
Output : 1
|
||||||
|
函数功能：将多个字节写入指定设备指定寄存器
|
||||||
|
入口参数：dev：目标设备地址；reg：寄存器地址；length：要写的字节数；
|
||||||
|
*data：将要写的数据的首地址
|
||||||
|
返回 值：1：返回是否成功
|
||||||
|
**************************************************************************/
|
||||||
|
u8 IICwriteBytes(u8 dev, u8 reg, u8 length, u8 *data)
|
||||||
|
{
|
||||||
|
|
||||||
|
u8 count = 0;
|
||||||
|
IIC_Start();
|
||||||
|
IIC_Send_Byte(dev); // 发送写命令
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
IIC_Send_Byte(reg); // 发送地址
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
for (count = 0; count < length; count++)
|
||||||
|
{
|
||||||
|
IIC_Send_Byte(data[count]);
|
||||||
|
IIC_Wait_Ack();
|
||||||
|
}
|
||||||
|
IIC_Stop(); // 产生一个停止条件
|
||||||
|
|
||||||
|
return 1; // status == 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Reads a byte of the specified register of the specified device
|
||||||
|
Input : dev：Target device IIC address；reg：Register address；*data：The pointer where the read data will be stored
|
||||||
|
Output : 1
|
||||||
|
函数功能：读取指定设备指定寄存器的一个值
|
||||||
|
入口参数：dev：目标设备地址；reg：寄存器地址；*data：将要写的数据的首地址
|
||||||
|
返回 值：1：返回是否成功
|
||||||
|
**************************************************************************/
|
||||||
|
u8 IICreadByte(u8 dev, u8 reg, u8 *data)
|
||||||
|
{
|
||||||
|
*data = I2C_ReadOneByte(dev, reg);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Write a byte to the specified register of the specified device
|
||||||
|
Input : dev：Target device IIC address；reg：Register address；data：Data to be writtenwill be stored
|
||||||
|
Output : 1
|
||||||
|
函数功能：写入指定设备指定寄存器一个字节
|
||||||
|
入口参数：dev：目标设备地址；reg：寄存器地址；data：将要写的数据
|
||||||
|
返回 值：1
|
||||||
|
**************************************************************************/
|
||||||
|
unsigned char IICwriteByte(unsigned char dev, unsigned char reg, unsigned char data)
|
||||||
|
{
|
||||||
|
return IICwriteBytes(dev, reg, 1, &data);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Read, modify, and write multiple bits in a byte of the specified device specified register
|
||||||
|
Input : dev：Target device IIC address；reg：Register address；length：Number of bytes；
|
||||||
|
bitStart：Start bit of target byte；data：Stores the value of the target byte bit to be changed
|
||||||
|
Output : 1：success；0：fail
|
||||||
|
函数功能：读 修改 写 指定设备 指定寄存器一个字节 中的多个位
|
||||||
|
入口参数：dev：目标设备地址；reg：寄存器地址；bitStart：目标字节的起始位；
|
||||||
|
data：存放改变目标字节位的值
|
||||||
|
返回 值：1：成功；0：失败
|
||||||
|
**************************************************************************/
|
||||||
|
u8 IICwriteBits(u8 dev, u8 reg, u8 bitStart, u8 length, u8 data)
|
||||||
|
{
|
||||||
|
|
||||||
|
u8 b;
|
||||||
|
if (IICreadByte(dev, reg, &b) != 0)
|
||||||
|
{
|
||||||
|
u8 mask = (0xFF << (bitStart + 1)) | 0xFF >> ((8 - bitStart) + length - 1);
|
||||||
|
data <<= (8 - length);
|
||||||
|
data >>= (7 - bitStart);
|
||||||
|
b &= mask;
|
||||||
|
b |= data;
|
||||||
|
return IICwriteByte(dev, reg, b);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Read, modify, and write one bit in a byte of the specified device specified register
|
||||||
|
Input : dev：Target device IIC address；reg：Register address；
|
||||||
|
bitNum：To modify the bitnum bit of the target byte；data：When it is 0, the target bit will be cleared, otherwise it will be set
|
||||||
|
Output : 1：success；0：fail
|
||||||
|
函数功能：读 修改 写 指定设备 指定寄存器一个字节 中的1个位
|
||||||
|
入口参数：dev：目标设备地址；reg：寄存器地址；bitNum：要修改目标字节的bitNum位；
|
||||||
|
data：为0时，目标位将被清，否则将被置位
|
||||||
|
返回 值：1：成功；0：失败
|
||||||
|
**************************************************************************/
|
||||||
|
u8 IICwriteBit(u8 dev, u8 reg, u8 bitNum, u8 data)
|
||||||
|
{
|
||||||
|
u8 b;
|
||||||
|
IICreadByte(dev, reg, &b);
|
||||||
|
b = (data != 0) ? (b | (1 << bitNum)) : (b & ~(1 << bitNum));
|
||||||
|
return IICwriteByte(dev, reg, b);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#ifndef __IOI2C_H
|
||||||
|
#define __IOI2C_H
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
/**************************************************************************
|
||||||
|
作者：平衡小车之家
|
||||||
|
我的淘宝小店：http://shop114407458.taobao.com/
|
||||||
|
**************************************************************************/
|
||||||
|
//IO口操作宏定义
|
||||||
|
#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
|
||||||
|
#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
|
||||||
|
#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
|
||||||
|
|
||||||
|
//IO口地址映射
|
||||||
|
#define GPIOA_ODR_Addr (GPIOA_BASE+12) //0x4001080C
|
||||||
|
#define GPIOB_ODR_Addr (GPIOB_BASE+12) //0x40010C0C
|
||||||
|
#define GPIOC_ODR_Addr (GPIOC_BASE+12) //0x4001100C
|
||||||
|
#define GPIOD_ODR_Addr (GPIOD_BASE+12) //0x4001140C
|
||||||
|
#define GPIOE_ODR_Addr (GPIOE_BASE+12) //0x4001180C
|
||||||
|
#define GPIOF_ODR_Addr (GPIOF_BASE+12) //0x40011A0C
|
||||||
|
#define GPIOG_ODR_Addr (GPIOG_BASE+12) //0x40011E0C
|
||||||
|
|
||||||
|
#define GPIOA_IDR_Addr (GPIOA_BASE+8) //0x40010808
|
||||||
|
#define GPIOB_IDR_Addr (GPIOB_BASE+8) //0x40010C08
|
||||||
|
#define GPIOC_IDR_Addr (GPIOC_BASE+8) //0x40011008
|
||||||
|
#define GPIOD_IDR_Addr (GPIOD_BASE+8) //0x40011408
|
||||||
|
#define GPIOE_IDR_Addr (GPIOE_BASE+8) //0x40011808
|
||||||
|
#define GPIOF_IDR_Addr (GPIOF_BASE+8) //0x40011A08
|
||||||
|
#define GPIOG_IDR_Addr (GPIOG_BASE+8) //0x40011E08
|
||||||
|
|
||||||
|
#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //输出
|
||||||
|
#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //输入
|
||||||
|
|
||||||
|
#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //输出
|
||||||
|
#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //输入
|
||||||
|
|
||||||
|
#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //输出
|
||||||
|
#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //输入
|
||||||
|
|
||||||
|
|
||||||
|
//IO方向设置
|
||||||
|
#define SDA_IN() {GPIOB->CRH&=0XFFFFFF0F;GPIOB->CRH|=8<<4;}
|
||||||
|
#define SDA_OUT() {GPIOB->CRH&=0XFFFFFF0F;GPIOB->CRH|=3<<4;}
|
||||||
|
|
||||||
|
//IO操作函数
|
||||||
|
#define IIC_SCL PBout(8) //SCL
|
||||||
|
#define IIC_SDA PBout(9) //SDA
|
||||||
|
#define READ_SDA PBin(9) //输入SDA
|
||||||
|
|
||||||
|
//IIC所有操作函数
|
||||||
|
void IIC_Init(void); // 初始化IIC的IO口
|
||||||
|
int IIC_Start(void); // 发送IIC开始信号
|
||||||
|
void IIC_Stop(void); // 发送IIC停止信号
|
||||||
|
void IIC_Send_Byte(u8 txd); //IIC发送一个字节
|
||||||
|
u8 IIC_Read_Byte(unsigned char ack); // IIC读取一个字节
|
||||||
|
int IIC_Wait_Ack(void); // IIC等待ACK信号
|
||||||
|
void IIC_Ack(void); //IIC发送ACK信号
|
||||||
|
void IIC_NAck(void); //IIC不发送ACK信号
|
||||||
|
|
||||||
|
void IIC_Write_One_Byte(u8 daddr,u8 addr,u8 data);
|
||||||
|
u8 IIC_Read_One_Byte(u8 daddr,u8 addr);
|
||||||
|
unsigned char I2C_Readkey(unsigned char I2C_Addr);
|
||||||
|
|
||||||
|
unsigned char I2C_ReadOneByte(unsigned char I2C_Addr,unsigned char addr);
|
||||||
|
unsigned char IICwriteByte(unsigned char dev, unsigned char reg, unsigned char data);
|
||||||
|
|
||||||
|
|
||||||
|
u8 IICwriteBytes(u8 dev, u8 reg, u8 length, u8* data);
|
||||||
|
u8 IICwriteBits(u8 dev,u8 reg,u8 bitStart,u8 length,u8 data);
|
||||||
|
u8 IICwriteBit(u8 dev,u8 reg,u8 bitNum,u8 data);
|
||||||
|
u8 IICreadBytes(u8 dev, u8 reg, u8 length, u8 *data);
|
||||||
|
|
||||||
|
int i2cWrite(uint8_t addr, uint8_t reg, uint8_t len, uint8_t *data);
|
||||||
|
int i2cRead(uint8_t addr, uint8_t reg, uint8_t len, uint8_t *buf);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//------------------End of File----------------------------
|
||||||
|
|
@ -0,0 +1,38 @@
|
||||||
|
|
||||||
|
#include "key.h"
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Key initialization
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：按键初始化
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void KEY_Init(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); // 使能PA端口时钟
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; // 端口配置
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; // 上拉输入
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure); // 根据设定参数初始化GPIOA
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Key scan
|
||||||
|
Input : none
|
||||||
|
Output : 0：No action；1：click；
|
||||||
|
函数功能：按键扫描
|
||||||
|
入口参数：无
|
||||||
|
返回 值：按键状态 0：无动作 1：单击
|
||||||
|
**************************************************************************/
|
||||||
|
u8 click(void)
|
||||||
|
{
|
||||||
|
static u8 flag_key = 1; // 按键松开标志
|
||||||
|
if (flag_key && KEY == 0) // 检测到按键按下
|
||||||
|
{
|
||||||
|
flag_key = 0;
|
||||||
|
return 1; // 按键按下
|
||||||
|
}
|
||||||
|
else if (1 == KEY)
|
||||||
|
flag_key = 1;
|
||||||
|
return 0; // 无按键按下
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,7 @@
|
||||||
|
#ifndef __KEY_H__
|
||||||
|
#define __KEY_H__
|
||||||
|
#include "sys.h"
|
||||||
|
#define KEY PAin(5)
|
||||||
|
void KEY_Init(void);
|
||||||
|
u8 click(void);
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,84 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#include "motor.h"
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Initialize Motor Interface
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：初始化电机接口
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void Motor_Init(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); //使能PB端口时钟
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15; //端口配置
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //推挽输出
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; //50M
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure); //根据设定参数初始化GPIOB
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Initialize PWM to drive motor
|
||||||
|
Input : arr：Auto reload value；psc：Prescaler coefficient
|
||||||
|
Output : none
|
||||||
|
函数功能：初始化PWM，用于驱动电机
|
||||||
|
入口参数：arr：自动重装值；psc：预分频系数
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void MiniBalance_PWM_Init(u16 arr,u16 psc)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
|
||||||
|
TIM_OCInitTypeDef TIM_OCInitStructure;
|
||||||
|
Motor_Init();
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);//
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA , ENABLE); //使能GPIO外设时钟使能
|
||||||
|
//设置该引脚为复用输出功能,输出TIM1 CH1 CH4的PWM脉冲波形
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_11; //TIM_CH1 //TIM_CH4
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; //复用推挽输出
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
TIM_TimeBaseStructure.TIM_Period = arr; //设置在下一个更新事件装入活动的自动重装载寄存器周期的值
|
||||||
|
TIM_TimeBaseStructure.TIM_Prescaler =psc; //设置用来作为TIMx时钟频率除数的预分频值 不分频
|
||||||
|
TIM_TimeBaseStructure.TIM_ClockDivision = 0; //设置时钟分割:TDTS = Tck_tim
|
||||||
|
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; //TIM向上计数模式
|
||||||
|
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure); //根据TIM_TimeBaseInitStruct中指定的参数初始化TIMx的时间基数单位
|
||||||
|
|
||||||
|
|
||||||
|
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; //选择定时器模式:TIM脉冲宽度调制模式1
|
||||||
|
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; //比较输出使能
|
||||||
|
TIM_OCInitStructure.TIM_Pulse = 0; //设置待装入捕获比较寄存器的脉冲值
|
||||||
|
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; //输出极性:TIM输出比较极性高
|
||||||
|
TIM_OC1Init(TIM1, &TIM_OCInitStructure); //根据TIM_OCInitStruct中指定的参数初始化外设TIMx
|
||||||
|
TIM_OC4Init(TIM1, &TIM_OCInitStructure); //根据TIM_OCInitStruct中指定的参数初始化外设TIMx
|
||||||
|
|
||||||
|
TIM_CtrlPWMOutputs(TIM1,ENABLE); //MOE 主输出使能
|
||||||
|
|
||||||
|
TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable); //CH1预装载使能
|
||||||
|
TIM_OC4PreloadConfig(TIM1, TIM_OCPreload_Enable); //CH4预装载使能
|
||||||
|
|
||||||
|
TIM_ARRPreloadConfig(TIM1, ENABLE); //使能TIMx在ARR上的预装载寄存器
|
||||||
|
|
||||||
|
TIM_Cmd(TIM1, ENABLE); //使能TIM1
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/***********************************************
|
||||||
|
<EFBFBD><EFBFBD>˾<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȥ<EFBFBD>Ƽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݸ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˾
|
||||||
|
Ʒ<EFBFBD>ƣ<EFBFBD>WHEELTEC
|
||||||
|
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>wheeltec.net
|
||||||
|
<EFBFBD>Ա<EFBFBD><EFBFBD><EFBFBD><EFBFBD>̣<EFBFBD>shop114407458.taobao.com
|
||||||
|
<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
<EFBFBD>汾<EFBFBD><EFBFBD>5.7
|
||||||
|
<EFBFBD><EFBFBD>ʱ<EFBFBD>䣺2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update<EFBFBD><EFBFBD>2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#ifndef __MOTOR_H
|
||||||
|
#define __MOTOR_H
|
||||||
|
#include <sys.h>
|
||||||
|
#define PWMB TIM1->CCR4 //PA11
|
||||||
|
#define BIN2 PBout(12)
|
||||||
|
#define BIN1 PBout(13)
|
||||||
|
#define AIN2 PBout(15)
|
||||||
|
#define AIN1 PBout(14)
|
||||||
|
#define PWMA TIM1->CCR1 //PA8
|
||||||
|
void MiniBalance_PWM_Init(u16 arr,u16 psc);
|
||||||
|
void Motor_Init(void);
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,366 @@
|
||||||
|
#include "MPU6050.h"
|
||||||
|
#include "IOI2C.h"
|
||||||
|
#include "usart.h"
|
||||||
|
#define PRINT_ACCEL (0x01)
|
||||||
|
#define PRINT_GYRO (0x02)
|
||||||
|
#define PRINT_QUAT (0x04)
|
||||||
|
#define ACCEL_ON (0x01)
|
||||||
|
#define GYRO_ON (0x02)
|
||||||
|
#define MOTION (0)
|
||||||
|
#define NO_MOTION (1)
|
||||||
|
#define DEFAULT_MPU_HZ (200)
|
||||||
|
#define FLASH_SIZE (512)
|
||||||
|
#define FLASH_MEM_START ((void *)0x1800)
|
||||||
|
#define q30 1073741824.0f
|
||||||
|
short gyro[3], accel[3], sensors;
|
||||||
|
float Roll, Pitch;
|
||||||
|
float q0 = 1.0f, q1 = 0.0f, q2 = 0.0f, q3 = 0.0f;
|
||||||
|
static signed char gyro_orientation[9] = {-1, 0, 0,
|
||||||
|
0, -1, 0,
|
||||||
|
0, 0, 1};
|
||||||
|
|
||||||
|
static unsigned short inv_row_2_scale(const signed char *row)
|
||||||
|
{
|
||||||
|
unsigned short b;
|
||||||
|
|
||||||
|
if (row[0] > 0)
|
||||||
|
b = 0;
|
||||||
|
else if (row[0] < 0)
|
||||||
|
b = 4;
|
||||||
|
else if (row[1] > 0)
|
||||||
|
b = 1;
|
||||||
|
else if (row[1] < 0)
|
||||||
|
b = 5;
|
||||||
|
else if (row[2] > 0)
|
||||||
|
b = 2;
|
||||||
|
else if (row[2] < 0)
|
||||||
|
b = 6;
|
||||||
|
else
|
||||||
|
b = 7; // error
|
||||||
|
return b;
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned short inv_orientation_matrix_to_scalar(
|
||||||
|
const signed char *mtx)
|
||||||
|
{
|
||||||
|
unsigned short scalar;
|
||||||
|
scalar = inv_row_2_scale(mtx);
|
||||||
|
scalar |= inv_row_2_scale(mtx + 3) << 3;
|
||||||
|
scalar |= inv_row_2_scale(mtx + 6) << 6;
|
||||||
|
|
||||||
|
return scalar;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void run_self_test(void)
|
||||||
|
{
|
||||||
|
int result;
|
||||||
|
long gyro[3], accel[3];
|
||||||
|
|
||||||
|
result = mpu_run_self_test(gyro, accel);
|
||||||
|
if (result == 0x7)
|
||||||
|
{
|
||||||
|
/* Test passed. We can trust the gyro data here, so let's push it down
|
||||||
|
* to the DMP.
|
||||||
|
*/
|
||||||
|
float sens;
|
||||||
|
unsigned short accel_sens;
|
||||||
|
mpu_get_gyro_sens(&sens);
|
||||||
|
gyro[0] = (long)(gyro[0] * sens);
|
||||||
|
gyro[1] = (long)(gyro[1] * sens);
|
||||||
|
gyro[2] = (long)(gyro[2] * sens);
|
||||||
|
dmp_set_gyro_bias(gyro);
|
||||||
|
mpu_get_accel_sens(&accel_sens);
|
||||||
|
accel[0] *= accel_sens;
|
||||||
|
accel[1] *= accel_sens;
|
||||||
|
accel[2] *= accel_sens;
|
||||||
|
dmp_set_accel_bias(accel);
|
||||||
|
printf("setting bias succesfully ......\r\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t buffer[14];
|
||||||
|
|
||||||
|
int16_t MPU6050_FIFO[6][11];
|
||||||
|
int16_t Gx_offset = 0, Gy_offset = 0, Gz_offset = 0;
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: The new ADC data is updated to FIFO array for filtering
|
||||||
|
Input : ax，ay，az：x，y, z-axis acceleration data；gx，gy，gz：x. Y, z-axis angular acceleration data
|
||||||
|
Output : none
|
||||||
|
函数功能：将新的ADC数据更新到 FIFO数组，进行滤波处理
|
||||||
|
入口参数：ax，ay，az：x，y，z轴加速度数据；gx，gy，gz：x，y，z轴角加速度数据
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
|
||||||
|
void MPU6050_newValues(int16_t ax, int16_t ay, int16_t az, int16_t gx, int16_t gy, int16_t gz)
|
||||||
|
{
|
||||||
|
unsigned char i;
|
||||||
|
int32_t sum = 0;
|
||||||
|
for (i = 1; i < 10; i++)
|
||||||
|
{ // FIFO 操作
|
||||||
|
MPU6050_FIFO[0][i - 1] = MPU6050_FIFO[0][i];
|
||||||
|
MPU6050_FIFO[1][i - 1] = MPU6050_FIFO[1][i];
|
||||||
|
MPU6050_FIFO[2][i - 1] = MPU6050_FIFO[2][i];
|
||||||
|
MPU6050_FIFO[3][i - 1] = MPU6050_FIFO[3][i];
|
||||||
|
MPU6050_FIFO[4][i - 1] = MPU6050_FIFO[4][i];
|
||||||
|
MPU6050_FIFO[5][i - 1] = MPU6050_FIFO[5][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[0][9] = ax; // 将新的数据放置到 数据的最后面
|
||||||
|
MPU6050_FIFO[1][9] = ay;
|
||||||
|
MPU6050_FIFO[2][9] = az;
|
||||||
|
MPU6050_FIFO[3][9] = gx;
|
||||||
|
MPU6050_FIFO[4][9] = gy;
|
||||||
|
MPU6050_FIFO[5][9] = gz;
|
||||||
|
|
||||||
|
sum = 0;
|
||||||
|
for (i = 0; i < 10; i++)
|
||||||
|
{ // 求当前数组的合，再取平均值
|
||||||
|
sum += MPU6050_FIFO[0][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[0][10] = sum / 10;
|
||||||
|
|
||||||
|
sum = 0;
|
||||||
|
for (i = 0; i < 10; i++)
|
||||||
|
{
|
||||||
|
sum += MPU6050_FIFO[1][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[1][10] = sum / 10;
|
||||||
|
|
||||||
|
sum = 0;
|
||||||
|
for (i = 0; i < 10; i++)
|
||||||
|
{
|
||||||
|
sum += MPU6050_FIFO[2][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[2][10] = sum / 10;
|
||||||
|
|
||||||
|
sum = 0;
|
||||||
|
for (i = 0; i < 10; i++)
|
||||||
|
{
|
||||||
|
sum += MPU6050_FIFO[3][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[3][10] = sum / 10;
|
||||||
|
|
||||||
|
sum = 0;
|
||||||
|
for (i = 0; i < 10; i++)
|
||||||
|
{
|
||||||
|
sum += MPU6050_FIFO[4][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[4][10] = sum / 10;
|
||||||
|
|
||||||
|
sum = 0;
|
||||||
|
for (i = 0; i < 10; i++)
|
||||||
|
{
|
||||||
|
sum += MPU6050_FIFO[5][i];
|
||||||
|
}
|
||||||
|
MPU6050_FIFO[5][10] = sum / 10;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Setting the clock source of mpu6050
|
||||||
|
Input : source：Clock source number
|
||||||
|
Output : none
|
||||||
|
函数功能：设置 MPU6050 的时钟源
|
||||||
|
入口参数：source：时钟源编号
|
||||||
|
返回 值：无
|
||||||
|
* CLK_SEL | Clock Source
|
||||||
|
* --------+--------------------------------------
|
||||||
|
* 0 | Internal oscillator
|
||||||
|
* 1 | PLL with X Gyro reference
|
||||||
|
* 2 | PLL with Y Gyro reference
|
||||||
|
* 3 | PLL with Z Gyro reference
|
||||||
|
* 4 | PLL with external 32.768kHz reference
|
||||||
|
* 5 | PLL with external 19.2MHz reference
|
||||||
|
* 6 | Reserved
|
||||||
|
* 7 | Stops the clock and keeps the timing generator in reset
|
||||||
|
**************************************************************************/
|
||||||
|
void MPU6050_setClockSource(uint8_t source)
|
||||||
|
{
|
||||||
|
IICwriteBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, source);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Set full-scale gyroscope range.
|
||||||
|
* @param range New full-scale gyroscope range value
|
||||||
|
* @see getFullScaleRange()
|
||||||
|
* @see MPU6050_GYRO_FS_250
|
||||||
|
* @see MPU6050_RA_GYRO_CONFIG
|
||||||
|
* @see MPU6050_GCONFIG_FS_SEL_BIT
|
||||||
|
* @see MPU6050_GCONFIG_FS_SEL_LENGTH
|
||||||
|
*/
|
||||||
|
void MPU6050_setFullScaleGyroRange(uint8_t range)
|
||||||
|
{
|
||||||
|
IICwriteBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH, range);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Setting the maximum range of mpu6050 accelerometer
|
||||||
|
Input : range：Acceleration maximum range number
|
||||||
|
Output : none
|
||||||
|
函数功能：设置 MPU6050 加速度计的最大量程
|
||||||
|
入口参数：range：加速度最大量程编号
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
// #define MPU6050_ACCEL_FS_2 0x00 //===最大量程+-2G
|
||||||
|
// #define MPU6050_ACCEL_FS_4 0x01 //===最大量程+-4G
|
||||||
|
// #define MPU6050_ACCEL_FS_8 0x02 //===最大量程+-8G
|
||||||
|
// #define MPU6050_ACCEL_FS_16 0x03 //===最大量程+-16G
|
||||||
|
void MPU6050_setFullScaleAccelRange(uint8_t range)
|
||||||
|
{
|
||||||
|
IICwriteBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH, range);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Set mpu6050 to sleep mode or not
|
||||||
|
Input : enable：1，sleep；0，work；
|
||||||
|
Output : none
|
||||||
|
函数功能：设置 MPU6050 是否进入睡眠模式
|
||||||
|
入口参数：enable：1，睡觉；0，工作；
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void MPU6050_setSleepEnabled(uint8_t enabled)
|
||||||
|
{
|
||||||
|
IICwriteBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, enabled);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Read identity
|
||||||
|
Input : none
|
||||||
|
Output : 0x68
|
||||||
|
函数功能：读取 MPU6050 WHO_AM_I 标识
|
||||||
|
入口参数：无
|
||||||
|
返回 值：0x68
|
||||||
|
**************************************************************************/
|
||||||
|
uint8_t MPU6050_getDeviceID(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
IICreadBytes(devAddr, MPU6050_RA_WHO_AM_I, 1, buffer);
|
||||||
|
return buffer[0];
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Check whether mpu6050 is connected
|
||||||
|
Input : none
|
||||||
|
Output : 1：Connected；0：Not connected
|
||||||
|
函数功能：检测MPU6050 是否已经连接
|
||||||
|
入口参数：无
|
||||||
|
返回 值：1：已连接；0：未连接
|
||||||
|
**************************************************************************/
|
||||||
|
uint8_t MPU6050_testConnection(void)
|
||||||
|
{
|
||||||
|
if (MPU6050_getDeviceID() == 0x68) // 0b01101000;
|
||||||
|
return 1;
|
||||||
|
else
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Setting whether mpu6050 is the host of aux I2C cable
|
||||||
|
Input : enable：1，yes；0;not
|
||||||
|
Output : none
|
||||||
|
函数功能：设置 MPU6050 是否为AUX I2C线的主机
|
||||||
|
入口参数：enable：1，是；0：否
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void MPU6050_setI2CMasterModeEnabled(uint8_t enabled)
|
||||||
|
{
|
||||||
|
IICwriteBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, enabled);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Setting whether mpu6050 is the host of aux I2C cable
|
||||||
|
Input : enable：1，yes；0;not
|
||||||
|
Output : none
|
||||||
|
函数功能：设置 MPU6050 是否为AUX I2C线的主机
|
||||||
|
入口参数：enable：1，是；0：否
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void MPU6050_setI2CBypassEnabled(uint8_t enabled)
|
||||||
|
{
|
||||||
|
IICwriteBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, enabled);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: initialization Mpu6050 to enter the available state
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：初始化 MPU6050 以进入可用状态
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void MPU6050_initialize(void)
|
||||||
|
{
|
||||||
|
MPU6050_setClockSource(MPU6050_CLOCK_PLL_YGYRO); // 设置时钟
|
||||||
|
MPU6050_setFullScaleGyroRange(MPU6050_GYRO_FS_2000); // 陀螺仪量程设置
|
||||||
|
MPU6050_setFullScaleAccelRange(MPU6050_ACCEL_FS_2); // 加速度度最大量程 +-2G
|
||||||
|
MPU6050_setSleepEnabled(0); // 进入工作状态
|
||||||
|
MPU6050_setI2CMasterModeEnabled(0); // 不让MPU6050 控制AUXI2C
|
||||||
|
MPU6050_setI2CBypassEnabled(0); // 主控制器的I2C与 MPU6050的AUXI2C 直通关闭
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Initialization of DMP in mpu6050
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：MPU6050内置DMP的初始化
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void DMP_Init(void)
|
||||||
|
{
|
||||||
|
u8 temp[1] = {0};
|
||||||
|
i2cRead(0x68, 0x75, 1, temp);
|
||||||
|
if (temp[0] != 0x68)
|
||||||
|
NVIC_SystemReset();
|
||||||
|
if (!mpu_init())
|
||||||
|
{
|
||||||
|
if (!mpu_set_sensors(INV_XYZ_GYRO | INV_XYZ_ACCEL))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
if (!mpu_configure_fifo(INV_XYZ_GYRO | INV_XYZ_ACCEL))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
if (!mpu_set_sample_rate(DEFAULT_MPU_HZ))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
if (!dmp_load_motion_driver_firmware())
|
||||||
|
{
|
||||||
|
}
|
||||||
|
if (!dmp_set_orientation(inv_orientation_matrix_to_scalar(gyro_orientation)))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
if (!dmp_enable_feature(DMP_FEATURE_6X_LP_QUAT | DMP_FEATURE_TAP |
|
||||||
|
DMP_FEATURE_ANDROID_ORIENT | DMP_FEATURE_SEND_RAW_ACCEL | DMP_FEATURE_SEND_CAL_GYRO |
|
||||||
|
DMP_FEATURE_GYRO_CAL))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
if (!dmp_set_fifo_rate(DEFAULT_MPU_HZ))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
run_self_test();
|
||||||
|
if (!mpu_set_dmp_state(1))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Read the attitude information of DMP in mpu6050
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：读取MPU6050内置DMP的姿态信息
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void Read_DMP(void)
|
||||||
|
{
|
||||||
|
unsigned long sensor_timestamp;
|
||||||
|
unsigned char more;
|
||||||
|
long quat[4];
|
||||||
|
dmp_read_fifo(gyro, accel, quat, &sensor_timestamp, &sensors, &more); // 读取DMP数据
|
||||||
|
if (sensors & INV_WXYZ_QUAT)
|
||||||
|
{
|
||||||
|
q0 = quat[0] / q30;
|
||||||
|
q1 = quat[1] / q30;
|
||||||
|
q2 = quat[2] / q30;
|
||||||
|
q3 = quat[3] / q30; // 四元数
|
||||||
|
Pitch = atan2(2 * q2 * q3 + 2 * q0 * q1, -2 * q1 * q1 - 2 * q2 * q2 + 1) * 57.3; // 计算出俯仰角
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,371 @@
|
||||||
|
#ifndef __MPU6050_H
|
||||||
|
#define __MPU6050_H
|
||||||
|
|
||||||
|
#include "sys.h"
|
||||||
|
#define devAddr 0xD0
|
||||||
|
|
||||||
|
#define MPU6050_ADDRESS_AD0_LOW 0x68 // address pin low (GND), default for InvenSense evaluation board
|
||||||
|
#define MPU6050_ADDRESS_AD0_HIGH 0x69 // address pin high (VCC)
|
||||||
|
#define MPU6050_DEFAULT_ADDRESS MPU6050_ADDRESS_AD0_LOW
|
||||||
|
|
||||||
|
#define MPU6050_RA_XG_OFFS_TC 0x00 //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD
|
||||||
|
#define MPU6050_RA_YG_OFFS_TC 0x01 //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD
|
||||||
|
#define MPU6050_RA_ZG_OFFS_TC 0x02 //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD
|
||||||
|
#define MPU6050_RA_X_FINE_GAIN 0x03 //[7:0] X_FINE_GAIN
|
||||||
|
#define MPU6050_RA_Y_FINE_GAIN 0x04 //[7:0] Y_FINE_GAIN
|
||||||
|
#define MPU6050_RA_Z_FINE_GAIN 0x05 //[7:0] Z_FINE_GAIN
|
||||||
|
#define MPU6050_RA_XA_OFFS_H 0x06 //[15:0] XA_OFFS
|
||||||
|
#define MPU6050_RA_XA_OFFS_L_TC 0x07
|
||||||
|
#define MPU6050_RA_YA_OFFS_H 0x08 //[15:0] YA_OFFS
|
||||||
|
#define MPU6050_RA_YA_OFFS_L_TC 0x09
|
||||||
|
#define MPU6050_RA_ZA_OFFS_H 0x0A //[15:0] ZA_OFFS
|
||||||
|
#define MPU6050_RA_ZA_OFFS_L_TC 0x0B
|
||||||
|
#define MPU6050_RA_XG_OFFS_USRH 0x13 //[15:0] XG_OFFS_USR
|
||||||
|
#define MPU6050_RA_XG_OFFS_USRL 0x14
|
||||||
|
#define MPU6050_RA_YG_OFFS_USRH 0x15 //[15:0] YG_OFFS_USR
|
||||||
|
#define MPU6050_RA_YG_OFFS_USRL 0x16
|
||||||
|
#define MPU6050_RA_ZG_OFFS_USRH 0x17 //[15:0] ZG_OFFS_USR
|
||||||
|
#define MPU6050_RA_ZG_OFFS_USRL 0x18
|
||||||
|
#define MPU6050_RA_SMPLRT_DIV 0x19
|
||||||
|
#define MPU6050_RA_CONFIG 0x1A
|
||||||
|
#define MPU6050_RA_GYRO_CONFIG 0x1B
|
||||||
|
#define MPU6050_RA_ACCEL_CONFIG 0x1C
|
||||||
|
#define MPU6050_RA_FF_THR 0x1D
|
||||||
|
#define MPU6050_RA_FF_DUR 0x1E
|
||||||
|
#define MPU6050_RA_MOT_THR 0x1F
|
||||||
|
#define MPU6050_RA_MOT_DUR 0x20
|
||||||
|
#define MPU6050_RA_ZRMOT_THR 0x21
|
||||||
|
#define MPU6050_RA_ZRMOT_DUR 0x22
|
||||||
|
#define MPU6050_RA_FIFO_EN 0x23
|
||||||
|
#define MPU6050_RA_I2C_MST_CTRL 0x24
|
||||||
|
#define MPU6050_RA_I2C_SLV0_ADDR 0x25
|
||||||
|
#define MPU6050_RA_I2C_SLV0_REG 0x26
|
||||||
|
# define MPU6050_RA_I2C_SLV0_CTRL 0x27
|
||||||
|
#define MPU6050_RA_I2C_SLV1_ADDR 0x28
|
||||||
|
#define MPU6050_RA_I2C_SLV1_REG 0x29
|
||||||
|
#define MPU6050_RA_I2C_SLV1_CTRL 0x2A
|
||||||
|
#define MPU6050_RA_I2C_SLV2_ADDR 0x2B
|
||||||
|
#define MPU6050_RA_I2C_SLV2_REG 0x2C
|
||||||
|
#define MPU6050_RA_I2C_SLV2_CTRL 0x2D
|
||||||
|
#define MPU6050_RA_I2C_SLV3_ADDR 0x2E
|
||||||
|
#define MPU6050_RA_I2C_SLV3_REG 0x2F
|
||||||
|
#define MPU6050_RA_I2C_SLV3_CTRL 0x30
|
||||||
|
#define MPU6050_RA_I2C_SLV4_ADDR 0x31
|
||||||
|
#define MPU6050_RA_I2C_SLV4_REG 0x32
|
||||||
|
#define MPU6050_RA_I2C_SLV4_DO 0x33
|
||||||
|
#define MPU6050_RA_I2C_SLV4_CTRL 0x34
|
||||||
|
#define MPU6050_RA_I2C_SLV4_DI 0x35
|
||||||
|
#define MPU6050_RA_I2C_MST_STATUS 0x36
|
||||||
|
#define MPU6050_RA_INT_PIN_CFG 0x37
|
||||||
|
#define MPU6050_RA_INT_ENABLE 0x38
|
||||||
|
#define MPU6050_RA_DMP_INT_STATUS 0x39
|
||||||
|
#define MPU6050_RA_INT_STATUS 0x3A
|
||||||
|
#define MPU6050_RA_ACCEL_XOUT_H 0x3B
|
||||||
|
#define MPU6050_RA_ACCEL_XOUT_L 0x3C
|
||||||
|
#define MPU6050_RA_ACCEL_YOUT_H 0x3D
|
||||||
|
#define MPU6050_RA_ACCEL_YOUT_L 0x3E
|
||||||
|
#define MPU6050_RA_ACCEL_ZOUT_H 0x3F
|
||||||
|
#define MPU6050_RA_ACCEL_ZOUT_L 0x40
|
||||||
|
#define MPU6050_RA_TEMP_OUT_H 0x41
|
||||||
|
#define MPU6050_RA_TEMP_OUT_L 0x42
|
||||||
|
#define MPU6050_RA_GYRO_XOUT_H 0x43
|
||||||
|
#define MPU6050_RA_GYRO_XOUT_L 0x44
|
||||||
|
#define MPU6050_RA_GYRO_YOUT_H 0x45
|
||||||
|
#define MPU6050_RA_GYRO_YOUT_L 0x46
|
||||||
|
#define MPU6050_RA_GYRO_ZOUT_H 0x47
|
||||||
|
#define MPU6050_RA_GYRO_ZOUT_L 0x48
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_00 0x49
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_01 0x4A
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_02 0x4B
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_03 0x4C
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_04 0x4D
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_05 0x4E
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_06 0x4F
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_07 0x50
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_08 0x51
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_09 0x52
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_10 0x53
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_11 0x54
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_12 0x55
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_13 0x56
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_14 0x57
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_15 0x58
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_16 0x59
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_17 0x5A
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_18 0x5B
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_19 0x5C
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_20 0x5D
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_21 0x5E
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_22 0x5F
|
||||||
|
#define MPU6050_RA_EXT_SENS_DATA_23 0x60
|
||||||
|
#define MPU6050_RA_MOT_DETECT_STATUS 0x61
|
||||||
|
#define MPU6050_RA_I2C_SLV0_DO 0x63
|
||||||
|
#define MPU6050_RA_I2C_SLV1_DO 0x64
|
||||||
|
#define MPU6050_RA_I2C_SLV2_DO 0x65
|
||||||
|
#define MPU6050_RA_I2C_SLV3_DO 0x66
|
||||||
|
#define MPU6050_RA_I2C_MST_DELAY_CTRL 0x67
|
||||||
|
#define MPU6050_RA_SIGNAL_PATH_RESET 0x68
|
||||||
|
#define MPU6050_RA_MOT_DETECT_CTRL 0x69
|
||||||
|
#define MPU6050_RA_USER_CTRL 0x6A
|
||||||
|
#define MPU6050_RA_PWR_MGMT_1 0x6B
|
||||||
|
#define MPU6050_RA_PWR_MGMT_2 0x6C
|
||||||
|
#define MPU6050_RA_BANK_SEL 0x6D
|
||||||
|
#define MPU6050_RA_MEM_START_ADDR 0x6E
|
||||||
|
#define MPU6050_RA_MEM_R_W 0x6F
|
||||||
|
#define MPU6050_RA_DMP_CFG_1 0x70
|
||||||
|
#define MPU6050_RA_DMP_CFG_2 0x71
|
||||||
|
#define MPU6050_RA_FIFO_COUNTH 0x72
|
||||||
|
#define MPU6050_RA_FIFO_COUNTL 0x73
|
||||||
|
#define MPU6050_RA_FIFO_R_W 0x74
|
||||||
|
#define MPU6050_RA_WHO_AM_I 0x75
|
||||||
|
|
||||||
|
#define MPU6050_TC_PWR_MODE_BIT 7
|
||||||
|
#define MPU6050_TC_OFFSET_BIT 6
|
||||||
|
#define MPU6050_TC_OFFSET_LENGTH 6
|
||||||
|
#define MPU6050_TC_OTP_BNK_VLD_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_VDDIO_LEVEL_VLOGIC 0
|
||||||
|
#define MPU6050_VDDIO_LEVEL_VDD 1
|
||||||
|
|
||||||
|
#define MPU6050_CFG_EXT_SYNC_SET_BIT 5
|
||||||
|
#define MPU6050_CFG_EXT_SYNC_SET_LENGTH 3
|
||||||
|
#define MPU6050_CFG_DLPF_CFG_BIT 2
|
||||||
|
#define MPU6050_CFG_DLPF_CFG_LENGTH 3
|
||||||
|
|
||||||
|
#define MPU6050_EXT_SYNC_DISABLED 0x0
|
||||||
|
#define MPU6050_EXT_SYNC_TEMP_OUT_L 0x1
|
||||||
|
#define MPU6050_EXT_SYNC_GYRO_XOUT_L 0x2
|
||||||
|
#define MPU6050_EXT_SYNC_GYRO_YOUT_L 0x3
|
||||||
|
#define MPU6050_EXT_SYNC_GYRO_ZOUT_L 0x4
|
||||||
|
#define MPU6050_EXT_SYNC_ACCEL_XOUT_L 0x5
|
||||||
|
#define MPU6050_EXT_SYNC_ACCEL_YOUT_L 0x6
|
||||||
|
#define MPU6050_EXT_SYNC_ACCEL_ZOUT_L 0x7
|
||||||
|
|
||||||
|
#define MPU6050_DLPF_BW_256 0x00
|
||||||
|
#define MPU6050_DLPF_BW_188 0x01
|
||||||
|
#define MPU6050_DLPF_BW_98 0x02
|
||||||
|
#define MPU6050_DLPF_BW_42 0x03
|
||||||
|
#define MPU6050_DLPF_BW_20 0x04
|
||||||
|
#define MPU6050_DLPF_BW_10 0x05
|
||||||
|
#define MPU6050_DLPF_BW_5 0x06
|
||||||
|
|
||||||
|
#define MPU6050_GCONFIG_FS_SEL_BIT 4
|
||||||
|
#define MPU6050_GCONFIG_FS_SEL_LENGTH 2
|
||||||
|
|
||||||
|
#define MPU6050_GYRO_FS_250 0x00
|
||||||
|
#define MPU6050_GYRO_FS_500 0x01
|
||||||
|
#define MPU6050_GYRO_FS_1000 0x02
|
||||||
|
#define MPU6050_GYRO_FS_2000 0x03
|
||||||
|
|
||||||
|
#define MPU6050_ACONFIG_XA_ST_BIT 7
|
||||||
|
#define MPU6050_ACONFIG_YA_ST_BIT 6
|
||||||
|
#define MPU6050_ACONFIG_ZA_ST_BIT 5
|
||||||
|
#define MPU6050_ACONFIG_AFS_SEL_BIT 4
|
||||||
|
#define MPU6050_ACONFIG_AFS_SEL_LENGTH 2
|
||||||
|
#define MPU6050_ACONFIG_ACCEL_HPF_BIT 2
|
||||||
|
#define MPU6050_ACONFIG_ACCEL_HPF_LENGTH 3
|
||||||
|
|
||||||
|
#define MPU6050_ACCEL_FS_2 0x00
|
||||||
|
#define MPU6050_ACCEL_FS_4 0x01
|
||||||
|
#define MPU6050_ACCEL_FS_8 0x02
|
||||||
|
#define MPU6050_ACCEL_FS_16 0x03
|
||||||
|
|
||||||
|
#define MPU6050_DHPF_RESET 0x00
|
||||||
|
#define MPU6050_DHPF_5 0x01
|
||||||
|
#define MPU6050_DHPF_2P5 0x02
|
||||||
|
#define MPU6050_DHPF_1P25 0x03
|
||||||
|
#define MPU6050_DHPF_0P63 0x04
|
||||||
|
#define MPU6050_DHPF_HOLD 0x07
|
||||||
|
|
||||||
|
#define MPU6050_TEMP_FIFO_EN_BIT 7
|
||||||
|
#define MPU6050_XG_FIFO_EN_BIT 6
|
||||||
|
#define MPU6050_YG_FIFO_EN_BIT 5
|
||||||
|
#define MPU6050_ZG_FIFO_EN_BIT 4
|
||||||
|
#define MPU6050_ACCEL_FIFO_EN_BIT 3
|
||||||
|
#define MPU6050_SLV2_FIFO_EN_BIT 2
|
||||||
|
#define MPU6050_SLV1_FIFO_EN_BIT 1
|
||||||
|
#define MPU6050_SLV0_FIFO_EN_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_MULT_MST_EN_BIT 7
|
||||||
|
#define MPU6050_WAIT_FOR_ES_BIT 6
|
||||||
|
#define MPU6050_SLV_3_FIFO_EN_BIT 5
|
||||||
|
#define MPU6050_I2C_MST_P_NSR_BIT 4
|
||||||
|
#define MPU6050_I2C_MST_CLK_BIT 3
|
||||||
|
#define MPU6050_I2C_MST_CLK_LENGTH 4
|
||||||
|
|
||||||
|
#define MPU6050_CLOCK_DIV_348 0x0
|
||||||
|
#define MPU6050_CLOCK_DIV_333 0x1
|
||||||
|
#define MPU6050_CLOCK_DIV_320 0x2
|
||||||
|
#define MPU6050_CLOCK_DIV_308 0x3
|
||||||
|
#define MPU6050_CLOCK_DIV_296 0x4
|
||||||
|
#define MPU6050_CLOCK_DIV_286 0x5
|
||||||
|
#define MPU6050_CLOCK_DIV_276 0x6
|
||||||
|
#define MPU6050_CLOCK_DIV_267 0x7
|
||||||
|
#define MPU6050_CLOCK_DIV_258 0x8
|
||||||
|
#define MPU6050_CLOCK_DIV_500 0x9
|
||||||
|
#define MPU6050_CLOCK_DIV_471 0xA
|
||||||
|
#define MPU6050_CLOCK_DIV_444 0xB
|
||||||
|
#define MPU6050_CLOCK_DIV_421 0xC
|
||||||
|
#define MPU6050_CLOCK_DIV_400 0xD
|
||||||
|
#define MPU6050_CLOCK_DIV_381 0xE
|
||||||
|
#define MPU6050_CLOCK_DIV_364 0xF
|
||||||
|
|
||||||
|
#define MPU6050_I2C_SLV_RW_BIT 7
|
||||||
|
#define MPU6050_I2C_SLV_ADDR_BIT 6
|
||||||
|
#define MPU6050_I2C_SLV_ADDR_LENGTH 7
|
||||||
|
#define MPU6050_I2C_SLV_EN_BIT 7
|
||||||
|
#define MPU6050_I2C_SLV_BYTE_SW_BIT 6
|
||||||
|
#define MPU6050_I2C_SLV_REG_DIS_BIT 5
|
||||||
|
#define MPU6050_I2C_SLV_GRP_BIT 4
|
||||||
|
#define MPU6050_I2C_SLV_LEN_BIT 3
|
||||||
|
#define MPU6050_I2C_SLV_LEN_LENGTH 4
|
||||||
|
|
||||||
|
#define MPU6050_I2C_SLV4_RW_BIT 7
|
||||||
|
#define MPU6050_I2C_SLV4_ADDR_BIT 6
|
||||||
|
#define MPU6050_I2C_SLV4_ADDR_LENGTH 7
|
||||||
|
#define MPU6050_I2C_SLV4_EN_BIT 7
|
||||||
|
#define MPU6050_I2C_SLV4_INT_EN_BIT 6
|
||||||
|
#define MPU6050_I2C_SLV4_REG_DIS_BIT 5
|
||||||
|
#define MPU6050_I2C_SLV4_MST_DLY_BIT 4
|
||||||
|
#define MPU6050_I2C_SLV4_MST_DLY_LENGTH 5
|
||||||
|
|
||||||
|
#define MPU6050_MST_PASS_THROUGH_BIT 7
|
||||||
|
#define MPU6050_MST_I2C_SLV4_DONE_BIT 6
|
||||||
|
#define MPU6050_MST_I2C_LOST_ARB_BIT 5
|
||||||
|
#define MPU6050_MST_I2C_SLV4_NACK_BIT 4
|
||||||
|
#define MPU6050_MST_I2C_SLV3_NACK_BIT 3
|
||||||
|
#define MPU6050_MST_I2C_SLV2_NACK_BIT 2
|
||||||
|
#define MPU6050_MST_I2C_SLV1_NACK_BIT 1
|
||||||
|
#define MPU6050_MST_I2C_SLV0_NACK_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_INTCFG_INT_LEVEL_BIT 7
|
||||||
|
#define MPU6050_INTCFG_INT_OPEN_BIT 6
|
||||||
|
#define MPU6050_INTCFG_LATCH_INT_EN_BIT 5
|
||||||
|
#define MPU6050_INTCFG_INT_RD_CLEAR_BIT 4
|
||||||
|
#define MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT 3
|
||||||
|
#define MPU6050_INTCFG_FSYNC_INT_EN_BIT 2
|
||||||
|
#define MPU6050_INTCFG_I2C_BYPASS_EN_BIT 1
|
||||||
|
#define MPU6050_INTCFG_CLKOUT_EN_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_INTMODE_ACTIVEHIGH 0x00
|
||||||
|
#define MPU6050_INTMODE_ACTIVELOW 0x01
|
||||||
|
|
||||||
|
#define MPU6050_INTDRV_PUSHPULL 0x00
|
||||||
|
#define MPU6050_INTDRV_OPENDRAIN 0x01
|
||||||
|
|
||||||
|
#define MPU6050_INTLATCH_50USPULSE 0x00
|
||||||
|
#define MPU6050_INTLATCH_WAITCLEAR 0x01
|
||||||
|
|
||||||
|
#define MPU6050_INTCLEAR_STATUSREAD 0x00
|
||||||
|
#define MPU6050_INTCLEAR_ANYREAD 0x01
|
||||||
|
|
||||||
|
#define MPU6050_INTERRUPT_FF_BIT 7
|
||||||
|
#define MPU6050_INTERRUPT_MOT_BIT 6
|
||||||
|
#define MPU6050_INTERRUPT_ZMOT_BIT 5
|
||||||
|
#define MPU6050_INTERRUPT_FIFO_OFLOW_BIT 4
|
||||||
|
#define MPU6050_INTERRUPT_I2C_MST_INT_BIT 3
|
||||||
|
#define MPU6050_INTERRUPT_PLL_RDY_INT_BIT 2
|
||||||
|
#define MPU6050_INTERRUPT_DMP_INT_BIT 1
|
||||||
|
#define MPU6050_INTERRUPT_DATA_RDY_BIT 0
|
||||||
|
|
||||||
|
// TODO: figure out what these actually do
|
||||||
|
// UMPL source code is not very obivous
|
||||||
|
#define MPU6050_DMPINT_5_BIT 5
|
||||||
|
#define MPU6050_DMPINT_4_BIT 4
|
||||||
|
#define MPU6050_DMPINT_3_BIT 3
|
||||||
|
#define MPU6050_DMPINT_2_BIT 2
|
||||||
|
#define MPU6050_DMPINT_1_BIT 1
|
||||||
|
#define MPU6050_DMPINT_0_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_MOTION_MOT_XNEG_BIT 7
|
||||||
|
#define MPU6050_MOTION_MOT_XPOS_BIT 6
|
||||||
|
#define MPU6050_MOTION_MOT_YNEG_BIT 5
|
||||||
|
#define MPU6050_MOTION_MOT_YPOS_BIT 4
|
||||||
|
#define MPU6050_MOTION_MOT_ZNEG_BIT 3
|
||||||
|
#define MPU6050_MOTION_MOT_ZPOS_BIT 2
|
||||||
|
#define MPU6050_MOTION_MOT_ZRMOT_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT 7
|
||||||
|
#define MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT 4
|
||||||
|
#define MPU6050_DELAYCTRL_I2C_SLV3_DLY_EN_BIT 3
|
||||||
|
#define MPU6050_DELAYCTRL_I2C_SLV2_DLY_EN_BIT 2
|
||||||
|
#define MPU6050_DELAYCTRL_I2C_SLV1_DLY_EN_BIT 1
|
||||||
|
#define MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_PATHRESET_GYRO_RESET_BIT 2
|
||||||
|
#define MPU6050_PATHRESET_ACCEL_RESET_BIT 1
|
||||||
|
#define MPU6050_PATHRESET_TEMP_RESET_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_DETECT_ACCEL_ON_DELAY_BIT 5
|
||||||
|
#define MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH 2
|
||||||
|
#define MPU6050_DETECT_FF_COUNT_BIT 3
|
||||||
|
#define MPU6050_DETECT_FF_COUNT_LENGTH 2
|
||||||
|
#define MPU6050_DETECT_MOT_COUNT_BIT 1
|
||||||
|
#define MPU6050_DETECT_MOT_COUNT_LENGTH 2
|
||||||
|
|
||||||
|
#define MPU6050_DETECT_DECREMENT_RESET 0x0
|
||||||
|
#define MPU6050_DETECT_DECREMENT_1 0x1
|
||||||
|
#define MPU6050_DETECT_DECREMENT_2 0x2
|
||||||
|
#define MPU6050_DETECT_DECREMENT_4 0x3
|
||||||
|
|
||||||
|
#define MPU6050_USERCTRL_DMP_EN_BIT 7
|
||||||
|
#define MPU6050_USERCTRL_FIFO_EN_BIT 6
|
||||||
|
#define MPU6050_USERCTRL_I2C_MST_EN_BIT 5
|
||||||
|
#define MPU6050_USERCTRL_I2C_IF_DIS_BIT 4
|
||||||
|
#define MPU6050_USERCTRL_DMP_RESET_BIT 3
|
||||||
|
#define MPU6050_USERCTRL_FIFO_RESET_BIT 2
|
||||||
|
#define MPU6050_USERCTRL_I2C_MST_RESET_BIT 1
|
||||||
|
#define MPU6050_USERCTRL_SIG_COND_RESET_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_PWR1_DEVICE_RESET_BIT 7
|
||||||
|
#define MPU6050_PWR1_SLEEP_BIT 6
|
||||||
|
#define MPU6050_PWR1_CYCLE_BIT 5
|
||||||
|
#define MPU6050_PWR1_TEMP_DIS_BIT 3
|
||||||
|
#define MPU6050_PWR1_CLKSEL_BIT 2
|
||||||
|
#define MPU6050_PWR1_CLKSEL_LENGTH 3
|
||||||
|
|
||||||
|
#define MPU6050_CLOCK_INTERNAL 0x00
|
||||||
|
#define MPU6050_CLOCK_PLL_XGYRO 0x01
|
||||||
|
#define MPU6050_CLOCK_PLL_YGYRO 0x02
|
||||||
|
#define MPU6050_CLOCK_PLL_ZGYRO 0x03
|
||||||
|
#define MPU6050_CLOCK_PLL_EXT32K 0x04
|
||||||
|
#define MPU6050_CLOCK_PLL_EXT19M 0x05
|
||||||
|
#define MPU6050_CLOCK_KEEP_RESET 0x07
|
||||||
|
|
||||||
|
#define MPU6050_PWR2_LP_WAKE_CTRL_BIT 7
|
||||||
|
#define MPU6050_PWR2_LP_WAKE_CTRL_LENGTH 2
|
||||||
|
#define MPU6050_PWR2_STBY_XA_BIT 5
|
||||||
|
#define MPU6050_PWR2_STBY_YA_BIT 4
|
||||||
|
#define MPU6050_PWR2_STBY_ZA_BIT 3
|
||||||
|
#define MPU6050_PWR2_STBY_XG_BIT 2
|
||||||
|
#define MPU6050_PWR2_STBY_YG_BIT 1
|
||||||
|
#define MPU6050_PWR2_STBY_ZG_BIT 0
|
||||||
|
|
||||||
|
#define MPU6050_WAKE_FREQ_1P25 0x0
|
||||||
|
#define MPU6050_WAKE_FREQ_2P5 0x1
|
||||||
|
#define MPU6050_WAKE_FREQ_5 0x2
|
||||||
|
#define MPU6050_WAKE_FREQ_10 0x3
|
||||||
|
|
||||||
|
#define MPU6050_BANKSEL_PRFTCH_EN_BIT 6
|
||||||
|
#define MPU6050_BANKSEL_CFG_USER_BANK_BIT 5
|
||||||
|
#define MPU6050_BANKSEL_MEM_SEL_BIT 4
|
||||||
|
#define MPU6050_BANKSEL_MEM_SEL_LENGTH 5
|
||||||
|
|
||||||
|
#define MPU6050_WHO_AM_I_BIT 6
|
||||||
|
#define MPU6050_WHO_AM_I_LENGTH 6
|
||||||
|
extern short gyro[3], accel[3];
|
||||||
|
extern int16_t Gx_offset,Gy_offset,Gz_offset;
|
||||||
|
extern float Acc1G_Values;
|
||||||
|
extern float Roll,Pitch;
|
||||||
|
//供外部调用的API
|
||||||
|
void MPU6050_initialize(void); //初始化
|
||||||
|
uint8_t MPU6050_testConnection(void); //检测MPU6050是否存在
|
||||||
|
//读取ADC值
|
||||||
|
void MPU6050_getMotion6(int16_t* ax, int16_t* ay, int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz);
|
||||||
|
void MPU6050_getlastMotion6(int16_t* ax, int16_t* ay,
|
||||||
|
int16_t* az, int16_t* gx, int16_t* gy, int16_t* gz);
|
||||||
|
uint8_t MPU6050_getDeviceID(void); //读取MPU6050的ID
|
||||||
|
void MPU6050_InitGyro_Offset(void);//初始化陀螺仪偏置
|
||||||
|
void DMP_Init(void);
|
||||||
|
void Read_DMP(void);
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,310 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#include "oled.h"
|
||||||
|
#include "stdlib.h"
|
||||||
|
#include "oledfont.h"
|
||||||
|
#include "delay.h"
|
||||||
|
u8 OLED_GRAM[128][8];
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Refresh the OLED screen
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：刷新OLED屏幕
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void OLED_Refresh_Gram(void)
|
||||||
|
{
|
||||||
|
u8 i, n;
|
||||||
|
for (i = 0; i < 8; i++)
|
||||||
|
{
|
||||||
|
OLED_WR_Byte(0xb0 + i, OLED_CMD); // 设置页地址（0~7）
|
||||||
|
OLED_WR_Byte(0x00, OLED_CMD); // 设置显示位置—列低地址
|
||||||
|
OLED_WR_Byte(0x10, OLED_CMD); // 设置显示位置—列高地址
|
||||||
|
for (n = 0; n < 128; n++)
|
||||||
|
OLED_WR_Byte(OLED_GRAM[n][i], OLED_DATA);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Refresh the OLED screen
|
||||||
|
Input : Dat: data/command to write, CMD: data/command flag 0, represents the command;1, represents data
|
||||||
|
Output : none
|
||||||
|
函数功能：向OLED写入一个字节
|
||||||
|
入口参数：dat:要写入的数据/命令，cmd:数据/命令标志 0,表示命令;1,表示数据
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void OLED_WR_Byte(u8 dat, u8 cmd)
|
||||||
|
{
|
||||||
|
u8 i;
|
||||||
|
if (cmd)
|
||||||
|
OLED_RS_Set();
|
||||||
|
else
|
||||||
|
OLED_RS_Clr();
|
||||||
|
for (i = 0; i < 8; i++)
|
||||||
|
{
|
||||||
|
OLED_SCLK_Clr();
|
||||||
|
if (dat & 0x80)
|
||||||
|
OLED_SDIN_Set();
|
||||||
|
else
|
||||||
|
OLED_SDIN_Clr();
|
||||||
|
OLED_SCLK_Set();
|
||||||
|
dat <<= 1;
|
||||||
|
}
|
||||||
|
OLED_RS_Set();
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Turn on the OLED display
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：开启OLED显示
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void OLED_Display_On(void)
|
||||||
|
{
|
||||||
|
OLED_WR_Byte(0X8D, OLED_CMD); // SET DCDC命令
|
||||||
|
OLED_WR_Byte(0X14, OLED_CMD); // DCDC ON
|
||||||
|
OLED_WR_Byte(0XAF, OLED_CMD); // DISPLAY ON
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Turn off the OLED display
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：关闭OLED显示
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void OLED_Display_Off(void)
|
||||||
|
{
|
||||||
|
OLED_WR_Byte(0X8D, OLED_CMD); // SET DCDC命令
|
||||||
|
OLED_WR_Byte(0X10, OLED_CMD); // DCDC OFF
|
||||||
|
OLED_WR_Byte(0XAE, OLED_CMD); // DISPLAY OFF
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Screen clear function, clear the screen, the entire screen is black, and did not light up the same
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：清屏函数,清完屏,整个屏幕是黑色的，和没点亮一样
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void OLED_Clear(void)
|
||||||
|
{
|
||||||
|
u8 i, n;
|
||||||
|
for (i = 0; i < 8; i++)
|
||||||
|
for (n = 0; n < 128; n++)
|
||||||
|
OLED_GRAM[n][i] = 0X00;
|
||||||
|
OLED_Refresh_Gram(); // 更新显示
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Draw point
|
||||||
|
Input : x,y: starting coordinate;T :1, fill,0, empty
|
||||||
|
Output : none
|
||||||
|
函数功能：画点
|
||||||
|
入口参数：x,y :起点坐标; t:1,填充,0,清空
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void OLED_DrawPoint(u8 x, u8 y, u8 t)
|
||||||
|
{
|
||||||
|
u8 pos, bx, temp = 0;
|
||||||
|
if (x > 127 || y > 63)
|
||||||
|
return; // 超出范围了.
|
||||||
|
pos = 7 - y / 8;
|
||||||
|
bx = y % 8;
|
||||||
|
temp = 1 << (7 - bx);
|
||||||
|
if (t)
|
||||||
|
OLED_GRAM[x][pos] |= temp;
|
||||||
|
else
|
||||||
|
OLED_GRAM[x][pos] &= ~temp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Displays a character, including partial characters, at the specified position
|
||||||
|
Input : x,y: starting coordinate;Len: The number of digits;Size: font size;Mode :0, anti-white display,1, normal display
|
||||||
|
Output : none
|
||||||
|
函数功能：在指定位置显示一个字符,包括部分字符
|
||||||
|
入口参数：x,y :起点坐标; len :数字的位数; size:字体大小; mode:0,反白显示,1,正常显示
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void OLED_ShowChar(u8 x, u8 y, u8 chr, u8 size, u8 mode)
|
||||||
|
{
|
||||||
|
u8 temp, t, t1;
|
||||||
|
u8 y0 = y;
|
||||||
|
chr = chr - ' '; // 得到偏移后的值
|
||||||
|
for (t = 0; t < size; t++)
|
||||||
|
{
|
||||||
|
if (size == 12)
|
||||||
|
temp = oled_asc2_1206[chr][t]; // 调用1206字体
|
||||||
|
else
|
||||||
|
temp = oled_asc2_1608[chr][t]; // 调用1608字体
|
||||||
|
for (t1 = 0; t1 < 8; t1++)
|
||||||
|
{
|
||||||
|
if (temp & 0x80)
|
||||||
|
OLED_DrawPoint(x, y, mode);
|
||||||
|
else
|
||||||
|
OLED_DrawPoint(x, y, !mode);
|
||||||
|
temp <<= 1;
|
||||||
|
y++;
|
||||||
|
if ((y - y0) == size)
|
||||||
|
{
|
||||||
|
y = y0;
|
||||||
|
x++;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Find m to the NTH power
|
||||||
|
Input : m: base number, n: power number
|
||||||
|
Output : none
|
||||||
|
函数功能：求m的n次方的函数
|
||||||
|
入口参数：m：底数，n：次方数
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
u32 oled_pow(u8 m, u8 n)
|
||||||
|
{
|
||||||
|
u32 result = 1;
|
||||||
|
while (n--)
|
||||||
|
result *= m;
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Displays 2 numbers
|
||||||
|
Input : x,y: starting coordinate;Len: The number of digits;Size: font size;Mode: mode, 0, fill mode, 1, overlay mode;Num: value (0 ~ 4294967295);
|
||||||
|
Output : none
|
||||||
|
函数功能：显示2个数字
|
||||||
|
入口参数：x,y :起点坐标; len :数字的位数; size:字体大小; mode:模式, 0,填充模式, 1,叠加模式; num:数值(0~4294967295);
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void OLED_ShowNumber(u8 x, u8 y, u32 num, u8 len, u8 size)
|
||||||
|
{
|
||||||
|
u8 t, temp;
|
||||||
|
u8 enshow = 0;
|
||||||
|
for (t = 0; t < len; t++)
|
||||||
|
{
|
||||||
|
temp = (num / oled_pow(10, len - t - 1)) % 10;
|
||||||
|
if (enshow == 0 && t < (len - 1))
|
||||||
|
{
|
||||||
|
if (temp == 0)
|
||||||
|
{
|
||||||
|
OLED_ShowChar(x + (size / 2) * t, y, ' ', size, 1);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
enshow = 1;
|
||||||
|
}
|
||||||
|
OLED_ShowChar(x + (size / 2) * t, y, temp + '0', size, 1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Display string
|
||||||
|
Input : x,y: starting coordinate;*p: starting address of the string
|
||||||
|
Output : none
|
||||||
|
函数功能：显示字符串
|
||||||
|
入口参数：x,y :起点坐标; *p:字符串起始地址
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
// 用16字体
|
||||||
|
void OLED_ShowString(u8 x, u8 y, const u8 *p)
|
||||||
|
{
|
||||||
|
#define MAX_CHAR_POSX 122
|
||||||
|
#define MAX_CHAR_POSY 58
|
||||||
|
while (*p != '\0')
|
||||||
|
{
|
||||||
|
if (x > MAX_CHAR_POSX)
|
||||||
|
{
|
||||||
|
x = 0;
|
||||||
|
y += 16;
|
||||||
|
}
|
||||||
|
if (y > MAX_CHAR_POSY)
|
||||||
|
{
|
||||||
|
y = x = 0;
|
||||||
|
OLED_Clear();
|
||||||
|
}
|
||||||
|
OLED_ShowChar(x, y, *p, 12, 1);
|
||||||
|
x += 8;
|
||||||
|
p++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Initialize the OLED
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：初始化OLED
|
||||||
|
入口参数: 无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void OLED_Init(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); // 使能PB端口时钟
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5; // 端口配置
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; // 推挽输出
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; // 2M
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure); // 根据设定参数初始化GPIO
|
||||||
|
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); // 开A口时钟。
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; // 设为输出
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
PWR_BackupAccessCmd(ENABLE); // 允许修改RTC 和后备寄存器
|
||||||
|
RCC_LSEConfig(RCC_LSE_OFF); // 关闭外部低速外部时钟信号功能 后，PC13 PC14 PC15 才可以当普通IO用。
|
||||||
|
BKP_TamperPinCmd(DISABLE); // 关闭入侵检测功能，也就是 PC13，也可以当普通IO 使用
|
||||||
|
PWR_BackupAccessCmd(DISABLE); // 禁止修改后备寄存器
|
||||||
|
|
||||||
|
OLED_RST_Clr();
|
||||||
|
delay_ms(100);
|
||||||
|
OLED_RST_Set();
|
||||||
|
|
||||||
|
OLED_WR_Byte(0xAE, OLED_CMD); // 关闭显示
|
||||||
|
OLED_WR_Byte(0xD5, OLED_CMD); // 设置时钟分频因子,震荡频率
|
||||||
|
OLED_WR_Byte(80, OLED_CMD); //[3:0],分频因子;[7:4],震荡频率
|
||||||
|
OLED_WR_Byte(0xA8, OLED_CMD); // 设置驱动路数
|
||||||
|
OLED_WR_Byte(0X3F, OLED_CMD); // 默认0X3F(1/64)
|
||||||
|
OLED_WR_Byte(0xD3, OLED_CMD); // 设置显示偏移
|
||||||
|
OLED_WR_Byte(0X00, OLED_CMD); // 默认为0
|
||||||
|
|
||||||
|
OLED_WR_Byte(0x40, OLED_CMD); // 设置显示开始行 [5:0],行数.
|
||||||
|
|
||||||
|
OLED_WR_Byte(0x8D, OLED_CMD); // 电荷泵设置
|
||||||
|
OLED_WR_Byte(0x14, OLED_CMD); // bit2，开启/关闭
|
||||||
|
OLED_WR_Byte(0x20, OLED_CMD); // 设置内存地址模式
|
||||||
|
OLED_WR_Byte(0x02, OLED_CMD); //[1:0],00，列地址模式;01，行地址模式;10,页地址模式;默认10;
|
||||||
|
OLED_WR_Byte(0xA1, OLED_CMD); // 段重定义设置,bit0:0,0->0;1,0->127;
|
||||||
|
OLED_WR_Byte(0xC0, OLED_CMD); // 设置COM扫描方向;bit3:0,普通模式;1,重定义模式 COM[N-1]->COM0;N:驱动路数
|
||||||
|
OLED_WR_Byte(0xDA, OLED_CMD); // 设置COM硬件引脚配置
|
||||||
|
OLED_WR_Byte(0x12, OLED_CMD); //[5:4]配置
|
||||||
|
|
||||||
|
OLED_WR_Byte(0x81, OLED_CMD); // 对比度设置
|
||||||
|
OLED_WR_Byte(0xEF, OLED_CMD); // 1~255;默认0X7F (亮度设置,越大越亮)
|
||||||
|
OLED_WR_Byte(0xD9, OLED_CMD); // 设置预充电周期
|
||||||
|
OLED_WR_Byte(0xf1, OLED_CMD); //[3:0],PHASE 1;[7:4],PHASE 2;
|
||||||
|
OLED_WR_Byte(0xDB, OLED_CMD); // 设置VCOMH 电压倍率
|
||||||
|
OLED_WR_Byte(0x30, OLED_CMD); //[6:4] 000,0.65*vcc;001,0.77*vcc;011,0.83*vcc;
|
||||||
|
|
||||||
|
OLED_WR_Byte(0xA4, OLED_CMD); // 全局显示开启;bit0:1,开启;0,关闭;(白屏/黑屏)
|
||||||
|
OLED_WR_Byte(0xA6, OLED_CMD); // 设置显示方式;bit0:1,反相显示;0,正常显示
|
||||||
|
OLED_WR_Byte(0xAF, OLED_CMD); // 开启显示
|
||||||
|
OLED_Clear();
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#ifndef __OLED_H
|
||||||
|
#define __OLED_H
|
||||||
|
#include "sys.h"
|
||||||
|
//-----------------OLED端口定义----------------
|
||||||
|
#define OLED_RST_Clr() PBout(3)=0 //RST
|
||||||
|
#define OLED_RST_Set() PBout(3)=1 //RST
|
||||||
|
|
||||||
|
#define OLED_RS_Clr() PAout(15)=0 //DC
|
||||||
|
#define OLED_RS_Set() PAout(15)=1 //DC
|
||||||
|
|
||||||
|
#define OLED_SCLK_Clr() PBout(5)=0 //SCL
|
||||||
|
#define OLED_SCLK_Set() PBout(5)=1 //SCL
|
||||||
|
|
||||||
|
#define OLED_SDIN_Clr() PBout(4)=0 //SDA
|
||||||
|
#define OLED_SDIN_Set() PBout(4)=1 //SDA
|
||||||
|
|
||||||
|
#define OLED_CMD 0 //写命令
|
||||||
|
#define OLED_DATA 1 //写数据
|
||||||
|
//OLED控制用函数
|
||||||
|
void OLED_WR_Byte(u8 dat,u8 cmd);
|
||||||
|
void OLED_Display_On(void);
|
||||||
|
void OLED_Display_Off(void);
|
||||||
|
void OLED_Refresh_Gram(void);
|
||||||
|
void OLED_Init(void);
|
||||||
|
void OLED_Clear(void);
|
||||||
|
void OLED_DrawPoint(u8 x,u8 y,u8 t);
|
||||||
|
void OLED_ShowChar(u8 x,u8 y,u8 chr,u8 size,u8 mode);
|
||||||
|
void OLED_ShowNumber(u8 x,u8 y,u32 num,u8 len,u8 size);
|
||||||
|
void OLED_ShowString(u8 x,u8 y,const u8 *p);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
@ -0,0 +1,202 @@
|
||||||
|
#ifndef __OLEDFONT_H
|
||||||
|
#define __OLEDFONT_H
|
||||||
|
//常用ASCII表
|
||||||
|
//偏移量32
|
||||||
|
//ASCII字符集
|
||||||
|
//偏移量32
|
||||||
|
//大小:12*6
|
||||||
|
const unsigned char oled_asc2_1206[95][12]={
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x3F,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/
|
||||||
|
{0x00,0x00,0x30,0x00,0x40,0x00,0x30,0x00,0x40,0x00,0x00,0x00},/*""",2*/
|
||||||
|
{0x09,0x00,0x0B,0xC0,0x3D,0x00,0x0B,0xC0,0x3D,0x00,0x09,0x00},/*"#",3*/
|
||||||
|
{0x18,0xC0,0x24,0x40,0x7F,0xE0,0x22,0x40,0x31,0x80,0x00,0x00},/*"$",4*/
|
||||||
|
{0x18,0x00,0x24,0xC0,0x1B,0x00,0x0D,0x80,0x32,0x40,0x01,0x80},/*"%",5*/
|
||||||
|
{0x03,0x80,0x1C,0x40,0x27,0x40,0x1C,0x80,0x07,0x40,0x00,0x40},/*"&",6*/
|
||||||
|
{0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x20,0x40,0x40,0x20},/*"(",8*/
|
||||||
|
{0x00,0x00,0x40,0x20,0x20,0x40,0x1F,0x80,0x00,0x00,0x00,0x00},/*")",9*/
|
||||||
|
{0x09,0x00,0x06,0x00,0x1F,0x80,0x06,0x00,0x09,0x00,0x00,0x00},/*"*",10*/
|
||||||
|
{0x04,0x00,0x04,0x00,0x3F,0x80,0x04,0x00,0x04,0x00,0x00,0x00},/*"+",11*/
|
||||||
|
{0x00,0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/
|
||||||
|
{0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x00,0x00},/*"-",13*/
|
||||||
|
{0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/
|
||||||
|
{0x00,0x20,0x01,0xC0,0x06,0x00,0x38,0x00,0x40,0x00,0x00,0x00},/*"/",15*/
|
||||||
|
{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"0",16*/
|
||||||
|
{0x00,0x00,0x10,0x40,0x3F,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"1",17*/
|
||||||
|
{0x18,0xC0,0x21,0x40,0x22,0x40,0x24,0x40,0x18,0x40,0x00,0x00},/*"2",18*/
|
||||||
|
{0x10,0x80,0x20,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"3",19*/
|
||||||
|
{0x02,0x00,0x0D,0x00,0x11,0x00,0x3F,0xC0,0x01,0x40,0x00,0x00},/*"4",20*/
|
||||||
|
{0x3C,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x23,0x80,0x00,0x00},/*"5",21*/
|
||||||
|
{0x1F,0x80,0x24,0x40,0x24,0x40,0x34,0x40,0x03,0x80,0x00,0x00},/*"6",22*/
|
||||||
|
{0x30,0x00,0x20,0x00,0x27,0xC0,0x38,0x00,0x20,0x00,0x00,0x00},/*"7",23*/
|
||||||
|
{0x1B,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"8",24*/
|
||||||
|
{0x1C,0x00,0x22,0xC0,0x22,0x40,0x22,0x40,0x1F,0x80,0x00,0x00},/*"9",25*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x08,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x04,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/
|
||||||
|
{0x00,0x00,0x04,0x00,0x0A,0x00,0x11,0x00,0x20,0x80,0x40,0x40},/*"<",28*/
|
||||||
|
{0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x00,0x00},/*"=",29*/
|
||||||
|
{0x00,0x00,0x40,0x40,0x20,0x80,0x11,0x00,0x0A,0x00,0x04,0x00},/*">",30*/
|
||||||
|
{0x18,0x00,0x20,0x00,0x23,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"?",31*/
|
||||||
|
{0x1F,0x80,0x20,0x40,0x27,0x40,0x29,0x40,0x1F,0x40,0x00,0x00},/*"@",32*/
|
||||||
|
{0x00,0x40,0x07,0xC0,0x39,0x00,0x0F,0x00,0x01,0xC0,0x00,0x40},/*"A",33*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"B",34*/
|
||||||
|
{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x30,0x80,0x00,0x00},/*"C",35*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"D",36*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x40,0x30,0xC0,0x00,0x00},/*"E",37*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x00,0x30,0x00,0x00,0x00},/*"F",38*/
|
||||||
|
{0x0F,0x00,0x10,0x80,0x20,0x40,0x22,0x40,0x33,0x80,0x02,0x00},/*"G",39*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x04,0x00,0x04,0x00,0x3F,0xC0,0x20,0x40},/*"H",40*/
|
||||||
|
{0x20,0x40,0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x00,0x00},/*"I",41*/
|
||||||
|
{0x00,0x60,0x20,0x20,0x20,0x20,0x3F,0xC0,0x20,0x00,0x20,0x00},/*"J",42*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x24,0x40,0x0B,0x00,0x30,0xC0,0x20,0x40},/*"K",43*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x20,0x40,0x00,0x40,0x00,0x40,0x00,0xC0},/*"L",44*/
|
||||||
|
{0x3F,0xC0,0x3C,0x00,0x03,0xC0,0x3C,0x00,0x3F,0xC0,0x00,0x00},/*"M",45*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x0C,0x40,0x23,0x00,0x3F,0xC0,0x20,0x00},/*"N",46*/
|
||||||
|
{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"O",47*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"P",48*/
|
||||||
|
{0x1F,0x80,0x21,0x40,0x21,0x40,0x20,0xE0,0x1F,0xA0,0x00,0x00},/*"Q",49*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x24,0x40,0x26,0x00,0x19,0xC0,0x00,0x40},/*"R",50*/
|
||||||
|
{0x18,0xC0,0x24,0x40,0x24,0x40,0x22,0x40,0x31,0x80,0x00,0x00},/*"S",51*/
|
||||||
|
{0x30,0x00,0x20,0x40,0x3F,0xC0,0x20,0x40,0x30,0x00,0x00,0x00},/*"T",52*/
|
||||||
|
{0x20,0x00,0x3F,0x80,0x00,0x40,0x00,0x40,0x3F,0x80,0x20,0x00},/*"U",53*/
|
||||||
|
{0x20,0x00,0x3E,0x00,0x01,0xC0,0x07,0x00,0x38,0x00,0x20,0x00},/*"V",54*/
|
||||||
|
{0x38,0x00,0x07,0xC0,0x3C,0x00,0x07,0xC0,0x38,0x00,0x00,0x00},/*"W",55*/
|
||||||
|
{0x20,0x40,0x39,0xC0,0x06,0x00,0x39,0xC0,0x20,0x40,0x00,0x00},/*"X",56*/
|
||||||
|
{0x20,0x00,0x38,0x40,0x07,0xC0,0x38,0x40,0x20,0x00,0x00,0x00},/*"Y",57*/
|
||||||
|
{0x30,0x40,0x21,0xC0,0x26,0x40,0x38,0x40,0x20,0xC0,0x00,0x00},/*"Z",58*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x7F,0xE0,0x40,0x20,0x40,0x20,0x00,0x00},/*"[",59*/
|
||||||
|
{0x00,0x00,0x70,0x00,0x0C,0x00,0x03,0x80,0x00,0x40,0x00,0x00},/*"\",60*/
|
||||||
|
{0x00,0x00,0x40,0x20,0x40,0x20,0x7F,0xE0,0x00,0x00,0x00,0x00},/*"]",61*/
|
||||||
|
{0x00,0x00,0x20,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00},/*"^",62*/
|
||||||
|
{0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10},/*"_",63*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
|
||||||
|
{0x00,0x00,0x02,0x80,0x05,0x40,0x05,0x40,0x03,0xC0,0x00,0x40},/*"a",65*/
|
||||||
|
{0x20,0x00,0x3F,0xC0,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"b",66*/
|
||||||
|
{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x06,0x40,0x00,0x00},/*"c",67*/
|
||||||
|
{0x00,0x00,0x03,0x80,0x04,0x40,0x24,0x40,0x3F,0xC0,0x00,0x40},/*"d",68*/
|
||||||
|
{0x00,0x00,0x03,0x80,0x05,0x40,0x05,0x40,0x03,0x40,0x00,0x00},/*"e",69*/
|
||||||
|
{0x00,0x00,0x04,0x40,0x1F,0xC0,0x24,0x40,0x24,0x40,0x20,0x00},/*"f",70*/
|
||||||
|
{0x00,0x00,0x02,0xE0,0x05,0x50,0x05,0x50,0x06,0x50,0x04,0x20},/*"g",71*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"h",72*/
|
||||||
|
{0x00,0x00,0x04,0x40,0x27,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"i",73*/
|
||||||
|
{0x00,0x10,0x00,0x10,0x04,0x10,0x27,0xE0,0x00,0x00,0x00,0x00},/*"j",74*/
|
||||||
|
{0x20,0x40,0x3F,0xC0,0x01,0x40,0x07,0x00,0x04,0xC0,0x04,0x40},/*"k",75*/
|
||||||
|
{0x20,0x40,0x20,0x40,0x3F,0xC0,0x00,0x40,0x00,0x40,0x00,0x00},/*"l",76*/
|
||||||
|
{0x07,0xC0,0x04,0x00,0x07,0xC0,0x04,0x00,0x03,0xC0,0x00,0x00},/*"m",77*/
|
||||||
|
{0x04,0x40,0x07,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"n",78*/
|
||||||
|
{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"o",79*/
|
||||||
|
{0x04,0x10,0x07,0xF0,0x04,0x50,0x04,0x40,0x03,0x80,0x00,0x00},/*"p",80*/
|
||||||
|
{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x50,0x07,0xF0,0x00,0x10},/*"q",81*/
|
||||||
|
{0x04,0x40,0x07,0xC0,0x02,0x40,0x04,0x00,0x04,0x00,0x00,0x00},/*"r",82*/
|
||||||
|
{0x00,0x00,0x06,0x40,0x05,0x40,0x05,0x40,0x04,0xC0,0x00,0x00},/*"s",83*/
|
||||||
|
{0x00,0x00,0x04,0x00,0x1F,0x80,0x04,0x40,0x00,0x40,0x00,0x00},/*"t",84*/
|
||||||
|
{0x04,0x00,0x07,0x80,0x00,0x40,0x04,0x40,0x07,0xC0,0x00,0x40},/*"u",85*/
|
||||||
|
{0x04,0x00,0x07,0x00,0x04,0xC0,0x01,0x80,0x06,0x00,0x04,0x00},/*"v",86*/
|
||||||
|
{0x06,0x00,0x01,0xC0,0x07,0x00,0x01,0xC0,0x06,0x00,0x00,0x00},/*"w",87*/
|
||||||
|
{0x04,0x40,0x06,0xC0,0x01,0x00,0x06,0xC0,0x04,0x40,0x00,0x00},/*"x",88*/
|
||||||
|
{0x04,0x10,0x07,0x10,0x04,0xE0,0x01,0x80,0x06,0x00,0x04,0x00},/*"y",89*/
|
||||||
|
{0x00,0x00,0x04,0x40,0x05,0xC0,0x06,0x40,0x04,0x40,0x00,0x00},/*"z",90*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x04,0x00,0x7B,0xE0,0x40,0x20,0x00,0x00},/*"{",91*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00},/*"|",92*/
|
||||||
|
{0x00,0x00,0x40,0x20,0x7B,0xE0,0x04,0x00,0x00,0x00,0x00,0x00},/*"}",93*/
|
||||||
|
{0x40,0x00,0x80,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x40,0x00},/*"~",94*/
|
||||||
|
};
|
||||||
|
const unsigned char oled_asc2_1608[95][16]={
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xCC,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/
|
||||||
|
{0x00,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x00,0x00},/*""",2*/
|
||||||
|
{0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x00,0x00},/*"#",3*/
|
||||||
|
{0x00,0x00,0x0E,0x18,0x11,0x04,0x3F,0xFF,0x10,0x84,0x0C,0x78,0x00,0x00,0x00,0x00},/*"$",4*/
|
||||||
|
{0x0F,0x00,0x10,0x84,0x0F,0x38,0x00,0xC0,0x07,0x78,0x18,0x84,0x00,0x78,0x00,0x00},/*"%",5*/
|
||||||
|
{0x00,0x78,0x0F,0x84,0x10,0xC4,0x11,0x24,0x0E,0x98,0x00,0xE4,0x00,0x84,0x00,0x08},/*"&",6*/
|
||||||
|
{0x08,0x00,0x68,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x18,0x18,0x20,0x04,0x40,0x02,0x00,0x00},/*"(",8*/
|
||||||
|
{0x00,0x00,0x40,0x02,0x20,0x04,0x18,0x18,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/
|
||||||
|
{0x02,0x40,0x02,0x40,0x01,0x80,0x0F,0xF0,0x01,0x80,0x02,0x40,0x02,0x40,0x00,0x00},/*"*",10*/
|
||||||
|
{0x00,0x80,0x00,0x80,0x00,0x80,0x0F,0xF8,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00},/*"+",11*/
|
||||||
|
{0x00,0x01,0x00,0x0D,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/
|
||||||
|
{0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80},/*"-",13*/
|
||||||
|
{0x00,0x00,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/
|
||||||
|
{0x00,0x00,0x00,0x06,0x00,0x18,0x00,0x60,0x01,0x80,0x06,0x00,0x18,0x00,0x20,0x00},/*"/",15*/
|
||||||
|
{0x00,0x00,0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"0",16*/
|
||||||
|
{0x00,0x00,0x08,0x04,0x08,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"1",17*/
|
||||||
|
{0x00,0x00,0x0E,0x0C,0x10,0x14,0x10,0x24,0x10,0x44,0x11,0x84,0x0E,0x0C,0x00,0x00},/*"2",18*/
|
||||||
|
{0x00,0x00,0x0C,0x18,0x10,0x04,0x11,0x04,0x11,0x04,0x12,0x88,0x0C,0x70,0x00,0x00},/*"3",19*/
|
||||||
|
{0x00,0x00,0x00,0xE0,0x03,0x20,0x04,0x24,0x08,0x24,0x1F,0xFC,0x00,0x24,0x00,0x00},/*"4",20*/
|
||||||
|
{0x00,0x00,0x1F,0x98,0x10,0x84,0x11,0x04,0x11,0x04,0x10,0x88,0x10,0x70,0x00,0x00},/*"5",21*/
|
||||||
|
{0x00,0x00,0x07,0xF0,0x08,0x88,0x11,0x04,0x11,0x04,0x18,0x88,0x00,0x70,0x00,0x00},/*"6",22*/
|
||||||
|
{0x00,0x00,0x1C,0x00,0x10,0x00,0x10,0xFC,0x13,0x00,0x1C,0x00,0x10,0x00,0x00,0x00},/*"7",23*/
|
||||||
|
{0x00,0x00,0x0E,0x38,0x11,0x44,0x10,0x84,0x10,0x84,0x11,0x44,0x0E,0x38,0x00,0x00},/*"8",24*/
|
||||||
|
{0x00,0x00,0x07,0x00,0x08,0x8C,0x10,0x44,0x10,0x44,0x08,0x88,0x07,0xF0,0x00,0x00},/*"9",25*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x0C,0x03,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/
|
||||||
|
{0x00,0x00,0x00,0x80,0x01,0x40,0x02,0x20,0x04,0x10,0x08,0x08,0x10,0x04,0x00,0x00},/*"<",28*/
|
||||||
|
{0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x00,0x00},/*"=",29*/
|
||||||
|
{0x00,0x00,0x10,0x04,0x08,0x08,0x04,0x10,0x02,0x20,0x01,0x40,0x00,0x80,0x00,0x00},/*">",30*/
|
||||||
|
{0x00,0x00,0x0E,0x00,0x12,0x00,0x10,0x0C,0x10,0x6C,0x10,0x80,0x0F,0x00,0x00,0x00},/*"?",31*/
|
||||||
|
{0x03,0xE0,0x0C,0x18,0x13,0xE4,0x14,0x24,0x17,0xC4,0x08,0x28,0x07,0xD0,0x00,0x00},/*"@",32*/
|
||||||
|
{0x00,0x04,0x00,0x3C,0x03,0xC4,0x1C,0x40,0x07,0x40,0x00,0xE4,0x00,0x1C,0x00,0x04},/*"A",33*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x11,0x04,0x0E,0x88,0x00,0x70,0x00,0x00},/*"B",34*/
|
||||||
|
{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x04,0x10,0x08,0x1C,0x10,0x00,0x00},/*"C",35*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"D",36*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x17,0xC4,0x10,0x04,0x08,0x18,0x00,0x00},/*"E",37*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x17,0xC0,0x10,0x00,0x08,0x00,0x00,0x00},/*"F",38*/
|
||||||
|
{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x44,0x1C,0x78,0x00,0x40,0x00,0x00},/*"G",39*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x10,0x84,0x00,0x80,0x00,0x80,0x10,0x84,0x1F,0xFC,0x10,0x04},/*"H",40*/
|
||||||
|
{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x00,0x00,0x00,0x00},/*"I",41*/
|
||||||
|
{0x00,0x03,0x00,0x01,0x10,0x01,0x10,0x01,0x1F,0xFE,0x10,0x00,0x10,0x00,0x00,0x00},/*"J",42*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x11,0x04,0x03,0x80,0x14,0x64,0x18,0x1C,0x10,0x04,0x00,0x00},/*"K",43*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x10,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x0C,0x00,0x00},/*"L",44*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x1F,0x00,0x00,0xFC,0x1F,0x00,0x1F,0xFC,0x10,0x04,0x00,0x00},/*"M",45*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x0C,0x04,0x03,0x00,0x00,0xE0,0x10,0x18,0x1F,0xFC,0x10,0x00},/*"N",46*/
|
||||||
|
{0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"O",47*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x10,0x84,0x10,0x80,0x10,0x80,0x10,0x80,0x0F,0x00,0x00,0x00},/*"P",48*/
|
||||||
|
{0x07,0xF0,0x08,0x18,0x10,0x24,0x10,0x24,0x10,0x1C,0x08,0x0A,0x07,0xF2,0x00,0x00},/*"Q",49*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x11,0xC0,0x11,0x30,0x0E,0x0C,0x00,0x04},/*"R",50*/
|
||||||
|
{0x00,0x00,0x0E,0x1C,0x11,0x04,0x10,0x84,0x10,0x84,0x10,0x44,0x1C,0x38,0x00,0x00},/*"S",51*/
|
||||||
|
{0x18,0x00,0x10,0x00,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x00,0x18,0x00,0x00,0x00},/*"T",52*/
|
||||||
|
{0x10,0x00,0x1F,0xF8,0x10,0x04,0x00,0x04,0x00,0x04,0x10,0x04,0x1F,0xF8,0x10,0x00},/*"U",53*/
|
||||||
|
{0x10,0x00,0x1E,0x00,0x11,0xE0,0x00,0x1C,0x00,0x70,0x13,0x80,0x1C,0x00,0x10,0x00},/*"V",54*/
|
||||||
|
{0x1F,0xC0,0x10,0x3C,0x00,0xE0,0x1F,0x00,0x00,0xE0,0x10,0x3C,0x1F,0xC0,0x00,0x00},/*"W",55*/
|
||||||
|
{0x10,0x04,0x18,0x0C,0x16,0x34,0x01,0xC0,0x01,0xC0,0x16,0x34,0x18,0x0C,0x10,0x04},/*"X",56*/
|
||||||
|
{0x10,0x00,0x1C,0x00,0x13,0x04,0x00,0xFC,0x13,0x04,0x1C,0x00,0x10,0x00,0x00,0x00},/*"Y",57*/
|
||||||
|
{0x08,0x04,0x10,0x1C,0x10,0x64,0x10,0x84,0x13,0x04,0x1C,0x04,0x10,0x18,0x00,0x00},/*"Z",58*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x40,0x02,0x40,0x02,0x40,0x02,0x00,0x00},/*"[",59*/
|
||||||
|
{0x00,0x00,0x30,0x00,0x0C,0x00,0x03,0x80,0x00,0x60,0x00,0x1C,0x00,0x03,0x00,0x00},/*"\",60*/
|
||||||
|
{0x00,0x00,0x40,0x02,0x40,0x02,0x40,0x02,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00},/*"^",62*/
|
||||||
|
{0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01},/*"_",63*/
|
||||||
|
{0x00,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
|
||||||
|
{0x00,0x00,0x00,0x98,0x01,0x24,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xFC,0x00,0x04},/*"a",65*/
|
||||||
|
{0x10,0x00,0x1F,0xFC,0x00,0x88,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"b",66*/
|
||||||
|
{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x00},/*"c",67*/
|
||||||
|
{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x11,0x08,0x1F,0xFC,0x00,0x04},/*"d",68*/
|
||||||
|
{0x00,0x00,0x00,0xF8,0x01,0x44,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xC8,0x00,0x00},/*"e",69*/
|
||||||
|
{0x00,0x00,0x01,0x04,0x01,0x04,0x0F,0xFC,0x11,0x04,0x11,0x04,0x11,0x00,0x18,0x00},/*"f",70*/
|
||||||
|
{0x00,0x00,0x00,0xD6,0x01,0x29,0x01,0x29,0x01,0x29,0x01,0xC9,0x01,0x06,0x00,0x00},/*"g",71*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"h",72*/
|
||||||
|
{0x00,0x00,0x01,0x04,0x19,0x04,0x19,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"i",73*/
|
||||||
|
{0x00,0x00,0x00,0x03,0x00,0x01,0x01,0x01,0x19,0x01,0x19,0xFE,0x00,0x00,0x00,0x00},/*"j",74*/
|
||||||
|
{0x10,0x04,0x1F,0xFC,0x00,0x24,0x00,0x40,0x01,0xB4,0x01,0x0C,0x01,0x04,0x00,0x00},/*"k",75*/
|
||||||
|
{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"l",76*/
|
||||||
|
{0x01,0x04,0x01,0xFC,0x01,0x04,0x01,0x00,0x01,0xFC,0x01,0x04,0x01,0x00,0x00,0xFC},/*"m",77*/
|
||||||
|
{0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"n",78*/
|
||||||
|
{0x00,0x00,0x00,0xF8,0x01,0x04,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0xF8,0x00,0x00},/*"o",79*/
|
||||||
|
{0x01,0x01,0x01,0xFF,0x00,0x85,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"p",80*/
|
||||||
|
{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x05,0x01,0xFF,0x00,0x01},/*"q",81*/
|
||||||
|
{0x01,0x04,0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x04,0x01,0x00,0x01,0x80,0x00,0x00},/*"r",82*/
|
||||||
|
{0x00,0x00,0x00,0xCC,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x98,0x00,0x00},/*"s",83*/
|
||||||
|
{0x00,0x00,0x01,0x00,0x01,0x00,0x07,0xF8,0x01,0x04,0x01,0x04,0x00,0x00,0x00,0x00},/*"t",84*/
|
||||||
|
{0x01,0x00,0x01,0xF8,0x00,0x04,0x00,0x04,0x00,0x04,0x01,0x08,0x01,0xFC,0x00,0x04},/*"u",85*/
|
||||||
|
{0x01,0x00,0x01,0x80,0x01,0x70,0x00,0x0C,0x00,0x10,0x01,0x60,0x01,0x80,0x01,0x00},/*"v",86*/
|
||||||
|
{0x01,0xF0,0x01,0x0C,0x00,0x30,0x01,0xC0,0x00,0x30,0x01,0x0C,0x01,0xF0,0x01,0x00},/*"w",87*/
|
||||||
|
{0x00,0x00,0x01,0x04,0x01,0x8C,0x00,0x74,0x01,0x70,0x01,0x8C,0x01,0x04,0x00,0x00},/*"x",88*/
|
||||||
|
{0x01,0x01,0x01,0x81,0x01,0x71,0x00,0x0E,0x00,0x18,0x01,0x60,0x01,0x80,0x01,0x00},/*"y",89*/
|
||||||
|
{0x00,0x00,0x01,0x84,0x01,0x0C,0x01,0x34,0x01,0x44,0x01,0x84,0x01,0x0C,0x00,0x00},/*"z",90*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x3E,0xFC,0x40,0x02,0x40,0x02},/*"{",91*/
|
||||||
|
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/
|
||||||
|
{0x00,0x00,0x40,0x02,0x40,0x02,0x3E,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/
|
||||||
|
{0x00,0x00,0x60,0x00,0x80,0x00,0x80,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00},/*"~",94*/
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,47 @@
|
||||||
|
--cpu Cortex-M3
|
||||||
|
"..\obj\stm32f10x_it.o"
|
||||||
|
"..\obj\system_stm32f10x.o"
|
||||||
|
"..\obj\minibalance.o"
|
||||||
|
"..\obj\core_cm3.o"
|
||||||
|
"..\obj\startup_stm32f10x_md.o"
|
||||||
|
"..\obj\misc.o"
|
||||||
|
"..\obj\stm32f10x_adc.o"
|
||||||
|
"..\obj\stm32f10x_bkp.o"
|
||||||
|
"..\obj\stm32f10x_can.o"
|
||||||
|
"..\obj\stm32f10x_cec.o"
|
||||||
|
"..\obj\stm32f10x_crc.o"
|
||||||
|
"..\obj\stm32f10x_dac.o"
|
||||||
|
"..\obj\stm32f10x_dbgmcu.o"
|
||||||
|
"..\obj\stm32f10x_dma.o"
|
||||||
|
"..\obj\stm32f10x_exti.o"
|
||||||
|
"..\obj\stm32f10x_flash.o"
|
||||||
|
"..\obj\stm32f10x_fsmc.o"
|
||||||
|
"..\obj\stm32f10x_gpio.o"
|
||||||
|
"..\obj\stm32f10x_i2c.o"
|
||||||
|
"..\obj\stm32f10x_iwdg.o"
|
||||||
|
"..\obj\stm32f10x_pwr.o"
|
||||||
|
"..\obj\stm32f10x_rcc.o"
|
||||||
|
"..\obj\stm32f10x_rtc.o"
|
||||||
|
"..\obj\stm32f10x_sdio.o"
|
||||||
|
"..\obj\stm32f10x_spi.o"
|
||||||
|
"..\obj\stm32f10x_tim.o"
|
||||||
|
"..\obj\stm32f10x_usart.o"
|
||||||
|
"..\obj\stm32f10x_wwdg.o"
|
||||||
|
"..\obj\delay.o"
|
||||||
|
"..\obj\sys.o"
|
||||||
|
"..\obj\usart.o"
|
||||||
|
"..\obj\key.o"
|
||||||
|
"..\obj\oled.o"
|
||||||
|
"..\obj\motor.o"
|
||||||
|
"..\obj\encoder.o"
|
||||||
|
"..\obj\ioi2c.o"
|
||||||
|
"..\obj\exti.o"
|
||||||
|
"..\obj\control.o"
|
||||||
|
"..\obj\show.o"
|
||||||
|
"..\obj\inv_mpu.o"
|
||||||
|
"..\obj\inv_mpu_dmp_motion_driver.o"
|
||||||
|
"..\obj\mpu6050.o"
|
||||||
|
--strict --scatter "..\OBJ\MiniBalance.sct"
|
||||||
|
--summary_stderr --info summarysizes --map --xref --callgraph --symbols
|
||||||
|
--info sizes --info totals --info unused --info veneers
|
||||||
|
--list ".\MiniBalance.map" -o ..\OBJ\MiniBalance.axf
|
||||||
|
|
@ -0,0 +1,16 @@
|
||||||
|
; *************************************************************
|
||||||
|
; *** Scatter-Loading Description File generated by uVision ***
|
||||||
|
; *************************************************************
|
||||||
|
|
||||||
|
LR_IROM1 0x08000000 0x00010000 { ; load region size_region
|
||||||
|
ER_IROM1 0x08000000 0x00010000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
.ANY (+XO)
|
||||||
|
}
|
||||||
|
RW_IRAM1 0x20000000 0x00005000 { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,220 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file misc.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||||
|
* firmware library functions (add-on to CMSIS functions).
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __MISC_H
|
||||||
|
#define __MISC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup MISC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief NVIC Init Structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||||
|
This parameter can be a value of @ref IRQn_Type
|
||||||
|
(For the complete STM32 Devices IRQ Channels list, please
|
||||||
|
refer to stm32f10x.h file) */
|
||||||
|
|
||||||
|
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||||
|
specified in NVIC_IRQChannel. This parameter can be a value
|
||||||
|
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||||
|
|
||||||
|
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||||
|
in NVIC_IRQChannel. This parameter can be a value
|
||||||
|
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||||
|
|
||||||
|
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||||
|
will be enabled or disabled.
|
||||||
|
This parameter can be set either to ENABLE or DISABLE */
|
||||||
|
} NVIC_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup NVIC_Priority_Table
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
@code
|
||||||
|
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||||
|
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||||
|
============================================================================================================================
|
||||||
|
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||||
|
============================================================================================================================
|
||||||
|
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||||
|
| | | 4 bits for subpriority
|
||||||
|
----------------------------------------------------------------------------------------------------------------------------
|
||||||
|
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||||
|
| | | 3 bits for subpriority
|
||||||
|
----------------------------------------------------------------------------------------------------------------------------
|
||||||
|
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||||
|
| | | 2 bits for subpriority
|
||||||
|
----------------------------------------------------------------------------------------------------------------------------
|
||||||
|
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||||
|
| | | 1 bits for subpriority
|
||||||
|
----------------------------------------------------------------------------------------------------------------------------
|
||||||
|
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||||
|
| | | 0 bits for subpriority
|
||||||
|
============================================================================================================================
|
||||||
|
@endcode
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Vector_Table_Base
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||||
|
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||||
|
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
||||||
|
((VECTTAB) == NVIC_VectTab_FLASH))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup System_Low_Power
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||||
|
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||||
|
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||||
|
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||||
|
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||||
|
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Preemption_Priority_Group
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
||||||
|
4 bits for subpriority */
|
||||||
|
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
||||||
|
3 bits for subpriority */
|
||||||
|
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
||||||
|
2 bits for subpriority */
|
||||||
|
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
||||||
|
1 bits for subpriority */
|
||||||
|
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
||||||
|
0 bits for subpriority */
|
||||||
|
|
||||||
|
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
||||||
|
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||||
|
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||||
|
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||||
|
((GROUP) == NVIC_PriorityGroup_4))
|
||||||
|
|
||||||
|
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||||
|
|
||||||
|
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||||
|
|
||||||
|
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SysTick_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||||
|
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||||
|
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||||
|
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||||
|
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||||
|
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||||
|
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||||
|
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __MISC_H */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,483 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_adc.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_ADC_H
|
||||||
|
#define __STM32F10x_ADC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup ADC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADC Init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
|
||||||
|
dual mode.
|
||||||
|
This parameter can be a value of @ref ADC_mode */
|
||||||
|
|
||||||
|
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
|
||||||
|
Scan (multichannels) or Single (one channel) mode.
|
||||||
|
This parameter can be set to ENABLE or DISABLE */
|
||||||
|
|
||||||
|
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
||||||
|
Continuous or Single mode.
|
||||||
|
This parameter can be set to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
|
||||||
|
to digital conversion of regular channels. This parameter
|
||||||
|
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||||
|
|
||||||
|
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||||
|
This parameter can be a value of @ref ADC_data_align */
|
||||||
|
|
||||||
|
uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
|
||||||
|
using the sequencer for regular channel group.
|
||||||
|
This parameter must range from 1 to 16. */
|
||||||
|
}ADC_InitTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||||
|
((PERIPH) == ADC2) || \
|
||||||
|
((PERIPH) == ADC3))
|
||||||
|
|
||||||
|
#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
|
||||||
|
((PERIPH) == ADC3))
|
||||||
|
|
||||||
|
/** @defgroup ADC_mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ADC_Mode_Independent ((uint32_t)0x00000000)
|
||||||
|
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
|
||||||
|
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
|
||||||
|
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
|
||||||
|
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
|
||||||
|
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
|
||||||
|
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
|
||||||
|
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
|
||||||
|
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
|
||||||
|
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
|
||||||
|
|
||||||
|
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
|
||||||
|
((MODE) == ADC_Mode_RegInjecSimult) || \
|
||||||
|
((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
|
||||||
|
((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
|
||||||
|
((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
|
||||||
|
((MODE) == ADC_Mode_InjecSimult) || \
|
||||||
|
((MODE) == ADC_Mode_RegSimult) || \
|
||||||
|
((MODE) == ADC_Mode_FastInterl) || \
|
||||||
|
((MODE) == ADC_Mode_SlowInterl) || \
|
||||||
|
((MODE) == ADC_Mode_AlterTrig))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
|
||||||
|
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
|
||||||
|
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
|
||||||
|
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
|
||||||
|
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
|
||||||
|
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
|
||||||
|
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
|
||||||
|
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
|
||||||
|
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
|
||||||
|
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
|
||||||
|
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
|
||||||
|
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
|
||||||
|
|
||||||
|
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_None) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
|
||||||
|
((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_data_align
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||||
|
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||||
|
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||||
|
((ALIGN) == ADC_DataAlign_Left))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_channels
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||||
|
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||||
|
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||||
|
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||||
|
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||||
|
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||||
|
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||||
|
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||||
|
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||||
|
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||||
|
#define ADC_Channel_10 ((uint8_t)0x0A)
|
||||||
|
#define ADC_Channel_11 ((uint8_t)0x0B)
|
||||||
|
#define ADC_Channel_12 ((uint8_t)0x0C)
|
||||||
|
#define ADC_Channel_13 ((uint8_t)0x0D)
|
||||||
|
#define ADC_Channel_14 ((uint8_t)0x0E)
|
||||||
|
#define ADC_Channel_15 ((uint8_t)0x0F)
|
||||||
|
#define ADC_Channel_16 ((uint8_t)0x10)
|
||||||
|
#define ADC_Channel_17 ((uint8_t)0x11)
|
||||||
|
|
||||||
|
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||||
|
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
|
||||||
|
|
||||||
|
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
|
||||||
|
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
|
||||||
|
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
|
||||||
|
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
|
||||||
|
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
|
||||||
|
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
|
||||||
|
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
|
||||||
|
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
|
||||||
|
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_sampling_time
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
|
||||||
|
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
|
||||||
|
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
|
||||||
|
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
|
||||||
|
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
|
||||||
|
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
|
||||||
|
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
|
||||||
|
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
|
||||||
|
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
|
||||||
|
((TIME) == ADC_SampleTime_7Cycles5) || \
|
||||||
|
((TIME) == ADC_SampleTime_13Cycles5) || \
|
||||||
|
((TIME) == ADC_SampleTime_28Cycles5) || \
|
||||||
|
((TIME) == ADC_SampleTime_41Cycles5) || \
|
||||||
|
((TIME) == ADC_SampleTime_55Cycles5) || \
|
||||||
|
((TIME) == ADC_SampleTime_71Cycles5) || \
|
||||||
|
((TIME) == ADC_SampleTime_239Cycles5))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
|
||||||
|
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
|
||||||
|
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
|
||||||
|
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
|
||||||
|
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
|
||||||
|
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
|
||||||
|
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
|
||||||
|
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
|
||||||
|
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
|
||||||
|
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
|
||||||
|
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
|
||||||
|
|
||||||
|
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
|
||||||
|
((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_injected_channel_selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||||
|
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||||
|
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
|
||||||
|
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
|
||||||
|
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
||||||
|
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||||
|
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||||
|
((CHANNEL) == ADC_InjectedChannel_4))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_analog_watchdog_selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||||
|
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||||
|
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||||
|
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||||
|
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||||
|
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||||
|
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||||||
|
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||||
|
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||||
|
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||||
|
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||||
|
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||||
|
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_interrupts_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ADC_IT_EOC ((uint16_t)0x0220)
|
||||||
|
#define ADC_IT_AWD ((uint16_t)0x0140)
|
||||||
|
#define ADC_IT_JEOC ((uint16_t)0x0480)
|
||||||
|
|
||||||
|
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
|
||||||
|
|
||||||
|
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
|
||||||
|
((IT) == ADC_IT_JEOC))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_flags_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ADC_FLAG_AWD ((uint8_t)0x01)
|
||||||
|
#define ADC_FLAG_EOC ((uint8_t)0x02)
|
||||||
|
#define ADC_FLAG_JEOC ((uint8_t)0x04)
|
||||||
|
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
|
||||||
|
#define ADC_FLAG_STRT ((uint8_t)0x10)
|
||||||
|
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
|
||||||
|
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
|
||||||
|
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
|
||||||
|
((FLAG) == ADC_FLAG_STRT))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_thresholds
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_injected_offset
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_injected_length
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_injected_rank
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup ADC_regular_length
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_regular_rank
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup ADC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||||
|
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||||
|
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||||
|
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
|
||||||
|
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_StartCalibration(ADC_TypeDef* ADCx);
|
||||||
|
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||||
|
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||||
|
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||||
|
uint32_t ADC_GetDualModeConversionValue(void);
|
||||||
|
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||||
|
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||||
|
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
||||||
|
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||||
|
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||||
|
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||||
|
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||||
|
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||||
|
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
||||||
|
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||||
|
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||||
|
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||||
|
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__STM32F10x_ADC_H */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,195 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_bkp.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the BKP firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_BKP_H
|
||||||
|
#define __STM32F10x_BKP_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup BKP
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup BKP_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup BKP_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Tamper_Pin_active_level
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
|
||||||
|
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
|
||||||
|
#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
|
||||||
|
((LEVEL) == BKP_TamperPinLevel_Low))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
|
||||||
|
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
|
||||||
|
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
|
||||||
|
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
|
||||||
|
#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
|
||||||
|
((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
|
||||||
|
((SOURCE) == BKP_RTCOutputSource_Alarm) || \
|
||||||
|
((SOURCE) == BKP_RTCOutputSource_Second))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Data_Backup_Register
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define BKP_DR1 ((uint16_t)0x0004)
|
||||||
|
#define BKP_DR2 ((uint16_t)0x0008)
|
||||||
|
#define BKP_DR3 ((uint16_t)0x000C)
|
||||||
|
#define BKP_DR4 ((uint16_t)0x0010)
|
||||||
|
#define BKP_DR5 ((uint16_t)0x0014)
|
||||||
|
#define BKP_DR6 ((uint16_t)0x0018)
|
||||||
|
#define BKP_DR7 ((uint16_t)0x001C)
|
||||||
|
#define BKP_DR8 ((uint16_t)0x0020)
|
||||||
|
#define BKP_DR9 ((uint16_t)0x0024)
|
||||||
|
#define BKP_DR10 ((uint16_t)0x0028)
|
||||||
|
#define BKP_DR11 ((uint16_t)0x0040)
|
||||||
|
#define BKP_DR12 ((uint16_t)0x0044)
|
||||||
|
#define BKP_DR13 ((uint16_t)0x0048)
|
||||||
|
#define BKP_DR14 ((uint16_t)0x004C)
|
||||||
|
#define BKP_DR15 ((uint16_t)0x0050)
|
||||||
|
#define BKP_DR16 ((uint16_t)0x0054)
|
||||||
|
#define BKP_DR17 ((uint16_t)0x0058)
|
||||||
|
#define BKP_DR18 ((uint16_t)0x005C)
|
||||||
|
#define BKP_DR19 ((uint16_t)0x0060)
|
||||||
|
#define BKP_DR20 ((uint16_t)0x0064)
|
||||||
|
#define BKP_DR21 ((uint16_t)0x0068)
|
||||||
|
#define BKP_DR22 ((uint16_t)0x006C)
|
||||||
|
#define BKP_DR23 ((uint16_t)0x0070)
|
||||||
|
#define BKP_DR24 ((uint16_t)0x0074)
|
||||||
|
#define BKP_DR25 ((uint16_t)0x0078)
|
||||||
|
#define BKP_DR26 ((uint16_t)0x007C)
|
||||||
|
#define BKP_DR27 ((uint16_t)0x0080)
|
||||||
|
#define BKP_DR28 ((uint16_t)0x0084)
|
||||||
|
#define BKP_DR29 ((uint16_t)0x0088)
|
||||||
|
#define BKP_DR30 ((uint16_t)0x008C)
|
||||||
|
#define BKP_DR31 ((uint16_t)0x0090)
|
||||||
|
#define BKP_DR32 ((uint16_t)0x0094)
|
||||||
|
#define BKP_DR33 ((uint16_t)0x0098)
|
||||||
|
#define BKP_DR34 ((uint16_t)0x009C)
|
||||||
|
#define BKP_DR35 ((uint16_t)0x00A0)
|
||||||
|
#define BKP_DR36 ((uint16_t)0x00A4)
|
||||||
|
#define BKP_DR37 ((uint16_t)0x00A8)
|
||||||
|
#define BKP_DR38 ((uint16_t)0x00AC)
|
||||||
|
#define BKP_DR39 ((uint16_t)0x00B0)
|
||||||
|
#define BKP_DR40 ((uint16_t)0x00B4)
|
||||||
|
#define BKP_DR41 ((uint16_t)0x00B8)
|
||||||
|
#define BKP_DR42 ((uint16_t)0x00BC)
|
||||||
|
|
||||||
|
#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
|
||||||
|
((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
|
||||||
|
((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
|
||||||
|
((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
|
||||||
|
((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
|
||||||
|
((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
|
||||||
|
((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
|
||||||
|
((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
|
||||||
|
((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
|
||||||
|
((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
|
||||||
|
((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
|
||||||
|
((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
|
||||||
|
((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
|
||||||
|
((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
|
||||||
|
|
||||||
|
#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup BKP_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup BKP_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void BKP_DeInit(void);
|
||||||
|
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
|
||||||
|
void BKP_TamperPinCmd(FunctionalState NewState);
|
||||||
|
void BKP_ITConfig(FunctionalState NewState);
|
||||||
|
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
|
||||||
|
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
|
||||||
|
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
|
||||||
|
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
|
||||||
|
FlagStatus BKP_GetFlagStatus(void);
|
||||||
|
void BKP_ClearFlag(void);
|
||||||
|
ITStatus BKP_GetITStatus(void);
|
||||||
|
void BKP_ClearITPendingBit(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_BKP_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,697 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_can.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the CAN firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_CAN_H
|
||||||
|
#define __STM32F10x_CAN_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CAN
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
|
||||||
|
((PERIPH) == CAN2))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CAN init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
|
||||||
|
It ranges from 1 to 1024. */
|
||||||
|
|
||||||
|
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_operating_mode */
|
||||||
|
|
||||||
|
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
|
||||||
|
the CAN hardware is allowed to lengthen or
|
||||||
|
shorten a bit to perform resynchronization.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_synchronisation_jump_width */
|
||||||
|
|
||||||
|
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
|
||||||
|
Segment 1. This parameter can be a value of
|
||||||
|
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||||
|
|
||||||
|
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit
|
||||||
|
Segment 2.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_time_quantum_in_bit_segment_2 */
|
||||||
|
|
||||||
|
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
|
||||||
|
communication mode. This parameter can be set
|
||||||
|
either to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off
|
||||||
|
management. This parameter can be set either
|
||||||
|
to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
|
||||||
|
This parameter can be set either to ENABLE or
|
||||||
|
DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_NART; /*!< Enable or disable the no-automatic
|
||||||
|
retransmission mode. This parameter can be
|
||||||
|
set either to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||||
|
This parameter can be set either to ENABLE
|
||||||
|
or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
|
||||||
|
This parameter can be set either to ENABLE
|
||||||
|
or DISABLE. */
|
||||||
|
} CAN_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CAN filter init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||||
|
configuration, first one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||||
|
configuration, second one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||||
|
according to the mode (MSBs for a 32-bit configuration,
|
||||||
|
first one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||||
|
according to the mode (LSBs for a 32-bit configuration,
|
||||||
|
second one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||||
|
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||||
|
|
||||||
|
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||||
|
|
||||||
|
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||||
|
This parameter can be a value of @ref CAN_filter_mode */
|
||||||
|
|
||||||
|
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
|
||||||
|
This parameter can be a value of @ref CAN_filter_scale */
|
||||||
|
|
||||||
|
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
|
||||||
|
This parameter can be set either to ENABLE or DISABLE. */
|
||||||
|
} CAN_FilterInitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CAN Tx message structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||||
|
This parameter can be a value between 0 to 0x7FF. */
|
||||||
|
|
||||||
|
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||||
|
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||||
|
|
||||||
|
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||||
|
will be transmitted. This parameter can be a value
|
||||||
|
of @ref CAN_identifier_type */
|
||||||
|
|
||||||
|
uint8_t RTR; /*!< Specifies the type of frame for the message that will
|
||||||
|
be transmitted. This parameter can be a value of
|
||||||
|
@ref CAN_remote_transmission_request */
|
||||||
|
|
||||||
|
uint8_t DLC; /*!< Specifies the length of the frame that will be
|
||||||
|
transmitted. This parameter can be a value between
|
||||||
|
0 to 8 */
|
||||||
|
|
||||||
|
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
|
||||||
|
to 0xFF. */
|
||||||
|
} CanTxMsg;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CAN Rx message structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||||
|
This parameter can be a value between 0 to 0x7FF. */
|
||||||
|
|
||||||
|
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||||
|
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||||
|
|
||||||
|
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||||
|
will be received. This parameter can be a value of
|
||||||
|
@ref CAN_identifier_type */
|
||||||
|
|
||||||
|
uint8_t RTR; /*!< Specifies the type of frame for the received message.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_remote_transmission_request */
|
||||||
|
|
||||||
|
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||||
|
This parameter can be a value between 0 to 8 */
|
||||||
|
|
||||||
|
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
|
||||||
|
0xFF. */
|
||||||
|
|
||||||
|
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
|
||||||
|
the mailbox passes through. This parameter can be a
|
||||||
|
value between 0 to 0xFF */
|
||||||
|
} CanRxMsg;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_sleep_constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
|
||||||
|
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
|
||||||
|
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
|
||||||
|
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
|
||||||
|
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
|
||||||
|
|
||||||
|
#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
|
||||||
|
((MODE) == CAN_Mode_LoopBack)|| \
|
||||||
|
((MODE) == CAN_Mode_Silent) || \
|
||||||
|
((MODE) == CAN_Mode_Silent_LoopBack))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @defgroup CAN_Operating_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
|
||||||
|
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
|
||||||
|
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
|
||||||
|
|
||||||
|
|
||||||
|
#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
|
||||||
|
((MODE) == CAN_OperatingMode_Normal)|| \
|
||||||
|
((MODE) == CAN_OperatingMode_Sleep))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @defgroup CAN_Mode_Status
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
|
||||||
|
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_synchronisation_jump_width
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||||
|
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||||
|
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||||
|
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||||
|
|
||||||
|
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
|
||||||
|
((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_time_quantum_in_bit_segment_1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||||
|
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||||
|
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||||
|
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||||
|
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||||
|
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||||
|
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||||
|
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||||
|
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
|
||||||
|
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
|
||||||
|
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
|
||||||
|
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
|
||||||
|
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
|
||||||
|
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
|
||||||
|
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
|
||||||
|
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
|
||||||
|
|
||||||
|
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_time_quantum_in_bit_segment_2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||||
|
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||||
|
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||||
|
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||||
|
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||||
|
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||||
|
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||||
|
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||||
|
|
||||||
|
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_clock_prescaler
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_filter_number
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#ifndef STM32F10X_CL
|
||||||
|
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
|
||||||
|
#else
|
||||||
|
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_filter_mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
|
||||||
|
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
|
||||||
|
|
||||||
|
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
|
||||||
|
((MODE) == CAN_FilterMode_IdList))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_filter_scale
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||||
|
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||||
|
|
||||||
|
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
|
||||||
|
((SCALE) == CAN_FilterScale_32bit))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_filter_FIFO
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
|
||||||
|
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
|
||||||
|
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
|
||||||
|
((FIFO) == CAN_FilterFIFO1))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Start_bank_filter_for_slave_CAN
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Tx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||||
|
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||||
|
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||||
|
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_identifier_type
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
|
||||||
|
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
|
||||||
|
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
|
||||||
|
((IDTYPE) == CAN_Id_Extended))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_remote_transmission_request
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
|
||||||
|
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
|
||||||
|
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_transmit_constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
|
||||||
|
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||||
|
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||||
|
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_receive_FIFO_number_constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
|
||||||
|
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
|
||||||
|
|
||||||
|
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_sleep_constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
|
||||||
|
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_wake_up_constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
|
||||||
|
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @defgroup CAN_Error_Code_constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
|
||||||
|
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
|
||||||
|
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
|
||||||
|
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
|
||||||
|
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
|
||||||
|
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
|
||||||
|
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
|
||||||
|
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_flags
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||||
|
and CAN_ClearFlag() functions. */
|
||||||
|
/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */
|
||||||
|
|
||||||
|
/* Transmit Flags */
|
||||||
|
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
|
||||||
|
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
|
||||||
|
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
|
||||||
|
|
||||||
|
/* Receive Flags */
|
||||||
|
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
|
||||||
|
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
|
||||||
|
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
|
||||||
|
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
|
||||||
|
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
|
||||||
|
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
|
||||||
|
|
||||||
|
/* Operating Mode Flags */
|
||||||
|
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
|
||||||
|
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
|
||||||
|
/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||||
|
In this case the SLAK bit can be polled.*/
|
||||||
|
|
||||||
|
/* Error Flags */
|
||||||
|
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
|
||||||
|
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
|
||||||
|
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
|
||||||
|
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
|
||||||
|
|
||||||
|
#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
|
||||||
|
((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
|
||||||
|
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
|
||||||
|
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
|
||||||
|
((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
|
||||||
|
((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||||
|
((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||||
|
((FLAG) == CAN_FLAG_SLAK ))
|
||||||
|
|
||||||
|
#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
|
||||||
|
((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
|
||||||
|
((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
|
||||||
|
((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
|
||||||
|
((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup CAN_interrupts
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
|
||||||
|
|
||||||
|
/* Receive Interrupts */
|
||||||
|
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
|
||||||
|
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
|
||||||
|
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
|
||||||
|
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
|
||||||
|
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
|
||||||
|
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
|
||||||
|
|
||||||
|
/* Operating Mode Interrupts */
|
||||||
|
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
|
||||||
|
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
|
||||||
|
|
||||||
|
/* Error Interrupts */
|
||||||
|
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
|
||||||
|
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
|
||||||
|
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
|
||||||
|
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
|
||||||
|
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
|
||||||
|
|
||||||
|
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||||
|
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||||
|
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||||
|
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||||
|
|
||||||
|
|
||||||
|
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
|
||||||
|
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
|
||||||
|
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
|
||||||
|
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
|
||||||
|
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||||
|
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||||
|
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||||
|
|
||||||
|
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
|
||||||
|
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
|
||||||
|
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
|
||||||
|
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
|
||||||
|
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
|
||||||
|
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Legacy
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CANINITFAILED CAN_InitStatus_Failed
|
||||||
|
#define CANINITOK CAN_InitStatus_Success
|
||||||
|
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||||
|
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||||
|
#define CAN_ID_STD CAN_Id_Standard
|
||||||
|
#define CAN_ID_EXT CAN_Id_Extended
|
||||||
|
#define CAN_RTR_DATA CAN_RTR_Data
|
||||||
|
#define CAN_RTR_REMOTE CAN_RTR_Remote
|
||||||
|
#define CANTXFAILE CAN_TxStatus_Failed
|
||||||
|
#define CANTXOK CAN_TxStatus_Ok
|
||||||
|
#define CANTXPENDING CAN_TxStatus_Pending
|
||||||
|
#define CAN_NO_MB CAN_TxStatus_NoMailBox
|
||||||
|
#define CANSLEEPFAILED CAN_Sleep_Failed
|
||||||
|
#define CANSLEEPOK CAN_Sleep_Ok
|
||||||
|
#define CANWAKEUPFAILED CAN_WakeUp_Failed
|
||||||
|
#define CANWAKEUPOK CAN_WakeUp_Ok
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CAN_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Function used to set the CAN configuration to the default reset state *****/
|
||||||
|
void CAN_DeInit(CAN_TypeDef* CANx);
|
||||||
|
|
||||||
|
/* Initialization and Configuration functions *********************************/
|
||||||
|
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
|
||||||
|
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
|
||||||
|
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
|
||||||
|
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||||
|
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||||
|
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||||
|
|
||||||
|
/* Transmit functions *********************************************************/
|
||||||
|
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
|
||||||
|
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
|
||||||
|
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
|
||||||
|
|
||||||
|
/* Receive functions **********************************************************/
|
||||||
|
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
|
||||||
|
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||||
|
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||||
|
|
||||||
|
|
||||||
|
/* Operation modes functions **************************************************/
|
||||||
|
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
|
||||||
|
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
|
||||||
|
|
||||||
|
/* Error management functions *************************************************/
|
||||||
|
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
|
||||||
|
|
||||||
|
/* Interrupts and flags management functions **********************************/
|
||||||
|
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
|
||||||
|
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||||
|
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||||
|
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||||
|
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_CAN_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,210 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_cec.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the CEC firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_CEC_H
|
||||||
|
#define __STM32F10x_CEC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CEC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup CEC_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CEC Init structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
|
||||||
|
This parameter can be a value of @ref CEC_BitTiming_Mode */
|
||||||
|
uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
|
||||||
|
This parameter can be a value of @ref CEC_BitPeriod_Mode */
|
||||||
|
}CEC_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_BitTiming_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
|
||||||
|
#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
|
||||||
|
|
||||||
|
#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
|
||||||
|
((MODE) == CEC_BitTimingErrFreeMode))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_BitPeriod_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
|
||||||
|
#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
|
||||||
|
|
||||||
|
#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
|
||||||
|
((MODE) == CEC_BitPeriodFlexibleMode))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup CEC_interrupts_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CEC_IT_TERR CEC_CSR_TERR
|
||||||
|
#define CEC_IT_TBTRF CEC_CSR_TBTRF
|
||||||
|
#define CEC_IT_RERR CEC_CSR_RERR
|
||||||
|
#define CEC_IT_RBTF CEC_CSR_RBTF
|
||||||
|
#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
|
||||||
|
((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup CEC_Own_Address
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Prescaler
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_flags_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ESR register flags
|
||||||
|
*/
|
||||||
|
#define CEC_FLAG_BTE ((uint32_t)0x10010000)
|
||||||
|
#define CEC_FLAG_BPE ((uint32_t)0x10020000)
|
||||||
|
#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
|
||||||
|
#define CEC_FLAG_SBE ((uint32_t)0x10080000)
|
||||||
|
#define CEC_FLAG_ACKE ((uint32_t)0x10100000)
|
||||||
|
#define CEC_FLAG_LINE ((uint32_t)0x10200000)
|
||||||
|
#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CSR register flags
|
||||||
|
*/
|
||||||
|
#define CEC_FLAG_TEOM ((uint32_t)0x00000002)
|
||||||
|
#define CEC_FLAG_TERR ((uint32_t)0x00000004)
|
||||||
|
#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
|
||||||
|
#define CEC_FLAG_RSOM ((uint32_t)0x00000010)
|
||||||
|
#define CEC_FLAG_REOM ((uint32_t)0x00000020)
|
||||||
|
#define CEC_FLAG_RERR ((uint32_t)0x00000040)
|
||||||
|
#define CEC_FLAG_RBTF ((uint32_t)0x00000080)
|
||||||
|
|
||||||
|
#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
|
||||||
|
|
||||||
|
#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
|
||||||
|
((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
|
||||||
|
((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
|
||||||
|
((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
|
||||||
|
((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
|
||||||
|
((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
|
||||||
|
((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
void CEC_DeInit(void);
|
||||||
|
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
|
||||||
|
void CEC_Cmd(FunctionalState NewState);
|
||||||
|
void CEC_ITConfig(FunctionalState NewState);
|
||||||
|
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
|
||||||
|
void CEC_SetPrescaler(uint16_t CEC_Prescaler);
|
||||||
|
void CEC_SendDataByte(uint8_t Data);
|
||||||
|
uint8_t CEC_ReceiveDataByte(void);
|
||||||
|
void CEC_StartOfMessage(void);
|
||||||
|
void CEC_EndOfMessageCmd(FunctionalState NewState);
|
||||||
|
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
|
||||||
|
void CEC_ClearFlag(uint32_t CEC_FLAG);
|
||||||
|
ITStatus CEC_GetITStatus(uint8_t CEC_IT);
|
||||||
|
void CEC_ClearITPendingBit(uint16_t CEC_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_CEC_H */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,94 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_crc.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_CRC_H
|
||||||
|
#define __STM32F10x_CRC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void CRC_ResetDR(void);
|
||||||
|
uint32_t CRC_CalcCRC(uint32_t Data);
|
||||||
|
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||||
|
uint32_t CRC_GetCRC(void);
|
||||||
|
void CRC_SetIDRegister(uint8_t IDValue);
|
||||||
|
uint8_t CRC_GetIDRegister(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_CRC_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,317 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_dac.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_DAC_H
|
||||||
|
#define __STM32F10x_DAC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DAC Init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||||
|
This parameter can be a value of @ref DAC_trigger_selection */
|
||||||
|
|
||||||
|
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||||
|
are generated, or whether no wave is generated.
|
||||||
|
This parameter can be a value of @ref DAC_wave_generation */
|
||||||
|
|
||||||
|
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||||
|
the maximum amplitude triangle generation for the DAC channel.
|
||||||
|
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||||
|
|
||||||
|
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref DAC_output_buffer */
|
||||||
|
}DAC_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_trigger_selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||||
|
has been loaded, and not by external trigger */
|
||||||
|
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||||
|
only in High-density devices*/
|
||||||
|
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||||
|
only in Connectivity line, Medium-density and Low-density Value Line devices */
|
||||||
|
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
|
||||||
|
only in Medium-density and Low-density Value Line devices*/
|
||||||
|
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
||||||
|
|
||||||
|
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||||
|
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_Trigger_T8_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||||
|
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||||
|
((TRIGGER) == DAC_Trigger_Software))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_wave_generation
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||||
|
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||||
|
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||||
|
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
||||||
|
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||||
|
((WAVE) == DAC_WaveGeneration_Triangle))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||||
|
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||||
|
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||||
|
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||||
|
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||||
|
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||||
|
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||||
|
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||||
|
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||||
|
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||||
|
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||||
|
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||||
|
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||||
|
|
||||||
|
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||||
|
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||||
|
((VALUE) == DAC_TriangleAmplitude_4095))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_output_buffer
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||||
|
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
||||||
|
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
||||||
|
((STATE) == DAC_OutputBuffer_Disable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Channel_selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||||
|
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||||
|
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||||
|
((CHANNEL) == DAC_Channel_2))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_data_alignment
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||||
|
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||||
|
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||||
|
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||||
|
((ALIGN) == DAC_Align_12b_L) || \
|
||||||
|
((ALIGN) == DAC_Align_8b_R))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_wave_generation
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||||
|
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||||
|
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||||
|
((WAVE) == DAC_Wave_Triangle))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_data
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||||
|
/** @defgroup DAC_interrupts_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
||||||
|
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_flags_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
||||||
|
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void DAC_DeInit(void);
|
||||||
|
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||||
|
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||||
|
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||||
|
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||||
|
#endif
|
||||||
|
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||||
|
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||||
|
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||||
|
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||||
|
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||||
|
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
||||||
|
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||||
|
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||||
|
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||||
|
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||||
|
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||||
|
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__STM32F10x_DAC_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,119 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_dbgmcu.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the DBGMCU
|
||||||
|
* firmware library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_DBGMCU_H
|
||||||
|
#define __STM32F10x_DBGMCU_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DBGMCU
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||||
|
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||||
|
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||||
|
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
|
||||||
|
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
|
||||||
|
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
|
||||||
|
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
|
||||||
|
#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
|
||||||
|
#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
|
||||||
|
#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
|
||||||
|
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
|
||||||
|
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
|
||||||
|
#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
|
||||||
|
#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
|
||||||
|
#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
|
||||||
|
#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
|
||||||
|
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
|
||||||
|
#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
|
||||||
|
#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
|
||||||
|
#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
|
||||||
|
#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
|
||||||
|
#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
|
||||||
|
#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
|
||||||
|
#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
|
||||||
|
#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
|
||||||
|
#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
|
||||||
|
|
||||||
|
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
uint32_t DBGMCU_GetREVID(void);
|
||||||
|
uint32_t DBGMCU_GetDEVID(void);
|
||||||
|
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_DBGMCU_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,439 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_dma.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_DMA_H
|
||||||
|
#define __STM32F10x_DMA_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DMA
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA Init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
||||||
|
|
||||||
|
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
||||||
|
|
||||||
|
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
||||||
|
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||||
|
|
||||||
|
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||||
|
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||||
|
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||||
|
|
||||||
|
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||||
|
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||||
|
|
||||||
|
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||||
|
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||||
|
|
||||||
|
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||||
|
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||||
|
|
||||||
|
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||||
|
This parameter can be a value of @ref DMA_memory_data_size */
|
||||||
|
|
||||||
|
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||||
|
This parameter can be a value of @ref DMA_circular_normal_mode.
|
||||||
|
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||||
|
data transfer is configured on the selected Channel */
|
||||||
|
|
||||||
|
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||||
|
This parameter can be a value of @ref DMA_priority_level */
|
||||||
|
|
||||||
|
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||||
|
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||||
|
}DMA_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
|
||||||
|
((PERIPH) == DMA1_Channel2) || \
|
||||||
|
((PERIPH) == DMA1_Channel3) || \
|
||||||
|
((PERIPH) == DMA1_Channel4) || \
|
||||||
|
((PERIPH) == DMA1_Channel5) || \
|
||||||
|
((PERIPH) == DMA1_Channel6) || \
|
||||||
|
((PERIPH) == DMA1_Channel7) || \
|
||||||
|
((PERIPH) == DMA2_Channel1) || \
|
||||||
|
((PERIPH) == DMA2_Channel2) || \
|
||||||
|
((PERIPH) == DMA2_Channel3) || \
|
||||||
|
((PERIPH) == DMA2_Channel4) || \
|
||||||
|
((PERIPH) == DMA2_Channel5))
|
||||||
|
|
||||||
|
/** @defgroup DMA_data_transfer_direction
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
||||||
|
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||||
|
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
|
||||||
|
((DIR) == DMA_DIR_PeripheralSRC))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_peripheral_incremented_mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
||||||
|
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||||
|
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
|
||||||
|
((STATE) == DMA_PeripheralInc_Disable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_memory_incremented_mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
||||||
|
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||||
|
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
|
||||||
|
((STATE) == DMA_MemoryInc_Disable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_peripheral_data_size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||||
|
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
||||||
|
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
||||||
|
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||||
|
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||||
|
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_memory_data_size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||||
|
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||||
|
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||||
|
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||||
|
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||||
|
((SIZE) == DMA_MemoryDataSize_Word))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_circular_normal_mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
||||||
|
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||||
|
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_priority_level
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
||||||
|
#define DMA_Priority_High ((uint32_t)0x00002000)
|
||||||
|
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
||||||
|
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||||
|
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
||||||
|
((PRIORITY) == DMA_Priority_High) || \
|
||||||
|
((PRIORITY) == DMA_Priority_Medium) || \
|
||||||
|
((PRIORITY) == DMA_Priority_Low))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_memory_to_memory
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
||||||
|
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||||
|
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_interrupts_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||||
|
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||||
|
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||||
|
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
||||||
|
|
||||||
|
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||||
|
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||||
|
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||||
|
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||||
|
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||||
|
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||||
|
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||||
|
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||||
|
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||||
|
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||||
|
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||||
|
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||||
|
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||||
|
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||||
|
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||||
|
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||||
|
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||||
|
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||||
|
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||||
|
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||||
|
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||||
|
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||||
|
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||||
|
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||||
|
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||||
|
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||||
|
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||||
|
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||||
|
|
||||||
|
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||||
|
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||||
|
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||||
|
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||||
|
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||||
|
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||||
|
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||||
|
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||||
|
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||||
|
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||||
|
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||||
|
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||||
|
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||||
|
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||||
|
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||||
|
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||||
|
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||||
|
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||||
|
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||||
|
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||||
|
|
||||||
|
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
|
||||||
|
|
||||||
|
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
|
||||||
|
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
||||||
|
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
||||||
|
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
||||||
|
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
||||||
|
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
||||||
|
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
||||||
|
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
||||||
|
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
||||||
|
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
|
||||||
|
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
|
||||||
|
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
|
||||||
|
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
|
||||||
|
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
|
||||||
|
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
|
||||||
|
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
|
||||||
|
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
|
||||||
|
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
|
||||||
|
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
|
||||||
|
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
|
||||||
|
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
|
||||||
|
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
|
||||||
|
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
|
||||||
|
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_flags_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||||
|
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||||
|
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||||
|
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||||
|
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||||
|
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||||
|
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||||
|
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||||
|
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||||
|
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||||
|
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||||
|
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||||
|
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||||
|
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||||
|
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||||
|
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||||
|
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||||
|
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||||
|
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||||
|
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||||
|
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||||
|
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||||
|
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||||
|
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||||
|
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||||
|
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||||
|
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||||
|
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||||
|
|
||||||
|
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||||
|
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||||
|
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||||
|
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||||
|
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||||
|
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||||
|
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||||
|
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||||
|
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||||
|
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||||
|
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||||
|
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||||
|
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||||
|
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||||
|
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||||
|
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||||
|
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||||
|
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||||
|
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||||
|
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||||
|
|
||||||
|
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
|
||||||
|
|
||||||
|
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
|
||||||
|
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
||||||
|
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
||||||
|
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
||||||
|
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
||||||
|
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
||||||
|
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
||||||
|
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
||||||
|
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
||||||
|
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
|
||||||
|
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
|
||||||
|
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
|
||||||
|
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
|
||||||
|
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
|
||||||
|
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
|
||||||
|
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
|
||||||
|
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
|
||||||
|
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
|
||||||
|
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
|
||||||
|
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
|
||||||
|
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
|
||||||
|
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
|
||||||
|
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
|
||||||
|
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Buffer_Size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||||
|
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||||
|
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||||
|
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||||
|
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||||
|
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||||
|
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||||
|
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||||
|
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||||
|
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||||
|
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__STM32F10x_DMA_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,184 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_exti.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the EXTI firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_EXTI_H
|
||||||
|
#define __STM32F10x_EXTI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EXTI
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI mode enumeration
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
EXTI_Mode_Interrupt = 0x00,
|
||||||
|
EXTI_Mode_Event = 0x04
|
||||||
|
}EXTIMode_TypeDef;
|
||||||
|
|
||||||
|
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Trigger enumeration
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
EXTI_Trigger_Rising = 0x08,
|
||||||
|
EXTI_Trigger_Falling = 0x0C,
|
||||||
|
EXTI_Trigger_Rising_Falling = 0x10
|
||||||
|
}EXTITrigger_TypeDef;
|
||||||
|
|
||||||
|
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||||
|
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||||
|
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||||
|
/**
|
||||||
|
* @brief EXTI Init Structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||||
|
This parameter can be any combination of @ref EXTI_Lines */
|
||||||
|
|
||||||
|
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||||
|
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||||
|
|
||||||
|
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||||
|
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||||
|
|
||||||
|
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||||
|
This parameter can be set either to ENABLE or DISABLE */
|
||||||
|
}EXTI_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Lines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
|
||||||
|
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
|
||||||
|
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
|
||||||
|
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
|
||||||
|
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
|
||||||
|
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
|
||||||
|
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
|
||||||
|
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
|
||||||
|
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
|
||||||
|
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
|
||||||
|
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
|
||||||
|
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
|
||||||
|
#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
|
||||||
|
#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
|
||||||
|
#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
|
||||||
|
#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
|
||||||
|
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||||
|
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||||
|
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
|
||||||
|
Wakeup from suspend event */
|
||||||
|
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||||
|
|
||||||
|
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
||||||
|
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||||
|
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||||
|
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||||
|
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||||
|
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||||
|
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||||
|
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||||
|
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||||
|
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||||
|
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void EXTI_DeInit(void);
|
||||||
|
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||||
|
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||||
|
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||||
|
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||||
|
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||||
|
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||||
|
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_EXTI_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,426 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_flash.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the FLASH
|
||||||
|
* firmware library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_FLASH_H
|
||||||
|
#define __STM32F10x_FLASH_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup FLASH
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FLASH_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FLASH Status
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
FLASH_BUSY = 1,
|
||||||
|
FLASH_ERROR_PG,
|
||||||
|
FLASH_ERROR_WRP,
|
||||||
|
FLASH_COMPLETE,
|
||||||
|
FLASH_TIMEOUT
|
||||||
|
}FLASH_Status;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FLASH_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Flash_Latency
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
|
||||||
|
#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
|
||||||
|
#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
|
||||||
|
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||||
|
((LATENCY) == FLASH_Latency_1) || \
|
||||||
|
((LATENCY) == FLASH_Latency_2))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Half_Cycle_Enable_Disable
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
|
||||||
|
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
|
||||||
|
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
|
||||||
|
((STATE) == FLASH_HalfCycleAccess_Disable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Prefetch_Buffer_Enable_Disable
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
|
||||||
|
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
|
||||||
|
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
|
||||||
|
((STATE) == FLASH_PrefetchBuffer_Disable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Option_Bytes_Write_Protection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Values to be used with STM32 Low and Medium density devices */
|
||||||
|
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
|
||||||
|
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
|
||||||
|
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
|
||||||
|
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
|
||||||
|
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
|
||||||
|
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
|
||||||
|
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
|
||||||
|
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
|
||||||
|
|
||||||
|
/* Values to be used with STM32 Medium-density devices */
|
||||||
|
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
|
||||||
|
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
|
||||||
|
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
|
||||||
|
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
|
||||||
|
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
|
||||||
|
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
|
||||||
|
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
|
||||||
|
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
|
||||||
|
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
|
||||||
|
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
|
||||||
|
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
|
||||||
|
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
|
||||||
|
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
|
||||||
|
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
|
||||||
|
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
|
||||||
|
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
|
||||||
|
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
|
||||||
|
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
|
||||||
|
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
|
||||||
|
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
|
||||||
|
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
|
||||||
|
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
|
||||||
|
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
|
||||||
|
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
|
||||||
|
|
||||||
|
/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
|
||||||
|
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 0 to 1 */
|
||||||
|
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 2 to 3 */
|
||||||
|
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 4 to 5 */
|
||||||
|
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 6 to 7 */
|
||||||
|
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 8 to 9 */
|
||||||
|
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 10 to 11 */
|
||||||
|
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 12 to 13 */
|
||||||
|
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 14 to 15 */
|
||||||
|
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 16 to 17 */
|
||||||
|
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 18 to 19 */
|
||||||
|
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 20 to 21 */
|
||||||
|
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 22 to 23 */
|
||||||
|
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 24 to 25 */
|
||||||
|
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 26 to 27 */
|
||||||
|
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 28 to 29 */
|
||||||
|
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 30 to 31 */
|
||||||
|
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 32 to 33 */
|
||||||
|
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 34 to 35 */
|
||||||
|
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 36 to 37 */
|
||||||
|
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 38 to 39 */
|
||||||
|
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 40 to 41 */
|
||||||
|
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 42 to 43 */
|
||||||
|
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 44 to 45 */
|
||||||
|
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 46 to 47 */
|
||||||
|
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 48 to 49 */
|
||||||
|
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 50 to 51 */
|
||||||
|
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 52 to 53 */
|
||||||
|
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 54 to 55 */
|
||||||
|
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 56 to 57 */
|
||||||
|
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 58 to 59 */
|
||||||
|
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
|
||||||
|
Write protection of page 60 to 61 */
|
||||||
|
#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
|
||||||
|
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
|
||||||
|
#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
|
||||||
|
|
||||||
|
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
|
||||||
|
|
||||||
|
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
|
||||||
|
|
||||||
|
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
|
||||||
|
|
||||||
|
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Option_Bytes_IWatchdog
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
|
||||||
|
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
|
||||||
|
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Option_Bytes_nRST_STOP
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
|
||||||
|
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
|
||||||
|
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Option_Bytes_nRST_STDBY
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
|
||||||
|
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
|
||||||
|
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||||
|
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/** @defgroup FLASH_Boot
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||||
|
and this parameter is selected the device will boot from Bank1(Default) */
|
||||||
|
#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||||
|
and this parameter is selected the device will boot from Bank 2 or Bank 1,
|
||||||
|
depending on the activation of the bank */
|
||||||
|
#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/** @defgroup FLASH_Interrupts
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */
|
||||||
|
#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */
|
||||||
|
|
||||||
|
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
|
||||||
|
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||||
|
|
||||||
|
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */
|
||||||
|
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||||
|
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||||
|
#else
|
||||||
|
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
|
||||||
|
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
|
||||||
|
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
|
||||||
|
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
|
||||||
|
|
||||||
|
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FLASH_Flags
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */
|
||||||
|
#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */
|
||||||
|
#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */
|
||||||
|
#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */
|
||||||
|
|
||||||
|
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
|
||||||
|
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
|
||||||
|
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
|
||||||
|
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
|
||||||
|
|
||||||
|
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
|
||||||
|
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
|
||||||
|
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
|
||||||
|
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||||
|
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
|
||||||
|
|
||||||
|
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||||
|
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
|
||||||
|
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
|
||||||
|
((FLAG) == FLASH_FLAG_OPTERR)|| \
|
||||||
|
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
|
||||||
|
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
|
||||||
|
((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
|
||||||
|
((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
|
||||||
|
#else
|
||||||
|
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
|
||||||
|
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
|
||||||
|
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
|
||||||
|
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||||
|
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
|
||||||
|
|
||||||
|
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
|
||||||
|
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
|
||||||
|
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
|
||||||
|
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
|
||||||
|
|
||||||
|
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||||
|
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
|
||||||
|
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
|
||||||
|
((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
|
||||||
|
((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
|
||||||
|
((FLAG) == FLASH_FLAG_OPTERR))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FLASH_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FLASH_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*------------ Functions used for all STM32F10x devices -----*/
|
||||||
|
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||||
|
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
|
||||||
|
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
|
||||||
|
void FLASH_Unlock(void);
|
||||||
|
void FLASH_Lock(void);
|
||||||
|
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||||
|
FLASH_Status FLASH_EraseAllPages(void);
|
||||||
|
FLASH_Status FLASH_EraseOptionBytes(void);
|
||||||
|
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||||
|
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||||
|
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||||
|
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
|
||||||
|
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
|
||||||
|
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
|
||||||
|
uint32_t FLASH_GetUserOptionByte(void);
|
||||||
|
uint32_t FLASH_GetWriteProtectionOptionByte(void);
|
||||||
|
FlagStatus FLASH_GetReadOutProtectionStatus(void);
|
||||||
|
FlagStatus FLASH_GetPrefetchBufferStatus(void);
|
||||||
|
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||||
|
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||||
|
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||||
|
FLASH_Status FLASH_GetStatus(void);
|
||||||
|
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||||
|
|
||||||
|
/*------------ New function used for all STM32F10x devices -----*/
|
||||||
|
void FLASH_UnlockBank1(void);
|
||||||
|
void FLASH_LockBank1(void);
|
||||||
|
FLASH_Status FLASH_EraseAllBank1Pages(void);
|
||||||
|
FLASH_Status FLASH_GetBank1Status(void);
|
||||||
|
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
|
||||||
|
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
/*---- New Functions used only with STM32F10x_XL density devices -----*/
|
||||||
|
void FLASH_UnlockBank2(void);
|
||||||
|
void FLASH_LockBank2(void);
|
||||||
|
FLASH_Status FLASH_EraseAllBank2Pages(void);
|
||||||
|
FLASH_Status FLASH_GetBank2Status(void);
|
||||||
|
FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
|
||||||
|
FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_FLASH_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,733 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_fsmc.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the FSMC firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_FSMC_H
|
||||||
|
#define __STM32F10x_FSMC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup FSMC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Timing parameters For NOR/SRAM Banks
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the address setup time.
|
||||||
|
This parameter can be a value between 0 and 0xF.
|
||||||
|
@note: It is not used with synchronous NOR Flash memories. */
|
||||||
|
|
||||||
|
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the address hold time.
|
||||||
|
This parameter can be a value between 0 and 0xF.
|
||||||
|
@note: It is not used with synchronous NOR Flash memories.*/
|
||||||
|
|
||||||
|
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the data setup time.
|
||||||
|
This parameter can be a value between 0 and 0xFF.
|
||||||
|
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||||
|
|
||||||
|
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the bus turnaround.
|
||||||
|
This parameter can be a value between 0 and 0xF.
|
||||||
|
@note: It is only used for multiplexed NOR Flash memories. */
|
||||||
|
|
||||||
|
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||||
|
This parameter can be a value between 1 and 0xF.
|
||||||
|
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||||
|
|
||||||
|
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||||
|
to the memory before getting the first data.
|
||||||
|
The value of this parameter depends on the memory type as shown below:
|
||||||
|
- It must be set to 0 in case of a CRAM
|
||||||
|
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||||
|
- It may assume a value between 0 and 0xF in NOR Flash memories
|
||||||
|
with synchronous burst mode enable */
|
||||||
|
|
||||||
|
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||||
|
}FSMC_NORSRAMTimingInitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FSMC NOR/SRAM Init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
|
||||||
|
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
|
||||||
|
|
||||||
|
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
|
||||||
|
multiplexed on the databus or not.
|
||||||
|
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
|
||||||
|
|
||||||
|
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
|
||||||
|
the corresponding memory bank.
|
||||||
|
This parameter can be a value of @ref FSMC_Memory_Type */
|
||||||
|
|
||||||
|
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||||
|
This parameter can be a value of @ref FSMC_Data_Width */
|
||||||
|
|
||||||
|
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||||
|
valid only with synchronous burst Flash memories.
|
||||||
|
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
|
||||||
|
|
||||||
|
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||||
|
valid only with asynchronous Flash memories.
|
||||||
|
This parameter can be a value of @ref FSMC_AsynchronousWait */
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||||
|
the Flash memory in burst mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
|
||||||
|
|
||||||
|
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||||
|
memory, valid only when accessing Flash memories in burst mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Wrap_Mode */
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||||
|
clock cycle before the wait state or during the wait state,
|
||||||
|
valid only when accessing memories in burst mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Wait_Timing */
|
||||||
|
|
||||||
|
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
|
||||||
|
This parameter can be a value of @ref FSMC_Write_Operation */
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
|
||||||
|
signal, valid for Flash memory access in burst mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Wait_Signal */
|
||||||
|
|
||||||
|
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Extended_Mode */
|
||||||
|
|
||||||
|
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
|
||||||
|
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||||
|
|
||||||
|
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
|
||||||
|
|
||||||
|
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
|
||||||
|
}FSMC_NORSRAMInitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Timing parameters For FSMC NAND and PCCARD Banks
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||||
|
the command assertion for NAND-Flash read or write access
|
||||||
|
to common/Attribute or I/O memory space (depending on
|
||||||
|
the memory space timing to be configured).
|
||||||
|
This parameter can be a value between 0 and 0xFF.*/
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||||
|
command for NAND-Flash read or write access to
|
||||||
|
common/Attribute or I/O memory space (depending on the
|
||||||
|
memory space timing to be configured).
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
|
||||||
|
uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||||
|
(and data for write access) after the command deassertion
|
||||||
|
for NAND-Flash read or write access to common/Attribute
|
||||||
|
or I/O memory space (depending on the memory space timing
|
||||||
|
to be configured).
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
|
||||||
|
uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||||
|
databus is kept in HiZ after the start of a NAND-Flash
|
||||||
|
write access to common/Attribute or I/O memory space (depending
|
||||||
|
on the memory space timing to be configured).
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
}FSMC_NAND_PCCARDTimingInitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FSMC NAND Init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
|
||||||
|
This parameter can be a value of @ref FSMC_NAND_Bank */
|
||||||
|
|
||||||
|
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
|
||||||
|
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||||
|
|
||||||
|
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||||
|
This parameter can be any value of @ref FSMC_Data_Width */
|
||||||
|
|
||||||
|
uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
|
||||||
|
This parameter can be any value of @ref FSMC_ECC */
|
||||||
|
|
||||||
|
uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
|
||||||
|
This parameter can be any value of @ref FSMC_ECC_Page_Size */
|
||||||
|
|
||||||
|
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||||
|
delay between CLE low and RE low.
|
||||||
|
This parameter can be a value between 0 and 0xFF. */
|
||||||
|
|
||||||
|
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||||
|
delay between ALE low and RE low.
|
||||||
|
This parameter can be a number between 0x0 and 0xFF */
|
||||||
|
|
||||||
|
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||||
|
|
||||||
|
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||||
|
}FSMC_NANDInitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FSMC PCCARD Init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
|
||||||
|
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||||
|
|
||||||
|
uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||||
|
delay between CLE low and RE low.
|
||||||
|
This parameter can be a value between 0 and 0xFF. */
|
||||||
|
|
||||||
|
uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
|
||||||
|
delay between ALE low and RE low.
|
||||||
|
This parameter can be a number between 0x0 and 0xFF */
|
||||||
|
|
||||||
|
|
||||||
|
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
|
||||||
|
|
||||||
|
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
|
||||||
|
|
||||||
|
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
|
||||||
|
}FSMC_PCCARDInitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_NORSRAM_Bank
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
|
||||||
|
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
|
||||||
|
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_NAND_Bank
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
|
||||||
|
#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_PCCARD_Bank
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
|
||||||
|
((BANK) == FSMC_Bank1_NORSRAM2) || \
|
||||||
|
((BANK) == FSMC_Bank1_NORSRAM3) || \
|
||||||
|
((BANK) == FSMC_Bank1_NORSRAM4))
|
||||||
|
|
||||||
|
#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||||
|
((BANK) == FSMC_Bank3_NAND))
|
||||||
|
|
||||||
|
#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||||
|
((BANK) == FSMC_Bank3_NAND) || \
|
||||||
|
((BANK) == FSMC_Bank4_PCCARD))
|
||||||
|
|
||||||
|
#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
|
||||||
|
((BANK) == FSMC_Bank3_NAND) || \
|
||||||
|
((BANK) == FSMC_Bank4_PCCARD))
|
||||||
|
|
||||||
|
/** @defgroup NOR_SRAM_Controller
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
|
||||||
|
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
|
||||||
|
((MUX) == FSMC_DataAddressMux_Enable))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Memory_Type
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
|
||||||
|
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
|
||||||
|
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
|
||||||
|
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
|
||||||
|
((MEMORY) == FSMC_MemoryType_NOR))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Data_Width
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||||
|
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
|
||||||
|
((WIDTH) == FSMC_MemoryDataWidth_16b))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Burst_Access_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
|
||||||
|
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
|
||||||
|
((STATE) == FSMC_BurstAccessMode_Enable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_AsynchronousWait
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
|
||||||
|
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
|
||||||
|
((STATE) == FSMC_AsynchronousWait_Enable))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Wait_Signal_Polarity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
|
||||||
|
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
|
||||||
|
((POLARITY) == FSMC_WaitSignalPolarity_High))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Wrap_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
|
||||||
|
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
|
||||||
|
((MODE) == FSMC_WrapMode_Enable))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Wait_Timing
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
|
||||||
|
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
|
||||||
|
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Write_Operation
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||||||
|
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
|
||||||
|
((OPERATION) == FSMC_WriteOperation_Enable))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Wait_Signal
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||||||
|
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
|
||||||
|
((SIGNAL) == FSMC_WaitSignal_Enable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Extended_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
|
||||||
|
|
||||||
|
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
|
||||||
|
((MODE) == FSMC_ExtendedMode_Enable))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Write_Burst
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
|
||||||
|
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
|
||||||
|
((BURST) == FSMC_WriteBurst_Enable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Address_Setup_Time
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Address_Hold_Time
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Data_Setup_Time
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Bus_Turn_around_Duration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_CLK_Division
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Data_Latency
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Access_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
|
||||||
|
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
|
||||||
|
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
|
||||||
|
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
|
||||||
|
((MODE) == FSMC_AccessMode_B) || \
|
||||||
|
((MODE) == FSMC_AccessMode_C) || \
|
||||||
|
((MODE) == FSMC_AccessMode_D))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup NAND_PCCARD_Controller
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Wait_feature
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
|
||||||
|
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
|
||||||
|
((FEATURE) == FSMC_Waitfeature_Enable))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup FSMC_ECC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
|
||||||
|
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
|
||||||
|
((STATE) == FSMC_ECC_Enable))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_ECC_Page_Size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
|
||||||
|
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
|
||||||
|
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
|
||||||
|
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
|
||||||
|
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
|
||||||
|
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
|
||||||
|
((SIZE) == FSMC_ECCPageSize_512Bytes) || \
|
||||||
|
((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
|
||||||
|
((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
|
||||||
|
((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
|
||||||
|
((SIZE) == FSMC_ECCPageSize_8192Bytes))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_TCLR_Setup_Time
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_TAR_Setup_Time
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Setup_Time
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Wait_Setup_Time
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Hold_Setup_Time
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_HiZ_Setup_Time
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Interrupt_sources
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
|
||||||
|
#define FSMC_IT_Level ((uint32_t)0x00000010)
|
||||||
|
#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
|
||||||
|
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
|
||||||
|
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
|
||||||
|
((IT) == FSMC_IT_Level) || \
|
||||||
|
((IT) == FSMC_IT_FallingEdge))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Flags
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
|
||||||
|
#define FSMC_FLAG_Level ((uint32_t)0x00000002)
|
||||||
|
#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
|
||||||
|
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||||||
|
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
|
||||||
|
((FLAG) == FSMC_FLAG_Level) || \
|
||||||
|
((FLAG) == FSMC_FLAG_FallingEdge) || \
|
||||||
|
((FLAG) == FSMC_FLAG_FEMPT))
|
||||||
|
|
||||||
|
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
|
||||||
|
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
|
||||||
|
void FSMC_PCCARDDeInit(void);
|
||||||
|
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||||
|
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||||
|
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||||||
|
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||||
|
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||||
|
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||||||
|
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||||
|
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||||
|
void FSMC_PCCARDCmd(FunctionalState NewState);
|
||||||
|
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||||
|
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
|
||||||
|
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
|
||||||
|
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||||
|
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||||
|
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||||||
|
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__STM32F10x_FSMC_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,385 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_gpio.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the GPIO
|
||||||
|
* firmware library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_GPIO_H
|
||||||
|
#define __STM32F10x_GPIO_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup GPIO
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||||
|
((PERIPH) == GPIOB) || \
|
||||||
|
((PERIPH) == GPIOC) || \
|
||||||
|
((PERIPH) == GPIOD) || \
|
||||||
|
((PERIPH) == GPIOE) || \
|
||||||
|
((PERIPH) == GPIOF) || \
|
||||||
|
((PERIPH) == GPIOG))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Output Maximum frequency selection
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
GPIO_Speed_10MHz = 1,
|
||||||
|
GPIO_Speed_2MHz,
|
||||||
|
GPIO_Speed_50MHz
|
||||||
|
}GPIOSpeed_TypeDef;
|
||||||
|
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
|
||||||
|
((SPEED) == GPIO_Speed_50MHz))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configuration Mode enumeration
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{ GPIO_Mode_AIN = 0x0,
|
||||||
|
GPIO_Mode_IN_FLOATING = 0x04,
|
||||||
|
GPIO_Mode_IPD = 0x28,
|
||||||
|
GPIO_Mode_IPU = 0x48,
|
||||||
|
GPIO_Mode_Out_OD = 0x14,
|
||||||
|
GPIO_Mode_Out_PP = 0x10,
|
||||||
|
GPIO_Mode_AF_OD = 0x1C,
|
||||||
|
GPIO_Mode_AF_PP = 0x18
|
||||||
|
}GPIOMode_TypeDef;
|
||||||
|
|
||||||
|
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
|
||||||
|
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
|
||||||
|
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
|
||||||
|
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief GPIO Init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||||
|
This parameter can be any value of @ref GPIO_pins_define */
|
||||||
|
|
||||||
|
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||||
|
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||||
|
|
||||||
|
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||||
|
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||||
|
}GPIO_InitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Bit_SET and Bit_RESET enumeration
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{ Bit_RESET = 0,
|
||||||
|
Bit_SET
|
||||||
|
}BitAction;
|
||||||
|
|
||||||
|
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_pins_define
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||||
|
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||||
|
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||||
|
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||||
|
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||||
|
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||||
|
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||||
|
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||||
|
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||||
|
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||||
|
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||||
|
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||||
|
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||||
|
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||||
|
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||||
|
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||||
|
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||||
|
|
||||||
|
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
|
||||||
|
|
||||||
|
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||||
|
((PIN) == GPIO_Pin_1) || \
|
||||||
|
((PIN) == GPIO_Pin_2) || \
|
||||||
|
((PIN) == GPIO_Pin_3) || \
|
||||||
|
((PIN) == GPIO_Pin_4) || \
|
||||||
|
((PIN) == GPIO_Pin_5) || \
|
||||||
|
((PIN) == GPIO_Pin_6) || \
|
||||||
|
((PIN) == GPIO_Pin_7) || \
|
||||||
|
((PIN) == GPIO_Pin_8) || \
|
||||||
|
((PIN) == GPIO_Pin_9) || \
|
||||||
|
((PIN) == GPIO_Pin_10) || \
|
||||||
|
((PIN) == GPIO_Pin_11) || \
|
||||||
|
((PIN) == GPIO_Pin_12) || \
|
||||||
|
((PIN) == GPIO_Pin_13) || \
|
||||||
|
((PIN) == GPIO_Pin_14) || \
|
||||||
|
((PIN) == GPIO_Pin_15))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Remap_define
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
|
||||||
|
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
|
||||||
|
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
|
||||||
|
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
|
||||||
|
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
|
||||||
|
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
|
||||||
|
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
|
||||||
|
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
|
||||||
|
#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||||
|
to TIM2 Internal Trigger 1 for calibration
|
||||||
|
(only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
|
||||||
|
|
||||||
|
#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */
|
||||||
|
#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */
|
||||||
|
#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */
|
||||||
|
#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */
|
||||||
|
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
|
||||||
|
|
||||||
|
#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
|
||||||
|
#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
|
||||||
|
#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
|
||||||
|
#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||||
|
#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||||
|
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
|
||||||
|
|
||||||
|
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
|
||||||
|
#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
|
||||||
|
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
|
||||||
|
only for High density Value line devices) */
|
||||||
|
|
||||||
|
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
|
||||||
|
((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
|
||||||
|
((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
|
||||||
|
((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
|
||||||
|
((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
|
||||||
|
((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
|
||||||
|
((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
|
||||||
|
((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
|
||||||
|
((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
|
||||||
|
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
|
||||||
|
((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
|
||||||
|
((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
|
||||||
|
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
|
||||||
|
((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
|
||||||
|
((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
|
||||||
|
((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
|
||||||
|
((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
|
||||||
|
((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
|
||||||
|
((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
|
||||||
|
((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
|
||||||
|
((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
|
||||||
|
((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Port_Sources
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
|
||||||
|
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
|
||||||
|
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
|
||||||
|
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
|
||||||
|
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
|
||||||
|
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
|
||||||
|
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
|
||||||
|
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
|
||||||
|
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
|
||||||
|
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
|
||||||
|
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
|
||||||
|
((PORTSOURCE) == GPIO_PortSourceGPIOE))
|
||||||
|
|
||||||
|
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
|
||||||
|
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
|
||||||
|
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
|
||||||
|
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
|
||||||
|
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
|
||||||
|
((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
|
||||||
|
((PORTSOURCE) == GPIO_PortSourceGPIOG))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Pin_sources
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||||
|
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||||
|
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||||
|
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||||
|
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||||
|
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||||
|
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||||
|
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||||
|
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||||
|
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||||
|
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||||
|
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||||
|
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||||
|
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||||
|
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||||
|
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||||
|
|
||||||
|
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource1) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource2) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource3) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource4) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource5) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource6) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource7) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource8) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource9) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource10) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource11) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource12) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource13) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource14) || \
|
||||||
|
((PINSOURCE) == GPIO_PinSource15))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Ethernet_Media_Interface
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
|
||||||
|
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
|
||||||
|
|
||||||
|
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
|
||||||
|
((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||||
|
void GPIO_AFIODeInit(void);
|
||||||
|
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||||
|
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||||
|
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||||
|
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||||
|
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||||
|
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||||
|
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||||
|
void GPIO_EventOutputCmd(FunctionalState NewState);
|
||||||
|
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
|
||||||
|
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||||
|
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_GPIO_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,684 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_i2c.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_I2C_H
|
||||||
|
#define __STM32F10x_I2C_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2C
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief I2C Init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
|
||||||
|
This parameter must be set to a value lower than 400kHz */
|
||||||
|
|
||||||
|
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||||
|
This parameter can be a value of @ref I2C_mode */
|
||||||
|
|
||||||
|
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||||
|
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||||
|
|
||||||
|
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
|
||||||
|
This parameter can be a 7-bit or 10-bit address. */
|
||||||
|
|
||||||
|
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||||
|
This parameter can be a value of @ref I2C_acknowledgement */
|
||||||
|
|
||||||
|
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||||
|
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||||
|
}I2C_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup I2C_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
|
||||||
|
((PERIPH) == I2C2))
|
||||||
|
/** @defgroup I2C_mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_Mode_I2C ((uint16_t)0x0000)
|
||||||
|
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
|
||||||
|
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
|
||||||
|
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
|
||||||
|
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||||
|
((MODE) == I2C_Mode_SMBusHost))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_duty_cycle_in_fast_mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
||||||
|
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
|
||||||
|
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
|
||||||
|
((CYCLE) == I2C_DutyCycle_2))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_acknowledgement
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_Ack_Enable ((uint16_t)0x0400)
|
||||||
|
#define I2C_Ack_Disable ((uint16_t)0x0000)
|
||||||
|
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
|
||||||
|
((STATE) == I2C_Ack_Disable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_transfer_direction
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_Direction_Transmitter ((uint8_t)0x00)
|
||||||
|
#define I2C_Direction_Receiver ((uint8_t)0x01)
|
||||||
|
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
|
||||||
|
((DIRECTION) == I2C_Direction_Receiver))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_acknowledged_address
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
|
||||||
|
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
|
||||||
|
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
|
||||||
|
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_registers
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_Register_CR1 ((uint8_t)0x00)
|
||||||
|
#define I2C_Register_CR2 ((uint8_t)0x04)
|
||||||
|
#define I2C_Register_OAR1 ((uint8_t)0x08)
|
||||||
|
#define I2C_Register_OAR2 ((uint8_t)0x0C)
|
||||||
|
#define I2C_Register_DR ((uint8_t)0x10)
|
||||||
|
#define I2C_Register_SR1 ((uint8_t)0x14)
|
||||||
|
#define I2C_Register_SR2 ((uint8_t)0x18)
|
||||||
|
#define I2C_Register_CCR ((uint8_t)0x1C)
|
||||||
|
#define I2C_Register_TRISE ((uint8_t)0x20)
|
||||||
|
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||||
|
((REGISTER) == I2C_Register_CR2) || \
|
||||||
|
((REGISTER) == I2C_Register_OAR1) || \
|
||||||
|
((REGISTER) == I2C_Register_OAR2) || \
|
||||||
|
((REGISTER) == I2C_Register_DR) || \
|
||||||
|
((REGISTER) == I2C_Register_SR1) || \
|
||||||
|
((REGISTER) == I2C_Register_SR2) || \
|
||||||
|
((REGISTER) == I2C_Register_CCR) || \
|
||||||
|
((REGISTER) == I2C_Register_TRISE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_SMBus_alert_pin_level
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
|
||||||
|
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
|
||||||
|
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
|
||||||
|
((ALERT) == I2C_SMBusAlert_High))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_PEC_position
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_PECPosition_Next ((uint16_t)0x0800)
|
||||||
|
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
|
||||||
|
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
|
||||||
|
((POSITION) == I2C_PECPosition_Current))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_NCAK_position
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
|
||||||
|
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
|
||||||
|
#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
|
||||||
|
((POSITION) == I2C_NACKPosition_Current))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_interrupts_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_IT_BUF ((uint16_t)0x0400)
|
||||||
|
#define I2C_IT_EVT ((uint16_t)0x0200)
|
||||||
|
#define I2C_IT_ERR ((uint16_t)0x0100)
|
||||||
|
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_interrupts_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
|
||||||
|
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
|
||||||
|
#define I2C_IT_PECERR ((uint32_t)0x01001000)
|
||||||
|
#define I2C_IT_OVR ((uint32_t)0x01000800)
|
||||||
|
#define I2C_IT_AF ((uint32_t)0x01000400)
|
||||||
|
#define I2C_IT_ARLO ((uint32_t)0x01000200)
|
||||||
|
#define I2C_IT_BERR ((uint32_t)0x01000100)
|
||||||
|
#define I2C_IT_TXE ((uint32_t)0x06000080)
|
||||||
|
#define I2C_IT_RXNE ((uint32_t)0x06000040)
|
||||||
|
#define I2C_IT_STOPF ((uint32_t)0x02000010)
|
||||||
|
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
|
||||||
|
#define I2C_IT_BTF ((uint32_t)0x02000004)
|
||||||
|
#define I2C_IT_ADDR ((uint32_t)0x02000002)
|
||||||
|
#define I2C_IT_SB ((uint32_t)0x02000001)
|
||||||
|
|
||||||
|
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
|
||||||
|
|
||||||
|
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
|
||||||
|
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
|
||||||
|
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
|
||||||
|
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
|
||||||
|
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
|
||||||
|
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
|
||||||
|
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_flags_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SR2 register flags
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
|
||||||
|
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
|
||||||
|
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
|
||||||
|
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
|
||||||
|
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
|
||||||
|
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||||
|
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SR1 register flags
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
|
||||||
|
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
|
||||||
|
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||||
|
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
|
||||||
|
#define I2C_FLAG_AF ((uint32_t)0x10000400)
|
||||||
|
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
|
||||||
|
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
|
||||||
|
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
|
||||||
|
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
|
||||||
|
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||||
|
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
|
||||||
|
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
|
||||||
|
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
|
||||||
|
#define I2C_FLAG_SB ((uint32_t)0x10000001)
|
||||||
|
|
||||||
|
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||||
|
|
||||||
|
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
|
||||||
|
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
|
||||||
|
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
|
||||||
|
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
|
||||||
|
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||||
|
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
|
||||||
|
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
|
||||||
|
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
|
||||||
|
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
|
||||||
|
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||||
|
((FLAG) == I2C_FLAG_SB))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_Events
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*========================================
|
||||||
|
|
||||||
|
I2C Master Events (Events grouped in order of communication)
|
||||||
|
==========================================*/
|
||||||
|
/**
|
||||||
|
* @brief Communication start
|
||||||
|
*
|
||||||
|
* After sending the START condition (I2C_GenerateSTART() function) the master
|
||||||
|
* has to wait for this event. It means that the Start condition has been correctly
|
||||||
|
* released on the I2C bus (the bus is free, no other devices is communicating).
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
/* --EV5 */
|
||||||
|
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Address Acknowledge
|
||||||
|
*
|
||||||
|
* After checking on EV5 (start condition correctly released on the bus), the
|
||||||
|
* master sends the address of the slave(s) with which it will communicate
|
||||||
|
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
|
||||||
|
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
|
||||||
|
* his address. If an acknowledge is sent on the bus, one of the following events will
|
||||||
|
* be set:
|
||||||
|
*
|
||||||
|
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
|
||||||
|
* event is set.
|
||||||
|
*
|
||||||
|
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
|
||||||
|
* is set
|
||||||
|
*
|
||||||
|
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
|
||||||
|
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
|
||||||
|
* function). Then master should wait on EV9. It means that the 10-bit addressing
|
||||||
|
* header has been correctly sent on the bus. Then master should send the second part of
|
||||||
|
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
|
||||||
|
* should wait for event EV6.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* --EV6 */
|
||||||
|
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||||
|
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||||
|
/* --EV9 */
|
||||||
|
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Communication events
|
||||||
|
*
|
||||||
|
* If a communication is established (START condition generated and slave address
|
||||||
|
* acknowledged) then the master has to check on one of the following events for
|
||||||
|
* communication procedures:
|
||||||
|
*
|
||||||
|
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
|
||||||
|
* the data received from the slave (I2C_ReceiveData() function).
|
||||||
|
*
|
||||||
|
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
|
||||||
|
* function) then to wait on event EV8 or EV8_2.
|
||||||
|
* These two events are similar:
|
||||||
|
* - EV8 means that the data has been written in the data register and is
|
||||||
|
* being shifted out.
|
||||||
|
* - EV8_2 means that the data has been physically shifted out and output
|
||||||
|
* on the bus.
|
||||||
|
* In most cases, using EV8 is sufficient for the application.
|
||||||
|
* Using EV8_2 leads to a slower communication but ensure more reliable test.
|
||||||
|
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
|
||||||
|
* (before Stop condition generation).
|
||||||
|
*
|
||||||
|
* @note In case the user software does not guarantee that this event EV7 is
|
||||||
|
* managed before the current byte end of transfer, then user may check on EV7
|
||||||
|
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||||
|
* In this case the communication may be slower.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Master RECEIVER mode -----------------------------*/
|
||||||
|
/* --EV7 */
|
||||||
|
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||||
|
|
||||||
|
/* Master TRANSMITTER mode --------------------------*/
|
||||||
|
/* --EV8 */
|
||||||
|
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||||
|
/* --EV8_2 */
|
||||||
|
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||||
|
|
||||||
|
|
||||||
|
/*========================================
|
||||||
|
|
||||||
|
I2C Slave Events (Events grouped in order of communication)
|
||||||
|
==========================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Communication start events
|
||||||
|
*
|
||||||
|
* Wait on one of these events at the start of the communication. It means that
|
||||||
|
* the I2C peripheral detected a Start condition on the bus (generated by master
|
||||||
|
* device) followed by the peripheral address. The peripheral generates an ACK
|
||||||
|
* condition on the bus (if the acknowledge feature is enabled through function
|
||||||
|
* I2C_AcknowledgeConfig()) and the events listed above are set :
|
||||||
|
*
|
||||||
|
* 1) In normal case (only one address managed by the slave), when the address
|
||||||
|
* sent by the master matches the own address of the peripheral (configured by
|
||||||
|
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||||
|
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||||
|
*
|
||||||
|
* 2) In case the address sent by the master matches the second address of the
|
||||||
|
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||||
|
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||||
|
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||||
|
*
|
||||||
|
* 3) In case the address sent by the master is General Call (address 0x00) and
|
||||||
|
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||||
|
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* --EV1 (all the events below are variants of EV1) */
|
||||||
|
/* 1) Case of One Single Address managed by the slave */
|
||||||
|
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||||
|
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||||
|
|
||||||
|
/* 2) Case of Dual address managed by the slave */
|
||||||
|
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||||
|
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||||
|
|
||||||
|
/* 3) Case of General Call enabled for the slave */
|
||||||
|
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Communication events
|
||||||
|
*
|
||||||
|
* Wait on one of these events when EV1 has already been checked and:
|
||||||
|
*
|
||||||
|
* - Slave RECEIVER mode:
|
||||||
|
* - EV2: When the application is expecting a data byte to be received.
|
||||||
|
* - EV4: When the application is expecting the end of the communication: master
|
||||||
|
* sends a stop condition and data transmission is stopped.
|
||||||
|
*
|
||||||
|
* - Slave Transmitter mode:
|
||||||
|
* - EV3: When a byte has been transmitted by the slave and the application is expecting
|
||||||
|
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
|
||||||
|
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
|
||||||
|
* used when the user software doesn't guarantee the EV3 is managed before the
|
||||||
|
* current byte end of transfer.
|
||||||
|
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
|
||||||
|
* shall end (before sending the STOP condition). In this case slave has to stop sending
|
||||||
|
* data bytes and expect a Stop condition on the bus.
|
||||||
|
*
|
||||||
|
* @note In case the user software does not guarantee that the event EV2 is
|
||||||
|
* managed before the current byte end of transfer, then user may check on EV2
|
||||||
|
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||||
|
* In this case the communication may be slower.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Slave RECEIVER mode --------------------------*/
|
||||||
|
/* --EV2 */
|
||||||
|
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||||
|
/* --EV4 */
|
||||||
|
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
||||||
|
|
||||||
|
/* Slave TRANSMITTER mode -----------------------*/
|
||||||
|
/* --EV3 */
|
||||||
|
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||||
|
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||||
|
/* --EV3_2 */
|
||||||
|
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||||
|
|
||||||
|
/*=========================== End of Events Description ==========================================*/
|
||||||
|
|
||||||
|
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
|
||||||
|
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
|
||||||
|
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
|
||||||
|
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
|
||||||
|
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
|
||||||
|
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
|
||||||
|
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
|
||||||
|
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
|
||||||
|
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
|
||||||
|
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
|
||||||
|
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
|
||||||
|
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
|
||||||
|
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
|
||||||
|
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
|
||||||
|
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
|
||||||
|
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
|
||||||
|
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
|
||||||
|
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
|
||||||
|
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
|
||||||
|
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_own_address1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_clock_speed
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2C_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||||
|
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||||
|
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||||
|
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
|
||||||
|
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
|
||||||
|
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||||
|
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||||
|
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||||
|
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||||
|
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
|
||||||
|
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
|
||||||
|
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
|
||||||
|
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||||
|
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief
|
||||||
|
****************************************************************************************
|
||||||
|
*
|
||||||
|
* I2C State Monitoring Functions
|
||||||
|
*
|
||||||
|
****************************************************************************************
|
||||||
|
* This I2C driver provides three different ways for I2C state monitoring
|
||||||
|
* depending on the application requirements and constraints:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* 1) Basic state monitoring:
|
||||||
|
* Using I2C_CheckEvent() function:
|
||||||
|
* It compares the status registers (SR1 and SR2) content to a given event
|
||||||
|
* (can be the combination of one or more flags).
|
||||||
|
* It returns SUCCESS if the current status includes the given flags
|
||||||
|
* and returns ERROR if one or more flags are missing in the current status.
|
||||||
|
* - When to use:
|
||||||
|
* - This function is suitable for most applications as well as for startup
|
||||||
|
* activity since the events are fully described in the product reference manual
|
||||||
|
* (RM0008).
|
||||||
|
* - It is also suitable for users who need to define their own events.
|
||||||
|
* - Limitations:
|
||||||
|
* - If an error occurs (ie. error flags are set besides to the monitored flags),
|
||||||
|
* the I2C_CheckEvent() function may return SUCCESS despite the communication
|
||||||
|
* hold or corrupted real state.
|
||||||
|
* In this case, it is advised to use error interrupts to monitor the error
|
||||||
|
* events and handle them in the interrupt IRQ handler.
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* For error management, it is advised to use the following functions:
|
||||||
|
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
|
||||||
|
* - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
|
||||||
|
* Where x is the peripheral instance (I2C1, I2C2 ...)
|
||||||
|
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
|
||||||
|
* in order to determine which error occurred.
|
||||||
|
* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
|
||||||
|
* and/or I2C_GenerateStop() in order to clear the error flag and source,
|
||||||
|
* and return to correct communication status.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* 2) Advanced state monitoring:
|
||||||
|
* Using the function I2C_GetLastEvent() which returns the image of both status
|
||||||
|
* registers in a single word (uint32_t) (Status Register 2 value is shifted left
|
||||||
|
* by 16 bits and concatenated to Status Register 1).
|
||||||
|
* - When to use:
|
||||||
|
* - This function is suitable for the same applications above but it allows to
|
||||||
|
* overcome the limitations of I2C_GetFlagStatus() function (see below).
|
||||||
|
* The returned value could be compared to events already defined in the
|
||||||
|
* library (stm32f10x_i2c.h) or to custom values defined by user.
|
||||||
|
* - This function is suitable when multiple flags are monitored at the same time.
|
||||||
|
* - At the opposite of I2C_CheckEvent() function, this function allows user to
|
||||||
|
* choose when an event is accepted (when all events flags are set and no
|
||||||
|
* other flags are set or just when the needed flags are set like
|
||||||
|
* I2C_CheckEvent() function).
|
||||||
|
* - Limitations:
|
||||||
|
* - User may need to define his own events.
|
||||||
|
* - Same remark concerning the error management is applicable for this
|
||||||
|
* function if user decides to check only regular communication flags (and
|
||||||
|
* ignores error flags).
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* 3) Flag-based state monitoring:
|
||||||
|
* Using the function I2C_GetFlagStatus() which simply returns the status of
|
||||||
|
* one single flag (ie. I2C_FLAG_RXNE ...).
|
||||||
|
* - When to use:
|
||||||
|
* - This function could be used for specific applications or in debug phase.
|
||||||
|
* - It is suitable when only one flag checking is needed (most I2C events
|
||||||
|
* are monitored through multiple flags).
|
||||||
|
* - Limitations:
|
||||||
|
* - When calling this function, the Status register is accessed. Some flags are
|
||||||
|
* cleared when the status register is accessed. So checking the status
|
||||||
|
* of one Flag, may clear other ones.
|
||||||
|
* - Function may need to be called twice or more in order to monitor one
|
||||||
|
* single event.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
*
|
||||||
|
* 1) Basic state monitoring
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
|
||||||
|
/**
|
||||||
|
*
|
||||||
|
* 2) Advanced state monitoring
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
||||||
|
/**
|
||||||
|
*
|
||||||
|
* 3) Flag-based state monitoring
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||||
|
/**
|
||||||
|
*
|
||||||
|
*******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||||
|
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||||
|
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__STM32F10x_I2C_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,140 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_iwdg.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the IWDG
|
||||||
|
* firmware library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_IWDG_H
|
||||||
|
#define __STM32F10x_IWDG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup IWDG
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_WriteAccess
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||||
|
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||||
|
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
|
||||||
|
((ACCESS) == IWDG_WriteAccess_Disable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_prescaler
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||||
|
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||||
|
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||||
|
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||||
|
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||||
|
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||||
|
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||||
|
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
|
||||||
|
((PRESCALER) == IWDG_Prescaler_8) || \
|
||||||
|
((PRESCALER) == IWDG_Prescaler_16) || \
|
||||||
|
((PRESCALER) == IWDG_Prescaler_32) || \
|
||||||
|
((PRESCALER) == IWDG_Prescaler_64) || \
|
||||||
|
((PRESCALER) == IWDG_Prescaler_128)|| \
|
||||||
|
((PRESCALER) == IWDG_Prescaler_256))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Flag
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||||
|
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||||
|
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
|
||||||
|
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||||
|
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||||
|
void IWDG_SetReload(uint16_t Reload);
|
||||||
|
void IWDG_ReloadCounter(void);
|
||||||
|
void IWDG_Enable(void);
|
||||||
|
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_IWDG_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,156 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_pwr.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the PWR firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_PWR_H
|
||||||
|
#define __STM32F10x_PWR_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PWR
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PVD_detection_level
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
|
||||||
|
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
|
||||||
|
#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
|
||||||
|
#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
|
||||||
|
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
|
||||||
|
#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
|
||||||
|
#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
|
||||||
|
#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
|
||||||
|
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
|
||||||
|
((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
|
||||||
|
((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
|
||||||
|
((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Regulator_state_is_STOP_mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||||
|
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
|
||||||
|
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
|
||||||
|
((REGULATOR) == PWR_Regulator_LowPower))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup STOP_mode_entry
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||||
|
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||||
|
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Flag
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PWR_FLAG_WU ((uint32_t)0x00000001)
|
||||||
|
#define PWR_FLAG_SB ((uint32_t)0x00000002)
|
||||||
|
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
|
||||||
|
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
|
||||||
|
((FLAG) == PWR_FLAG_PVDO))
|
||||||
|
|
||||||
|
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void PWR_DeInit(void);
|
||||||
|
void PWR_BackupAccessCmd(FunctionalState NewState);
|
||||||
|
void PWR_PVDCmd(FunctionalState NewState);
|
||||||
|
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||||
|
void PWR_WakeUpPinCmd(FunctionalState NewState);
|
||||||
|
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||||
|
void PWR_EnterSTANDBYMode(void);
|
||||||
|
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||||
|
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_PWR_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,727 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_rcc.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the RCC firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_RCC_H
|
||||||
|
#define __STM32F10x_RCC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RCC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RCC_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
|
||||||
|
uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
|
||||||
|
uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
|
||||||
|
uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
|
||||||
|
uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
|
||||||
|
}RCC_ClocksTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RCC_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HSE_configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_HSE_OFF ((uint32_t)0x00000000)
|
||||||
|
#define RCC_HSE_ON ((uint32_t)0x00010000)
|
||||||
|
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
|
||||||
|
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||||
|
((HSE) == RCC_HSE_Bypass))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PLL_entry_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
|
||||||
|
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
|
||||||
|
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
|
||||||
|
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
|
||||||
|
((SOURCE) == RCC_PLLSource_HSE_Div1) || \
|
||||||
|
((SOURCE) == RCC_PLLSource_HSE_Div2))
|
||||||
|
#else
|
||||||
|
#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
|
||||||
|
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
|
||||||
|
((SOURCE) == RCC_PLLSource_PREDIV1))
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PLL_multiplication_factor
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#ifndef STM32F10X_CL
|
||||||
|
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
|
||||||
|
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
|
||||||
|
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
|
||||||
|
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
|
||||||
|
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
|
||||||
|
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
|
||||||
|
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
|
||||||
|
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
|
||||||
|
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
|
||||||
|
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
|
||||||
|
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
|
||||||
|
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
|
||||||
|
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
|
||||||
|
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
|
||||||
|
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
|
||||||
|
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
|
||||||
|
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
|
||||||
|
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
|
||||||
|
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
|
||||||
|
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
|
||||||
|
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
|
||||||
|
((MUL) == RCC_PLLMul_16))
|
||||||
|
|
||||||
|
#else
|
||||||
|
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
|
||||||
|
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
|
||||||
|
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
|
||||||
|
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
|
||||||
|
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
|
||||||
|
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
|
||||||
|
#define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
|
||||||
|
|
||||||
|
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
|
||||||
|
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
|
||||||
|
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
|
||||||
|
((MUL) == RCC_PLLMul_6_5))
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PREDIV1_division_factor
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
|
||||||
|
#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
|
||||||
|
#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
|
||||||
|
#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
|
||||||
|
#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
|
||||||
|
#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
|
||||||
|
#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
|
||||||
|
#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
|
||||||
|
#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
|
||||||
|
#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
|
||||||
|
#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
|
||||||
|
#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
|
||||||
|
#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
|
||||||
|
#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
|
||||||
|
#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
|
||||||
|
#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
|
||||||
|
|
||||||
|
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
|
||||||
|
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
|
||||||
|
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
|
||||||
|
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
|
||||||
|
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
|
||||||
|
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
|
||||||
|
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
|
||||||
|
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup PREDIV1_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#ifdef STM32F10X_CL
|
||||||
|
/* PREDIV1 clock source (for STM32 connectivity line devices) */
|
||||||
|
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
|
||||||
|
|
||||||
|
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
|
||||||
|
((SOURCE) == RCC_PREDIV1_Source_PLL2))
|
||||||
|
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||||
|
/* PREDIV1 clock source (for STM32 Value line devices) */
|
||||||
|
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
#define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef STM32F10X_CL
|
||||||
|
/** @defgroup PREDIV2_division_factor
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
|
||||||
|
#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
|
||||||
|
#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
|
||||||
|
#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
|
||||||
|
#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
|
||||||
|
#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
|
||||||
|
#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
|
||||||
|
#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
|
||||||
|
#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
|
||||||
|
#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
|
||||||
|
#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
|
||||||
|
#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
|
||||||
|
#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
|
||||||
|
#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
|
||||||
|
#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
|
||||||
|
|
||||||
|
#define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
|
||||||
|
((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
|
||||||
|
((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
|
||||||
|
((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
|
||||||
|
((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
|
||||||
|
((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
|
||||||
|
((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
|
||||||
|
((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup PLL2_multiplication_factor
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
|
||||||
|
#define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
|
||||||
|
#define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
|
||||||
|
#define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
|
||||||
|
#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
|
||||||
|
#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
|
||||||
|
#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
|
||||||
|
#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
|
||||||
|
#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
|
||||||
|
|
||||||
|
#define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
|
||||||
|
((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
|
||||||
|
((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
|
||||||
|
((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
|
||||||
|
((MUL) == RCC_PLL2Mul_20))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup PLL3_multiplication_factor
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
|
||||||
|
#define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
|
||||||
|
#define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
|
||||||
|
#define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
|
||||||
|
#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
|
||||||
|
#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
|
||||||
|
#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
|
||||||
|
#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
|
||||||
|
#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
|
||||||
|
|
||||||
|
#define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
|
||||||
|
((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
|
||||||
|
((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
|
||||||
|
((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
|
||||||
|
((MUL) == RCC_PLL3Mul_20))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup System_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||||
|
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||||
|
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||||
|
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||||
|
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||||
|
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup AHB_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
|
||||||
|
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
|
||||||
|
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
|
||||||
|
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||||
|
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
|
||||||
|
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
|
||||||
|
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
|
||||||
|
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
|
||||||
|
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||||
|
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||||
|
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||||
|
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||||
|
((HCLK) == RCC_SYSCLK_Div512))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup APB1_APB2_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
|
||||||
|
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
|
||||||
|
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
|
||||||
|
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
|
||||||
|
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||||
|
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||||
|
((PCLK) == RCC_HCLK_Div16))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RCC_Interrupt_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||||
|
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||||
|
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||||
|
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||||
|
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||||
|
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||||
|
|
||||||
|
#ifndef STM32F10X_CL
|
||||||
|
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
|
||||||
|
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||||
|
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||||
|
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
|
||||||
|
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
|
||||||
|
#else
|
||||||
|
#define RCC_IT_PLL2RDY ((uint8_t)0x20)
|
||||||
|
#define RCC_IT_PLL3RDY ((uint8_t)0x40)
|
||||||
|
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
|
||||||
|
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||||
|
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||||
|
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
|
||||||
|
((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
|
||||||
|
#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef STM32F10X_CL
|
||||||
|
/** @defgroup USB_Device_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
|
||||||
|
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
|
||||||
|
|
||||||
|
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
|
||||||
|
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#else
|
||||||
|
/** @defgroup USB_OTG_FS_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
|
||||||
|
#define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
|
||||||
|
|
||||||
|
#define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
|
||||||
|
((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef STM32F10X_CL
|
||||||
|
/** @defgroup I2S2_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
|
||||||
|
#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
|
||||||
|
|
||||||
|
#define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
|
||||||
|
((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S3_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
|
||||||
|
#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
|
||||||
|
|
||||||
|
#define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
|
||||||
|
((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup ADC_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
|
||||||
|
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
|
||||||
|
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
|
||||||
|
((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup LSE_configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||||
|
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||||
|
#define RCC_LSE_Bypass ((uint8_t)0x04)
|
||||||
|
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||||
|
((LSE) == RCC_LSE_Bypass))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_clock_source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
|
||||||
|
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
|
||||||
|
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
|
||||||
|
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||||
|
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||||
|
((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup AHB_peripheral
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
|
||||||
|
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
|
||||||
|
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
|
||||||
|
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
|
||||||
|
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
|
||||||
|
|
||||||
|
#ifndef STM32F10X_CL
|
||||||
|
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
|
||||||
|
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
|
||||||
|
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
|
||||||
|
#else
|
||||||
|
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
|
||||||
|
#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
|
||||||
|
#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
|
||||||
|
#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
|
||||||
|
|
||||||
|
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
|
||||||
|
#define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup APB2_peripheral
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
|
||||||
|
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
|
||||||
|
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
|
||||||
|
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
|
||||||
|
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
|
||||||
|
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
|
||||||
|
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
|
||||||
|
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
|
||||||
|
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
|
||||||
|
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
|
||||||
|
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
|
||||||
|
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||||
|
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
|
||||||
|
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
|
||||||
|
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
|
||||||
|
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
|
||||||
|
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
|
||||||
|
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
|
||||||
|
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
|
||||||
|
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
|
||||||
|
|
||||||
|
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup APB1_peripheral
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||||
|
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||||
|
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||||
|
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
|
||||||
|
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||||
|
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||||
|
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
|
||||||
|
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
|
||||||
|
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
|
||||||
|
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||||
|
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
|
||||||
|
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||||
|
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||||
|
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||||
|
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||||
|
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||||
|
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||||
|
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
|
||||||
|
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||||
|
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
|
||||||
|
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
|
||||||
|
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||||
|
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||||
|
#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
|
||||||
|
|
||||||
|
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup Clock_source_to_output_on_MCO_pin
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_MCO_NoClock ((uint8_t)0x00)
|
||||||
|
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
|
||||||
|
#define RCC_MCO_HSI ((uint8_t)0x05)
|
||||||
|
#define RCC_MCO_HSE ((uint8_t)0x06)
|
||||||
|
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
|
||||||
|
|
||||||
|
#ifndef STM32F10X_CL
|
||||||
|
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
|
||||||
|
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
|
||||||
|
((MCO) == RCC_MCO_PLLCLK_Div2))
|
||||||
|
#else
|
||||||
|
#define RCC_MCO_PLL2CLK ((uint8_t)0x08)
|
||||||
|
#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
|
||||||
|
#define RCC_MCO_XT1 ((uint8_t)0x0A)
|
||||||
|
#define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
|
||||||
|
|
||||||
|
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
|
||||||
|
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
|
||||||
|
((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
|
||||||
|
((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
|
||||||
|
((MCO) == RCC_MCO_PLL3CLK))
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RCC_Flag
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||||
|
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||||
|
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||||
|
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
|
||||||
|
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||||
|
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||||
|
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||||
|
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||||
|
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||||
|
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||||
|
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||||
|
|
||||||
|
#ifndef STM32F10X_CL
|
||||||
|
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||||
|
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||||
|
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
|
||||||
|
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
|
||||||
|
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
|
||||||
|
((FLAG) == RCC_FLAG_LPWRRST))
|
||||||
|
#else
|
||||||
|
#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
|
||||||
|
#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
|
||||||
|
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||||
|
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||||
|
((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
|
||||||
|
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
|
||||||
|
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
|
||||||
|
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
|
||||||
|
((FLAG) == RCC_FLAG_LPWRRST))
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RCC_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RCC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void RCC_DeInit(void);
|
||||||
|
void RCC_HSEConfig(uint32_t RCC_HSE);
|
||||||
|
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||||
|
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||||
|
void RCC_HSICmd(FunctionalState NewState);
|
||||||
|
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||||||
|
void RCC_PLLCmd(FunctionalState NewState);
|
||||||
|
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
|
||||||
|
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef STM32F10X_CL
|
||||||
|
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
|
||||||
|
void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
|
||||||
|
void RCC_PLL2Cmd(FunctionalState NewState);
|
||||||
|
void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
|
||||||
|
void RCC_PLL3Cmd(FunctionalState NewState);
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||||
|
uint8_t RCC_GetSYSCLKSource(void);
|
||||||
|
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||||
|
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||||
|
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||||
|
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||||
|
|
||||||
|
#ifndef STM32F10X_CL
|
||||||
|
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
|
||||||
|
#else
|
||||||
|
void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
|
||||||
|
|
||||||
|
#ifdef STM32F10X_CL
|
||||||
|
void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
|
||||||
|
void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||||
|
void RCC_LSICmd(FunctionalState NewState);
|
||||||
|
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||||
|
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||||
|
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||||
|
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||||
|
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||||
|
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||||
|
|
||||||
|
#ifdef STM32F10X_CL
|
||||||
|
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||||
|
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||||
|
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||||
|
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||||
|
void RCC_MCOConfig(uint8_t RCC_MCO);
|
||||||
|
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||||
|
void RCC_ClearFlag(void);
|
||||||
|
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||||
|
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_RCC_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,135 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_rtc.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the RTC firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_RTC_H
|
||||||
|
#define __STM32F10x_RTC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RTC
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_interrupts_define
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
|
||||||
|
#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
|
||||||
|
#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
|
||||||
|
#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
|
||||||
|
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
|
||||||
|
((IT) == RTC_IT_SEC))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_interrupts_flags
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
|
||||||
|
#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
|
||||||
|
#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
|
||||||
|
#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
|
||||||
|
#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
|
||||||
|
#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
|
||||||
|
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
|
||||||
|
((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
|
||||||
|
((FLAG) == RTC_FLAG_SEC))
|
||||||
|
#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
|
||||||
|
void RTC_EnterConfigMode(void);
|
||||||
|
void RTC_ExitConfigMode(void);
|
||||||
|
uint32_t RTC_GetCounter(void);
|
||||||
|
void RTC_SetCounter(uint32_t CounterValue);
|
||||||
|
void RTC_SetPrescaler(uint32_t PrescalerValue);
|
||||||
|
void RTC_SetAlarm(uint32_t AlarmValue);
|
||||||
|
uint32_t RTC_GetDivider(void);
|
||||||
|
void RTC_WaitForLastTask(void);
|
||||||
|
void RTC_WaitForSynchro(void);
|
||||||
|
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
|
||||||
|
void RTC_ClearFlag(uint16_t RTC_FLAG);
|
||||||
|
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
|
||||||
|
void RTC_ClearITPendingBit(uint16_t RTC_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_RTC_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,531 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_sdio.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the SDIO firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_SDIO_H
|
||||||
|
#define __STM32F10x_SDIO_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SDIO
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
|
||||||
|
This parameter can be a value of @ref SDIO_Clock_Edge */
|
||||||
|
|
||||||
|
uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
|
||||||
|
enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_Clock_Bypass */
|
||||||
|
|
||||||
|
uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
|
||||||
|
disabled when the bus is idle.
|
||||||
|
This parameter can be a value of @ref SDIO_Clock_Power_Save */
|
||||||
|
|
||||||
|
uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
|
||||||
|
This parameter can be a value of @ref SDIO_Bus_Wide */
|
||||||
|
|
||||||
|
uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
|
||||||
|
|
||||||
|
uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
|
||||||
|
This parameter can be a value between 0x00 and 0xFF. */
|
||||||
|
|
||||||
|
} SDIO_InitTypeDef;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
|
||||||
|
to a card as part of a command message. If a command
|
||||||
|
contains an argument, it must be loaded into this register
|
||||||
|
before writing the command to the command register */
|
||||||
|
|
||||||
|
uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
|
||||||
|
|
||||||
|
uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
|
||||||
|
This parameter can be a value of @ref SDIO_Response_Type */
|
||||||
|
|
||||||
|
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
|
||||||
|
|
||||||
|
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
|
||||||
|
is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_CPSM_State */
|
||||||
|
} SDIO_CmdInitTypeDef;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
|
||||||
|
|
||||||
|
uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
|
||||||
|
|
||||||
|
uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
|
||||||
|
This parameter can be a value of @ref SDIO_Data_Block_Size */
|
||||||
|
|
||||||
|
uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
|
||||||
|
is a read or write.
|
||||||
|
This parameter can be a value of @ref SDIO_Transfer_Direction */
|
||||||
|
|
||||||
|
uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
|
||||||
|
This parameter can be a value of @ref SDIO_Transfer_Type */
|
||||||
|
|
||||||
|
uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
|
||||||
|
is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_DPSM_State */
|
||||||
|
} SDIO_DataInitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Clock_Edge
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
|
||||||
|
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
|
||||||
|
((EDGE) == SDIO_ClockEdge_Falling))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Clock_Bypass
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
|
||||||
|
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
|
||||||
|
((BYPASS) == SDIO_ClockBypass_Enable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Clock_Power_Save
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
|
||||||
|
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
|
||||||
|
((SAVE) == SDIO_ClockPowerSave_Enable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Bus_Wide
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
|
||||||
|
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
|
||||||
|
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
|
||||||
|
((WIDE) == SDIO_BusWide_8b))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Hardware_Flow_Control
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
|
||||||
|
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
|
||||||
|
((CONTROL) == SDIO_HardwareFlowControl_Enable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Power_State
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
|
||||||
|
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Interrupt_sources
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
|
||||||
|
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
|
||||||
|
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
|
||||||
|
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
|
||||||
|
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
|
||||||
|
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
|
||||||
|
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
|
||||||
|
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
|
||||||
|
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
|
||||||
|
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
|
||||||
|
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
|
||||||
|
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
|
||||||
|
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
|
||||||
|
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
|
||||||
|
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
|
||||||
|
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
|
||||||
|
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
|
||||||
|
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
|
||||||
|
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
|
||||||
|
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
|
||||||
|
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Command_Index
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Response_Type
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_Response_No ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_Response_Short ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_Response_Long ((uint32_t)0x000000C0)
|
||||||
|
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
|
||||||
|
((RESPONSE) == SDIO_Response_Short) || \
|
||||||
|
((RESPONSE) == SDIO_Response_Long))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Wait_Interrupt_State
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
|
||||||
|
#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
|
||||||
|
#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
|
||||||
|
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
|
||||||
|
((WAIT) == SDIO_Wait_Pend))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_CPSM_State
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
|
||||||
|
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Response_Registers
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_RESP1 ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_RESP2 ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_RESP3 ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_RESP4 ((uint32_t)0x0000000C)
|
||||||
|
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
|
||||||
|
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Data_Length
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Data_Block_Size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
|
||||||
|
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
|
||||||
|
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
|
||||||
|
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
|
||||||
|
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
|
||||||
|
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
|
||||||
|
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
|
||||||
|
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
|
||||||
|
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
|
||||||
|
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
|
||||||
|
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
|
||||||
|
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
|
||||||
|
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
|
||||||
|
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_2b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_4b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_8b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_16b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_32b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_64b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_128b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_256b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_512b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_1024b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_2048b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_4096b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_8192b) || \
|
||||||
|
((SIZE) == SDIO_DataBlockSize_16384b))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Transfer_Direction
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
|
||||||
|
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
|
||||||
|
((DIR) == SDIO_TransferDir_ToSDIO))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Transfer_Type
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
|
||||||
|
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
|
||||||
|
((MODE) == SDIO_TransferMode_Block))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_DPSM_State
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
|
||||||
|
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Flags
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
|
||||||
|
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
|
||||||
|
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
|
||||||
|
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
|
||||||
|
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
|
||||||
|
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
|
||||||
|
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
|
||||||
|
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
|
||||||
|
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
|
||||||
|
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
|
||||||
|
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
|
||||||
|
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
|
||||||
|
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
|
||||||
|
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
|
||||||
|
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
|
||||||
|
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
|
||||||
|
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
|
||||||
|
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
|
||||||
|
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
|
||||||
|
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
|
||||||
|
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
|
||||||
|
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
|
||||||
|
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
|
||||||
|
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
|
||||||
|
((FLAG) == SDIO_FLAG_TXUNDERR) || \
|
||||||
|
((FLAG) == SDIO_FLAG_RXOVERR) || \
|
||||||
|
((FLAG) == SDIO_FLAG_CMDREND) || \
|
||||||
|
((FLAG) == SDIO_FLAG_CMDSENT) || \
|
||||||
|
((FLAG) == SDIO_FLAG_DATAEND) || \
|
||||||
|
((FLAG) == SDIO_FLAG_STBITERR) || \
|
||||||
|
((FLAG) == SDIO_FLAG_DBCKEND) || \
|
||||||
|
((FLAG) == SDIO_FLAG_CMDACT) || \
|
||||||
|
((FLAG) == SDIO_FLAG_TXACT) || \
|
||||||
|
((FLAG) == SDIO_FLAG_RXACT) || \
|
||||||
|
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
|
||||||
|
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
|
||||||
|
((FLAG) == SDIO_FLAG_TXFIFOF) || \
|
||||||
|
((FLAG) == SDIO_FLAG_RXFIFOF) || \
|
||||||
|
((FLAG) == SDIO_FLAG_TXFIFOE) || \
|
||||||
|
((FLAG) == SDIO_FLAG_RXFIFOE) || \
|
||||||
|
((FLAG) == SDIO_FLAG_TXDAVL) || \
|
||||||
|
((FLAG) == SDIO_FLAG_RXDAVL) || \
|
||||||
|
((FLAG) == SDIO_FLAG_SDIOIT) || \
|
||||||
|
((FLAG) == SDIO_FLAG_CEATAEND))
|
||||||
|
|
||||||
|
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
|
||||||
|
|
||||||
|
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
|
||||||
|
((IT) == SDIO_IT_DCRCFAIL) || \
|
||||||
|
((IT) == SDIO_IT_CTIMEOUT) || \
|
||||||
|
((IT) == SDIO_IT_DTIMEOUT) || \
|
||||||
|
((IT) == SDIO_IT_TXUNDERR) || \
|
||||||
|
((IT) == SDIO_IT_RXOVERR) || \
|
||||||
|
((IT) == SDIO_IT_CMDREND) || \
|
||||||
|
((IT) == SDIO_IT_CMDSENT) || \
|
||||||
|
((IT) == SDIO_IT_DATAEND) || \
|
||||||
|
((IT) == SDIO_IT_STBITERR) || \
|
||||||
|
((IT) == SDIO_IT_DBCKEND) || \
|
||||||
|
((IT) == SDIO_IT_CMDACT) || \
|
||||||
|
((IT) == SDIO_IT_TXACT) || \
|
||||||
|
((IT) == SDIO_IT_RXACT) || \
|
||||||
|
((IT) == SDIO_IT_TXFIFOHE) || \
|
||||||
|
((IT) == SDIO_IT_RXFIFOHF) || \
|
||||||
|
((IT) == SDIO_IT_TXFIFOF) || \
|
||||||
|
((IT) == SDIO_IT_RXFIFOF) || \
|
||||||
|
((IT) == SDIO_IT_TXFIFOE) || \
|
||||||
|
((IT) == SDIO_IT_RXFIFOE) || \
|
||||||
|
((IT) == SDIO_IT_TXDAVL) || \
|
||||||
|
((IT) == SDIO_IT_RXDAVL) || \
|
||||||
|
((IT) == SDIO_IT_SDIOIT) || \
|
||||||
|
((IT) == SDIO_IT_CEATAEND))
|
||||||
|
|
||||||
|
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Read_Wait_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
|
||||||
|
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
|
||||||
|
((MODE) == SDIO_ReadWaitMode_DATA2))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void SDIO_DeInit(void);
|
||||||
|
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||||
|
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||||
|
void SDIO_ClockCmd(FunctionalState NewState);
|
||||||
|
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
|
||||||
|
uint32_t SDIO_GetPowerState(void);
|
||||||
|
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
|
||||||
|
void SDIO_DMACmd(FunctionalState NewState);
|
||||||
|
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
|
||||||
|
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
|
||||||
|
uint8_t SDIO_GetCommandResponse(void);
|
||||||
|
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
|
||||||
|
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||||
|
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||||
|
uint32_t SDIO_GetDataCounter(void);
|
||||||
|
uint32_t SDIO_ReadData(void);
|
||||||
|
void SDIO_WriteData(uint32_t Data);
|
||||||
|
uint32_t SDIO_GetFIFOCount(void);
|
||||||
|
void SDIO_StartSDIOReadWait(FunctionalState NewState);
|
||||||
|
void SDIO_StopSDIOReadWait(FunctionalState NewState);
|
||||||
|
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
|
||||||
|
void SDIO_SetSDIOOperation(FunctionalState NewState);
|
||||||
|
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
|
||||||
|
void SDIO_CommandCompletionCmd(FunctionalState NewState);
|
||||||
|
void SDIO_CEATAITCmd(FunctionalState NewState);
|
||||||
|
void SDIO_SendCEATACmd(FunctionalState NewState);
|
||||||
|
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
|
||||||
|
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
|
||||||
|
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
|
||||||
|
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_SDIO_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,487 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_spi.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the SPI firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_SPI_H
|
||||||
|
#define __STM32F10x_SPI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SPI Init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||||
|
This parameter can be a value of @ref SPI_data_direction */
|
||||||
|
|
||||||
|
uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
|
||||||
|
This parameter can be a value of @ref SPI_mode */
|
||||||
|
|
||||||
|
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
|
||||||
|
This parameter can be a value of @ref SPI_data_size */
|
||||||
|
|
||||||
|
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
|
||||||
|
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||||
|
|
||||||
|
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
|
||||||
|
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||||
|
|
||||||
|
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
|
||||||
|
hardware (NSS pin) or by software using the SSI bit.
|
||||||
|
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||||
|
|
||||||
|
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||||
|
used to configure the transmit and receive SCK clock.
|
||||||
|
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
|
||||||
|
@note The communication clock is derived from the master
|
||||||
|
clock. The slave clock does not need to be set. */
|
||||||
|
|
||||||
|
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||||
|
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||||
|
|
||||||
|
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
|
||||||
|
}SPI_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief I2S Init structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
|
||||||
|
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
|
||||||
|
This parameter can be a value of @ref I2S_Mode */
|
||||||
|
|
||||||
|
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Standard */
|
||||||
|
|
||||||
|
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Data_Format */
|
||||||
|
|
||||||
|
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||||
|
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||||
|
|
||||||
|
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||||
|
|
||||||
|
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||||
|
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||||
|
}I2S_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
|
||||||
|
((PERIPH) == SPI2) || \
|
||||||
|
((PERIPH) == SPI3))
|
||||||
|
|
||||||
|
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
|
||||||
|
((PERIPH) == SPI3))
|
||||||
|
|
||||||
|
/** @defgroup SPI_data_direction
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||||
|
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||||
|
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||||
|
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||||
|
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
|
||||||
|
((MODE) == SPI_Direction_2Lines_RxOnly) || \
|
||||||
|
((MODE) == SPI_Direction_1Line_Rx) || \
|
||||||
|
((MODE) == SPI_Direction_1Line_Tx))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||||
|
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||||
|
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
|
||||||
|
((MODE) == SPI_Mode_Slave))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_data_size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_DataSize_16b ((uint16_t)0x0800)
|
||||||
|
#define SPI_DataSize_8b ((uint16_t)0x0000)
|
||||||
|
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
|
||||||
|
((DATASIZE) == SPI_DataSize_8b))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Clock_Polarity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||||
|
#define SPI_CPOL_High ((uint16_t)0x0002)
|
||||||
|
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
|
||||||
|
((CPOL) == SPI_CPOL_High))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Clock_Phase
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||||
|
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||||
|
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
|
||||||
|
((CPHA) == SPI_CPHA_2Edge))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Slave_Select_management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||||
|
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||||
|
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
|
||||||
|
((NSS) == SPI_NSS_Hard))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_BaudRate_Prescaler
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||||
|
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||||
|
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||||
|
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||||
|
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||||
|
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||||
|
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||||
|
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||||
|
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
|
||||||
|
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
|
||||||
|
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
|
||||||
|
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
|
||||||
|
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
|
||||||
|
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
|
||||||
|
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
|
||||||
|
((PRESCALER) == SPI_BaudRatePrescaler_256))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_MSB_LSB_transmission
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||||
|
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
|
||||||
|
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
|
||||||
|
((BIT) == SPI_FirstBit_LSB))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||||
|
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||||
|
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||||
|
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||||
|
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
|
||||||
|
((MODE) == I2S_Mode_SlaveRx) || \
|
||||||
|
((MODE) == I2S_Mode_MasterTx) || \
|
||||||
|
((MODE) == I2S_Mode_MasterRx) )
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Standard
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||||
|
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||||
|
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||||
|
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||||
|
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||||
|
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
|
||||||
|
((STANDARD) == I2S_Standard_MSB) || \
|
||||||
|
((STANDARD) == I2S_Standard_LSB) || \
|
||||||
|
((STANDARD) == I2S_Standard_PCMShort) || \
|
||||||
|
((STANDARD) == I2S_Standard_PCMLong))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Data_Format
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||||
|
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||||
|
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||||
|
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||||
|
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
|
||||||
|
((FORMAT) == I2S_DataFormat_16bextended) || \
|
||||||
|
((FORMAT) == I2S_DataFormat_24b) || \
|
||||||
|
((FORMAT) == I2S_DataFormat_32b))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_MCLK_Output
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
|
||||||
|
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||||
|
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
|
||||||
|
((OUTPUT) == I2S_MCLKOutput_Disable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Audio_Frequency
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||||
|
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||||
|
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||||
|
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||||
|
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||||
|
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||||
|
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||||
|
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||||
|
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||||
|
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||||
|
|
||||||
|
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
|
||||||
|
((FREQ) <= I2S_AudioFreq_192k)) || \
|
||||||
|
((FREQ) == I2S_AudioFreq_Default))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup I2S_Clock_Polarity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||||
|
#define I2S_CPOL_High ((uint16_t)0x0008)
|
||||||
|
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
|
||||||
|
((CPOL) == I2S_CPOL_High))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_I2S_DMA_transfer_requests
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||||
|
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||||
|
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_NSS_internal_software_management
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||||
|
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||||
|
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
|
||||||
|
((INTERNAL) == SPI_NSSInternalSoft_Reset))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_CRC_Transmit_Receive
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||||
|
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||||
|
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_direction_transmit_receive
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||||
|
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||||
|
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
|
||||||
|
((DIRECTION) == SPI_Direction_Tx))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_I2S_interrupts_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||||
|
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||||
|
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||||
|
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
|
||||||
|
((IT) == SPI_I2S_IT_RXNE) || \
|
||||||
|
((IT) == SPI_I2S_IT_ERR))
|
||||||
|
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||||
|
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||||
|
#define SPI_IT_CRCERR ((uint8_t)0x54)
|
||||||
|
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||||
|
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
|
||||||
|
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
|
||||||
|
((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
|
||||||
|
((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_I2S_flags_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||||
|
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||||
|
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
|
||||||
|
#define I2S_FLAG_UDR ((uint16_t)0x0008)
|
||||||
|
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||||
|
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||||
|
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||||
|
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||||
|
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
|
||||||
|
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
|
||||||
|
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
|
||||||
|
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
|
||||||
|
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_CRC_polynomial
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||||
|
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||||
|
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||||
|
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||||
|
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||||
|
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||||
|
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
|
||||||
|
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||||
|
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||||
|
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||||
|
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||||
|
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||||
|
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||||
|
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||||
|
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__STM32F10x_SPI_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,412 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_usart.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the USART
|
||||||
|
* firmware library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_USART_H
|
||||||
|
#define __STM32F10x_USART_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USART
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief USART Init Structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
|
||||||
|
The baud rate is computed using the following formula:
|
||||||
|
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||||
|
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
|
||||||
|
|
||||||
|
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||||
|
This parameter can be a value of @ref USART_Word_Length */
|
||||||
|
|
||||||
|
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||||
|
This parameter can be a value of @ref USART_Stop_Bits */
|
||||||
|
|
||||||
|
uint16_t USART_Parity; /*!< Specifies the parity mode.
|
||||||
|
This parameter can be a value of @ref USART_Parity
|
||||||
|
@note When parity is enabled, the computed parity is inserted
|
||||||
|
at the MSB position of the transmitted data (9th bit when
|
||||||
|
the word length is set to 9 data bits; 8th bit when the
|
||||||
|
word length is set to 8 data bits). */
|
||||||
|
|
||||||
|
uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref USART_Mode */
|
||||||
|
|
||||||
|
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
|
||||||
|
or disabled.
|
||||||
|
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||||
|
} USART_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief USART Clock Init Structure definition
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
|
||||||
|
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref USART_Clock */
|
||||||
|
|
||||||
|
uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
|
||||||
|
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||||
|
|
||||||
|
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
|
||||||
|
This parameter can be a value of @ref USART_Clock_Phase */
|
||||||
|
|
||||||
|
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||||
|
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||||
|
This parameter can be a value of @ref USART_Last_Bit */
|
||||||
|
} USART_ClockInitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||||
|
((PERIPH) == USART2) || \
|
||||||
|
((PERIPH) == USART3) || \
|
||||||
|
((PERIPH) == UART4) || \
|
||||||
|
((PERIPH) == UART5))
|
||||||
|
|
||||||
|
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||||
|
((PERIPH) == USART2) || \
|
||||||
|
((PERIPH) == USART3))
|
||||||
|
|
||||||
|
#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||||
|
((PERIPH) == USART2) || \
|
||||||
|
((PERIPH) == USART3) || \
|
||||||
|
((PERIPH) == UART4))
|
||||||
|
/** @defgroup USART_Word_Length
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_WordLength_8b ((uint16_t)0x0000)
|
||||||
|
#define USART_WordLength_9b ((uint16_t)0x1000)
|
||||||
|
|
||||||
|
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
|
||||||
|
((LENGTH) == USART_WordLength_9b))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Stop_Bits
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_StopBits_1 ((uint16_t)0x0000)
|
||||||
|
#define USART_StopBits_0_5 ((uint16_t)0x1000)
|
||||||
|
#define USART_StopBits_2 ((uint16_t)0x2000)
|
||||||
|
#define USART_StopBits_1_5 ((uint16_t)0x3000)
|
||||||
|
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
|
||||||
|
((STOPBITS) == USART_StopBits_0_5) || \
|
||||||
|
((STOPBITS) == USART_StopBits_2) || \
|
||||||
|
((STOPBITS) == USART_StopBits_1_5))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Parity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_Parity_No ((uint16_t)0x0000)
|
||||||
|
#define USART_Parity_Even ((uint16_t)0x0400)
|
||||||
|
#define USART_Parity_Odd ((uint16_t)0x0600)
|
||||||
|
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
|
||||||
|
((PARITY) == USART_Parity_Even) || \
|
||||||
|
((PARITY) == USART_Parity_Odd))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_Mode_Rx ((uint16_t)0x0004)
|
||||||
|
#define USART_Mode_Tx ((uint16_t)0x0008)
|
||||||
|
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Hardware_Flow_Control
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
|
||||||
|
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
|
||||||
|
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
|
||||||
|
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
|
||||||
|
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||||
|
(((CONTROL) == USART_HardwareFlowControl_None) || \
|
||||||
|
((CONTROL) == USART_HardwareFlowControl_RTS) || \
|
||||||
|
((CONTROL) == USART_HardwareFlowControl_CTS) || \
|
||||||
|
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Clock
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define USART_Clock_Disable ((uint16_t)0x0000)
|
||||||
|
#define USART_Clock_Enable ((uint16_t)0x0800)
|
||||||
|
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
|
||||||
|
((CLOCK) == USART_Clock_Enable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Clock_Polarity
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_CPOL_Low ((uint16_t)0x0000)
|
||||||
|
#define USART_CPOL_High ((uint16_t)0x0400)
|
||||||
|
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Clock_Phase
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_CPHA_1Edge ((uint16_t)0x0000)
|
||||||
|
#define USART_CPHA_2Edge ((uint16_t)0x0200)
|
||||||
|
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Last_Bit
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_LastBit_Disable ((uint16_t)0x0000)
|
||||||
|
#define USART_LastBit_Enable ((uint16_t)0x0100)
|
||||||
|
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||||
|
((LASTBIT) == USART_LastBit_Enable))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Interrupt_definition
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_IT_PE ((uint16_t)0x0028)
|
||||||
|
#define USART_IT_TXE ((uint16_t)0x0727)
|
||||||
|
#define USART_IT_TC ((uint16_t)0x0626)
|
||||||
|
#define USART_IT_RXNE ((uint16_t)0x0525)
|
||||||
|
#define USART_IT_IDLE ((uint16_t)0x0424)
|
||||||
|
#define USART_IT_LBD ((uint16_t)0x0846)
|
||||||
|
#define USART_IT_CTS ((uint16_t)0x096A)
|
||||||
|
#define USART_IT_ERR ((uint16_t)0x0060)
|
||||||
|
#define USART_IT_ORE ((uint16_t)0x0360)
|
||||||
|
#define USART_IT_NE ((uint16_t)0x0260)
|
||||||
|
#define USART_IT_FE ((uint16_t)0x0160)
|
||||||
|
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||||
|
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||||
|
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||||
|
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
|
||||||
|
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||||
|
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||||
|
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||||
|
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
|
||||||
|
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
|
||||||
|
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||||
|
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_DMA_Requests
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_DMAReq_Tx ((uint16_t)0x0080)
|
||||||
|
#define USART_DMAReq_Rx ((uint16_t)0x0040)
|
||||||
|
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_WakeUp_methods
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
|
||||||
|
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
|
||||||
|
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
|
||||||
|
((WAKEUP) == USART_WakeUp_AddressMark))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_LIN_Break_Detection_Length
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
|
||||||
|
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
|
||||||
|
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
|
||||||
|
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
|
||||||
|
((LENGTH) == USART_LINBreakDetectLength_11b))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_IrDA_Low_Power
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
|
||||||
|
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
|
||||||
|
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
|
||||||
|
((MODE) == USART_IrDAMode_Normal))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Flags
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USART_FLAG_CTS ((uint16_t)0x0200)
|
||||||
|
#define USART_FLAG_LBD ((uint16_t)0x0100)
|
||||||
|
#define USART_FLAG_TXE ((uint16_t)0x0080)
|
||||||
|
#define USART_FLAG_TC ((uint16_t)0x0040)
|
||||||
|
#define USART_FLAG_RXNE ((uint16_t)0x0020)
|
||||||
|
#define USART_FLAG_IDLE ((uint16_t)0x0010)
|
||||||
|
#define USART_FLAG_ORE ((uint16_t)0x0008)
|
||||||
|
#define USART_FLAG_NE ((uint16_t)0x0004)
|
||||||
|
#define USART_FLAG_FE ((uint16_t)0x0002)
|
||||||
|
#define USART_FLAG_PE ((uint16_t)0x0001)
|
||||||
|
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
|
||||||
|
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
|
||||||
|
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
|
||||||
|
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
|
||||||
|
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
|
||||||
|
|
||||||
|
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||||
|
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
|
||||||
|
((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
|
||||||
|
|| ((USART_FLAG) != USART_FLAG_CTS))
|
||||||
|
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
|
||||||
|
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
|
||||||
|
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup USART_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void USART_DeInit(USART_TypeDef* USARTx);
|
||||||
|
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||||
|
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||||
|
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||||
|
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||||
|
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
|
||||||
|
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
|
||||||
|
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||||
|
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
|
||||||
|
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
|
||||||
|
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||||
|
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||||
|
void USART_SendBreak(USART_TypeDef* USARTx);
|
||||||
|
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||||
|
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||||
|
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
|
||||||
|
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||||
|
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||||
|
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||||
|
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_USART_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,115 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_wwdg.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file contains all the functions prototypes for the WWDG firmware
|
||||||
|
* library.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32F10x_WWDG_H
|
||||||
|
#define __STM32F10x_WWDG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WWDG
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Exported_Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Prescaler
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||||
|
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||||
|
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||||
|
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||||
|
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
|
||||||
|
((PRESCALER) == WWDG_Prescaler_2) || \
|
||||||
|
((PRESCALER) == WWDG_Prescaler_4) || \
|
||||||
|
((PRESCALER) == WWDG_Prescaler_8))
|
||||||
|
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||||
|
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
void WWDG_DeInit(void);
|
||||||
|
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||||
|
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||||
|
void WWDG_EnableIT(void);
|
||||||
|
void WWDG_SetCounter(uint8_t Counter);
|
||||||
|
void WWDG_Enable(uint8_t Counter);
|
||||||
|
FlagStatus WWDG_GetFlagStatus(void);
|
||||||
|
void WWDG_ClearFlag(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32F10x_WWDG_H */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,225 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file misc.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||||
|
* to CMSIS functions).
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "misc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC
|
||||||
|
* @brief MISC driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup MISC_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the priority grouping: pre-emption priority and subpriority.
|
||||||
|
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
|
||||||
|
* 4 bits for subpriority
|
||||||
|
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
|
||||||
|
* 3 bits for subpriority
|
||||||
|
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
|
||||||
|
* 2 bits for subpriority
|
||||||
|
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
|
||||||
|
* 1 bits for subpriority
|
||||||
|
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
|
||||||
|
* 0 bits for subpriority
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
||||||
|
|
||||||
|
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
||||||
|
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the NVIC peripheral according to the specified
|
||||||
|
* parameters in the NVIC_InitStruct.
|
||||||
|
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
||||||
|
* the configuration information for the specified NVIC peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||||
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
||||||
|
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
||||||
|
|
||||||
|
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||||
|
{
|
||||||
|
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||||
|
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
|
||||||
|
tmppre = (0x4 - tmppriority);
|
||||||
|
tmpsub = tmpsub >> tmppriority;
|
||||||
|
|
||||||
|
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
||||||
|
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
|
||||||
|
tmppriority = tmppriority << 0x04;
|
||||||
|
|
||||||
|
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
||||||
|
|
||||||
|
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||||
|
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||||
|
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||||
|
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||||
|
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the vector table location and Offset.
|
||||||
|
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg NVIC_VectTab_RAM
|
||||||
|
* @arg NVIC_VectTab_FLASH
|
||||||
|
* @param Offset: Vector Table base offset field. This value must be a multiple
|
||||||
|
* of 0x200.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
||||||
|
assert_param(IS_NVIC_OFFSET(Offset));
|
||||||
|
|
||||||
|
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Selects the condition for the system to enter low power mode.
|
||||||
|
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg NVIC_LP_SEVONPEND
|
||||||
|
* @arg NVIC_LP_SLEEPDEEP
|
||||||
|
* @arg NVIC_LP_SLEEPONEXIT
|
||||||
|
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SCB->SCR |= LowPowerMode;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the SysTick clock source.
|
||||||
|
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
||||||
|
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||||
|
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||||
|
{
|
||||||
|
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,308 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_bkp.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the BKP firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_bkp.h"
|
||||||
|
#include "stm32f10x_rcc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup BKP
|
||||||
|
* @brief BKP driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup BKP_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup BKP_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ------------ BKP registers bit address in the alias region --------------- */
|
||||||
|
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
|
||||||
|
|
||||||
|
/* --- CR Register ----*/
|
||||||
|
|
||||||
|
/* Alias word address of TPAL bit */
|
||||||
|
#define CR_OFFSET (BKP_OFFSET + 0x30)
|
||||||
|
#define TPAL_BitNumber 0x01
|
||||||
|
#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of TPE bit */
|
||||||
|
#define TPE_BitNumber 0x00
|
||||||
|
#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
|
||||||
|
|
||||||
|
/* --- CSR Register ---*/
|
||||||
|
|
||||||
|
/* Alias word address of TPIE bit */
|
||||||
|
#define CSR_OFFSET (BKP_OFFSET + 0x34)
|
||||||
|
#define TPIE_BitNumber 0x02
|
||||||
|
#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of TIF bit */
|
||||||
|
#define TIF_BitNumber 0x09
|
||||||
|
#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of TEF bit */
|
||||||
|
#define TEF_BitNumber 0x08
|
||||||
|
#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
|
||||||
|
|
||||||
|
/* ---------------------- BKP registers bit mask ------------------------ */
|
||||||
|
|
||||||
|
/* RTCCR register bit mask */
|
||||||
|
#define RTCCR_CAL_MASK ((uint16_t)0xFF80)
|
||||||
|
#define RTCCR_MASK ((uint16_t)0xFC7F)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup BKP_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup BKP_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup BKP_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup BKP_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the BKP peripheral registers to their default reset values.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void BKP_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC_BackupResetCmd(ENABLE);
|
||||||
|
RCC_BackupResetCmd(DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the Tamper Pin active level.
|
||||||
|
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg BKP_TamperPinLevel_High: Tamper pin active on high level
|
||||||
|
* @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
|
||||||
|
*(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the Tamper Pin activation.
|
||||||
|
* @param NewState: new state of the Tamper Pin activation.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void BKP_TamperPinCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
*(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the Tamper Pin Interrupt.
|
||||||
|
* @param NewState: new state of the Tamper Pin Interrupt.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void BKP_ITConfig(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
*(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Select the RTC output source to output on the Tamper pin.
|
||||||
|
* @param BKP_RTCOutputSource: specifies the RTC output source.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
|
||||||
|
* @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
|
||||||
|
* divided by 64 on the Tamper pin.
|
||||||
|
* @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
|
||||||
|
* the Tamper pin.
|
||||||
|
* @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
|
||||||
|
* the Tamper pin.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
|
||||||
|
tmpreg = BKP->RTCCR;
|
||||||
|
/* Clear CCO, ASOE and ASOS bits */
|
||||||
|
tmpreg &= RTCCR_MASK;
|
||||||
|
|
||||||
|
/* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
|
||||||
|
tmpreg |= BKP_RTCOutputSource;
|
||||||
|
/* Store the new value */
|
||||||
|
BKP->RTCCR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets RTC Clock Calibration value.
|
||||||
|
* @param CalibrationValue: specifies the RTC Clock Calibration value.
|
||||||
|
* This parameter must be a number between 0 and 0x7F.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
|
||||||
|
tmpreg = BKP->RTCCR;
|
||||||
|
/* Clear CAL[6:0] bits */
|
||||||
|
tmpreg &= RTCCR_CAL_MASK;
|
||||||
|
/* Set CAL[6:0] bits according to CalibrationValue value */
|
||||||
|
tmpreg |= CalibrationValue;
|
||||||
|
/* Store the new value */
|
||||||
|
BKP->RTCCR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes user data to the specified Data Backup Register.
|
||||||
|
* @param BKP_DR: specifies the Data Backup Register.
|
||||||
|
* This parameter can be BKP_DRx where x:[1, 42]
|
||||||
|
* @param Data: data to write
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_BKP_DR(BKP_DR));
|
||||||
|
|
||||||
|
tmp = (uint32_t)BKP_BASE;
|
||||||
|
tmp += BKP_DR;
|
||||||
|
|
||||||
|
*(__IO uint32_t *) tmp = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads data from the specified Data Backup Register.
|
||||||
|
* @param BKP_DR: specifies the Data Backup Register.
|
||||||
|
* This parameter can be BKP_DRx where x:[1, 42]
|
||||||
|
* @retval The content of the specified Data Backup Register
|
||||||
|
*/
|
||||||
|
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_BKP_DR(BKP_DR));
|
||||||
|
|
||||||
|
tmp = (uint32_t)BKP_BASE;
|
||||||
|
tmp += BKP_DR;
|
||||||
|
|
||||||
|
return (*(__IO uint16_t *) tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the Tamper Pin Event flag is set or not.
|
||||||
|
* @param None
|
||||||
|
* @retval The new state of the Tamper Pin Event flag (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus BKP_GetFlagStatus(void)
|
||||||
|
{
|
||||||
|
return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears Tamper Pin Event pending flag.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void BKP_ClearFlag(void)
|
||||||
|
{
|
||||||
|
/* Set CTE bit to clear Tamper Pin Event flag */
|
||||||
|
BKP->CSR |= BKP_CSR_CTE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
|
||||||
|
* @param None
|
||||||
|
* @retval The new state of the Tamper Pin Interrupt (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus BKP_GetITStatus(void)
|
||||||
|
{
|
||||||
|
return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears Tamper Pin Interrupt pending bit.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void BKP_ClearITPendingBit(void)
|
||||||
|
{
|
||||||
|
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
|
||||||
|
BKP->CSR |= BKP_CSR_CTI;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,433 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_cec.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the CEC firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_cec.h"
|
||||||
|
#include "stm32f10x_rcc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC
|
||||||
|
* @brief CEC driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CEC_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup CEC_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ------------ CEC registers bit address in the alias region ----------- */
|
||||||
|
#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
|
||||||
|
|
||||||
|
/* --- CFGR Register ---*/
|
||||||
|
|
||||||
|
/* Alias word address of PE bit */
|
||||||
|
#define CFGR_OFFSET (CEC_OFFSET + 0x00)
|
||||||
|
#define PE_BitNumber 0x00
|
||||||
|
#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of IE bit */
|
||||||
|
#define IE_BitNumber 0x01
|
||||||
|
#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
|
||||||
|
|
||||||
|
/* --- CSR Register ---*/
|
||||||
|
|
||||||
|
/* Alias word address of TSOM bit */
|
||||||
|
#define CSR_OFFSET (CEC_OFFSET + 0x10)
|
||||||
|
#define TSOM_BitNumber 0x00
|
||||||
|
#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of TEOM bit */
|
||||||
|
#define TEOM_BitNumber 0x01
|
||||||
|
#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
|
||||||
|
|
||||||
|
#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
|
||||||
|
#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup CEC_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup CEC_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup CEC_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup CEC_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the CEC peripheral registers to their default reset
|
||||||
|
* values.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_DeInit(void)
|
||||||
|
{
|
||||||
|
/* Enable CEC reset state */
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
|
||||||
|
/* Release CEC from reset state */
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the CEC peripheral according to the specified
|
||||||
|
* parameters in the CEC_InitStruct.
|
||||||
|
* @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified
|
||||||
|
* CEC peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
|
||||||
|
assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
|
||||||
|
|
||||||
|
/*---------------------------- CEC CFGR Configuration -----------------*/
|
||||||
|
/* Get the CEC CFGR value */
|
||||||
|
tmpreg = CEC->CFGR;
|
||||||
|
|
||||||
|
/* Clear BTEM and BPEM bits */
|
||||||
|
tmpreg &= CFGR_CLEAR_Mask;
|
||||||
|
|
||||||
|
/* Configure CEC: Bit Timing Error and Bit Period Error */
|
||||||
|
tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
|
||||||
|
|
||||||
|
/* Write to CEC CFGR register*/
|
||||||
|
CEC->CFGR = tmpreg;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified CEC peripheral.
|
||||||
|
* @param NewState: new state of the CEC peripheral.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_Cmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
|
||||||
|
|
||||||
|
if(NewState == DISABLE)
|
||||||
|
{
|
||||||
|
/* Wait until the PE bit is cleared by hardware (Idle Line detected) */
|
||||||
|
while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the CEC interrupt.
|
||||||
|
* @param NewState: new state of the CEC interrupt.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_ITConfig(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Defines the Own Address of the CEC device.
|
||||||
|
* @param CEC_OwnAddress: The CEC own address
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
|
||||||
|
|
||||||
|
/* Set the CEC own address */
|
||||||
|
CEC->OAR = CEC_OwnAddress;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the CEC prescaler value.
|
||||||
|
* @param CEC_Prescaler: CEC prescaler new value
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_SetPrescaler(uint16_t CEC_Prescaler)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
|
||||||
|
|
||||||
|
/* Set the Prescaler value*/
|
||||||
|
CEC->PRES = CEC_Prescaler;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Transmits single data through the CEC peripheral.
|
||||||
|
* @param Data: the data to transmit.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_SendDataByte(uint8_t Data)
|
||||||
|
{
|
||||||
|
/* Transmit Data */
|
||||||
|
CEC->TXD = Data ;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the most recent received data by the CEC peripheral.
|
||||||
|
* @param None
|
||||||
|
* @retval The received data.
|
||||||
|
*/
|
||||||
|
uint8_t CEC_ReceiveDataByte(void)
|
||||||
|
{
|
||||||
|
/* Receive Data */
|
||||||
|
return (uint8_t)(CEC->RXD);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Starts a new message.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_StartOfMessage(void)
|
||||||
|
{
|
||||||
|
/* Starts of new message */
|
||||||
|
*(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Transmits message with or without an EOM bit.
|
||||||
|
* @param NewState: new state of the CEC Tx End Of Message.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_EndOfMessageCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
/* The data byte will be transmitted with or without an EOM bit*/
|
||||||
|
*(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Gets the CEC flag status
|
||||||
|
* @param CEC_FLAG: specifies the CEC flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg CEC_FLAG_BTE: Bit Timing Error
|
||||||
|
* @arg CEC_FLAG_BPE: Bit Period Error
|
||||||
|
* @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
|
||||||
|
* @arg CEC_FLAG_SBE: Start Bit Error
|
||||||
|
* @arg CEC_FLAG_ACKE: Block Acknowledge Error
|
||||||
|
* @arg CEC_FLAG_LINE: Line Error
|
||||||
|
* @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
|
||||||
|
* @arg CEC_FLAG_TEOM: Tx End Of Message
|
||||||
|
* @arg CEC_FLAG_TERR: Tx Error
|
||||||
|
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
|
||||||
|
* @arg CEC_FLAG_RSOM: Rx Start Of Message
|
||||||
|
* @arg CEC_FLAG_REOM: Rx End Of Message
|
||||||
|
* @arg CEC_FLAG_RERR: Rx Error
|
||||||
|
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
|
||||||
|
* @retval The new state of CEC_FLAG (SET or RESET)
|
||||||
|
*/
|
||||||
|
FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
uint32_t cecreg = 0, cecbase = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
|
||||||
|
|
||||||
|
/* Get the CEC peripheral base address */
|
||||||
|
cecbase = (uint32_t)(CEC_BASE);
|
||||||
|
|
||||||
|
/* Read flag register index */
|
||||||
|
cecreg = CEC_FLAG >> 28;
|
||||||
|
|
||||||
|
/* Get bit[23:0] of the flag */
|
||||||
|
CEC_FLAG &= FLAG_Mask;
|
||||||
|
|
||||||
|
if(cecreg != 0)
|
||||||
|
{
|
||||||
|
/* Flag in CEC ESR Register */
|
||||||
|
CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
|
||||||
|
|
||||||
|
/* Get the CEC ESR register address */
|
||||||
|
cecbase += 0xC;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Get the CEC CSR register address */
|
||||||
|
cecbase += 0x10;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
/* CEC_FLAG is set */
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* CEC_FLAG is reset */
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return the CEC_FLAG status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the CEC's pending flags.
|
||||||
|
* @param CEC_FLAG: specifies the flag to clear.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg CEC_FLAG_TERR: Tx Error
|
||||||
|
* @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
|
||||||
|
* @arg CEC_FLAG_RSOM: Rx Start Of Message
|
||||||
|
* @arg CEC_FLAG_REOM: Rx End Of Message
|
||||||
|
* @arg CEC_FLAG_RERR: Rx Error
|
||||||
|
* @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_ClearFlag(uint32_t CEC_FLAG)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
|
||||||
|
|
||||||
|
tmp = CEC->CSR & 0x2;
|
||||||
|
|
||||||
|
/* Clear the selected CEC flags */
|
||||||
|
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified CEC interrupt has occurred or not.
|
||||||
|
* @param CEC_IT: specifies the CEC interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg CEC_IT_TERR: Tx Error
|
||||||
|
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
|
||||||
|
* @arg CEC_IT_RERR: Rx Error
|
||||||
|
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
|
||||||
|
* @retval The new state of CEC_IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus CEC_GetITStatus(uint8_t CEC_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint32_t enablestatus = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CEC_GET_IT(CEC_IT));
|
||||||
|
|
||||||
|
/* Get the CEC IT enable bit status */
|
||||||
|
enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
|
||||||
|
|
||||||
|
/* Check the status of the specified CEC interrupt */
|
||||||
|
if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
|
||||||
|
{
|
||||||
|
/* CEC_IT is set */
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* CEC_IT is reset */
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
/* Return the CEC_IT status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the CEC's interrupt pending bits.
|
||||||
|
* @param CEC_IT: specifies the CEC interrupt pending bit to clear.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg CEC_IT_TERR: Tx Error
|
||||||
|
* @arg CEC_IT_TBTF: Tx Block Transfer Finished
|
||||||
|
* @arg CEC_IT_RERR: Rx Error
|
||||||
|
* @arg CEC_IT_RBTF: Rx Block Transfer Finished
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CEC_ClearITPendingBit(uint16_t CEC_IT)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_CEC_GET_IT(CEC_IT));
|
||||||
|
|
||||||
|
tmp = CEC->CSR & 0x2;
|
||||||
|
|
||||||
|
/* Clear the selected CEC interrupt pending bits */
|
||||||
|
CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,160 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_crc.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the CRC firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_crc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC
|
||||||
|
* @brief CRC driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CRC_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Resets the CRC Data register (DR).
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CRC_ResetDR(void)
|
||||||
|
{
|
||||||
|
/* Reset CRC generator */
|
||||||
|
CRC->CR = CRC_CR_RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||||
|
* @param Data: data word(32-bit) to compute its CRC
|
||||||
|
* @retval 32-bit CRC
|
||||||
|
*/
|
||||||
|
uint32_t CRC_CalcCRC(uint32_t Data)
|
||||||
|
{
|
||||||
|
CRC->DR = Data;
|
||||||
|
|
||||||
|
return (CRC->DR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||||
|
* @param pBuffer: pointer to the buffer containing the data to be computed
|
||||||
|
* @param BufferLength: length of the buffer to be computed
|
||||||
|
* @retval 32-bit CRC
|
||||||
|
*/
|
||||||
|
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
|
||||||
|
{
|
||||||
|
uint32_t index = 0;
|
||||||
|
|
||||||
|
for(index = 0; index < BufferLength; index++)
|
||||||
|
{
|
||||||
|
CRC->DR = pBuffer[index];
|
||||||
|
}
|
||||||
|
return (CRC->DR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the current CRC value.
|
||||||
|
* @param None
|
||||||
|
* @retval 32-bit CRC
|
||||||
|
*/
|
||||||
|
uint32_t CRC_GetCRC(void)
|
||||||
|
{
|
||||||
|
return (CRC->DR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||||
|
* @param IDValue: 8-bit value to be stored in the ID register
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void CRC_SetIDRegister(uint8_t IDValue)
|
||||||
|
{
|
||||||
|
CRC->IDR = IDValue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
|
||||||
|
* @param None
|
||||||
|
* @retval 8-bit value of the ID register
|
||||||
|
*/
|
||||||
|
uint8_t CRC_GetIDRegister(void)
|
||||||
|
{
|
||||||
|
return (CRC->IDR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,571 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_dac.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the DAC firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_dac.h"
|
||||||
|
#include "stm32f10x_rcc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC
|
||||||
|
* @brief DAC driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* CR register Mask */
|
||||||
|
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
|
||||||
|
|
||||||
|
/* DAC Dual Channels SWTRIG masks */
|
||||||
|
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
|
||||||
|
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
|
||||||
|
|
||||||
|
/* DHR registers offsets */
|
||||||
|
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
||||||
|
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
|
||||||
|
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
|
||||||
|
|
||||||
|
/* DOR register offset */
|
||||||
|
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DAC_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_DeInit(void)
|
||||||
|
{
|
||||||
|
/* Enable DAC reset state */
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
|
||||||
|
/* Release DAC from reset state */
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the DAC peripheral according to the specified
|
||||||
|
* parameters in the DAC_InitStruct.
|
||||||
|
* @param DAC_Channel: the selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified DAC channel.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||||
|
/* Check the DAC parameters */
|
||||||
|
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
|
||||||
|
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
|
||||||
|
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
|
||||||
|
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
|
||||||
|
/*---------------------------- DAC CR Configuration --------------------------*/
|
||||||
|
/* Get the DAC CR value */
|
||||||
|
tmpreg1 = DAC->CR;
|
||||||
|
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||||
|
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
|
||||||
|
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
|
||||||
|
mask/amplitude for wave generation */
|
||||||
|
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||||
|
/* Set WAVEx bits according to DAC_WaveGeneration value */
|
||||||
|
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
|
||||||
|
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||||
|
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
|
||||||
|
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
|
||||||
|
/* Calculate CR register value depending on DAC_Channel */
|
||||||
|
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||||
|
/* Write to DAC CR */
|
||||||
|
DAC->CR = tmpreg1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each DAC_InitStruct member with its default value.
|
||||||
|
* @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
|
||||||
|
* be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
|
||||||
|
{
|
||||||
|
/*--------------- Reset DAC init structure parameters values -----------------*/
|
||||||
|
/* Initialize the DAC_Trigger member */
|
||||||
|
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
||||||
|
/* Initialize the DAC_WaveGeneration member */
|
||||||
|
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
||||||
|
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
|
||||||
|
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
|
||||||
|
/* Initialize the DAC_OutputBuffer member */
|
||||||
|
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified DAC channel.
|
||||||
|
* @param DAC_Channel: the selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @param NewState: new state of the DAC channel.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected DAC channel */
|
||||||
|
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected DAC channel */
|
||||||
|
DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified DAC interrupts.
|
||||||
|
* @param DAC_Channel: the selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
|
||||||
|
* This parameter can be the following values:
|
||||||
|
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||||
|
* @param NewState: new state of the specified DAC interrupts.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
assert_param(IS_DAC_IT(DAC_IT));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected DAC interrupts */
|
||||||
|
DAC->CR |= (DAC_IT << DAC_Channel);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected DAC interrupts */
|
||||||
|
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified DAC channel DMA request.
|
||||||
|
* @param DAC_Channel: the selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @param NewState: new state of the selected DAC channel DMA request.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected DAC channel DMA request */
|
||||||
|
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected DAC channel DMA request */
|
||||||
|
DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the selected DAC channel software trigger.
|
||||||
|
* @param DAC_Channel: the selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @param NewState: new state of the selected DAC channel software trigger.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable software trigger for the selected DAC channel */
|
||||||
|
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable software trigger for the selected DAC channel */
|
||||||
|
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables simultaneously the two DAC channels software
|
||||||
|
* triggers.
|
||||||
|
* @param NewState: new state of the DAC channels software triggers.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable software trigger for both DAC channels */
|
||||||
|
DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable software trigger for both DAC channels */
|
||||||
|
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the selected DAC channel wave generation.
|
||||||
|
* @param DAC_Channel: the selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @param DAC_Wave: Specifies the wave type to enable or disable.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Wave_Noise: noise wave generation
|
||||||
|
* @arg DAC_Wave_Triangle: triangle wave generation
|
||||||
|
* @param NewState: new state of the selected DAC channel wave generation.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||||
|
assert_param(IS_DAC_WAVE(DAC_Wave));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected wave generation for the selected DAC channel */
|
||||||
|
DAC->CR |= DAC_Wave << DAC_Channel;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected wave generation for the selected DAC channel */
|
||||||
|
DAC->CR &= ~(DAC_Wave << DAC_Channel);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the specified data holding register value for DAC channel1.
|
||||||
|
* @param DAC_Align: Specifies the data alignment for DAC channel1.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||||
|
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||||
|
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||||
|
* @param Data : Data to be loaded in the selected data holding register.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||||
|
assert_param(IS_DAC_DATA(Data));
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DHR12R1_OFFSET + DAC_Align;
|
||||||
|
|
||||||
|
/* Set the DAC channel1 selected data holding register */
|
||||||
|
*(__IO uint32_t *) tmp = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the specified data holding register value for DAC channel2.
|
||||||
|
* @param DAC_Align: Specifies the data alignment for DAC channel2.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||||
|
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||||
|
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||||
|
* @param Data : Data to be loaded in the selected data holding register.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||||
|
assert_param(IS_DAC_DATA(Data));
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DHR12R2_OFFSET + DAC_Align;
|
||||||
|
|
||||||
|
/* Set the DAC channel2 selected data holding register */
|
||||||
|
*(__IO uint32_t *)tmp = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the specified data holding register value for dual channel
|
||||||
|
* DAC.
|
||||||
|
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||||
|
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||||
|
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||||
|
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
|
||||||
|
* holding register.
|
||||||
|
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
|
||||||
|
* holding register.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
||||||
|
{
|
||||||
|
uint32_t data = 0, tmp = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||||
|
assert_param(IS_DAC_DATA(Data1));
|
||||||
|
assert_param(IS_DAC_DATA(Data2));
|
||||||
|
|
||||||
|
/* Calculate and set dual DAC data holding register value */
|
||||||
|
if (DAC_Align == DAC_Align_8b_R)
|
||||||
|
{
|
||||||
|
data = ((uint32_t)Data2 << 8) | Data1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
data = ((uint32_t)Data2 << 16) | Data1;
|
||||||
|
}
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DHR12RD_OFFSET + DAC_Align;
|
||||||
|
|
||||||
|
/* Set the dual DAC selected data holding register */
|
||||||
|
*(__IO uint32_t *)tmp = data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the last data output value of the selected DAC channel.
|
||||||
|
* @param DAC_Channel: the selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @retval The selected DAC channel data output value.
|
||||||
|
*/
|
||||||
|
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||||
|
|
||||||
|
tmp = (uint32_t) DAC_BASE ;
|
||||||
|
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||||
|
|
||||||
|
/* Returns the DAC channel data output register value */
|
||||||
|
return (uint16_t) (*(__IO uint32_t*) tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified DAC flag is set or not.
|
||||||
|
* @param DAC_Channel: thee selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @param DAC_FLAG: specifies the flag to check.
|
||||||
|
* This parameter can be only of the following value:
|
||||||
|
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||||
|
* @retval The new state of DAC_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||||
|
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||||
|
|
||||||
|
/* Check the status of the specified DAC flag */
|
||||||
|
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
|
||||||
|
{
|
||||||
|
/* DAC_FLAG is set */
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* DAC_FLAG is reset */
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
/* Return the DAC_FLAG status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the DAC channelx's pending flags.
|
||||||
|
* @param DAC_Channel: the selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @param DAC_FLAG: specifies the flag to clear.
|
||||||
|
* This parameter can be of the following value:
|
||||||
|
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||||
|
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||||
|
|
||||||
|
/* Clear the selected DAC flags */
|
||||||
|
DAC->SR = (DAC_FLAG << DAC_Channel);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified DAC interrupt has occurred or not.
|
||||||
|
* @param DAC_Channel: the selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @param DAC_IT: specifies the DAC interrupt source to check.
|
||||||
|
* This parameter can be the following values:
|
||||||
|
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||||
|
* @retval The new state of DAC_IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint32_t enablestatus = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||||
|
assert_param(IS_DAC_IT(DAC_IT));
|
||||||
|
|
||||||
|
/* Get the DAC_IT enable bit status */
|
||||||
|
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
|
||||||
|
|
||||||
|
/* Check the status of the specified DAC interrupt */
|
||||||
|
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
|
||||||
|
{
|
||||||
|
/* DAC_IT is set */
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* DAC_IT is reset */
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
/* Return the DAC_IT status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the DAC channelx's interrupt pending bits.
|
||||||
|
* @param DAC_Channel: the selected DAC channel.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||||
|
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||||
|
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
|
||||||
|
* This parameter can be the following values:
|
||||||
|
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||||
|
assert_param(IS_DAC_IT(DAC_IT));
|
||||||
|
|
||||||
|
/* Clear the selected DAC interrupt pending bits */
|
||||||
|
DAC->SR = (DAC_IT << DAC_Channel);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,162 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_dbgmcu.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the DBGMCU firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_dbgmcu.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU
|
||||||
|
* @brief DBGMCU driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBGMCU_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the device revision identifier.
|
||||||
|
* @param None
|
||||||
|
* @retval Device revision identifier
|
||||||
|
*/
|
||||||
|
uint32_t DBGMCU_GetREVID(void)
|
||||||
|
{
|
||||||
|
return(DBGMCU->IDCODE >> 16);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the device identifier.
|
||||||
|
* @param None
|
||||||
|
* @retval Device identifier
|
||||||
|
*/
|
||||||
|
uint32_t DBGMCU_GetDEVID(void)
|
||||||
|
{
|
||||||
|
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the specified peripheral and low power mode behavior
|
||||||
|
* when the MCU under Debug mode.
|
||||||
|
* @param DBGMCU_Periph: specifies the peripheral and low power mode.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
|
||||||
|
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
|
||||||
|
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
|
||||||
|
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
|
||||||
|
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
|
||||||
|
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
|
||||||
|
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
|
||||||
|
* @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
|
||||||
|
* @param NewState: new state of the specified peripheral in Debug mode.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DBGMCU->CR |= DBGMCU_Periph;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DBGMCU->CR &= ~DBGMCU_Periph;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,714 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_dma.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the DMA firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_dma.h"
|
||||||
|
#include "stm32f10x_rcc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA
|
||||||
|
* @brief DMA driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* DMA1 Channelx interrupt pending bit masks */
|
||||||
|
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||||
|
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||||
|
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||||
|
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||||
|
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||||
|
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
|
||||||
|
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
|
||||||
|
|
||||||
|
/* DMA2 Channelx interrupt pending bit masks */
|
||||||
|
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||||
|
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||||
|
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||||
|
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||||
|
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||||
|
|
||||||
|
/* DMA2 FLAG mask */
|
||||||
|
#define FLAG_Mask ((uint32_t)0x10000000)
|
||||||
|
|
||||||
|
/* DMA registers Masks */
|
||||||
|
#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the DMAy Channelx registers to their default reset
|
||||||
|
* values.
|
||||||
|
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||||
|
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||||
|
|
||||||
|
/* Disable the selected DMAy Channelx */
|
||||||
|
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
||||||
|
|
||||||
|
/* Reset DMAy Channelx control register */
|
||||||
|
DMAy_Channelx->CCR = 0;
|
||||||
|
|
||||||
|
/* Reset DMAy Channelx remaining bytes register */
|
||||||
|
DMAy_Channelx->CNDTR = 0;
|
||||||
|
|
||||||
|
/* Reset DMAy Channelx peripheral address register */
|
||||||
|
DMAy_Channelx->CPAR = 0;
|
||||||
|
|
||||||
|
/* Reset DMAy Channelx memory address register */
|
||||||
|
DMAy_Channelx->CMAR = 0;
|
||||||
|
|
||||||
|
if (DMAy_Channelx == DMA1_Channel1)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA1 Channel1 */
|
||||||
|
DMA1->IFCR |= DMA1_Channel1_IT_Mask;
|
||||||
|
}
|
||||||
|
else if (DMAy_Channelx == DMA1_Channel2)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA1 Channel2 */
|
||||||
|
DMA1->IFCR |= DMA1_Channel2_IT_Mask;
|
||||||
|
}
|
||||||
|
else if (DMAy_Channelx == DMA1_Channel3)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA1 Channel3 */
|
||||||
|
DMA1->IFCR |= DMA1_Channel3_IT_Mask;
|
||||||
|
}
|
||||||
|
else if (DMAy_Channelx == DMA1_Channel4)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA1 Channel4 */
|
||||||
|
DMA1->IFCR |= DMA1_Channel4_IT_Mask;
|
||||||
|
}
|
||||||
|
else if (DMAy_Channelx == DMA1_Channel5)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA1 Channel5 */
|
||||||
|
DMA1->IFCR |= DMA1_Channel5_IT_Mask;
|
||||||
|
}
|
||||||
|
else if (DMAy_Channelx == DMA1_Channel6)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA1 Channel6 */
|
||||||
|
DMA1->IFCR |= DMA1_Channel6_IT_Mask;
|
||||||
|
}
|
||||||
|
else if (DMAy_Channelx == DMA1_Channel7)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA1 Channel7 */
|
||||||
|
DMA1->IFCR |= DMA1_Channel7_IT_Mask;
|
||||||
|
}
|
||||||
|
else if (DMAy_Channelx == DMA2_Channel1)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA2 Channel1 */
|
||||||
|
DMA2->IFCR |= DMA2_Channel1_IT_Mask;
|
||||||
|
}
|
||||||
|
else if (DMAy_Channelx == DMA2_Channel2)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA2 Channel2 */
|
||||||
|
DMA2->IFCR |= DMA2_Channel2_IT_Mask;
|
||||||
|
}
|
||||||
|
else if (DMAy_Channelx == DMA2_Channel3)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA2 Channel3 */
|
||||||
|
DMA2->IFCR |= DMA2_Channel3_IT_Mask;
|
||||||
|
}
|
||||||
|
else if (DMAy_Channelx == DMA2_Channel4)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA2 Channel4 */
|
||||||
|
DMA2->IFCR |= DMA2_Channel4_IT_Mask;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (DMAy_Channelx == DMA2_Channel5)
|
||||||
|
{
|
||||||
|
/* Reset interrupt pending bits for DMA2 Channel5 */
|
||||||
|
DMA2->IFCR |= DMA2_Channel5_IT_Mask;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the DMAy Channelx according to the specified
|
||||||
|
* parameters in the DMA_InitStruct.
|
||||||
|
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||||
|
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||||
|
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified DMA Channel.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||||
|
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
|
||||||
|
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
|
||||||
|
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
|
||||||
|
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
|
||||||
|
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
|
||||||
|
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
|
||||||
|
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
|
||||||
|
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
|
||||||
|
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
|
||||||
|
|
||||||
|
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
|
||||||
|
/* Get the DMAy_Channelx CCR value */
|
||||||
|
tmpreg = DMAy_Channelx->CCR;
|
||||||
|
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
|
||||||
|
tmpreg &= CCR_CLEAR_Mask;
|
||||||
|
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
|
||||||
|
/* Set DIR bit according to DMA_DIR value */
|
||||||
|
/* Set CIRC bit according to DMA_Mode value */
|
||||||
|
/* Set PINC bit according to DMA_PeripheralInc value */
|
||||||
|
/* Set MINC bit according to DMA_MemoryInc value */
|
||||||
|
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
|
||||||
|
/* Set MSIZE bits according to DMA_MemoryDataSize value */
|
||||||
|
/* Set PL bits according to DMA_Priority value */
|
||||||
|
/* Set the MEM2MEM bit according to DMA_M2M value */
|
||||||
|
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||||
|
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||||
|
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||||
|
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||||
|
|
||||||
|
/* Write to DMAy Channelx CCR */
|
||||||
|
DMAy_Channelx->CCR = tmpreg;
|
||||||
|
|
||||||
|
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
||||||
|
/* Write to DMAy Channelx CNDTR */
|
||||||
|
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
|
||||||
|
|
||||||
|
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
|
||||||
|
/* Write to DMAy Channelx CPAR */
|
||||||
|
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||||
|
|
||||||
|
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
|
||||||
|
/* Write to DMAy Channelx CMAR */
|
||||||
|
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each DMA_InitStruct member with its default value.
|
||||||
|
* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
|
||||||
|
* be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
|
||||||
|
{
|
||||||
|
/*-------------- Reset DMA init structure parameters values ------------------*/
|
||||||
|
/* Initialize the DMA_PeripheralBaseAddr member */
|
||||||
|
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||||
|
/* Initialize the DMA_MemoryBaseAddr member */
|
||||||
|
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||||
|
/* Initialize the DMA_DIR member */
|
||||||
|
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||||
|
/* Initialize the DMA_BufferSize member */
|
||||||
|
DMA_InitStruct->DMA_BufferSize = 0;
|
||||||
|
/* Initialize the DMA_PeripheralInc member */
|
||||||
|
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||||
|
/* Initialize the DMA_MemoryInc member */
|
||||||
|
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||||
|
/* Initialize the DMA_PeripheralDataSize member */
|
||||||
|
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||||
|
/* Initialize the DMA_MemoryDataSize member */
|
||||||
|
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||||
|
/* Initialize the DMA_Mode member */
|
||||||
|
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||||
|
/* Initialize the DMA_Priority member */
|
||||||
|
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||||
|
/* Initialize the DMA_M2M member */
|
||||||
|
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified DMAy Channelx.
|
||||||
|
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||||
|
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||||
|
* @param NewState: new state of the DMAy Channelx.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected DMAy Channelx */
|
||||||
|
DMAy_Channelx->CCR |= DMA_CCR1_EN;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected DMAy Channelx */
|
||||||
|
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||||
|
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||||
|
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||||
|
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
|
||||||
|
* or disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||||
|
* @arg DMA_IT_HT: Half transfer interrupt mask
|
||||||
|
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||||
|
* @param NewState: new state of the specified DMA interrupts.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||||
|
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected DMA interrupts */
|
||||||
|
DMAy_Channelx->CCR |= DMA_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected DMA interrupts */
|
||||||
|
DMAy_Channelx->CCR &= ~DMA_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||||
|
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||||
|
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||||
|
* @param DataNumber: The number of data units in the current DMAy Channelx
|
||||||
|
* transfer.
|
||||||
|
* @note This function can only be used when the DMAy_Channelx is disabled.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||||
|
|
||||||
|
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
||||||
|
/* Write to DMAy Channelx CNDTR */
|
||||||
|
DMAy_Channelx->CNDTR = DataNumber;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the number of remaining data units in the current
|
||||||
|
* DMAy Channelx transfer.
|
||||||
|
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
|
||||||
|
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||||
|
* @retval The number of remaining data units in the current DMAy Channelx
|
||||||
|
* transfer.
|
||||||
|
*/
|
||||||
|
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||||
|
/* Return the number of remaining data units for DMAy Channelx */
|
||||||
|
return ((uint16_t)(DMAy_Channelx->CNDTR));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||||
|
* @param DMAy_FLAG: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||||
|
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||||
|
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||||
|
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||||
|
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||||
|
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||||
|
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||||
|
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||||
|
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||||
|
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||||
|
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||||
|
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||||
|
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||||
|
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||||
|
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||||
|
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||||
|
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||||
|
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||||
|
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||||
|
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||||
|
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||||
|
* @retval The new state of DMAy_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
|
||||||
|
|
||||||
|
/* Calculate the used DMAy */
|
||||||
|
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
/* Get DMA2 ISR register value */
|
||||||
|
tmpreg = DMA2->ISR ;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Get DMA1 ISR register value */
|
||||||
|
tmpreg = DMA1->ISR ;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the status of the specified DMAy flag */
|
||||||
|
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
/* DMAy_FLAG is set */
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* DMAy_FLAG is reset */
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return the DMAy_FLAG status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the DMAy Channelx's pending flags.
|
||||||
|
* @param DMAy_FLAG: specifies the flag to clear.
|
||||||
|
* This parameter can be any combination (for the same DMA) of the following values:
|
||||||
|
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||||
|
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||||
|
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||||
|
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||||
|
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||||
|
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||||
|
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||||
|
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||||
|
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||||
|
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||||
|
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||||
|
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||||
|
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||||
|
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||||
|
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||||
|
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||||
|
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||||
|
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||||
|
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||||
|
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||||
|
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||||
|
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||||
|
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||||
|
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||||
|
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
|
||||||
|
|
||||||
|
/* Calculate the used DMAy */
|
||||||
|
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
/* Clear the selected DMAy flags */
|
||||||
|
DMA2->IFCR = DMAy_FLAG;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Clear the selected DMAy flags */
|
||||||
|
DMA1->IFCR = DMAy_FLAG;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
|
||||||
|
* @param DMAy_IT: specifies the DMAy interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||||
|
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||||
|
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||||
|
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||||
|
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||||
|
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||||
|
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||||
|
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||||
|
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||||
|
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||||
|
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||||
|
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||||
|
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||||
|
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||||
|
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||||
|
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||||
|
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||||
|
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||||
|
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||||
|
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||||
|
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||||
|
* @retval The new state of DMAy_IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DMA_GET_IT(DMAy_IT));
|
||||||
|
|
||||||
|
/* Calculate the used DMA */
|
||||||
|
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
/* Get DMA2 ISR register value */
|
||||||
|
tmpreg = DMA2->ISR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Get DMA1 ISR register value */
|
||||||
|
tmpreg = DMA1->ISR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the status of the specified DMAy interrupt */
|
||||||
|
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
/* DMAy_IT is set */
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* DMAy_IT is reset */
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
/* Return the DMA_IT status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||||
|
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
|
||||||
|
* This parameter can be any combination (for the same DMA) of the following values:
|
||||||
|
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||||
|
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||||
|
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||||
|
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||||
|
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||||
|
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||||
|
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||||
|
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||||
|
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||||
|
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||||
|
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||||
|
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||||
|
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||||
|
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||||
|
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||||
|
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||||
|
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||||
|
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||||
|
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||||
|
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||||
|
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||||
|
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||||
|
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||||
|
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||||
|
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
|
||||||
|
|
||||||
|
/* Calculate the used DMAy */
|
||||||
|
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
/* Clear the selected DMAy interrupt pending bits */
|
||||||
|
DMA2->IFCR = DMAy_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Clear the selected DMAy interrupt pending bits */
|
||||||
|
DMA1->IFCR = DMAy_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,269 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_exti.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the EXTI firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_exti.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI
|
||||||
|
* @brief EXTI driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void EXTI_DeInit(void)
|
||||||
|
{
|
||||||
|
EXTI->IMR = 0x00000000;
|
||||||
|
EXTI->EMR = 0x00000000;
|
||||||
|
EXTI->RTSR = 0x00000000;
|
||||||
|
EXTI->FTSR = 0x00000000;
|
||||||
|
EXTI->PR = 0x000FFFFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the EXTI peripheral according to the specified
|
||||||
|
* parameters in the EXTI_InitStruct.
|
||||||
|
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
|
||||||
|
* that contains the configuration information for the EXTI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
||||||
|
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
||||||
|
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
||||||
|
|
||||||
|
tmp = (uint32_t)EXTI_BASE;
|
||||||
|
|
||||||
|
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||||
|
{
|
||||||
|
/* Clear EXTI line configuration */
|
||||||
|
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
|
||||||
|
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||||
|
|
||||||
|
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
|
||||||
|
/* Clear Rising Falling edge configuration */
|
||||||
|
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
|
||||||
|
/* Select the trigger for the selected external interrupts */
|
||||||
|
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||||
|
{
|
||||||
|
/* Rising Falling edge */
|
||||||
|
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp = (uint32_t)EXTI_BASE;
|
||||||
|
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||||
|
|
||||||
|
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||||
|
|
||||||
|
/* Disable the selected external lines */
|
||||||
|
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||||
|
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
|
||||||
|
* be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||||
|
{
|
||||||
|
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||||
|
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||||
|
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||||
|
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Generates a Software interrupt.
|
||||||
|
* @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
|
||||||
|
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||||
|
|
||||||
|
EXTI->SWIER |= EXTI_Line;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||||
|
* @param EXTI_Line: specifies the EXTI line flag to check.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg EXTI_Linex: External interrupt line x where x(0..19)
|
||||||
|
* @retval The new state of EXTI_Line (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||||
|
|
||||||
|
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the EXTI's line pending flags.
|
||||||
|
* @param EXTI_Line: specifies the EXTI lines flags to clear.
|
||||||
|
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||||
|
|
||||||
|
EXTI->PR = EXTI_Line;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||||
|
* @param EXTI_Line: specifies the EXTI line to check.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg EXTI_Linex: External interrupt line x where x(0..19)
|
||||||
|
* @retval The new state of EXTI_Line (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint32_t enablestatus = 0;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||||
|
|
||||||
|
enablestatus = EXTI->IMR & EXTI_Line;
|
||||||
|
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the EXTI's line pending bits.
|
||||||
|
* @param EXTI_Line: specifies the EXTI lines to clear.
|
||||||
|
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||||
|
|
||||||
|
EXTI->PR = EXTI_Line;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,866 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_fsmc.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the FSMC firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_fsmc.h"
|
||||||
|
#include "stm32f10x_rcc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC
|
||||||
|
* @brief FSMC driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* --------------------- FSMC registers bit mask ---------------------------- */
|
||||||
|
|
||||||
|
/* FSMC BCRx Mask */
|
||||||
|
#define BCR_MBKEN_Set ((uint32_t)0x00000001)
|
||||||
|
#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
|
||||||
|
#define BCR_FACCEN_Set ((uint32_t)0x00000040)
|
||||||
|
|
||||||
|
/* FSMC PCRx Mask */
|
||||||
|
#define PCR_PBKEN_Set ((uint32_t)0x00000004)
|
||||||
|
#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
|
||||||
|
#define PCR_ECCEN_Set ((uint32_t)0x00000040)
|
||||||
|
#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
|
||||||
|
#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup FSMC_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
|
||||||
|
* reset values.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||||||
|
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||||||
|
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||||||
|
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
||||||
|
|
||||||
|
/* FSMC_Bank1_NORSRAM1 */
|
||||||
|
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
|
||||||
|
}
|
||||||
|
/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
|
||||||
|
}
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
|
||||||
|
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||||
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
|
||||||
|
{
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||||
|
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
/* Set the FSMC_Bank2 registers to their reset values */
|
||||||
|
FSMC_Bank2->PCR2 = 0x00000018;
|
||||||
|
FSMC_Bank2->SR2 = 0x00000040;
|
||||||
|
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
|
||||||
|
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
|
||||||
|
}
|
||||||
|
/* FSMC_Bank3_NAND */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Set the FSMC_Bank3 registers to their reset values */
|
||||||
|
FSMC_Bank3->PCR3 = 0x00000018;
|
||||||
|
FSMC_Bank3->SR3 = 0x00000040;
|
||||||
|
FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
|
||||||
|
FSMC_Bank3->PATT3 = 0xFCFCFCFC;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_PCCARDDeInit(void)
|
||||||
|
{
|
||||||
|
/* Set the FSMC_Bank4 registers to their reset values */
|
||||||
|
FSMC_Bank4->PCR4 = 0x00000018;
|
||||||
|
FSMC_Bank4->SR4 = 0x00000000;
|
||||||
|
FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
|
||||||
|
FSMC_Bank4->PATT4 = 0xFCFCFCFC;
|
||||||
|
FSMC_Bank4->PIO4 = 0xFCFCFCFC;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
|
||||||
|
* parameters in the FSMC_NORSRAMInitStruct.
|
||||||
|
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
|
||||||
|
* structure that contains the configuration information for
|
||||||
|
* the FSMC NOR/SRAM specified Banks.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
|
||||||
|
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
|
||||||
|
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
|
||||||
|
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
|
||||||
|
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
|
||||||
|
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
|
||||||
|
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
|
||||||
|
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
|
||||||
|
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
|
||||||
|
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
|
||||||
|
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
|
||||||
|
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
|
||||||
|
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
|
||||||
|
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
|
||||||
|
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
|
||||||
|
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
|
||||||
|
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
|
||||||
|
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
|
||||||
|
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
|
||||||
|
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
|
||||||
|
|
||||||
|
/* Bank1 NOR/SRAM control register configuration */
|
||||||
|
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||||
|
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
|
||||||
|
|
||||||
|
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Bank1 NOR/SRAM timing register configuration */
|
||||||
|
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
|
||||||
|
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
|
||||||
|
|
||||||
|
|
||||||
|
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
|
||||||
|
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
|
||||||
|
{
|
||||||
|
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
|
||||||
|
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
|
||||||
|
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
|
||||||
|
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
|
||||||
|
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
|
||||||
|
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
|
||||||
|
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||||
|
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the FSMC NAND Banks according to the specified
|
||||||
|
* parameters in the FSMC_NANDInitStruct.
|
||||||
|
* @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
|
||||||
|
* structure that contains the configuration information for the FSMC
|
||||||
|
* NAND specified Banks.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
|
||||||
|
assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
|
||||||
|
assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
|
||||||
|
assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
|
||||||
|
assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
|
||||||
|
assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
|
||||||
|
assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
|
||||||
|
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
|
||||||
|
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||||
|
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||||
|
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||||
|
assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
|
||||||
|
assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||||
|
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||||
|
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||||
|
|
||||||
|
/* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
|
||||||
|
tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
|
||||||
|
PCR_MemoryType_NAND |
|
||||||
|
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECC |
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECCPageSize |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
|
||||||
|
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
|
||||||
|
|
||||||
|
/* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
|
||||||
|
tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||||
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||||
|
|
||||||
|
/* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
|
||||||
|
tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||||
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||||
|
|
||||||
|
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
/* FSMC_Bank2_NAND registers configuration */
|
||||||
|
FSMC_Bank2->PCR2 = tmppcr;
|
||||||
|
FSMC_Bank2->PMEM2 = tmppmem;
|
||||||
|
FSMC_Bank2->PATT2 = tmppatt;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* FSMC_Bank3_NAND registers configuration */
|
||||||
|
FSMC_Bank3->PCR3 = tmppcr;
|
||||||
|
FSMC_Bank3->PMEM3 = tmppmem;
|
||||||
|
FSMC_Bank3->PATT3 = tmppatt;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the FSMC PCCARD Bank according to the specified
|
||||||
|
* parameters in the FSMC_PCCARDInitStruct.
|
||||||
|
* @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
|
||||||
|
* structure that contains the configuration information for the FSMC
|
||||||
|
* PCCARD Bank.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
|
||||||
|
assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
|
||||||
|
assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
|
||||||
|
|
||||||
|
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
|
||||||
|
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||||
|
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||||
|
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||||
|
|
||||||
|
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
|
||||||
|
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||||
|
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||||
|
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||||
|
assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
|
||||||
|
assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
|
||||||
|
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
|
||||||
|
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
|
||||||
|
|
||||||
|
/* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
|
||||||
|
FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
|
||||||
|
FSMC_MemoryDataWidth_16b |
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
|
||||||
|
|
||||||
|
/* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
|
||||||
|
FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||||
|
|
||||||
|
/* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
|
||||||
|
FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||||
|
|
||||||
|
/* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
|
||||||
|
FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||||||
|
(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
|
||||||
|
* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||||||
|
{
|
||||||
|
/* Reset NOR/SRAM Init structure parameters values */
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each FSMC_NANDInitStruct member with its default value.
|
||||||
|
* @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
||||||
|
{
|
||||||
|
/* Reset NAND Init structure parameters values */
|
||||||
|
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
|
||||||
|
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
||||||
|
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
|
||||||
|
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||||||
|
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each FSMC_PCCARDInitStruct member with its default value.
|
||||||
|
* @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
||||||
|
{
|
||||||
|
/* Reset PCCARD Init structure parameters values */
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||||
|
FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||||||
|
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||||||
|
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||||||
|
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||||||
|
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified NAND Memory Bank.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||||
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||||
|
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the PCCARD Memory Bank.
|
||||||
|
* @param NewState: new state of the PCCARD Memory Bank.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_PCCARDCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
|
||||||
|
FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
|
||||||
|
FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the FSMC NAND ECC feature.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||||
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||||
|
* @param NewState: new state of the FSMC NAND ECC feature.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the error correction code register value.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||||
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||||
|
* @retval The Error Correction Code (ECC) value.
|
||||||
|
*/
|
||||||
|
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
|
||||||
|
{
|
||||||
|
uint32_t eccval = 0x00000000;
|
||||||
|
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
/* Get the ECCR2 register value */
|
||||||
|
eccval = FSMC_Bank2->ECCR2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Get the ECCR3 register value */
|
||||||
|
eccval = FSMC_Bank3->ECCR3;
|
||||||
|
}
|
||||||
|
/* Return the error correction code value */
|
||||||
|
return(eccval);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified FSMC interrupts.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||||
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||||
|
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||||
|
* @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||||
|
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||||
|
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||||
|
* @param NewState: new state of the specified FSMC interrupts.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||||
|
assert_param(IS_FSMC_IT(FSMC_IT));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected FSMC_Bank2 interrupts */
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->SR2 |= FSMC_IT;
|
||||||
|
}
|
||||||
|
/* Enable the selected FSMC_Bank3 interrupts */
|
||||||
|
else if (FSMC_Bank == FSMC_Bank3_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank3->SR3 |= FSMC_IT;
|
||||||
|
}
|
||||||
|
/* Enable the selected FSMC_Bank4 interrupts */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank4->SR4 |= FSMC_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected FSMC_Bank2 interrupts */
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
|
||||||
|
FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
|
||||||
|
}
|
||||||
|
/* Disable the selected FSMC_Bank3 interrupts */
|
||||||
|
else if (FSMC_Bank == FSMC_Bank3_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
|
||||||
|
}
|
||||||
|
/* Disable the selected FSMC_Bank4 interrupts */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified FSMC flag is set or not.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||||
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||||
|
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||||
|
* @param FSMC_FLAG: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
|
||||||
|
* @arg FSMC_FLAG_Level: Level detection Flag.
|
||||||
|
* @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
|
||||||
|
* @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
|
||||||
|
* @retval The new state of FSMC_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
uint32_t tmpsr = 0x00000000;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
|
||||||
|
assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
|
||||||
|
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
tmpsr = FSMC_Bank2->SR2;
|
||||||
|
}
|
||||||
|
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||||
|
{
|
||||||
|
tmpsr = FSMC_Bank3->SR3;
|
||||||
|
}
|
||||||
|
/* FSMC_Bank4_PCCARD*/
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmpsr = FSMC_Bank4->SR4;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get the flag status */
|
||||||
|
if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
/* Return the flag status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the FSMC's pending flags.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||||
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||||
|
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||||
|
* @param FSMC_FLAG: specifies the flag to clear.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
|
||||||
|
* @arg FSMC_FLAG_Level: Level detection Flag.
|
||||||
|
* @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
|
||||||
|
assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
|
||||||
|
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->SR2 &= ~FSMC_FLAG;
|
||||||
|
}
|
||||||
|
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank3->SR3 &= ~FSMC_FLAG;
|
||||||
|
}
|
||||||
|
/* FSMC_Bank4_PCCARD*/
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank4->SR4 &= ~FSMC_FLAG;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified FSMC interrupt has occurred or not.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||||
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||||
|
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||||
|
* @param FSMC_IT: specifies the FSMC interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||||
|
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||||
|
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||||
|
* @retval The new state of FSMC_IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||||
|
assert_param(IS_FSMC_GET_IT(FSMC_IT));
|
||||||
|
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
tmpsr = FSMC_Bank2->SR2;
|
||||||
|
}
|
||||||
|
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||||
|
{
|
||||||
|
tmpsr = FSMC_Bank3->SR3;
|
||||||
|
}
|
||||||
|
/* FSMC_Bank4_PCCARD*/
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmpsr = FSMC_Bank4->SR4;
|
||||||
|
}
|
||||||
|
|
||||||
|
itstatus = tmpsr & FSMC_IT;
|
||||||
|
|
||||||
|
itenable = tmpsr & (FSMC_IT >> 3);
|
||||||
|
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the FSMC's interrupt pending bits.
|
||||||
|
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||||||
|
* @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||||||
|
* @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||||||
|
* @param FSMC_IT: specifies the interrupt pending bit to clear.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||||||
|
* @arg FSMC_IT_Level: Level edge detection interrupt.
|
||||||
|
* @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
|
||||||
|
assert_param(IS_FSMC_IT(FSMC_IT));
|
||||||
|
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
|
||||||
|
}
|
||||||
|
else if(FSMC_Bank == FSMC_Bank3_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
|
||||||
|
}
|
||||||
|
/* FSMC_Bank4_PCCARD*/
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,650 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_gpio.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the GPIO firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_gpio.h"
|
||||||
|
#include "stm32f10x_rcc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO
|
||||||
|
* @brief GPIO driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ------------ RCC registers bit address in the alias region ----------------*/
|
||||||
|
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
|
||||||
|
|
||||||
|
/* --- EVENTCR Register -----*/
|
||||||
|
|
||||||
|
/* Alias word address of EVOE bit */
|
||||||
|
#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
|
||||||
|
#define EVOE_BitNumber ((uint8_t)0x07)
|
||||||
|
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
|
||||||
|
|
||||||
|
|
||||||
|
/* --- MAPR Register ---*/
|
||||||
|
/* Alias word address of MII_RMII_SEL bit */
|
||||||
|
#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
|
||||||
|
#define MII_RMII_SEL_BitNumber ((u8)0x17)
|
||||||
|
#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
|
||||||
|
|
||||||
|
|
||||||
|
#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
|
||||||
|
#define LSB_MASK ((uint16_t)0xFFFF)
|
||||||
|
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
|
||||||
|
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
|
||||||
|
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
|
||||||
|
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup GPIO_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
|
||||||
|
if (GPIOx == GPIOA)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
|
||||||
|
}
|
||||||
|
else if (GPIOx == GPIOB)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
|
||||||
|
}
|
||||||
|
else if (GPIOx == GPIOC)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
|
||||||
|
}
|
||||||
|
else if (GPIOx == GPIOD)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
|
||||||
|
}
|
||||||
|
else if (GPIOx == GPIOE)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
|
||||||
|
}
|
||||||
|
else if (GPIOx == GPIOF)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (GPIOx == GPIOG)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the Alternate Functions (remap, event control
|
||||||
|
* and EXTI configuration) registers to their default reset values.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_AFIODeInit(void)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the GPIOx peripheral according to the specified
|
||||||
|
* parameters in the GPIO_InitStruct.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified GPIO peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
|
||||||
|
uint32_t tmpreg = 0x00, pinmask = 0x00;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||||
|
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||||
|
|
||||||
|
/*---------------------------- GPIO Mode Configuration -----------------------*/
|
||||||
|
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
|
||||||
|
if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||||
|
/* Output mode */
|
||||||
|
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
|
||||||
|
}
|
||||||
|
/*---------------------------- GPIO CRL Configuration ------------------------*/
|
||||||
|
/* Configure the eight low port pins */
|
||||||
|
if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
|
||||||
|
{
|
||||||
|
tmpreg = GPIOx->CRL;
|
||||||
|
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||||
|
{
|
||||||
|
pos = ((uint32_t)0x01) << pinpos;
|
||||||
|
/* Get the port pins position */
|
||||||
|
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||||
|
if (currentpin == pos)
|
||||||
|
{
|
||||||
|
pos = pinpos << 2;
|
||||||
|
/* Clear the corresponding low control register bits */
|
||||||
|
pinmask = ((uint32_t)0x0F) << pos;
|
||||||
|
tmpreg &= ~pinmask;
|
||||||
|
/* Write the mode configuration in the corresponding bits */
|
||||||
|
tmpreg |= (currentmode << pos);
|
||||||
|
/* Reset the corresponding ODR bit */
|
||||||
|
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||||
|
{
|
||||||
|
GPIOx->BRR = (((uint32_t)0x01) << pinpos);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Set the corresponding ODR bit */
|
||||||
|
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||||
|
{
|
||||||
|
GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
GPIOx->CRL = tmpreg;
|
||||||
|
}
|
||||||
|
/*---------------------------- GPIO CRH Configuration ------------------------*/
|
||||||
|
/* Configure the eight high port pins */
|
||||||
|
if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
|
||||||
|
{
|
||||||
|
tmpreg = GPIOx->CRH;
|
||||||
|
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||||
|
{
|
||||||
|
pos = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||||
|
/* Get the port pins position */
|
||||||
|
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
|
||||||
|
if (currentpin == pos)
|
||||||
|
{
|
||||||
|
pos = pinpos << 2;
|
||||||
|
/* Clear the corresponding high control register bits */
|
||||||
|
pinmask = ((uint32_t)0x0F) << pos;
|
||||||
|
tmpreg &= ~pinmask;
|
||||||
|
/* Write the mode configuration in the corresponding bits */
|
||||||
|
tmpreg |= (currentmode << pos);
|
||||||
|
/* Reset the corresponding ODR bit */
|
||||||
|
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||||
|
{
|
||||||
|
GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||||
|
}
|
||||||
|
/* Set the corresponding ODR bit */
|
||||||
|
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||||
|
{
|
||||||
|
GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
GPIOx->CRH = tmpreg;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||||
|
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
|
||||||
|
* be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||||
|
{
|
||||||
|
/* Reset GPIO init structure parameters values */
|
||||||
|
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||||
|
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||||
|
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads the specified input port pin.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @param GPIO_Pin: specifies the port bit to read.
|
||||||
|
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||||
|
* @retval The input port pin value.
|
||||||
|
*/
|
||||||
|
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
uint8_t bitstatus = 0x00;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||||
|
|
||||||
|
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads the specified GPIO input data port.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @retval GPIO input data port value.
|
||||||
|
*/
|
||||||
|
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
|
||||||
|
return ((uint16_t)GPIOx->IDR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads the specified output data port bit.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @param GPIO_Pin: specifies the port bit to read.
|
||||||
|
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||||
|
* @retval The output port pin value.
|
||||||
|
*/
|
||||||
|
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
uint8_t bitstatus = 0x00;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||||
|
|
||||||
|
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads the specified GPIO output data port.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @retval GPIO output data port value.
|
||||||
|
*/
|
||||||
|
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
|
||||||
|
return ((uint16_t)GPIOx->ODR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the selected data port bits.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @param GPIO_Pin: specifies the port bits to be written.
|
||||||
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||||
|
|
||||||
|
GPIOx->BSRR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the selected data port bits.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @param GPIO_Pin: specifies the port bits to be written.
|
||||||
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||||
|
|
||||||
|
GPIOx->BRR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets or clears the selected data port bit.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @param GPIO_Pin: specifies the port bit to be written.
|
||||||
|
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||||
|
* @param BitVal: specifies the value to be written to the selected bit.
|
||||||
|
* This parameter can be one of the BitAction enum values:
|
||||||
|
* @arg Bit_RESET: to clear the port pin
|
||||||
|
* @arg Bit_SET: to set the port pin
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||||
|
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||||
|
|
||||||
|
if (BitVal != Bit_RESET)
|
||||||
|
{
|
||||||
|
GPIOx->BSRR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
GPIOx->BRR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes data to the specified GPIO data port.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @param PortVal: specifies the value to be written to the port output data register.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
|
||||||
|
GPIOx->ODR = PortVal;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Locks GPIO Pins configuration registers.
|
||||||
|
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* @param GPIO_Pin: specifies the port bit to be written.
|
||||||
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x00010000;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||||
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||||
|
|
||||||
|
tmp |= GPIO_Pin;
|
||||||
|
/* Set LCKK bit */
|
||||||
|
GPIOx->LCKR = tmp;
|
||||||
|
/* Reset LCKK bit */
|
||||||
|
GPIOx->LCKR = GPIO_Pin;
|
||||||
|
/* Set LCKK bit */
|
||||||
|
GPIOx->LCKR = tmp;
|
||||||
|
/* Read LCKK bit*/
|
||||||
|
tmp = GPIOx->LCKR;
|
||||||
|
/* Read LCKK bit*/
|
||||||
|
tmp = GPIOx->LCKR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Selects the GPIO pin used as Event output.
|
||||||
|
* @param GPIO_PortSource: selects the GPIO port to be used as source
|
||||||
|
* for Event output.
|
||||||
|
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
|
||||||
|
* @param GPIO_PinSource: specifies the pin for the Event output.
|
||||||
|
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0x00;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
|
||||||
|
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||||
|
|
||||||
|
tmpreg = AFIO->EVCR;
|
||||||
|
/* Clear the PORT[6:4] and PIN[3:0] bits */
|
||||||
|
tmpreg &= EVCR_PORTPINCONFIG_MASK;
|
||||||
|
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
|
||||||
|
tmpreg |= GPIO_PinSource;
|
||||||
|
AFIO->EVCR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the Event Output.
|
||||||
|
* @param NewState: new state of the Event output.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_EventOutputCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Changes the mapping of the specified pin.
|
||||||
|
* @param GPIO_Remap: selects the pin to remap.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
|
||||||
|
* @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
|
||||||
|
* @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping
|
||||||
|
* @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping
|
||||||
|
* @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
|
||||||
|
* @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
|
||||||
|
* @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
|
||||||
|
* @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
|
||||||
|
* @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
|
||||||
|
* @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
|
||||||
|
* @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
|
||||||
|
* @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
|
||||||
|
* @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
|
||||||
|
* @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
|
||||||
|
* @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
|
||||||
|
* @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
|
||||||
|
* @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping
|
||||||
|
* @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
|
||||||
|
* @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
|
||||||
|
* @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
|
||||||
|
* @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
|
||||||
|
* @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
|
||||||
|
* @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
|
||||||
|
* @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
|
||||||
|
* @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
|
||||||
|
* @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
|
||||||
|
* @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
|
||||||
|
* @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
|
||||||
|
* When the SPI3/I2S3 is remapped using this function, the SWJ is configured
|
||||||
|
* to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
|
||||||
|
* @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||||
|
* to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
|
||||||
|
* If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
|
||||||
|
* Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
|
||||||
|
* @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
|
||||||
|
* @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
|
||||||
|
* @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
|
||||||
|
* @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
|
||||||
|
* @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
|
||||||
|
* @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
|
||||||
|
* @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
|
||||||
|
* @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
|
||||||
|
* @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
|
||||||
|
* @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||||
|
* @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||||
|
* @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
|
||||||
|
* @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
|
||||||
|
* @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
|
||||||
|
* @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
|
||||||
|
* only for High density Value line devices)
|
||||||
|
* @param NewState: new state of the port pin remapping.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_REMAP(GPIO_Remap));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||||
|
{
|
||||||
|
tmpreg = AFIO->MAPR2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmpreg = AFIO->MAPR;
|
||||||
|
}
|
||||||
|
|
||||||
|
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
|
||||||
|
tmp = GPIO_Remap & LSB_MASK;
|
||||||
|
|
||||||
|
if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
|
||||||
|
{
|
||||||
|
tmpreg &= DBGAFR_SWJCFG_MASK;
|
||||||
|
AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
|
||||||
|
}
|
||||||
|
else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
|
||||||
|
{
|
||||||
|
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||||
|
tmpreg &= ~tmp1;
|
||||||
|
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
|
||||||
|
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
|
||||||
|
}
|
||||||
|
|
||||||
|
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||||
|
{
|
||||||
|
AFIO->MAPR2 = tmpreg;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
AFIO->MAPR = tmpreg;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Selects the GPIO pin used as EXTI Line.
|
||||||
|
* @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
|
||||||
|
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
|
||||||
|
* @param GPIO_PinSource: specifies the EXTI line to be configured.
|
||||||
|
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x00;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
|
||||||
|
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||||
|
|
||||||
|
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
|
||||||
|
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
|
||||||
|
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Selects the Ethernet media interface.
|
||||||
|
* @note This function applies only to STM32 Connectivity line devices.
|
||||||
|
* @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg GPIO_ETH_MediaInterface_MII: MII mode
|
||||||
|
* @arg GPIO_ETH_MediaInterface_RMII: RMII mode
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
|
||||||
|
{
|
||||||
|
assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
|
||||||
|
|
||||||
|
/* Configure MII_RMII selection bit */
|
||||||
|
*(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,190 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_iwdg.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the IWDG firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_iwdg.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG
|
||||||
|
* @brief IWDG driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ---------------------- IWDG registers bit mask ----------------------------*/
|
||||||
|
|
||||||
|
/* KR register bit mask */
|
||||||
|
#define KR_KEY_Reload ((uint16_t)0xAAAA)
|
||||||
|
#define KR_KEY_Enable ((uint16_t)0xCCCC)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup IWDG_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
|
||||||
|
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
|
||||||
|
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
|
||||||
|
IWDG->KR = IWDG_WriteAccess;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets IWDG Prescaler value.
|
||||||
|
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
|
||||||
|
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
|
||||||
|
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
|
||||||
|
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
|
||||||
|
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
|
||||||
|
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
|
||||||
|
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
|
||||||
|
IWDG->PR = IWDG_Prescaler;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets IWDG Reload value.
|
||||||
|
* @param Reload: specifies the IWDG Reload value.
|
||||||
|
* This parameter must be a number between 0 and 0x0FFF.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void IWDG_SetReload(uint16_t Reload)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_IWDG_RELOAD(Reload));
|
||||||
|
IWDG->RLR = Reload;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reloads IWDG counter with value defined in the reload register
|
||||||
|
* (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void IWDG_ReloadCounter(void)
|
||||||
|
{
|
||||||
|
IWDG->KR = KR_KEY_Reload;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void IWDG_Enable(void)
|
||||||
|
{
|
||||||
|
IWDG->KR = KR_KEY_Enable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified IWDG flag is set or not.
|
||||||
|
* @param IWDG_FLAG: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
|
||||||
|
* @arg IWDG_FLAG_RVU: Reload Value Update on going
|
||||||
|
* @retval The new state of IWDG_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
|
||||||
|
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
/* Return the flag status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,307 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_pwr.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the PWR firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_pwr.h"
|
||||||
|
#include "stm32f10x_rcc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR
|
||||||
|
* @brief PWR driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* --------- PWR registers bit address in the alias region ---------- */
|
||||||
|
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
|
||||||
|
|
||||||
|
/* --- CR Register ---*/
|
||||||
|
|
||||||
|
/* Alias word address of DBP bit */
|
||||||
|
#define CR_OFFSET (PWR_OFFSET + 0x00)
|
||||||
|
#define DBP_BitNumber 0x08
|
||||||
|
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of PVDE bit */
|
||||||
|
#define PVDE_BitNumber 0x04
|
||||||
|
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
|
||||||
|
|
||||||
|
/* --- CSR Register ---*/
|
||||||
|
|
||||||
|
/* Alias word address of EWUP bit */
|
||||||
|
#define CSR_OFFSET (PWR_OFFSET + 0x04)
|
||||||
|
#define EWUP_BitNumber 0x08
|
||||||
|
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
|
||||||
|
|
||||||
|
/* ------------------ PWR registers bit mask ------------------------ */
|
||||||
|
|
||||||
|
/* CR register bit mask */
|
||||||
|
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
|
||||||
|
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup PWR_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void PWR_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables access to the RTC and backup registers.
|
||||||
|
* @param NewState: new state of the access to the RTC and backup registers.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void PWR_BackupAccessCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||||
|
* @param NewState: new state of the PVD.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void PWR_PVDCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||||
|
* @param PWR_PVDLevel: specifies the PVD detection level
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
|
||||||
|
* @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
|
||||||
|
* @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
|
||||||
|
* @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
|
||||||
|
* @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
|
||||||
|
* @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
|
||||||
|
* @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
|
||||||
|
* @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
|
||||||
|
tmpreg = PWR->CR;
|
||||||
|
/* Clear PLS[7:5] bits */
|
||||||
|
tmpreg &= CR_PLS_MASK;
|
||||||
|
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
|
||||||
|
tmpreg |= PWR_PVDLevel;
|
||||||
|
/* Store the new value */
|
||||||
|
PWR->CR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the WakeUp Pin functionality.
|
||||||
|
* @param NewState: new state of the WakeUp Pin functionality.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void PWR_WakeUpPinCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enters STOP mode.
|
||||||
|
* @param PWR_Regulator: specifies the regulator state in STOP mode.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg PWR_Regulator_ON: STOP mode with regulator ON
|
||||||
|
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
|
||||||
|
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
|
||||||
|
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
||||||
|
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
||||||
|
|
||||||
|
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||||
|
tmpreg = PWR->CR;
|
||||||
|
/* Clear PDDS and LPDS bits */
|
||||||
|
tmpreg &= CR_DS_MASK;
|
||||||
|
/* Set LPDS bit according to PWR_Regulator value */
|
||||||
|
tmpreg |= PWR_Regulator;
|
||||||
|
/* Store the new value */
|
||||||
|
PWR->CR = tmpreg;
|
||||||
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||||
|
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||||
|
|
||||||
|
/* Select STOP mode entry --------------------------------------------------*/
|
||||||
|
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||||
|
{
|
||||||
|
/* Request Wait For Interrupt */
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Request Wait For Event */
|
||||||
|
__WFE();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||||
|
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enters STANDBY mode.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode(void)
|
||||||
|
{
|
||||||
|
/* Clear Wake-up flag */
|
||||||
|
PWR->CR |= PWR_CR_CWUF;
|
||||||
|
/* Select STANDBY mode */
|
||||||
|
PWR->CR |= PWR_CR_PDDS;
|
||||||
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||||
|
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||||
|
/* This option is used to ensure that store operations are completed */
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
__force_stores();
|
||||||
|
#endif
|
||||||
|
/* Request Wait For Interrupt */
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified PWR flag is set or not.
|
||||||
|
* @param PWR_FLAG: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg PWR_FLAG_WU: Wake Up flag
|
||||||
|
* @arg PWR_FLAG_SB: StandBy flag
|
||||||
|
* @arg PWR_FLAG_PVDO: PVD Output
|
||||||
|
* @retval The new state of PWR_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
|
||||||
|
|
||||||
|
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
/* Return the flag status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the PWR's pending flags.
|
||||||
|
* @param PWR_FLAG: specifies the flag to clear.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg PWR_FLAG_WU: Wake Up flag
|
||||||
|
* @arg PWR_FLAG_SB: StandBy flag
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
|
||||||
|
|
||||||
|
PWR->CR |= PWR_FLAG << 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,339 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_rtc.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the RTC firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_rtc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC
|
||||||
|
* @brief RTC driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
|
||||||
|
#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup RTC_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified RTC interrupts.
|
||||||
|
* @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_IT_OW: Overflow interrupt
|
||||||
|
* @arg RTC_IT_ALR: Alarm interrupt
|
||||||
|
* @arg RTC_IT_SEC: Second interrupt
|
||||||
|
* @param NewState: new state of the specified RTC interrupts.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_IT(RTC_IT));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
RTC->CRH |= RTC_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RTC->CRH &= (uint16_t)~RTC_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enters the RTC configuration mode.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_EnterConfigMode(void)
|
||||||
|
{
|
||||||
|
/* Set the CNF flag to enter in the Configuration Mode */
|
||||||
|
RTC->CRL |= RTC_CRL_CNF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Exits from the RTC configuration mode.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_ExitConfigMode(void)
|
||||||
|
{
|
||||||
|
/* Reset the CNF flag to exit from the Configuration Mode */
|
||||||
|
RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Gets the RTC counter value.
|
||||||
|
* @param None
|
||||||
|
* @retval RTC counter value.
|
||||||
|
*/
|
||||||
|
uint32_t RTC_GetCounter(void)
|
||||||
|
{
|
||||||
|
uint16_t tmp = 0;
|
||||||
|
tmp = RTC->CNTL;
|
||||||
|
return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the RTC counter value.
|
||||||
|
* @param CounterValue: RTC counter new value.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_SetCounter(uint32_t CounterValue)
|
||||||
|
{
|
||||||
|
RTC_EnterConfigMode();
|
||||||
|
/* Set RTC COUNTER MSB word */
|
||||||
|
RTC->CNTH = CounterValue >> 16;
|
||||||
|
/* Set RTC COUNTER LSB word */
|
||||||
|
RTC->CNTL = (CounterValue & RTC_LSB_MASK);
|
||||||
|
RTC_ExitConfigMode();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the RTC prescaler value.
|
||||||
|
* @param PrescalerValue: RTC prescaler new value.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_SetPrescaler(uint32_t PrescalerValue)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_PRESCALER(PrescalerValue));
|
||||||
|
|
||||||
|
RTC_EnterConfigMode();
|
||||||
|
/* Set RTC PRESCALER MSB word */
|
||||||
|
RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
|
||||||
|
/* Set RTC PRESCALER LSB word */
|
||||||
|
RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
|
||||||
|
RTC_ExitConfigMode();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the RTC alarm value.
|
||||||
|
* @param AlarmValue: RTC alarm new value.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_SetAlarm(uint32_t AlarmValue)
|
||||||
|
{
|
||||||
|
RTC_EnterConfigMode();
|
||||||
|
/* Set the ALARM MSB word */
|
||||||
|
RTC->ALRH = AlarmValue >> 16;
|
||||||
|
/* Set the ALARM LSB word */
|
||||||
|
RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
|
||||||
|
RTC_ExitConfigMode();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Gets the RTC divider value.
|
||||||
|
* @param None
|
||||||
|
* @retval RTC Divider value.
|
||||||
|
*/
|
||||||
|
uint32_t RTC_GetDivider(void)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x00;
|
||||||
|
tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
|
||||||
|
tmp |= RTC->DIVL;
|
||||||
|
return tmp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Waits until last write operation on RTC registers has finished.
|
||||||
|
* @note This function must be called before any write to RTC registers.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_WaitForLastTask(void)
|
||||||
|
{
|
||||||
|
/* Loop until RTOFF flag is set */
|
||||||
|
while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
|
||||||
|
* are synchronized with RTC APB clock.
|
||||||
|
* @note This function must be called before any read operation after an APB reset
|
||||||
|
* or an APB clock stop.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_WaitForSynchro(void)
|
||||||
|
{
|
||||||
|
/* Clear RSF flag */
|
||||||
|
RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
|
||||||
|
/* Loop until RSF flag is set */
|
||||||
|
while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified RTC flag is set or not.
|
||||||
|
* @param RTC_FLAG: specifies the flag to check.
|
||||||
|
* This parameter can be one the following values:
|
||||||
|
* @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
|
||||||
|
* @arg RTC_FLAG_RSF: Registers Synchronized flag
|
||||||
|
* @arg RTC_FLAG_OW: Overflow flag
|
||||||
|
* @arg RTC_FLAG_ALR: Alarm flag
|
||||||
|
* @arg RTC_FLAG_SEC: Second flag
|
||||||
|
* @retval The new state of RTC_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
|
||||||
|
|
||||||
|
if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the RTC's pending flags.
|
||||||
|
* @param RTC_FLAG: specifies the flag to clear.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
|
||||||
|
* an APB reset or an APB Clock stop.
|
||||||
|
* @arg RTC_FLAG_OW: Overflow flag
|
||||||
|
* @arg RTC_FLAG_ALR: Alarm flag
|
||||||
|
* @arg RTC_FLAG_SEC: Second flag
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_ClearFlag(uint16_t RTC_FLAG)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
|
||||||
|
|
||||||
|
/* Clear the corresponding RTC flag */
|
||||||
|
RTC->CRL &= (uint16_t)~RTC_FLAG;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified RTC interrupt has occurred or not.
|
||||||
|
* @param RTC_IT: specifies the RTC interrupts sources to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg RTC_IT_OW: Overflow interrupt
|
||||||
|
* @arg RTC_IT_ALR: Alarm interrupt
|
||||||
|
* @arg RTC_IT_SEC: Second interrupt
|
||||||
|
* @retval The new state of the RTC_IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus RTC_GetITStatus(uint16_t RTC_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_GET_IT(RTC_IT));
|
||||||
|
|
||||||
|
bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
|
||||||
|
if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the RTC's interrupt pending bits.
|
||||||
|
* @param RTC_IT: specifies the interrupt pending bit to clear.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg RTC_IT_OW: Overflow interrupt
|
||||||
|
* @arg RTC_IT_ALR: Alarm interrupt
|
||||||
|
* @arg RTC_IT_SEC: Second interrupt
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void RTC_ClearITPendingBit(uint16_t RTC_IT)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_RTC_IT(RTC_IT));
|
||||||
|
|
||||||
|
/* Clear the corresponding RTC pending bit */
|
||||||
|
RTC->CRL &= (uint16_t)~RTC_IT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,799 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_sdio.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the SDIO firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_sdio.h"
|
||||||
|
#include "stm32f10x_rcc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO
|
||||||
|
* @brief SDIO driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ------------ SDIO registers bit address in the alias region ----------- */
|
||||||
|
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
|
||||||
|
|
||||||
|
/* --- CLKCR Register ---*/
|
||||||
|
|
||||||
|
/* Alias word address of CLKEN bit */
|
||||||
|
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
|
||||||
|
#define CLKEN_BitNumber 0x08
|
||||||
|
#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
|
||||||
|
|
||||||
|
/* --- CMD Register ---*/
|
||||||
|
|
||||||
|
/* Alias word address of SDIOSUSPEND bit */
|
||||||
|
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
|
||||||
|
#define SDIOSUSPEND_BitNumber 0x0B
|
||||||
|
#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of ENCMDCOMPL bit */
|
||||||
|
#define ENCMDCOMPL_BitNumber 0x0C
|
||||||
|
#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of NIEN bit */
|
||||||
|
#define NIEN_BitNumber 0x0D
|
||||||
|
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of ATACMD bit */
|
||||||
|
#define ATACMD_BitNumber 0x0E
|
||||||
|
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
|
||||||
|
|
||||||
|
/* --- DCTRL Register ---*/
|
||||||
|
|
||||||
|
/* Alias word address of DMAEN bit */
|
||||||
|
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
|
||||||
|
#define DMAEN_BitNumber 0x03
|
||||||
|
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of RWSTART bit */
|
||||||
|
#define RWSTART_BitNumber 0x08
|
||||||
|
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of RWSTOP bit */
|
||||||
|
#define RWSTOP_BitNumber 0x09
|
||||||
|
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of RWMOD bit */
|
||||||
|
#define RWMOD_BitNumber 0x0A
|
||||||
|
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
|
||||||
|
|
||||||
|
/* Alias word address of SDIOEN bit */
|
||||||
|
#define SDIOEN_BitNumber 0x0B
|
||||||
|
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
|
||||||
|
|
||||||
|
/* ---------------------- SDIO registers bit mask ------------------------ */
|
||||||
|
|
||||||
|
/* --- CLKCR Register ---*/
|
||||||
|
|
||||||
|
/* CLKCR register clear mask */
|
||||||
|
#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
|
||||||
|
|
||||||
|
/* --- PWRCTRL Register ---*/
|
||||||
|
|
||||||
|
/* SDIO PWRCTRL Mask */
|
||||||
|
#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
|
||||||
|
|
||||||
|
/* --- DCTRL Register ---*/
|
||||||
|
|
||||||
|
/* SDIO DCTRL Clear Mask */
|
||||||
|
#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
|
||||||
|
|
||||||
|
/* --- CMD Register ---*/
|
||||||
|
|
||||||
|
/* CMD Register clear mask */
|
||||||
|
#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
|
||||||
|
|
||||||
|
/* SDIO RESP Registers Address */
|
||||||
|
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SDIO_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the SDIO peripheral registers to their default reset values.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_DeInit(void)
|
||||||
|
{
|
||||||
|
SDIO->POWER = 0x00000000;
|
||||||
|
SDIO->CLKCR = 0x00000000;
|
||||||
|
SDIO->ARG = 0x00000000;
|
||||||
|
SDIO->CMD = 0x00000000;
|
||||||
|
SDIO->DTIMER = 0x00000000;
|
||||||
|
SDIO->DLEN = 0x00000000;
|
||||||
|
SDIO->DCTRL = 0x00000000;
|
||||||
|
SDIO->ICR = 0x00C007FF;
|
||||||
|
SDIO->MASK = 0x00000000;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the SDIO peripheral according to the specified
|
||||||
|
* parameters in the SDIO_InitStruct.
|
||||||
|
* @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
|
||||||
|
* that contains the configuration information for the SDIO peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
|
||||||
|
assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
|
||||||
|
assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
|
||||||
|
assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
|
||||||
|
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
|
||||||
|
|
||||||
|
/*---------------------------- SDIO CLKCR Configuration ------------------------*/
|
||||||
|
/* Get the SDIO CLKCR value */
|
||||||
|
tmpreg = SDIO->CLKCR;
|
||||||
|
|
||||||
|
/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
|
||||||
|
tmpreg &= CLKCR_CLEAR_MASK;
|
||||||
|
|
||||||
|
/* Set CLKDIV bits according to SDIO_ClockDiv value */
|
||||||
|
/* Set PWRSAV bit according to SDIO_ClockPowerSave value */
|
||||||
|
/* Set BYPASS bit according to SDIO_ClockBypass value */
|
||||||
|
/* Set WIDBUS bits according to SDIO_BusWide value */
|
||||||
|
/* Set NEGEDGE bits according to SDIO_ClockEdge value */
|
||||||
|
/* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
|
||||||
|
tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
|
||||||
|
SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
|
||||||
|
SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
|
||||||
|
|
||||||
|
/* Write to SDIO CLKCR */
|
||||||
|
SDIO->CLKCR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each SDIO_InitStruct member with its default value.
|
||||||
|
* @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
|
||||||
|
* will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
|
||||||
|
{
|
||||||
|
/* SDIO_InitStruct members default value */
|
||||||
|
SDIO_InitStruct->SDIO_ClockDiv = 0x00;
|
||||||
|
SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
|
||||||
|
SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
|
||||||
|
SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
|
||||||
|
SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
|
||||||
|
SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the SDIO Clock.
|
||||||
|
* @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_ClockCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the power status of the controller.
|
||||||
|
* @param SDIO_PowerState: new state of the Power state.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SDIO_PowerState_OFF
|
||||||
|
* @arg SDIO_PowerState_ON
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
|
||||||
|
|
||||||
|
SDIO->POWER &= PWR_PWRCTRL_MASK;
|
||||||
|
SDIO->POWER |= SDIO_PowerState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Gets the power status of the controller.
|
||||||
|
* @param None
|
||||||
|
* @retval Power status of the controller. The returned value can
|
||||||
|
* be one of the following:
|
||||||
|
* - 0x00: Power OFF
|
||||||
|
* - 0x02: Power UP
|
||||||
|
* - 0x03: Power ON
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetPowerState(void)
|
||||||
|
{
|
||||||
|
return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the SDIO interrupts.
|
||||||
|
* @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||||
|
* bus mode interrupt
|
||||||
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||||
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||||
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
||||||
|
* @param NewState: new state of the specified SDIO interrupts.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_IT(SDIO_IT));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the SDIO interrupts */
|
||||||
|
SDIO->MASK |= SDIO_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the SDIO interrupts */
|
||||||
|
SDIO->MASK &= ~SDIO_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the SDIO DMA request.
|
||||||
|
* @param NewState: new state of the selected SDIO DMA request.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_DMACmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the SDIO Command according to the specified
|
||||||
|
* parameters in the SDIO_CmdInitStruct and send the command.
|
||||||
|
* @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
|
||||||
|
* structure that contains the configuration information for the SDIO command.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
|
||||||
|
assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
|
||||||
|
assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
|
||||||
|
assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
|
||||||
|
|
||||||
|
/*---------------------------- SDIO ARG Configuration ------------------------*/
|
||||||
|
/* Set the SDIO Argument value */
|
||||||
|
SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
|
||||||
|
|
||||||
|
/*---------------------------- SDIO CMD Configuration ------------------------*/
|
||||||
|
/* Get the SDIO CMD value */
|
||||||
|
tmpreg = SDIO->CMD;
|
||||||
|
/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
|
||||||
|
tmpreg &= CMD_CLEAR_MASK;
|
||||||
|
/* Set CMDINDEX bits according to SDIO_CmdIndex value */
|
||||||
|
/* Set WAITRESP bits according to SDIO_Response value */
|
||||||
|
/* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
|
||||||
|
/* Set CPSMEN bits according to SDIO_CPSM value */
|
||||||
|
tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
|
||||||
|
| SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
|
||||||
|
|
||||||
|
/* Write to SDIO CMD */
|
||||||
|
SDIO->CMD = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each SDIO_CmdInitStruct member with its default value.
|
||||||
|
* @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
|
||||||
|
{
|
||||||
|
/* SDIO_CmdInitStruct members default value */
|
||||||
|
SDIO_CmdInitStruct->SDIO_Argument = 0x00;
|
||||||
|
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
|
||||||
|
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
|
||||||
|
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
|
||||||
|
SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns command index of last command for which response received.
|
||||||
|
* @param None
|
||||||
|
* @retval Returns the command index of the last command response received.
|
||||||
|
*/
|
||||||
|
uint8_t SDIO_GetCommandResponse(void)
|
||||||
|
{
|
||||||
|
return (uint8_t)(SDIO->RESPCMD);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns response received from the card for the last command.
|
||||||
|
* @param SDIO_RESP: Specifies the SDIO response register.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SDIO_RESP1: Response Register 1
|
||||||
|
* @arg SDIO_RESP2: Response Register 2
|
||||||
|
* @arg SDIO_RESP3: Response Register 3
|
||||||
|
* @arg SDIO_RESP4: Response Register 4
|
||||||
|
* @retval The Corresponding response register value.
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_RESP(SDIO_RESP));
|
||||||
|
|
||||||
|
tmp = SDIO_RESP_ADDR + SDIO_RESP;
|
||||||
|
|
||||||
|
return (*(__IO uint32_t *) tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the SDIO data path according to the specified
|
||||||
|
* parameters in the SDIO_DataInitStruct.
|
||||||
|
* @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
|
||||||
|
* contains the configuration information for the SDIO command.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
|
||||||
|
assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
|
||||||
|
assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
|
||||||
|
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
|
||||||
|
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
|
||||||
|
|
||||||
|
/*---------------------------- SDIO DTIMER Configuration ---------------------*/
|
||||||
|
/* Set the SDIO Data TimeOut value */
|
||||||
|
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
|
||||||
|
|
||||||
|
/*---------------------------- SDIO DLEN Configuration -----------------------*/
|
||||||
|
/* Set the SDIO DataLength value */
|
||||||
|
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
|
||||||
|
|
||||||
|
/*---------------------------- SDIO DCTRL Configuration ----------------------*/
|
||||||
|
/* Get the SDIO DCTRL value */
|
||||||
|
tmpreg = SDIO->DCTRL;
|
||||||
|
/* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
|
||||||
|
tmpreg &= DCTRL_CLEAR_MASK;
|
||||||
|
/* Set DEN bit according to SDIO_DPSM value */
|
||||||
|
/* Set DTMODE bit according to SDIO_TransferMode value */
|
||||||
|
/* Set DTDIR bit according to SDIO_TransferDir value */
|
||||||
|
/* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
|
||||||
|
tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
|
||||||
|
| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
|
||||||
|
|
||||||
|
/* Write to SDIO DCTRL */
|
||||||
|
SDIO->DCTRL = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each SDIO_DataInitStruct member with its default value.
|
||||||
|
* @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
|
||||||
|
* will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
||||||
|
{
|
||||||
|
/* SDIO_DataInitStruct members default value */
|
||||||
|
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
|
||||||
|
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
|
||||||
|
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
|
||||||
|
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
|
||||||
|
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
|
||||||
|
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns number of remaining data bytes to be transferred.
|
||||||
|
* @param None
|
||||||
|
* @retval Number of remaining data bytes to be transferred
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetDataCounter(void)
|
||||||
|
{
|
||||||
|
return SDIO->DCOUNT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read one data word from Rx FIFO.
|
||||||
|
* @param None
|
||||||
|
* @retval Data received
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_ReadData(void)
|
||||||
|
{
|
||||||
|
return SDIO->FIFO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write one data word to Tx FIFO.
|
||||||
|
* @param Data: 32-bit data word to write.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_WriteData(uint32_t Data)
|
||||||
|
{
|
||||||
|
SDIO->FIFO = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the number of words left to be written to or read from FIFO.
|
||||||
|
* @param None
|
||||||
|
* @retval Remaining number of words.
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetFIFOCount(void)
|
||||||
|
{
|
||||||
|
return SDIO->FIFOCNT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Starts the SD I/O Read Wait operation.
|
||||||
|
* @param NewState: new state of the Start SDIO Read Wait operation.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_StartSDIOReadWait(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stops the SD I/O Read Wait operation.
|
||||||
|
* @param NewState: new state of the Stop SDIO Read Wait operation.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_StopSDIOReadWait(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets one of the two options of inserting read wait interval.
|
||||||
|
* @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
|
||||||
|
* This parameter can be:
|
||||||
|
* @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
|
||||||
|
* @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the SD I/O Mode Operation.
|
||||||
|
* @param NewState: new state of SDIO specific operation.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_SetSDIOOperation(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the SD I/O Mode suspend command sending.
|
||||||
|
* @param NewState: new state of the SD I/O Mode suspend command.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the command completion signal.
|
||||||
|
* @param NewState: new state of command completion signal.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_CommandCompletionCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the CE-ATA interrupt.
|
||||||
|
* @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_CEATAITCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sends CE-ATA command (CMD61).
|
||||||
|
* @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_SendCEATACmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
|
||||||
|
*(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified SDIO flag is set or not.
|
||||||
|
* @param SDIO_FLAG: specifies the flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||||
|
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||||
|
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||||
|
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||||
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||||
|
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||||
|
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
|
||||||
|
* bus mode.
|
||||||
|
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
|
||||||
|
* @arg SDIO_FLAG_TXACT: Data transmit in progress
|
||||||
|
* @arg SDIO_FLAG_RXACT: Data receive in progress
|
||||||
|
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
|
||||||
|
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
|
||||||
|
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
|
||||||
|
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
|
||||||
|
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
|
||||||
|
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
|
||||||
|
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
|
||||||
|
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
|
||||||
|
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||||
|
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||||
|
* @retval The new state of SDIO_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_FLAG(SDIO_FLAG));
|
||||||
|
|
||||||
|
if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the SDIO's pending flags.
|
||||||
|
* @param SDIO_FLAG: specifies the flag to clear.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
|
||||||
|
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
|
||||||
|
* @arg SDIO_FLAG_DTIMEOUT: Data timeout
|
||||||
|
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
|
||||||
|
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
|
||||||
|
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
|
||||||
|
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
|
||||||
|
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
|
||||||
|
* bus mode
|
||||||
|
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
|
||||||
|
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
|
||||||
|
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
|
||||||
|
|
||||||
|
SDIO->ICR = SDIO_FLAG;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified SDIO interrupt has occurred or not.
|
||||||
|
* @param SDIO_IT: specifies the SDIO interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||||
|
* bus mode interrupt
|
||||||
|
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
|
||||||
|
* @arg SDIO_IT_RXACT: Data receive in progress interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
|
||||||
|
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
|
||||||
|
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
|
||||||
|
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
|
||||||
|
* @retval The new state of SDIO_IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_GET_IT(SDIO_IT));
|
||||||
|
if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the SDIO's interrupt pending bits.
|
||||||
|
* @param SDIO_IT: specifies the interrupt pending bit to clear.
|
||||||
|
* This parameter can be one or a combination of the following values:
|
||||||
|
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
|
||||||
|
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
|
||||||
|
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
|
||||||
|
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
|
||||||
|
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
|
||||||
|
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
|
||||||
|
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
|
||||||
|
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||||
|
* bus mode interrupt
|
||||||
|
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
|
||||||
|
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
|
||||||
|
|
||||||
|
SDIO->ICR = SDIO_IT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,908 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_spi.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the SPI firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_spi.h"
|
||||||
|
#include "stm32f10x_rcc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI
|
||||||
|
* @brief SPI driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup SPI_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* SPI SPE mask */
|
||||||
|
#define CR1_SPE_Set ((uint16_t)0x0040)
|
||||||
|
#define CR1_SPE_Reset ((uint16_t)0xFFBF)
|
||||||
|
|
||||||
|
/* I2S I2SE mask */
|
||||||
|
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
|
||||||
|
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
|
||||||
|
|
||||||
|
/* SPI CRCNext mask */
|
||||||
|
#define CR1_CRCNext_Set ((uint16_t)0x1000)
|
||||||
|
|
||||||
|
/* SPI CRCEN mask */
|
||||||
|
#define CR1_CRCEN_Set ((uint16_t)0x2000)
|
||||||
|
#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)
|
||||||
|
|
||||||
|
/* SPI SSOE mask */
|
||||||
|
#define CR2_SSOE_Set ((uint16_t)0x0004)
|
||||||
|
#define CR2_SSOE_Reset ((uint16_t)0xFFFB)
|
||||||
|
|
||||||
|
/* SPI registers Masks */
|
||||||
|
#define CR1_CLEAR_Mask ((uint16_t)0x3040)
|
||||||
|
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
|
||||||
|
|
||||||
|
/* SPI or I2S mode selection masks */
|
||||||
|
#define SPI_Mode_Select ((uint16_t)0xF7FF)
|
||||||
|
#define I2S_Mode_Select ((uint16_t)0x0800)
|
||||||
|
|
||||||
|
/* I2S clock source selection masks */
|
||||||
|
#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
|
||||||
|
#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
|
||||||
|
#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
|
||||||
|
#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SPI_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the SPIx peripheral registers to their default
|
||||||
|
* reset values (Affects also the I2Ss).
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
|
||||||
|
if (SPIx == SPI1)
|
||||||
|
{
|
||||||
|
/* Enable SPI1 reset state */
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
|
||||||
|
/* Release SPI1 from reset state */
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
|
||||||
|
}
|
||||||
|
else if (SPIx == SPI2)
|
||||||
|
{
|
||||||
|
/* Enable SPI2 reset state */
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
|
||||||
|
/* Release SPI2 from reset state */
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (SPIx == SPI3)
|
||||||
|
{
|
||||||
|
/* Enable SPI3 reset state */
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
|
||||||
|
/* Release SPI3 from reset state */
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the SPIx peripheral according to the specified
|
||||||
|
* parameters in the SPI_InitStruct.
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0;
|
||||||
|
|
||||||
|
/* check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
|
||||||
|
/* Check the SPI parameters */
|
||||||
|
assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
|
||||||
|
assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
|
||||||
|
assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
|
||||||
|
assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
|
||||||
|
assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
|
||||||
|
assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
|
||||||
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
|
||||||
|
assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
|
||||||
|
assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
|
||||||
|
|
||||||
|
/*---------------------------- SPIx CR1 Configuration ------------------------*/
|
||||||
|
/* Get the SPIx CR1 value */
|
||||||
|
tmpreg = SPIx->CR1;
|
||||||
|
/* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
|
||||||
|
tmpreg &= CR1_CLEAR_Mask;
|
||||||
|
/* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
|
||||||
|
master/salve mode, CPOL and CPHA */
|
||||||
|
/* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
|
||||||
|
/* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
|
||||||
|
/* Set LSBFirst bit according to SPI_FirstBit value */
|
||||||
|
/* Set BR bits according to SPI_BaudRatePrescaler value */
|
||||||
|
/* Set CPOL bit according to SPI_CPOL value */
|
||||||
|
/* Set CPHA bit according to SPI_CPHA value */
|
||||||
|
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
|
||||||
|
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
|
||||||
|
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
|
||||||
|
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
|
||||||
|
/* Write to SPIx CR1 */
|
||||||
|
SPIx->CR1 = tmpreg;
|
||||||
|
|
||||||
|
/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
|
||||||
|
SPIx->I2SCFGR &= SPI_Mode_Select;
|
||||||
|
|
||||||
|
/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
|
||||||
|
/* Write to SPIx CRCPOLY */
|
||||||
|
SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initializes the SPIx peripheral according to the specified
|
||||||
|
* parameters in the I2S_InitStruct.
|
||||||
|
* @param SPIx: where x can be 2 or 3 to select the SPI peripheral
|
||||||
|
* (configured in I2S mode).
|
||||||
|
* @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified SPI peripheral
|
||||||
|
* configured in I2S mode.
|
||||||
|
* @note
|
||||||
|
* The function calculates the optimal prescaler needed to obtain the most
|
||||||
|
* accurate audio frequency (depending on the I2S clock source, the PLL values
|
||||||
|
* and the product configuration). But in case the prescaler value is greater
|
||||||
|
* than 511, the default value (0x02) will be configured instead. *
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
|
||||||
|
uint32_t tmp = 0;
|
||||||
|
RCC_ClocksTypeDef RCC_Clocks;
|
||||||
|
uint32_t sourceclock = 0;
|
||||||
|
|
||||||
|
/* Check the I2S parameters */
|
||||||
|
assert_param(IS_SPI_23_PERIPH(SPIx));
|
||||||
|
assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
|
||||||
|
assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
|
||||||
|
assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
|
||||||
|
assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
|
||||||
|
assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
|
||||||
|
assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
|
||||||
|
|
||||||
|
/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
|
||||||
|
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
|
||||||
|
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
|
||||||
|
SPIx->I2SPR = 0x0002;
|
||||||
|
|
||||||
|
/* Get the I2SCFGR register value */
|
||||||
|
tmpreg = SPIx->I2SCFGR;
|
||||||
|
|
||||||
|
/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
|
||||||
|
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
|
||||||
|
{
|
||||||
|
i2sodd = (uint16_t)0;
|
||||||
|
i2sdiv = (uint16_t)2;
|
||||||
|
}
|
||||||
|
/* If the requested audio frequency is not the default, compute the prescaler */
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Check the frame length (For the Prescaler computing) */
|
||||||
|
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
|
||||||
|
{
|
||||||
|
/* Packet length is 16 bits */
|
||||||
|
packetlength = 1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Packet length is 32 bits */
|
||||||
|
packetlength = 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get the I2S clock source mask depending on the peripheral number */
|
||||||
|
if(((uint32_t)SPIx) == SPI2_BASE)
|
||||||
|
{
|
||||||
|
/* The mask is relative to I2S2 */
|
||||||
|
tmp = I2S2_CLOCK_SRC;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* The mask is relative to I2S3 */
|
||||||
|
tmp = I2S3_CLOCK_SRC;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the I2S clock source configuration depending on the Device:
|
||||||
|
Only Connectivity line devices have the PLL3 VCO clock */
|
||||||
|
#ifdef STM32F10X_CL
|
||||||
|
if((RCC->CFGR2 & tmp) != 0)
|
||||||
|
{
|
||||||
|
/* Get the configuration bits of RCC PLL3 multiplier */
|
||||||
|
tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
|
||||||
|
|
||||||
|
/* Get the value of the PLL3 multiplier */
|
||||||
|
if((tmp > 5) && (tmp < 15))
|
||||||
|
{
|
||||||
|
/* Multiplier is between 8 and 14 (value 15 is forbidden) */
|
||||||
|
tmp += 2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (tmp == 15)
|
||||||
|
{
|
||||||
|
/* Multiplier is 20 */
|
||||||
|
tmp = 20;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Get the PREDIV2 value */
|
||||||
|
sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
|
||||||
|
|
||||||
|
/* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
|
||||||
|
sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* I2S Clock source is System clock: Get System Clock frequency */
|
||||||
|
RCC_GetClocksFreq(&RCC_Clocks);
|
||||||
|
|
||||||
|
/* Get the source clock value: based on System Clock value */
|
||||||
|
sourceclock = RCC_Clocks.SYSCLK_Frequency;
|
||||||
|
}
|
||||||
|
#else /* STM32F10X_HD */
|
||||||
|
/* I2S Clock source is System clock: Get System Clock frequency */
|
||||||
|
RCC_GetClocksFreq(&RCC_Clocks);
|
||||||
|
|
||||||
|
/* Get the source clock value: based on System Clock value */
|
||||||
|
sourceclock = RCC_Clocks.SYSCLK_Frequency;
|
||||||
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
/* Compute the Real divider depending on the MCLK output state with a floating point */
|
||||||
|
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
|
||||||
|
{
|
||||||
|
/* MCLK output is enabled */
|
||||||
|
tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* MCLK output is disabled */
|
||||||
|
tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Remove the floating point */
|
||||||
|
tmp = tmp / 10;
|
||||||
|
|
||||||
|
/* Check the parity of the divider */
|
||||||
|
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
|
||||||
|
|
||||||
|
/* Compute the i2sdiv prescaler */
|
||||||
|
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
|
||||||
|
|
||||||
|
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
|
||||||
|
i2sodd = (uint16_t) (i2sodd << 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
||||||
|
if ((i2sdiv < 2) || (i2sdiv > 0xFF))
|
||||||
|
{
|
||||||
|
/* Set the default values */
|
||||||
|
i2sdiv = 2;
|
||||||
|
i2sodd = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Write to SPIx I2SPR register the computed value */
|
||||||
|
SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
|
||||||
|
|
||||||
|
/* Configure the I2S with the SPI_InitStruct values */
|
||||||
|
tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
|
||||||
|
(uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
|
||||||
|
(uint16_t)I2S_InitStruct->I2S_CPOL))));
|
||||||
|
|
||||||
|
/* Write to SPIx I2SCFGR */
|
||||||
|
SPIx->I2SCFGR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each SPI_InitStruct member with its default value.
|
||||||
|
* @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
|
||||||
|
{
|
||||||
|
/*--------------- Reset SPI init structure parameters values -----------------*/
|
||||||
|
/* Initialize the SPI_Direction member */
|
||||||
|
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||||
|
/* initialize the SPI_Mode member */
|
||||||
|
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
|
||||||
|
/* initialize the SPI_DataSize member */
|
||||||
|
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
|
||||||
|
/* Initialize the SPI_CPOL member */
|
||||||
|
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
|
||||||
|
/* Initialize the SPI_CPHA member */
|
||||||
|
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
|
||||||
|
/* Initialize the SPI_NSS member */
|
||||||
|
SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
|
||||||
|
/* Initialize the SPI_BaudRatePrescaler member */
|
||||||
|
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||||
|
/* Initialize the SPI_FirstBit member */
|
||||||
|
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
|
||||||
|
/* Initialize the SPI_CRCPolynomial member */
|
||||||
|
SPI_InitStruct->SPI_CRCPolynomial = 7;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Fills each I2S_InitStruct member with its default value.
|
||||||
|
* @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
|
||||||
|
{
|
||||||
|
/*--------------- Reset I2S init structure parameters values -----------------*/
|
||||||
|
/* Initialize the I2S_Mode member */
|
||||||
|
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
|
||||||
|
|
||||||
|
/* Initialize the I2S_Standard member */
|
||||||
|
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
|
||||||
|
|
||||||
|
/* Initialize the I2S_DataFormat member */
|
||||||
|
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
|
||||||
|
|
||||||
|
/* Initialize the I2S_MCLKOutput member */
|
||||||
|
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
|
||||||
|
|
||||||
|
/* Initialize the I2S_AudioFreq member */
|
||||||
|
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
|
||||||
|
|
||||||
|
/* Initialize the I2S_CPOL member */
|
||||||
|
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified SPI peripheral.
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @param NewState: new state of the SPIx peripheral.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected SPI peripheral */
|
||||||
|
SPIx->CR1 |= CR1_SPE_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected SPI peripheral */
|
||||||
|
SPIx->CR1 &= CR1_SPE_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
|
||||||
|
* @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
|
||||||
|
* @param NewState: new state of the SPIx peripheral.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_23_PERIPH(SPIx));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected SPI peripheral (in I2S mode) */
|
||||||
|
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected SPI peripheral (in I2S mode) */
|
||||||
|
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the specified SPI/I2S interrupts.
|
||||||
|
* @param SPIx: where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode
|
||||||
|
* - 2 or 3 in I2S mode
|
||||||
|
* @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
|
||||||
|
* @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
|
||||||
|
* @arg SPI_I2S_IT_ERR: Error interrupt mask
|
||||||
|
* @param NewState: new state of the specified SPI/I2S interrupt.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
uint16_t itpos = 0, itmask = 0 ;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
|
||||||
|
|
||||||
|
/* Get the SPI/I2S IT index */
|
||||||
|
itpos = SPI_I2S_IT >> 4;
|
||||||
|
|
||||||
|
/* Set the IT mask */
|
||||||
|
itmask = (uint16_t)1 << (uint16_t)itpos;
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected SPI/I2S interrupt */
|
||||||
|
SPIx->CR2 |= itmask;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected SPI/I2S interrupt */
|
||||||
|
SPIx->CR2 &= (uint16_t)~itmask;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the SPIx/I2Sx DMA interface.
|
||||||
|
* @param SPIx: where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode
|
||||||
|
* - 2 or 3 in I2S mode
|
||||||
|
* @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
|
||||||
|
* @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
|
||||||
|
* @param NewState: new state of the selected SPI/I2S DMA transfer request.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected SPI/I2S DMA requests */
|
||||||
|
SPIx->CR2 |= SPI_I2S_DMAReq;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected SPI/I2S DMA requests */
|
||||||
|
SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
|
||||||
|
* @param SPIx: where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode
|
||||||
|
* - 2 or 3 in I2S mode
|
||||||
|
* @param Data : Data to be transmitted.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
|
||||||
|
/* Write in the DR register the data to be sent */
|
||||||
|
SPIx->DR = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
|
||||||
|
* @param SPIx: where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode
|
||||||
|
* - 2 or 3 in I2S mode
|
||||||
|
* @retval The value of the received data.
|
||||||
|
*/
|
||||||
|
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
|
||||||
|
/* Return the data in the DR register */
|
||||||
|
return SPIx->DR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures internally by software the NSS pin for the selected SPI.
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
|
||||||
|
* @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
|
||||||
|
if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
|
||||||
|
{
|
||||||
|
/* Set NSS pin internally by software */
|
||||||
|
SPIx->CR1 |= SPI_NSSInternalSoft_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Reset NSS pin internally by software */
|
||||||
|
SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the SS output for the selected SPI.
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @param NewState: new state of the SPIx SS output.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected SPI SS output */
|
||||||
|
SPIx->CR2 |= CR2_SSOE_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected SPI SS output */
|
||||||
|
SPIx->CR2 &= CR2_SSOE_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configures the data size for the selected SPI.
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @param SPI_DataSize: specifies the SPI data size.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_DataSize_16b: Set data frame format to 16bit
|
||||||
|
* @arg SPI_DataSize_8b: Set data frame format to 8bit
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_SPI_DATASIZE(SPI_DataSize));
|
||||||
|
/* Clear DFF bit */
|
||||||
|
SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
|
||||||
|
/* Set new DFF bit value */
|
||||||
|
SPIx->CR1 |= SPI_DataSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Transmit the SPIx CRC value.
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_TransmitCRC(SPI_TypeDef* SPIx)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
|
||||||
|
/* Enable the selected SPI CRC transmission */
|
||||||
|
SPIx->CR1 |= CR1_CRCNext_Set;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables or disables the CRC value calculation of the transferred bytes.
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @param NewState: new state of the SPIx CRC value calculation.
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
/* Enable the selected SPI CRC calculation */
|
||||||
|
SPIx->CR1 |= CR1_CRCEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the selected SPI CRC calculation */
|
||||||
|
SPIx->CR1 &= CR1_CRCEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @param SPI_CRC: specifies the CRC register to be read.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_CRC_Tx: Selects Tx CRC register
|
||||||
|
* @arg SPI_CRC_Rx: Selects Rx CRC register
|
||||||
|
* @retval The selected CRC register value..
|
||||||
|
*/
|
||||||
|
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
|
||||||
|
{
|
||||||
|
uint16_t crcreg = 0;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_SPI_CRC(SPI_CRC));
|
||||||
|
if (SPI_CRC != SPI_CRC_Rx)
|
||||||
|
{
|
||||||
|
/* Get the Tx CRC register */
|
||||||
|
crcreg = SPIx->TXCRCR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Get the Rx CRC register */
|
||||||
|
crcreg = SPIx->RXCRCR;
|
||||||
|
}
|
||||||
|
/* Return the selected CRC register */
|
||||||
|
return crcreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the CRC Polynomial register value for the specified SPI.
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @retval The CRC Polynomial register value.
|
||||||
|
*/
|
||||||
|
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
|
||||||
|
/* Return the CRC polynomial register */
|
||||||
|
return SPIx->CRCPR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
|
||||||
|
* @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* @param SPI_Direction: specifies the data transfer direction in bi-directional mode.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_Direction_Tx: Selects Tx transmission direction
|
||||||
|
* @arg SPI_Direction_Rx: Selects Rx receive direction
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_SPI_DIRECTION(SPI_Direction));
|
||||||
|
if (SPI_Direction == SPI_Direction_Tx)
|
||||||
|
{
|
||||||
|
/* Set the Tx only mode */
|
||||||
|
SPIx->CR1 |= SPI_Direction_Tx;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Set the Rx only mode */
|
||||||
|
SPIx->CR1 &= SPI_Direction_Rx;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified SPI/I2S flag is set or not.
|
||||||
|
* @param SPIx: where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode
|
||||||
|
* - 2 or 3 in I2S mode
|
||||||
|
* @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
|
||||||
|
* @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
|
||||||
|
* @arg SPI_I2S_FLAG_BSY: Busy flag.
|
||||||
|
* @arg SPI_I2S_FLAG_OVR: Overrun flag.
|
||||||
|
* @arg SPI_FLAG_MODF: Mode Fault flag.
|
||||||
|
* @arg SPI_FLAG_CRCERR: CRC Error flag.
|
||||||
|
* @arg I2S_FLAG_UDR: Underrun Error flag.
|
||||||
|
* @arg I2S_FLAG_CHSIDE: Channel Side flag.
|
||||||
|
* @retval The new state of SPI_I2S_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
|
||||||
|
/* Check the status of the specified SPI/I2S flag */
|
||||||
|
if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
/* SPI_I2S_FLAG is set */
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* SPI_I2S_FLAG is reset */
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
/* Return the SPI_I2S_FLAG status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the SPIx CRC Error (CRCERR) flag.
|
||||||
|
* @param SPIx: where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode
|
||||||
|
* @param SPI_I2S_FLAG: specifies the SPI flag to clear.
|
||||||
|
* This function clears only CRCERR flag.
|
||||||
|
* @note
|
||||||
|
* - OVR (OverRun error) flag is cleared by software sequence: a read
|
||||||
|
* operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
|
||||||
|
* operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
|
||||||
|
* - UDR (UnderRun error) flag is cleared by a read operation to
|
||||||
|
* SPI_SR register (SPI_I2S_GetFlagStatus()).
|
||||||
|
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
|
||||||
|
* operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
|
||||||
|
* write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
|
||||||
|
|
||||||
|
/* Clear the selected SPI CRC Error (CRCERR) flag */
|
||||||
|
SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
|
||||||
|
* @param SPIx: where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode
|
||||||
|
* - 2 or 3 in I2S mode
|
||||||
|
* @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
|
||||||
|
* @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
|
||||||
|
* @arg SPI_I2S_IT_OVR: Overrun interrupt.
|
||||||
|
* @arg SPI_IT_MODF: Mode Fault interrupt.
|
||||||
|
* @arg SPI_IT_CRCERR: CRC Error interrupt.
|
||||||
|
* @arg I2S_IT_UDR: Underrun Error interrupt.
|
||||||
|
* @retval The new state of SPI_I2S_IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
|
||||||
|
|
||||||
|
/* Get the SPI/I2S IT index */
|
||||||
|
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||||
|
|
||||||
|
/* Get the SPI/I2S IT mask */
|
||||||
|
itmask = SPI_I2S_IT >> 4;
|
||||||
|
|
||||||
|
/* Set the IT mask */
|
||||||
|
itmask = 0x01 << itmask;
|
||||||
|
|
||||||
|
/* Get the SPI_I2S_IT enable bit status */
|
||||||
|
enablestatus = (SPIx->CR2 & itmask) ;
|
||||||
|
|
||||||
|
/* Check the status of the specified SPI/I2S interrupt */
|
||||||
|
if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
|
||||||
|
{
|
||||||
|
/* SPI_I2S_IT is set */
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* SPI_I2S_IT is reset */
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
/* Return the SPI_I2S_IT status */
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
|
||||||
|
* @param SPIx: where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode
|
||||||
|
* @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
|
||||||
|
* This function clears only CRCERR interrupt pending bit.
|
||||||
|
* @note
|
||||||
|
* - OVR (OverRun Error) interrupt pending bit is cleared by software
|
||||||
|
* sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
|
||||||
|
* followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
|
||||||
|
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
|
||||||
|
* operation to SPI_SR register (SPI_I2S_GetITStatus()).
|
||||||
|
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
|
||||||
|
* a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
|
||||||
|
* followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
|
||||||
|
* the SPI).
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
|
||||||
|
{
|
||||||
|
uint16_t itpos = 0;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
||||||
|
assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
|
||||||
|
|
||||||
|
/* Get the SPI IT index */
|
||||||
|
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||||
|
|
||||||
|
/* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
|
||||||
|
SPIx->SR = (uint16_t)~itpos;
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,224 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f10x_wwdg.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @version V3.5.0
|
||||||
|
* @date 11-March-2011
|
||||||
|
* @brief This file provides all the WWDG firmware functions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
|
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f10x_wwdg.h"
|
||||||
|
#include "stm32f10x_rcc.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F10x_StdPeriph_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG
|
||||||
|
* @brief WWDG driver modules
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ----------- WWDG registers bit address in the alias region ----------- */
|
||||||
|
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
|
||||||
|
|
||||||
|
/* Alias word address of EWI bit */
|
||||||
|
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
|
||||||
|
#define EWI_BitNumber 0x09
|
||||||
|
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
|
||||||
|
|
||||||
|
/* --------------------- WWDG registers bit mask ------------------------ */
|
||||||
|
|
||||||
|
/* CR register bit mask */
|
||||||
|
#define CR_WDGA_Set ((uint32_t)0x00000080)
|
||||||
|
|
||||||
|
/* CFR register bit mask */
|
||||||
|
#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
|
||||||
|
#define CFR_W_Mask ((uint32_t)0xFFFFFF80)
|
||||||
|
#define BIT_Mask ((uint8_t)0x7F)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup WWDG_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void WWDG_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the WWDG Prescaler.
|
||||||
|
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
|
||||||
|
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
|
||||||
|
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
|
||||||
|
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
|
||||||
|
/* Clear WDGTB[1:0] bits */
|
||||||
|
tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
|
||||||
|
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
|
||||||
|
tmpreg |= WWDG_Prescaler;
|
||||||
|
/* Store the new value */
|
||||||
|
WWDG->CFR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the WWDG window value.
|
||||||
|
* @param WindowValue: specifies the window value to be compared to the downcounter.
|
||||||
|
* This parameter value must be lower than 0x80.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void WWDG_SetWindowValue(uint8_t WindowValue)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
|
||||||
|
/* Clear W[6:0] bits */
|
||||||
|
|
||||||
|
tmpreg = WWDG->CFR & CFR_W_Mask;
|
||||||
|
|
||||||
|
/* Set W[6:0] bits according to WindowValue value */
|
||||||
|
tmpreg |= WindowValue & (uint32_t) BIT_Mask;
|
||||||
|
|
||||||
|
/* Store the new value */
|
||||||
|
WWDG->CFR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void WWDG_EnableIT(void)
|
||||||
|
{
|
||||||
|
*(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the WWDG counter value.
|
||||||
|
* @param Counter: specifies the watchdog counter value.
|
||||||
|
* This parameter must be a number between 0x40 and 0x7F.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void WWDG_SetCounter(uint8_t Counter)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_WWDG_COUNTER(Counter));
|
||||||
|
/* Write to T[6:0] bits to configure the counter value, no need to do
|
||||||
|
a read-modify-write; writing a 0 to WDGA bit does nothing */
|
||||||
|
WWDG->CR = Counter & BIT_Mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables WWDG and load the counter value.
|
||||||
|
* @param Counter: specifies the watchdog counter value.
|
||||||
|
* This parameter must be a number between 0x40 and 0x7F.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void WWDG_Enable(uint8_t Counter)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_WWDG_COUNTER(Counter));
|
||||||
|
WWDG->CR = CR_WDGA_Set | Counter;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
|
||||||
|
* @param None
|
||||||
|
* @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
|
||||||
|
*/
|
||||||
|
FlagStatus WWDG_GetFlagStatus(void)
|
||||||
|
{
|
||||||
|
return (FlagStatus)(WWDG->SR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears Early Wakeup interrupt flag.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void WWDG_ClearFlag(void)
|
||||||
|
{
|
||||||
|
WWDG->SR = (uint32_t)RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
@ -0,0 +1,301 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#include "delay.h"
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
//如果需要使用OS,则包括下面的头文件即可.
|
||||||
|
#if SYSTEM_SUPPORT_OS
|
||||||
|
#include "includes.h" //ucos 使用
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static u8 fac_us=0; //us延时倍乘数
|
||||||
|
static u16 fac_ms=0; //ms延时倍乘数,在ucos下,代表每个节拍的ms数
|
||||||
|
|
||||||
|
#if SYSTEM_SUPPORT_OS //如果SYSTEM_SUPPORT_OS定义了,说明要支持OS了(不限于UCOS).
|
||||||
|
//当delay_us/delay_ms需要支持OS的时候需要三个与OS相关的宏定义和函数来支持
|
||||||
|
//首先是3个宏定义:
|
||||||
|
//delay_osrunning:用于表示OS当前是否正在运行,以决定是否可以使用相关函数
|
||||||
|
//delay_ostickspersec:用于表示OS设定的时钟节拍,delay_init将根据这个参数来初始哈systick
|
||||||
|
//delay_osintnesting:用于表示OS中断嵌套级别,因为中断里面不可以调度,delay_ms使用该参数来决定如何运行
|
||||||
|
//然后是3个函数:
|
||||||
|
//delay_osschedlock:用于锁定OS任务调度,禁止调度
|
||||||
|
//delay_osschedunlock:用于解锁OS任务调度,重新开启调度
|
||||||
|
//delay_ostimedly:用于OS延时,可以引起任务调度.
|
||||||
|
|
||||||
|
//本例程仅作UCOSII和UCOSIII的支持,其他OS,请自行参考着移植
|
||||||
|
//支持UCOSII
|
||||||
|
#ifdef OS_CRITICAL_METHOD //OS_CRITICAL_METHOD定义了,说明要支持UCOSII
|
||||||
|
#define delay_osrunning OSRunning //OS是否运行标记,0,不运行;1,在运行
|
||||||
|
#define delay_ostickspersec OS_TICKS_PER_SEC //OS时钟节拍,即每秒调度次数
|
||||||
|
#define delay_osintnesting OSIntNesting //中断嵌套级别,即中断嵌套次数
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//支持UCOSIII
|
||||||
|
#ifdef CPU_CFG_CRITICAL_METHOD //CPU_CFG_CRITICAL_METHOD定义了,说明要支持UCOSIII
|
||||||
|
#define delay_osrunning OSRunning //OS是否运行标记,0,不运行;1,在运行
|
||||||
|
#define delay_ostickspersec OSCfg_TickRate_Hz //OS时钟节拍,即每秒调度次数
|
||||||
|
#define delay_osintnesting OSIntNestingCtr //中断嵌套级别,即中断嵌套次数
|
||||||
|
#endif
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Turn off task scheduling when us level delay occurs (to prevent interruption of us level delay)
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：us级延时时,关闭任务调度(防止打断us级延迟)
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void delay_osschedlock(void)
|
||||||
|
{
|
||||||
|
#ifdef CPU_CFG_CRITICAL_METHOD //使用UCOSIII
|
||||||
|
OS_ERR err;
|
||||||
|
OSSchedLock(&err); //UCOSIII的方式,禁止调度，防止打断us延时
|
||||||
|
#else //否则UCOSII
|
||||||
|
OSSchedLock(); //UCOSII的方式,禁止调度，防止打断us延时
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Us level delay, resume task scheduling
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：us级延时,恢复任务调度
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void delay_osschedunlock(void)
|
||||||
|
{
|
||||||
|
#ifdef CPU_CFG_CRITICAL_METHOD //使用UCOSIII
|
||||||
|
OS_ERR err;
|
||||||
|
OSSchedUnlock(&err); //UCOSIII的方式,恢复调度
|
||||||
|
#else //否则UCOSII
|
||||||
|
OSSchedUnlock(); //UCOSII的方式,恢复调度
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Call the delay function of OS to delay
|
||||||
|
Input : ticks：Beat number of delay
|
||||||
|
Output : none
|
||||||
|
函数功能：调用OS自带的延时函数延时
|
||||||
|
入口参数：ticks:延时的节拍数
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void delay_ostimedly(u32 ticks)
|
||||||
|
{
|
||||||
|
#ifdef CPU_CFG_CRITICAL_METHOD
|
||||||
|
OS_ERR err;
|
||||||
|
OSTimeDly(ticks,OS_OPT_TIME_PERIODIC,&err); //UCOSIII延时采用周期模式
|
||||||
|
#else
|
||||||
|
OSTimeDly(ticks); //UCOSII延时
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: SYSTICK interrupts the service function for use with ucos
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：systick中断服务函数,使用ucos时用到
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{
|
||||||
|
if(delay_osrunning==1) //OS开始跑了,才执行正常的调度处理
|
||||||
|
{
|
||||||
|
OSIntEnter(); //进入中断
|
||||||
|
OSTimeTick(); //调用ucos的时钟服务程序
|
||||||
|
OSIntExit(); //触发任务切换软中断
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Initialize the delay function
|
||||||
|
Input : SYSCLK：System clock
|
||||||
|
Output : none
|
||||||
|
函数功能：初始化延迟函数
|
||||||
|
入口参数：SYSCLK:系统时钟
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
//当使用ucos的时候,此函数会初始化ucos的时钟节拍
|
||||||
|
//SYSTICK的时钟固定为HCLK时钟的1/8
|
||||||
|
void delay_init()
|
||||||
|
{
|
||||||
|
#if SYSTEM_SUPPORT_OS //如果需要支持OS.
|
||||||
|
u32 reload;
|
||||||
|
#endif
|
||||||
|
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8); //选择外部时钟 HCLK/8
|
||||||
|
fac_us=SystemCoreClock/8000000; //为系统时钟的1/8
|
||||||
|
#if SYSTEM_SUPPORT_OS //如果需要支持OS.
|
||||||
|
reload=SystemCoreClock/8000000; //每秒钟的计数次数 单位为M
|
||||||
|
reload*=1000000/delay_ostickspersec; //根据delay_ostickspersec设定溢出时间
|
||||||
|
//reload为24位寄存器,最大值:16777216,在72M下,约合1.86s左右
|
||||||
|
fac_ms=1000/delay_ostickspersec; //代表OS可以延时的最少单位
|
||||||
|
|
||||||
|
SysTick->CTRL|=SysTick_CTRL_TICKINT_Msk; //开启SYSTICK中断
|
||||||
|
SysTick->LOAD=reload; //每1/delay_ostickspersec秒中断一次
|
||||||
|
SysTick->CTRL|=SysTick_CTRL_ENABLE_Msk; //开启SYSTICK
|
||||||
|
|
||||||
|
#else
|
||||||
|
fac_ms=(u16)fac_us*1000; //非OS下,代表每个ms需要的systick时钟数
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#if SYSTEM_SUPPORT_OS //如果需要支持OS.
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Delay function（us）
|
||||||
|
Input : nus：The number of us to delay
|
||||||
|
Output : none
|
||||||
|
函数功能：延时函数（us）
|
||||||
|
入口参数：nus：要延时的us数
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void delay_us(u32 nus)
|
||||||
|
{
|
||||||
|
u32 ticks;
|
||||||
|
u32 told,tnow,tcnt=0;
|
||||||
|
u32 reload=SysTick->LOAD; //LOAD的值
|
||||||
|
ticks=nus*fac_us; //需要的节拍数
|
||||||
|
tcnt=0;
|
||||||
|
delay_osschedlock(); //阻止OS调度，防止打断us延时
|
||||||
|
told=SysTick->VAL; //刚进入时的计数器值
|
||||||
|
while(1)
|
||||||
|
{
|
||||||
|
tnow=SysTick->VAL;
|
||||||
|
if(tnow!=told)
|
||||||
|
{
|
||||||
|
if(tnow<told)tcnt+=told-tnow; //这里注意一下SYSTICK是一个递减的计数器就可以了.
|
||||||
|
else tcnt+=reload-tnow+told;
|
||||||
|
told=tnow;
|
||||||
|
if(tcnt>=ticks)break; //时间超过/等于要延迟的时间,则退出.
|
||||||
|
}
|
||||||
|
};
|
||||||
|
delay_osschedunlock(); //恢复OS调度
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Delay function（ms）
|
||||||
|
Input : mus：The number of ms to delay
|
||||||
|
Output : none
|
||||||
|
函数功能：延时函数（us）
|
||||||
|
入口参数：mus：要延时的ms数
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void delay_ms(u16 nms)
|
||||||
|
{
|
||||||
|
if(delay_osrunning&&delay_osintnesting==0) //如果OS已经在跑了,并且不是在中断里面(中断里面不能任务调度)
|
||||||
|
{
|
||||||
|
if(nms>=fac_ms) //延时的时间大于OS的最少时间周期
|
||||||
|
{
|
||||||
|
delay_ostimedly(nms/fac_ms); //OS延时
|
||||||
|
}
|
||||||
|
nms%=fac_ms; //OS已经无法提供这么小的延时了,采用普通方式延时
|
||||||
|
}
|
||||||
|
delay_us((u32)(nms*1000)); //普通方式延时
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
//不用ucos时
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Delay function（us）
|
||||||
|
Input : nus：The number of us to delay
|
||||||
|
Output : none
|
||||||
|
函数功能：延时函数（us）
|
||||||
|
入口参数：nus：要延时的us数
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void delay_us(u32 nus)
|
||||||
|
{
|
||||||
|
u32 temp;
|
||||||
|
SysTick->LOAD=nus*fac_us; //时间加载
|
||||||
|
SysTick->VAL=0x00; //清空计数器
|
||||||
|
SysTick->CTRL|=SysTick_CTRL_ENABLE_Msk ; //开始倒数
|
||||||
|
do
|
||||||
|
{
|
||||||
|
temp=SysTick->CTRL;
|
||||||
|
}while((temp&0x01)&&!(temp&(1<<16))); //等待时间到达
|
||||||
|
SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk; //关闭计数器
|
||||||
|
SysTick->VAL =0X00; //清空计数器
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Delay function（ms）
|
||||||
|
Input : mus：The number of ms to delay
|
||||||
|
Output : none
|
||||||
|
函数功能：延时函数（us）
|
||||||
|
入口参数：mus：要延时的ms数
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
//注意nms的范围
|
||||||
|
//SysTick->LOAD为24位寄存器,所以,最大延时为:
|
||||||
|
//nms<=0xffffff*8*1000/SYSCLK
|
||||||
|
//SYSCLK单位为Hz,nms单位为ms
|
||||||
|
//对72M条件下,nms<=1864
|
||||||
|
void delay_ms(u16 nms)
|
||||||
|
{
|
||||||
|
u32 temp;
|
||||||
|
SysTick->LOAD=(u32)nms*fac_ms; //时间加载(SysTick->LOAD为24bit)
|
||||||
|
SysTick->VAL =0x00; //清空计数器
|
||||||
|
SysTick->CTRL|=SysTick_CTRL_ENABLE_Msk ; //开始倒数
|
||||||
|
do
|
||||||
|
{
|
||||||
|
temp=SysTick->CTRL;
|
||||||
|
}while((temp&0x01)&&!(temp&(1<<16))); //等待时间到达
|
||||||
|
SysTick->CTRL&=~SysTick_CTRL_ENABLE_Msk; //关闭计数器
|
||||||
|
SysTick->VAL =0X00; //清空计数器
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,57 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#ifndef __DELAY_H
|
||||||
|
#define __DELAY_H
|
||||||
|
#include "sys.h"
|
||||||
|
|
||||||
|
void delay_init(void);
|
||||||
|
void delay_ms(u16 nms);
|
||||||
|
void delay_us(u32 nus);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,240 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#include "sys.h"
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Set the vector table offset address
|
||||||
|
Input : Base site Offsets
|
||||||
|
Output : none
|
||||||
|
函数功能：设置向量表偏移地址
|
||||||
|
入口参数：NVIC_VectTab:基址 Offset:偏移量
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void MY_NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
|
||||||
|
{
|
||||||
|
SCB->VTOR = NVIC_VectTab|(Offset & (u32)0x1FFFFF80);//设置NVIC的向量表偏移寄存器
|
||||||
|
//用于标识向量表是在CODE区还是在RAM区
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Set NVIC group
|
||||||
|
Input : NVIC_Group
|
||||||
|
Output : none
|
||||||
|
函数功能：设置中断分组
|
||||||
|
入口参数：NVIC_Group:NVIC分组 0~4 总共5组
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void MY_NVIC_PriorityGroupConfig(u8 NVIC_Group)
|
||||||
|
{
|
||||||
|
u32 temp,temp1;
|
||||||
|
temp1=(~NVIC_Group)&0x07;//取后三位
|
||||||
|
temp1<<=8;
|
||||||
|
temp=SCB->AIRCR; //读取先前的设置
|
||||||
|
temp&=0X0000F8FF; //清空先前分组
|
||||||
|
temp|=0X05FA0000; //写入钥匙
|
||||||
|
temp|=temp1;
|
||||||
|
SCB->AIRCR=temp; //设置分组
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Set NVIC group
|
||||||
|
Input : NVIC_PreemptionPriority NVIC_SubPriority NVIC_Channel NVIC_Group
|
||||||
|
Output : none
|
||||||
|
函数功能：设置中断分组
|
||||||
|
入口参数：抢占优先级 响应优先级 中断编号 中断分组号
|
||||||
|
返回 值：无
|
||||||
|
* 中断分组 | 作用
|
||||||
|
* --------+--------------------------------------
|
||||||
|
* 组0 | 0位抢占优先级,4位响应优先级
|
||||||
|
* 组1 | 1位抢占优先级,3位响应优先级
|
||||||
|
* 组2 | 2位抢占优先级,2位响应优先级
|
||||||
|
* 组3 | 3位抢占优先级,1位响应优先级
|
||||||
|
* 组4 | 4位抢占优先级,0位响应优先级
|
||||||
|
*NVIC_SubPriority和NVIC_PreemptionPriority的原则是,数值越小,越优先
|
||||||
|
**************************************************************************/
|
||||||
|
void MY_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group)
|
||||||
|
{ //注意优先级不能超过设定的组的范围!否则会有意想不到的错误
|
||||||
|
u32 temp;
|
||||||
|
MY_NVIC_PriorityGroupConfig(NVIC_Group); //设置分组
|
||||||
|
temp=NVIC_PreemptionPriority<<(4-NVIC_Group);
|
||||||
|
temp|=NVIC_SubPriority&(0x0f>>NVIC_Group);
|
||||||
|
temp&=0xf;//取低四位
|
||||||
|
NVIC->ISER[NVIC_Channel/32]|=(1<<NVIC_Channel%32);//使能中断位(要清除的话,相反操作就OK)
|
||||||
|
NVIC->IP[NVIC_Channel]|=temp<<4; //设置响应优先级和抢断优先级
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: External interrupt function configuration
|
||||||
|
Input : GPIOx：General-purpose input/output BITx：The port needed enable
|
||||||
|
TRIM：Trigger mode
|
||||||
|
Output : none
|
||||||
|
函数功能：外部中断函数配置
|
||||||
|
入口参数：GPIOx:0~6,代表GPIOA~G；
|
||||||
|
BITx:需要使能的位; TRIM:触发模式,1,下升沿;2,上降沿;3，任意电平触发
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
//该函数一次只能配置1个IO口,多个IO口,需多次调用
|
||||||
|
//该函数会自动开启对应中断,以及屏蔽线
|
||||||
|
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM)
|
||||||
|
{
|
||||||
|
u8 EXTADDR;
|
||||||
|
u8 EXTOFFSET;
|
||||||
|
EXTADDR=BITx/4;//得到中断寄存器组的编号
|
||||||
|
EXTOFFSET=(BITx%4)*4;
|
||||||
|
RCC->APB2ENR|=0x01;//使能io复用时钟
|
||||||
|
AFIO->EXTICR[EXTADDR]&=~(0x000F<<EXTOFFSET);//清除原来设置！！！
|
||||||
|
AFIO->EXTICR[EXTADDR]|=GPIOx<<EXTOFFSET;//EXTI.BITx映射到GPIOx.BITx
|
||||||
|
//自动设置
|
||||||
|
EXTI->IMR|=1<<BITx;// 开启line BITx上的中断
|
||||||
|
//EXTI->EMR|=1<<BITx;//不屏蔽line BITx上的事件 (如果不屏蔽这句,在硬件上是可以的,但是在软件仿真的时候无法进入中断!)
|
||||||
|
if(TRIM&0x01)EXTI->FTSR|=1<<BITx;//line BITx上事件下降沿触发
|
||||||
|
if(TRIM&0x02)EXTI->RTSR|=1<<BITx;//line BITx上事件上升降沿触发
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Reset all clock registers
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：把所有时钟寄存器复位
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
//不能在这里执行所有外设复位!否则至少引起串口不工作.
|
||||||
|
//把所有时钟寄存器复位
|
||||||
|
void MYRCC_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC->APB1RSTR = 0x00000000;//复位结束
|
||||||
|
RCC->APB2RSTR = 0x00000000;
|
||||||
|
|
||||||
|
RCC->AHBENR = 0x00000014; //睡眠模式闪存和SRAM时钟使能.其他关闭.
|
||||||
|
RCC->APB2ENR = 0x00000000; //外设时钟关闭.
|
||||||
|
RCC->APB1ENR = 0x00000000;
|
||||||
|
RCC->CR |= 0x00000001; //使能内部高速时钟HSION
|
||||||
|
RCC->CFGR &= 0xF8FF0000; //复位SW[1:0],HPRE[3:0],PPRE1[2:0],PPRE2[2:0],ADCPRE[1:0],MCO[2:0]
|
||||||
|
RCC->CR &= 0xFEF6FFFF; //复位HSEON,CSSON,PLLON
|
||||||
|
RCC->CR &= 0xFFFBFFFF; //复位HSEBYP
|
||||||
|
RCC->CFGR &= 0xFF80FFFF; //复位PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE
|
||||||
|
RCC->CIR = 0x00000000; //关闭所有中断
|
||||||
|
//配置向量表
|
||||||
|
#ifdef VECT_TAB_RAM
|
||||||
|
MY_NVIC_SetVectorTable(0x20000000, 0x0);
|
||||||
|
#else
|
||||||
|
MY_NVIC_SetVectorTable(0x08000000,0x0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
//THUMB指令不支持汇编内联
|
||||||
|
//采用如下方法实现执行汇编指令WFI
|
||||||
|
__asm void WFI_SET(void)
|
||||||
|
{
|
||||||
|
WFI;
|
||||||
|
}
|
||||||
|
//关闭所有中断
|
||||||
|
__asm void INTX_DISABLE(void)
|
||||||
|
{
|
||||||
|
CPSID I;
|
||||||
|
}
|
||||||
|
//开启所有中断
|
||||||
|
__asm void INTX_ENABLE(void)
|
||||||
|
{
|
||||||
|
CPSIE I;
|
||||||
|
}
|
||||||
|
//设置栈顶地址
|
||||||
|
//addr:栈顶地址
|
||||||
|
__asm void MSR_MSP(u32 addr)
|
||||||
|
{
|
||||||
|
MSR MSP, r0 //set Main Stack value
|
||||||
|
BX r14
|
||||||
|
}
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Go to standby mode
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：进入待机模式
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void Sys_Standby(void)
|
||||||
|
{
|
||||||
|
SCB->SCR|=1<<2; //使能SLEEPDEEP位 (SYS->CTRL)
|
||||||
|
RCC->APB1ENR|=1<<28; //使能电源时钟
|
||||||
|
PWR->CSR|=1<<8; //设置WKUP用于唤醒
|
||||||
|
PWR->CR|=1<<2; //清除Wake-up 标志
|
||||||
|
PWR->CR|=1<<1; //PDDS置位
|
||||||
|
WFI_SET(); //执行WFI指令
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: System soft reset
|
||||||
|
Input : none
|
||||||
|
Output : none
|
||||||
|
函数功能：系统软复位
|
||||||
|
入口参数：无
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void Sys_Soft_Reset(void)
|
||||||
|
{
|
||||||
|
SCB->AIRCR =0X05FA0000|(u32)0x04;
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Set JTAG mode
|
||||||
|
Input : mode:JTAG, swd mode settings；00，all enable；01，enable SWD；10，Full shutdown
|
||||||
|
Output : none
|
||||||
|
函数功能：设置JTAG模式
|
||||||
|
入口参数：mode:jtag,swd模式设置;00,全使能;01,使能SWD;10,全关闭;
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
//#define JTAG_SWD_DISABLE 0X02
|
||||||
|
//#define SWD_ENABLE 0X01
|
||||||
|
//#define JTAG_SWD_ENABLE 0X00
|
||||||
|
void JTAG_Set(u8 mode)
|
||||||
|
{
|
||||||
|
u32 temp;
|
||||||
|
temp=mode;
|
||||||
|
temp<<=25;
|
||||||
|
RCC->APB2ENR|=1<<0; //开启辅助时钟
|
||||||
|
AFIO->MAPR&=0XF8FFFFFF; //清除MAPR的[26:24]
|
||||||
|
AFIO->MAPR|=temp; //设置jtag模式
|
||||||
|
}
|
||||||
|
/**************************************************************************
|
||||||
|
Function: System clock initialization function
|
||||||
|
Input : pll：Selected frequency multiplication，Starting at 2, the maximum value is 16
|
||||||
|
Output : none
|
||||||
|
函数功能：系统时钟初始化函数
|
||||||
|
入口参数：pll:选择的倍频数，从2开始，最大值为16
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void Stm32_Clock_Init(u8 PLL)
|
||||||
|
{
|
||||||
|
unsigned char temp=0;
|
||||||
|
MYRCC_DeInit(); //复位并配置向量表
|
||||||
|
RCC->CR|=0x00010000; //外部高速时钟使能HSEON
|
||||||
|
while(!(RCC->CR>>17)); //等待外部时钟就绪
|
||||||
|
RCC->CFGR=0X00000400; //APB1=DIV2;APB2=DIV1;AHB=DIV1;
|
||||||
|
PLL-=2; //抵消2个单位
|
||||||
|
RCC->CFGR|=PLL<<18; //设置PLL值 2~16
|
||||||
|
RCC->CFGR|=1<<16; //PLLSRC ON
|
||||||
|
FLASH->ACR|=0x32; //FLASH 2个延时周期
|
||||||
|
|
||||||
|
RCC->CR|=0x01000000; //PLLON
|
||||||
|
while(!(RCC->CR>>25)); //等待PLL锁定
|
||||||
|
RCC->CFGR|=0x00000002; //PLL作为系统时钟
|
||||||
|
while(temp!=0x02) //等待PLL作为系统时钟设置成功
|
||||||
|
{
|
||||||
|
temp=RCC->CFGR>>2;
|
||||||
|
temp&=0x03;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,139 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#ifndef __SYS_H
|
||||||
|
#define __SYS_H
|
||||||
|
#include <stm32f10x.h>
|
||||||
|
//0,不支持ucos
|
||||||
|
//1,支持ucos
|
||||||
|
#define SYSTEM_SUPPORT_UCOS 0 //定义系统文件夹是否支持UCOS
|
||||||
|
|
||||||
|
|
||||||
|
//位带操作,实现51类似的GPIO控制功能
|
||||||
|
//具体实现思想,参考<<CM3权威指南>>第五章(87页~92页).
|
||||||
|
//IO口操作宏定义
|
||||||
|
#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
|
||||||
|
#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
|
||||||
|
#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
|
||||||
|
//IO口地址映射
|
||||||
|
#define GPIOA_ODR_Addr (GPIOA_BASE+12) //0x4001080C
|
||||||
|
#define GPIOB_ODR_Addr (GPIOB_BASE+12) //0x40010C0C
|
||||||
|
#define GPIOC_ODR_Addr (GPIOC_BASE+12) //0x4001100C
|
||||||
|
#define GPIOD_ODR_Addr (GPIOD_BASE+12) //0x4001140C
|
||||||
|
#define GPIOE_ODR_Addr (GPIOE_BASE+12) //0x4001180C
|
||||||
|
#define GPIOF_ODR_Addr (GPIOF_BASE+12) //0x40011A0C
|
||||||
|
#define GPIOG_ODR_Addr (GPIOG_BASE+12) //0x40011E0C
|
||||||
|
|
||||||
|
#define GPIOA_IDR_Addr (GPIOA_BASE+8) //0x40010808
|
||||||
|
#define GPIOB_IDR_Addr (GPIOB_BASE+8) //0x40010C08
|
||||||
|
#define GPIOC_IDR_Addr (GPIOC_BASE+8) //0x40011008
|
||||||
|
#define GPIOD_IDR_Addr (GPIOD_BASE+8) //0x40011408
|
||||||
|
#define GPIOE_IDR_Addr (GPIOE_BASE+8) //0x40011808
|
||||||
|
#define GPIOF_IDR_Addr (GPIOF_BASE+8) //0x40011A08
|
||||||
|
#define GPIOG_IDR_Addr (GPIOG_BASE+8) //0x40011E08
|
||||||
|
|
||||||
|
//IO口操作,只对单一的IO口!
|
||||||
|
//确保n的值小于16!
|
||||||
|
#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //输出
|
||||||
|
#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //输入
|
||||||
|
|
||||||
|
#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //输出
|
||||||
|
#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //输入
|
||||||
|
|
||||||
|
#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //输出
|
||||||
|
#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //输入
|
||||||
|
|
||||||
|
#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //输出
|
||||||
|
#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //输入
|
||||||
|
|
||||||
|
#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //输出
|
||||||
|
#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //输入
|
||||||
|
|
||||||
|
#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //输出
|
||||||
|
#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //输入
|
||||||
|
|
||||||
|
#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //输出
|
||||||
|
#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //输入
|
||||||
|
/////////////////////////////////////////////////////////////////
|
||||||
|
//Ex_NVIC_Config专用定义
|
||||||
|
#define GPIO_A 0
|
||||||
|
#define GPIO_B 1
|
||||||
|
#define GPIO_C 2
|
||||||
|
#define GPIO_D 3
|
||||||
|
#define GPIO_E 4
|
||||||
|
#define GPIO_F 5
|
||||||
|
#define GPIO_G 6
|
||||||
|
|
||||||
|
#define FTIR 1 //下降沿触发
|
||||||
|
#define RTIR 2 //上升沿触发
|
||||||
|
#include "delay.h"
|
||||||
|
#include "key.h"
|
||||||
|
#include "oled.h"
|
||||||
|
#include "usart.h"
|
||||||
|
#include "motor.h"
|
||||||
|
#include "encoder.h"
|
||||||
|
#include "ioi2c.h"
|
||||||
|
#include "mpu6050.h"
|
||||||
|
#include "show.h"
|
||||||
|
#include "exti.h"
|
||||||
|
#include "control.h"
|
||||||
|
//JTAG模式设置定义
|
||||||
|
#define JTAG_SWD_DISABLE 0X02
|
||||||
|
#define SWD_ENABLE 0X01
|
||||||
|
#define JTAG_SWD_ENABLE 0X00
|
||||||
|
extern int Encoder_Left,Encoder_Right; //左右编码器的脉冲计数
|
||||||
|
extern u8 Flag_Stop; //停止标志位和 显示标志位 默认停止 显示打开
|
||||||
|
extern float Angle_Balance,Gyro_Balance; //平衡倾角 平衡陀螺仪 转向陀螺仪
|
||||||
|
/////////////////////////////////////////////////////////////////
|
||||||
|
void Stm32_Clock_Init(u8 PLL); //时钟初始化
|
||||||
|
void Sys_Soft_Reset(void); //系统软复位
|
||||||
|
void Sys_Standby(void); //待机模式
|
||||||
|
void MY_NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset);//设置偏移地址
|
||||||
|
void MY_NVIC_PriorityGroupConfig(u8 NVIC_Group);//设置NVIC分组
|
||||||
|
void MY_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group);//设置中断
|
||||||
|
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM);//外部中断配置函数(只对GPIOA~G)
|
||||||
|
void JTAG_Set(u8 mode);
|
||||||
|
//////////////////////////////////////////////////////////////////////////////
|
||||||
|
//以下为汇编函数
|
||||||
|
void WFI_SET(void); //执行WFI指令
|
||||||
|
void INTX_DISABLE(void);//关闭所有中断
|
||||||
|
void INTX_ENABLE(void); //开启所有中断
|
||||||
|
void MSR_MSP(u32 addr); //设置堆栈地址
|
||||||
|
#include "inv_mpu.h"
|
||||||
|
#include "inv_mpu_dmp_motion_driver.h"
|
||||||
|
#include "dmpKey.h"
|
||||||
|
#include "dmpmap.h"
|
||||||
|
#include <string.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <math.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,68 @@
|
||||||
|
#include "sys.h"
|
||||||
|
#include "usart.h"
|
||||||
|
#if SYSTEM_SUPPORT_OS
|
||||||
|
#include "includes.h" //ucos 使用
|
||||||
|
#endif
|
||||||
|
//////////////////////////////////////////////////////////////////
|
||||||
|
// 加入以下代码,支持printf函数,而不需要选择use MicroLIB
|
||||||
|
#if 1
|
||||||
|
#pragma import(__use_no_semihosting)
|
||||||
|
// 标准库需要的支持函数
|
||||||
|
struct __FILE
|
||||||
|
{
|
||||||
|
int handle;
|
||||||
|
};
|
||||||
|
|
||||||
|
FILE __stdout;
|
||||||
|
// 定义_sys_exit()以避免使用半主机模式
|
||||||
|
_sys_exit(int x)
|
||||||
|
{
|
||||||
|
x = x;
|
||||||
|
}
|
||||||
|
// 重定义fputc函数
|
||||||
|
int fputc(int ch, FILE *f)
|
||||||
|
{
|
||||||
|
while ((USART1->SR & 0X40) == 0); // 使用串口1
|
||||||
|
USART1->DR = (u8)ch;
|
||||||
|
return ch;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
/**************************************************************************
|
||||||
|
Function: Serial port 1 initialization
|
||||||
|
Input : bound：Baud rate
|
||||||
|
Output : none
|
||||||
|
函数功能：串口1初始化
|
||||||
|
入口参数：bound：波特率
|
||||||
|
返回 值：无
|
||||||
|
**************************************************************************/
|
||||||
|
void uart_init(u32 bound)
|
||||||
|
{
|
||||||
|
// GPIO端口设置
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
USART_InitTypeDef USART_InitStructure;
|
||||||
|
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); // 使能USART1，GPIOA时钟
|
||||||
|
|
||||||
|
// USART1_TX GPIOA.9
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; // PA.9
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; // 复用推挽输出
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure); // 初始化GPIOA.9
|
||||||
|
|
||||||
|
// USART1_RX GPIOA.10初始化
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; // PA10
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; // 浮空输入
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure); // 初始化GPIOA.10
|
||||||
|
// USART 初始化设置
|
||||||
|
|
||||||
|
USART_InitStructure.USART_BaudRate = bound; // 串口波特率
|
||||||
|
USART_InitStructure.USART_WordLength = USART_WordLength_8b; // 字长为8位数据格式
|
||||||
|
USART_InitStructure.USART_StopBits = USART_StopBits_1; // 一个停止位
|
||||||
|
USART_InitStructure.USART_Parity = USART_Parity_No; // 无奇偶校验位
|
||||||
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; // 无硬件数据流控制
|
||||||
|
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; // 收发模式
|
||||||
|
|
||||||
|
USART_Init(USART1, &USART_InitStructure); // 初始化串口1
|
||||||
|
USART_ITConfig(USART1, USART_IT_RXNE, DISABLE); // 开启串口接受中断
|
||||||
|
USART_Cmd(USART1, ENABLE); // 使能串口1
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#ifndef __USART_H
|
||||||
|
#define __USART_H
|
||||||
|
#include "stdio.h"
|
||||||
|
#include "sys.h"
|
||||||
|
|
||||||
|
void uart_init(u32 bound);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,45 @@
|
||||||
|
/***********************************************
|
||||||
|
公司：轮趣科技（东莞）有限公司
|
||||||
|
品牌：WHEELTEC
|
||||||
|
官网：wheeltec.net
|
||||||
|
淘宝店铺：shop114407458.taobao.com
|
||||||
|
速卖通: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
版本：5.7
|
||||||
|
修改时间：2021-04-29
|
||||||
|
|
||||||
|
|
||||||
|
Brand: WHEELTEC
|
||||||
|
Website: wheeltec.net
|
||||||
|
Taobao shop: shop114407458.taobao.com
|
||||||
|
Aliexpress: https://minibalance.aliexpress.com/store/4455017
|
||||||
|
Version:5.7
|
||||||
|
Update：2021-04-29
|
||||||
|
|
||||||
|
All rights reserved
|
||||||
|
***********************************************/
|
||||||
|
#include "stm32f10x.h"
|
||||||
|
#include "sys.h"
|
||||||
|
u8 Flag_Stop=1; //电机停止标志位，默认关闭
|
||||||
|
int Encoder_Left,Encoder_Right; //左右编码器的脉冲计数
|
||||||
|
float Angle_Balance,Gyro_Balance; //平衡倾角 平衡陀螺仪
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
MY_NVIC_PriorityGroupConfig(2); //设置中断分组
|
||||||
|
delay_init(); //延时函数初始化
|
||||||
|
JTAG_Set(JTAG_SWD_DISABLE); //关闭JTAG接口
|
||||||
|
JTAG_Set(SWD_ENABLE); //打开SWD接口 可以利用主板的SWD接口调试
|
||||||
|
KEY_Init(); //按键初始化
|
||||||
|
MiniBalance_PWM_Init(7199,0); //初始化PWM 10KHZ，用于驱动电机 如需初始化电调接口 改为MiniBalance_PWM_Init(9999,35) 200HZ
|
||||||
|
Encoder_Init_TIM2(); //编码器接口
|
||||||
|
Encoder_Init_TIM4(); //初始化编码器2
|
||||||
|
IIC_Init(); //IIC初始化
|
||||||
|
OLED_Init(); //OLED初始化
|
||||||
|
MPU6050_initialize(); //MPU6050初始化
|
||||||
|
DMP_Init(); //初始化DMP
|
||||||
|
MiniBalance_EXTI_Init(); //MPU6050 5ms定时中断初始化
|
||||||
|
while(1)
|
||||||
|
{
|
||||||
|
oled_show(); //显示屏打开
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,415 @@
|
||||||
|
Component: ARM Compiler 5.06 update 3 (build 300) Tool: armlink [4d35c9]
|
||||||
|
|
||||||
|
==============================================================================
|
||||||
|
|
||||||
|
Section Cross References
|
||||||
|
|
||||||
|
system_stm32f10x.o(.text) refers to system_stm32f10x.o(.data) for SystemCoreClock
|
||||||
|
minibalance.o(.text) refers to sys.o(.text) for MY_NVIC_PriorityGroupConfig
|
||||||
|
minibalance.o(.text) refers to delay.o(.text) for delay_init
|
||||||
|
minibalance.o(.text) refers to key.o(.text) for KEY_Init
|
||||||
|
minibalance.o(.text) refers to motor.o(.text) for MiniBalance_PWM_Init
|
||||||
|
minibalance.o(.text) refers to encoder.o(.text) for Encoder_Init_TIM2
|
||||||
|
minibalance.o(.text) refers to ioi2c.o(.text) for IIC_Init
|
||||||
|
minibalance.o(.text) refers to oled.o(.text) for OLED_Init
|
||||||
|
minibalance.o(.text) refers to mpu6050.o(.text) for MPU6050_initialize
|
||||||
|
minibalance.o(.text) refers to exti.o(.text) for MiniBalance_EXTI_Init
|
||||||
|
minibalance.o(.text) refers to show.o(.text) for oled_show
|
||||||
|
startup_stm32f10x_md.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
|
||||||
|
startup_stm32f10x_md.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
|
||||||
|
startup_stm32f10x_md.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
|
||||||
|
startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
|
||||||
|
startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler
|
||||||
|
startup_stm32f10x_md.o(RESET) refers to stm32f10x_it.o(.text) for NMI_Handler
|
||||||
|
startup_stm32f10x_md.o(RESET) refers to encoder.o(.text) for TIM2_IRQHandler
|
||||||
|
startup_stm32f10x_md.o(RESET) refers to control.o(.text) for EXTI15_10_IRQHandler
|
||||||
|
startup_stm32f10x_md.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
|
||||||
|
startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(.text) for SystemInit
|
||||||
|
startup_stm32f10x_md.o(.text) refers to __main.o(!!!main) for __main
|
||||||
|
startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(HEAP) for Heap_Mem
|
||||||
|
startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(STACK) for Stack_Mem
|
||||||
|
stm32f10x_adc.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphResetCmd
|
||||||
|
stm32f10x_bkp.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_BackupResetCmd
|
||||||
|
stm32f10x_can.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB1PeriphResetCmd
|
||||||
|
stm32f10x_cec.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB1PeriphResetCmd
|
||||||
|
stm32f10x_dac.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB1PeriphResetCmd
|
||||||
|
stm32f10x_gpio.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphResetCmd
|
||||||
|
stm32f10x_i2c.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB1PeriphResetCmd
|
||||||
|
stm32f10x_pwr.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB1PeriphResetCmd
|
||||||
|
stm32f10x_rcc.o(.text) refers to stm32f10x_rcc.o(.data) for APBAHBPrescTable
|
||||||
|
stm32f10x_spi.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphResetCmd
|
||||||
|
stm32f10x_tim.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphResetCmd
|
||||||
|
stm32f10x_usart.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphResetCmd
|
||||||
|
stm32f10x_wwdg.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB1PeriphResetCmd
|
||||||
|
delay.o(.text) refers to misc.o(.text) for SysTick_CLKSourceConfig
|
||||||
|
delay.o(.text) refers to system_stm32f10x.o(.data) for SystemCoreClock
|
||||||
|
delay.o(.text) refers to delay.o(.data) for fac_us
|
||||||
|
sys.o(.text) refers to sys.o(.emb_text) for WFI_SET
|
||||||
|
usart.o(.text) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
|
||||||
|
usart.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphClockCmd
|
||||||
|
usart.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_Init
|
||||||
|
usart.o(.text) refers to stm32f10x_usart.o(.text) for USART_Init
|
||||||
|
usart.o(.data) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
|
||||||
|
key.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphClockCmd
|
||||||
|
key.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_Init
|
||||||
|
key.o(.text) refers to key.o(.data) for flag_key
|
||||||
|
oled.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphClockCmd
|
||||||
|
oled.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_Init
|
||||||
|
oled.o(.text) refers to stm32f10x_pwr.o(.text) for PWR_BackupAccessCmd
|
||||||
|
oled.o(.text) refers to stm32f10x_bkp.o(.text) for BKP_TamperPinCmd
|
||||||
|
oled.o(.text) refers to delay.o(.text) for delay_ms
|
||||||
|
oled.o(.text) refers to oled.o(.bss) for OLED_GRAM
|
||||||
|
oled.o(.text) refers to oled.o(.constdata) for oled_asc2_1206
|
||||||
|
motor.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphClockCmd
|
||||||
|
motor.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_Init
|
||||||
|
motor.o(.text) refers to stm32f10x_tim.o(.text) for TIM_TimeBaseInit
|
||||||
|
encoder.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB1PeriphClockCmd
|
||||||
|
encoder.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_Init
|
||||||
|
encoder.o(.text) refers to stm32f10x_tim.o(.text) for TIM_TimeBaseStructInit
|
||||||
|
ioi2c.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphClockCmd
|
||||||
|
ioi2c.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_Init
|
||||||
|
ioi2c.o(.text) refers to delay.o(.text) for delay_us
|
||||||
|
exti.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphClockCmd
|
||||||
|
exti.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_Init
|
||||||
|
exti.o(.text) refers to stm32f10x_exti.o(.text) for EXTI_Init
|
||||||
|
exti.o(.text) refers to misc.o(.text) for NVIC_Init
|
||||||
|
control.o(.text) refers to fleqf.o(x$fpl$fleqf) for __aeabi_cfcmple
|
||||||
|
control.o(.text) refers to frleqf.o(x$fpl$frleqf) for __aeabi_cfrcmple
|
||||||
|
control.o(.text) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f
|
||||||
|
control.o(.text) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d
|
||||||
|
control.o(.text) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul
|
||||||
|
control.o(.text) refers to d2f.o(x$fpl$d2f) for __aeabi_d2f
|
||||||
|
control.o(.text) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd
|
||||||
|
control.o(.text) refers to faddsub_clz.o(x$fpl$fadd) for __aeabi_fadd
|
||||||
|
control.o(.text) refers to fmul.o(x$fpl$fmul) for __aeabi_fmul
|
||||||
|
control.o(.text) refers to faddsub_clz.o(x$fpl$fsub) for __aeabi_fsub
|
||||||
|
control.o(.text) refers to ffix.o(x$fpl$ffix) for __aeabi_f2iz
|
||||||
|
control.o(.text) refers to faddsub_clz.o(x$fpl$frsb) for __aeabi_frsub
|
||||||
|
control.o(.text) refers to key.o(.text) for click
|
||||||
|
control.o(.text) refers to mpu6050.o(.text) for Read_DMP
|
||||||
|
control.o(.text) refers to encoder.o(.text) for Read_Encoder
|
||||||
|
control.o(.text) refers to minibalance.o(.data) for Flag_Stop
|
||||||
|
control.o(.text) refers to control.o(.data) for Encoder_Least
|
||||||
|
control.o(.text) refers to mpu6050.o(.data) for Pitch
|
||||||
|
show.o(.text) refers to oled.o(.text) for OLED_Display_On
|
||||||
|
show.o(.text) refers to fleqf.o(x$fpl$fleqf) for __aeabi_cfcmple
|
||||||
|
show.o(.text) refers to frleqf.o(x$fpl$frleqf) for __aeabi_cfrcmple
|
||||||
|
show.o(.text) refers to ffix.o(x$fpl$ffix) for __aeabi_f2iz
|
||||||
|
show.o(.text) refers to control.o(.text) for myabs
|
||||||
|
show.o(.text) refers to minibalance.o(.data) for Encoder_Left
|
||||||
|
show.o(.text) refers to control.o(.data) for Angle_Balance
|
||||||
|
inv_mpu.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
|
||||||
|
inv_mpu.o(.text) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d
|
||||||
|
inv_mpu.o(.text) refers to _printf_dec.o(.text) for _printf_int_dec
|
||||||
|
inv_mpu.o(.text) refers to ioi2c.o(.text) for i2cWrite
|
||||||
|
inv_mpu.o(.text) refers to delay.o(.text) for delay_ms
|
||||||
|
inv_mpu.o(.text) refers to inv_mpu.o(.data) for st
|
||||||
|
inv_mpu.o(.text) refers to noretval__2printf.o(.text) for __2printf
|
||||||
|
inv_mpu.o(.text) refers to fflt_clz.o(x$fpl$ffltu) for __aeabi_ui2f
|
||||||
|
inv_mpu.o(.text) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f
|
||||||
|
inv_mpu.o(.text) refers to faddsub_clz.o(x$fpl$fsub) for __aeabi_fsub
|
||||||
|
inv_mpu.o(.text) refers to fdiv.o(x$fpl$fdiv) for __aeabi_fdiv
|
||||||
|
inv_mpu.o(.text) refers to faddsub_clz.o(x$fpl$fadd) for __aeabi_fadd
|
||||||
|
inv_mpu.o(.text) refers to fmul.o(x$fpl$fmul) for __aeabi_fmul
|
||||||
|
inv_mpu.o(.text) refers to ffix.o(x$fpl$ffix) for __aeabi_f2iz
|
||||||
|
inv_mpu.o(.text) refers to inv_mpu.o(.conststring) for .conststring
|
||||||
|
inv_mpu.o(.text) refers to feqf.o(x$fpl$feqf) for __aeabi_cfcmpeq
|
||||||
|
inv_mpu.o(.text) refers to frleqf.o(x$fpl$frleqf) for __aeabi_cfrcmple
|
||||||
|
inv_mpu.o(.text) refers to fleqf.o(x$fpl$fleqf) for __aeabi_cfcmple
|
||||||
|
inv_mpu.o(.text) refers to inv_mpu.o(.constdata) for test
|
||||||
|
inv_mpu.o(.text) refers to llsdiv.o(.text) for __aeabi_ldivmod
|
||||||
|
inv_mpu.o(.text) refers to memcmp.o(.text) for memcmp
|
||||||
|
inv_mpu.o(.data) refers to inv_mpu.o(.constdata) for reg
|
||||||
|
inv_mpu_dmp_motion_driver.o(.text) refers to inv_mpu.o(.text) for mpu_load_firmware
|
||||||
|
inv_mpu_dmp_motion_driver.o(.text) refers to inv_mpu_dmp_motion_driver.o(.constdata) for dmp_memory
|
||||||
|
inv_mpu_dmp_motion_driver.o(.text) refers to inv_mpu_dmp_motion_driver.o(.bss) for dmp
|
||||||
|
inv_mpu_dmp_motion_driver.o(.text) refers to fflt_clz.o(x$fpl$ffltu) for __aeabi_ui2f
|
||||||
|
inv_mpu_dmp_motion_driver.o(.text) refers to fdiv.o(x$fpl$fdiv) for __aeabi_fdiv
|
||||||
|
inv_mpu_dmp_motion_driver.o(.text) refers to fmul.o(x$fpl$fmul) for __aeabi_fmul
|
||||||
|
inv_mpu_dmp_motion_driver.o(.text) refers to ffixu.o(x$fpl$ffixu) for __aeabi_f2uiz
|
||||||
|
inv_mpu_dmp_motion_driver.o(.text) refers to aeabi_memset.o(.text) for __aeabi_memset
|
||||||
|
mpu6050.o(.text) refers to inv_mpu.o(.text) for mpu_run_self_test
|
||||||
|
mpu6050.o(.text) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f
|
||||||
|
mpu6050.o(.text) refers to fmul.o(x$fpl$fmul) for __aeabi_fmul
|
||||||
|
mpu6050.o(.text) refers to ffix.o(x$fpl$ffix) for __aeabi_f2iz
|
||||||
|
mpu6050.o(.text) refers to inv_mpu_dmp_motion_driver.o(.text) for dmp_set_gyro_bias
|
||||||
|
mpu6050.o(.text) refers to noretval__2printf.o(.text) for __2printf
|
||||||
|
mpu6050.o(.text) refers to ioi2c.o(.text) for IICwriteBits
|
||||||
|
mpu6050.o(.text) refers to fdiv.o(x$fpl$fdiv) for __aeabi_fdiv
|
||||||
|
mpu6050.o(.text) refers to faddsub_clz.o(x$fpl$fsub) for __aeabi_fsub
|
||||||
|
mpu6050.o(.text) refers to faddsub_clz.o(x$fpl$fadd) for __aeabi_fadd
|
||||||
|
mpu6050.o(.text) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d
|
||||||
|
mpu6050.o(.text) refers to mpu6050.o(.bss) for MPU6050_FIFO
|
||||||
|
mpu6050.o(.text) refers to mpu6050.o(.data) for gyro_orientation
|
||||||
|
mpu6050.o(.text) refers to atan2.o(i.atan2) for atan2
|
||||||
|
mpu6050.o(.text) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul
|
||||||
|
mpu6050.o(.text) refers to d2f.o(x$fpl$d2f) for __aeabi_d2f
|
||||||
|
use_no_semi_2.o(.text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
|
||||||
|
llsdiv.o(.text) refers to lludivv7m.o(.text) for __aeabi_uldivmod
|
||||||
|
__2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file
|
||||||
|
__2printf.o(.text) refers to usart.o(.data) for __stdout
|
||||||
|
noretval__2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file
|
||||||
|
noretval__2printf.o(.text) refers to usart.o(.data) for __stdout
|
||||||
|
__printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
|
||||||
|
_printf_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
|
||||||
|
__printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
|
||||||
|
__printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata
|
||||||
|
__printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
|
||||||
|
__printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
|
||||||
|
__printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata
|
||||||
|
__printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
|
||||||
|
__printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
|
||||||
|
__printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
|
||||||
|
__printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
|
||||||
|
__printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata
|
||||||
|
__printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
|
||||||
|
__printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
|
||||||
|
__printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
|
||||||
|
__printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
|
||||||
|
__printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata
|
||||||
|
_printf_d.o(.ARM.Collect$$_printf_percent$$00000009) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec
|
||||||
|
_printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end
|
||||||
|
aeabi_memset.o(.text) refers to rt_memclr.o(.text) for _memset
|
||||||
|
__main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry
|
||||||
|
d2f.o(x$fpl$d2f) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
d2f.o(x$fpl$d2f) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf
|
||||||
|
d2f.o(x$fpl$d2f) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
|
||||||
|
daddsub_clz.o(x$fpl$dadd) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
daddsub_clz.o(x$fpl$dadd) refers to daddsub_clz.o(x$fpl$dsub) for _dsub1
|
||||||
|
daddsub_clz.o(x$fpl$dadd) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf
|
||||||
|
daddsub_clz.o(x$fpl$dadd) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
|
||||||
|
daddsub_clz.o(x$fpl$drsb) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
daddsub_clz.o(x$fpl$drsb) refers to daddsub_clz.o(x$fpl$dadd) for _dadd1
|
||||||
|
daddsub_clz.o(x$fpl$drsb) refers to daddsub_clz.o(x$fpl$dsub) for _dsub1
|
||||||
|
daddsub_clz.o(x$fpl$dsub) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
daddsub_clz.o(x$fpl$dsub) refers to daddsub_clz.o(x$fpl$dadd) for _dadd1
|
||||||
|
daddsub_clz.o(x$fpl$dsub) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
|
||||||
|
dmul.o(x$fpl$dmul) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
dmul.o(x$fpl$dmul) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf
|
||||||
|
dmul.o(x$fpl$dmul) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
|
||||||
|
f2d.o(x$fpl$f2d) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
f2d.o(x$fpl$f2d) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
f2d.o(x$fpl$f2d) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf
|
||||||
|
faddsub_clz.o(x$fpl$fadd) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
faddsub_clz.o(x$fpl$fadd) refers to faddsub_clz.o(x$fpl$fsub) for _fsub1
|
||||||
|
faddsub_clz.o(x$fpl$fadd) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf
|
||||||
|
faddsub_clz.o(x$fpl$fadd) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
faddsub_clz.o(x$fpl$frsb) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
faddsub_clz.o(x$fpl$frsb) refers to faddsub_clz.o(x$fpl$fadd) for _fadd1
|
||||||
|
faddsub_clz.o(x$fpl$frsb) refers to faddsub_clz.o(x$fpl$fsub) for _fsub1
|
||||||
|
faddsub_clz.o(x$fpl$fsub) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
faddsub_clz.o(x$fpl$fsub) refers to faddsub_clz.o(x$fpl$fadd) for _fadd1
|
||||||
|
faddsub_clz.o(x$fpl$fsub) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
fdiv.o(x$fpl$frdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
fdiv.o(x$fpl$frdiv) refers to fdiv.o(x$fpl$fdiv) for _fdiv1
|
||||||
|
fdiv.o(x$fpl$fdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
fdiv.o(x$fpl$fdiv) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf
|
||||||
|
fdiv.o(x$fpl$fdiv) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
feqf.o(x$fpl$feqf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
feqf.o(x$fpl$feqf) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
feqf.o(x$fpl$feqf) refers to fcmpi.o(x$fpl$fcmpinf) for __fpl_fcmp_Inf
|
||||||
|
ffix.o(x$fpl$ffix) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
ffix.o(x$fpl$ffix) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
ffix.o(x$fpl$ffixr) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
ffix.o(x$fpl$ffixr) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
ffixu.o(x$fpl$ffixu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
ffixu.o(x$fpl$ffixu) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
ffixu.o(x$fpl$ffixur) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
ffixu.o(x$fpl$ffixur) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
fflt_clz.o(x$fpl$ffltu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
fflt_clz.o(x$fpl$fflt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
fflt_clz.o(x$fpl$ffltn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
fleqf.o(x$fpl$fleqf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
fleqf.o(x$fpl$fleqf) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
fleqf.o(x$fpl$fleqf) refers to fcmpi.o(x$fpl$fcmpinf) for __fpl_fcmp_Inf
|
||||||
|
fmul.o(x$fpl$fmul) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
fmul.o(x$fpl$fmul) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf
|
||||||
|
fmul.o(x$fpl$fmul) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf
|
||||||
|
frleqf.o(x$fpl$frleqf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
frleqf.o(x$fpl$frleqf) refers to fleqf.o(x$fpl$fleqf) for __fpl_fcmple_InfNaN
|
||||||
|
atan2.o(i.__softfp_atan2) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
atan2.o(i.__softfp_atan2) refers to atan2.o(i.atan2) for atan2
|
||||||
|
atan2.o(i.atan2) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
atan2.o(i.atan2) refers to dunder.o(i.__mathlib_dbl_infnan2) for __mathlib_dbl_infnan2
|
||||||
|
atan2.o(i.atan2) refers to atan.o(i.atan) for atan
|
||||||
|
atan2.o(i.atan2) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv
|
||||||
|
atan2.o(i.atan2) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub
|
||||||
|
atan2.o(i.atan2) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub
|
||||||
|
atan2.o(i.atan2) refers to qnan.o(.constdata) for __mathlib_zero
|
||||||
|
atan2_x.o(i.____softfp_atan2$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
atan2_x.o(i.____softfp_atan2$lsc) refers to atan2_x.o(i.__atan2$lsc) for __atan2$lsc
|
||||||
|
atan2_x.o(i.__atan2$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
atan2_x.o(i.__atan2$lsc) refers to dunder.o(i.__mathlib_dbl_infnan2) for __mathlib_dbl_infnan2
|
||||||
|
atan2_x.o(i.__atan2$lsc) refers to atan.o(i.atan) for atan
|
||||||
|
atan2_x.o(i.__atan2$lsc) refers to _rserrno.o(.text) for __set_errno
|
||||||
|
atan2_x.o(i.__atan2$lsc) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv
|
||||||
|
atan2_x.o(i.__atan2$lsc) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub
|
||||||
|
atan2_x.o(i.__atan2$lsc) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub
|
||||||
|
atan2_x.o(i.__atan2$lsc) refers to qnan.o(.constdata) for __mathlib_zero
|
||||||
|
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li
|
||||||
|
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main
|
||||||
|
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1
|
||||||
|
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1
|
||||||
|
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1
|
||||||
|
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh
|
||||||
|
_rserrno.o(.text) refers to rt_errno_addr_intlibspace.o(.text) for __aeabi_errno_addr
|
||||||
|
_printf_char_file.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common
|
||||||
|
_printf_char_file.o(.text) refers to ferror.o(.text) for ferror
|
||||||
|
_printf_char_file.o(.text) refers to usart.o(.text) for fputc
|
||||||
|
rt_memclr.o(.text) refers to rt_memclr_w.o(.text) for _memset_w
|
||||||
|
ddiv.o(x$fpl$drdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
ddiv.o(x$fpl$drdiv) refers to ddiv.o(x$fpl$ddiv) for ddiv_entry
|
||||||
|
ddiv.o(x$fpl$ddiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
ddiv.o(x$fpl$ddiv) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf
|
||||||
|
ddiv.o(x$fpl$ddiv) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf
|
||||||
|
dnaninf.o(x$fpl$dnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
dretinf.o(x$fpl$dretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
fcmpi.o(x$fpl$fcmpinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
fnaninf.o(x$fpl$fnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
fretinf.o(x$fpl$fretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
atan.o(i.__softfp_atan) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
atan.o(i.__softfp_atan) refers to atan.o(i.atan) for atan
|
||||||
|
atan.o(i.atan) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
atan.o(i.atan) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan
|
||||||
|
atan.o(i.atan) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify
|
||||||
|
atan.o(i.atan) refers to dunder.o(i.__mathlib_dbl_underflow) for __mathlib_dbl_underflow
|
||||||
|
atan.o(i.atan) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd
|
||||||
|
atan.o(i.atan) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn
|
||||||
|
atan.o(i.atan) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub
|
||||||
|
atan.o(i.atan) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv
|
||||||
|
atan.o(i.atan) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul
|
||||||
|
atan.o(i.atan) refers to poly.o(i.__kernel_poly) for __kernel_poly
|
||||||
|
atan.o(i.atan) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub
|
||||||
|
atan.o(i.atan) refers to atan.o(.constdata) for .constdata
|
||||||
|
atan.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
atan_x.o(i.____softfp_atan$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
atan_x.o(i.____softfp_atan$lsc) refers to atan_x.o(i.__atan$lsc) for __atan$lsc
|
||||||
|
atan_x.o(i.__atan$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
atan_x.o(i.__atan$lsc) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan
|
||||||
|
atan_x.o(i.__atan$lsc) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd
|
||||||
|
atan_x.o(i.__atan$lsc) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn
|
||||||
|
atan_x.o(i.__atan$lsc) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub
|
||||||
|
atan_x.o(i.__atan$lsc) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv
|
||||||
|
atan_x.o(i.__atan$lsc) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul
|
||||||
|
atan_x.o(i.__atan$lsc) refers to poly.o(i.__kernel_poly) for __kernel_poly
|
||||||
|
atan_x.o(i.__atan$lsc) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub
|
||||||
|
atan_x.o(i.__atan$lsc) refers to atan_x.o(.constdata) for .constdata
|
||||||
|
atan_x.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
dunder.o(i.__mathlib_dbl_divzero) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv
|
||||||
|
dunder.o(i.__mathlib_dbl_infnan) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn
|
||||||
|
dunder.o(i.__mathlib_dbl_infnan2) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd
|
||||||
|
dunder.o(i.__mathlib_dbl_invalid) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv
|
||||||
|
dunder.o(i.__mathlib_dbl_overflow) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn
|
||||||
|
dunder.o(i.__mathlib_dbl_posinfnan) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul
|
||||||
|
dunder.o(i.__mathlib_dbl_underflow) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn
|
||||||
|
qnan.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
__rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init
|
||||||
|
__rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init
|
||||||
|
__rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init
|
||||||
|
__rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to minibalance.o(.text) for main
|
||||||
|
__rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit
|
||||||
|
__rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001
|
||||||
|
__rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008
|
||||||
|
__rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A
|
||||||
|
__rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B
|
||||||
|
__rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D
|
||||||
|
__rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap
|
||||||
|
__rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004
|
||||||
|
aeabi_ldiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0
|
||||||
|
rt_errno_addr.o(.text) refers to rt_errno_addr.o(.bss) for __aeabi_errno_addr_data
|
||||||
|
rt_errno_addr_intlibspace.o(.text) refers to libspace.o(.bss) for __libspace_start
|
||||||
|
_printf_char_common.o(.text) refers to __printf.o(.text) for __printf
|
||||||
|
scalbn.o(x$fpl$scalbn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
scalbn.o(x$fpl$scalbn) refers to dcheck1.o(x$fpl$dcheck1) for __fpl_dcheck_NaN1
|
||||||
|
fpclassify.o(i.__ARM_fpclassify) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
poly.o(i.__kernel_poly) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
poly.o(i.__kernel_poly) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul
|
||||||
|
poly.o(i.__kernel_poly) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd
|
||||||
|
libspace.o(.text) refers to libspace.o(.bss) for __libspace_start
|
||||||
|
sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace
|
||||||
|
sys_stackheap_outer.o(.text) refers to startup_stm32f10x_md.o(.text) for __user_initial_stackheap
|
||||||
|
rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE
|
||||||
|
exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1
|
||||||
|
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1
|
||||||
|
dcheck1.o(x$fpl$dcheck1) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
dcheck1.o(x$fpl$dcheck1) refers to retnan.o(x$fpl$retnan) for __fpl_return_NaN
|
||||||
|
rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
|
||||||
|
rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
|
||||||
|
rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
|
||||||
|
rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
|
||||||
|
rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
|
||||||
|
rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
|
||||||
|
rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000
|
||||||
|
defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner
|
||||||
|
defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit
|
||||||
|
defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise
|
||||||
|
libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
|
||||||
|
libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
|
||||||
|
libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
|
||||||
|
libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
|
||||||
|
libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
|
||||||
|
libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
|
||||||
|
libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
|
||||||
|
retnan.o(x$fpl$retnan) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
retnan.o(x$fpl$retnan) refers to trapv.o(x$fpl$trapveneer) for __fpl_cmpreturn
|
||||||
|
rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown
|
||||||
|
rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to usart.o(.text) for _sys_exit
|
||||||
|
rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001
|
||||||
|
rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003
|
||||||
|
rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004
|
||||||
|
rt_raise.o(.text) refers to __raise.o(.text) for __raise
|
||||||
|
rt_raise.o(.text) refers to usart.o(.text) for _sys_exit
|
||||||
|
defsig_exit.o(.text) refers to usart.o(.text) for _sys_exit
|
||||||
|
defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
|
||||||
|
argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv
|
||||||
|
trapv.o(x$fpl$trapveneer) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
|
||||||
|
__raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler
|
||||||
|
defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch
|
||||||
|
_get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard
|
||||||
|
_get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM
|
||||||
|
_get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string
|
||||||
|
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1
|
||||||
|
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1
|
||||||
|
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1
|
||||||
|
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return
|
||||||
|
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1
|
||||||
|
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1
|
||||||
|
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1
|
||||||
|
sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
|
||||||
|
sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
|
||||||
|
sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
|
||||||
|
sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
|
||||||
|
defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
|
||||||
|
defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit
|
||||||
|
defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise
|
||||||
|
defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner
|
||||||
|
defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
|
||||||
|
defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
|
||||||
|
defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
|
||||||
|
defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
|
||||||
|
defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
|
||||||
|
defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
|
||||||
|
defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
|
||||||
|
defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
|
||||||
|
defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display
|
||||||
|
|
||||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue