diff --git a/1.Hardware/ProProject_GeekTrack_2022-09-04.zip b/1.Hardware/ProProject_GeekTrack_2022-09-04.zip deleted file mode 100644 index 91b0b68..0000000 Binary files a/1.Hardware/ProProject_GeekTrack_2022-09-04.zip and /dev/null differ diff --git a/1.Hardware/ProProject_GeekTrack_2022-09-04 - 副本.zip b/1.Hardware/ProProject_GeekTrackv1_2022-09-04.zip similarity index 100% rename from 1.Hardware/ProProject_GeekTrack_2022-09-04 - 副本.zip rename to 1.Hardware/ProProject_GeekTrackv1_2022-09-04.zip diff --git a/3.Docs/esp32-pico-d4_datasheet_cn.pdf b/3.Docs/esp32-pico-d4_datasheet_cn.pdf new file mode 100644 index 0000000..ea2e75e --- /dev/null +++ b/3.Docs/esp32-pico-d4_datasheet_cn.pdf @@ -0,0 +1,964 @@ +ESP32­PICO­D4 + +࠯ඌܿ۬඀ + + ϱЧ 2.0 + ুᶈྐ༏॓࠯ + ϱಃ © 2022 + +www.espressif.com + ܱႿЧ໓֖ + +Ч໓ູ֖Ⴈ޼ิ‫ ܂‬ESP32-PICO-D4 ଆቆ֥࠯ඌܿ۬ྐ༏b + +໓֖ϱЧ + +౨ᇀুᶈܲຩ https://www.espressif.com/zh-hans/support/download/documents ༯ᄛቋྍϱЧ໓֖b + +ྩ‫ר‬৥ൎ + +౨ᇀ໓֖ቋު်Ұुྩ‫ר‬৥ൎb + +໓֖э۷๙ᆩ + +Ⴈ޼ॖၛ๙‫ুݖ‬ᶈܲຩ‫ר‬ᄇ်૫ www.espressif.com/zh-hans/subscribe ‫ר‬ᄇ࠯ඌ໓֖э۷֥‫׈‬ሰႯࡱ๙ᆩbଢ଼ +ླေ۷ྍ‫ר‬ᄇၛࢤ൬ႵܱྍӁ௖֥໓֖๙ᆩb + +ᆣ඀༯ᄛ + +Ⴈ޼ॖၛ๙‫ুݖ‬ᶈܲຩᆣ඀༯ᄛ်૫ www.espressif.com/zh-hans/certificates ༯ᄛӁ௖ᆣ඀b + ଢ੣ + +1 ‫ۀ‬ඍ 6 + +2 ܵ࢖‫ק‬ၬ 7 + +2.1 ܵ࢖҃अ 7 + +2.2 ܵ࢖૭ඍ 7 + +2.3 Strapping ܵ࢖ 9 + +3 ‫ିۿ‬૭ඍ 11 + +3.1 CPU ‫ބ‬ோഈթԥ 11 + +3.2 ຓ҆ Flash ‫ ބ‬SRAM 11 + +3.3 ࣖᆒ 11 + +3.4 RTC ‫ܵݻۿ֮ބ‬৘ 11 + +4 ຓഡࢤ१‫ބ‬Ԯ‫ۋ‬ఖ 12 + +5 ‫׈‬గหྟ 13 + +5.1 धؓቋն‫קح‬ᆴ 13 + +5.2 ࡹၰ‫۽‬ቔ่ࡱ 13 + +5.3 ᆰੀ‫׈‬గหྟ (3.3 V, 25 °C) 13 + +5.4 Wi-Fi ഝ௔ 14 + +5.5 ֮‫ݻۿ‬ড࿩ഝ௔ 15 + +5.5.1 ࢤ൬ఖ 15 + +5.5.2 ‫ؿ‬ഝఖ 15 + +5.6 ߭ੀ‫ݯ‬໑؇౷ཌ 16 + +6 ჰ৘๭ 17 + +7 ຓຶഡ࠹ჰ৘๭ 18 + +8 ‫ٿ‬ልྐ༏ 19 + +9 ཌྷܱ໓֖‫ބ‬ሧჷ 22 + +ྩ‫ר‬৥ൎ 23 + і۬ + +1 ESP32-PICO-D4 Ӂ௖ܿ۬ 6 + +2 ܵ࢖‫ק‬ၬ 7 + +3 Strapping ܵ࢖ 10 + +4 धؓቋն‫קح‬ᆴ 13 + +5 ࡹၰ‫۽‬ቔ่ࡱ 13 + +6 ᆰੀ‫׈‬గหྟ (3.3 V, 25 °C) 13 + +7 Wi-Fi ഝ௔หྟ 14 + +8 ֮‫ݻۿ‬ড࿩ࢤ൬ఖหྟ 15 + +9 ֮‫ݻۿ‬ড࿩‫ؿ‬ഝఖหྟ 15 + Ҭ๭ + +1 ESP32-PICO-D4 ܵ࢖҃अč‫ڤ‬൪๭Ď 7 + +2 ߭ੀ‫ݯ‬໑؇౷ཌ 16 + +3 ESP32-PICO-D4 ଆቆჰ৘๭ 17 + +4 ESP32-PICO-D4 ଆቆຓຶഡ࠹ჰ৘๭ 18 + +5 ESP32-PICO-D4 ‫ٿ‬ልྐ༏ 19 + +6 ESP32-PICO-D4 ‫ٿ‬ል๭ྙ 20 + +7 ESP32-PICO-D4 STENCIL 21 + 1 ‫ۀ‬ඍ + +1 ‫ۀ‬ඍ + +ESP32-PICO-D4 ൞၂ॻࠎႿ ESP32 ֥༢๤ࠩ‫ٿ‬ል (SiP) ଆቆđॖิ‫܂‬ປᆜ֥ Wi-Fi ‫ބ‬ড࿩ ® ‫ିۿ‬b‫ھ‬ଆቆ֥ຓ +ܴԄժࣇູ (7.000±0.100) mm × (7.000±0.100) mm × (0.940±0.100) mmđᆜุᅝႨ֥ PCB ૫ࠒቋཬđၘࠢӮ +1 ۱ 4 MB ԱྛຓຶഡСࢤ१ (SPI) flashb +ESP32-PICO-D4 ֥‫ྏނ‬൞ ESP32 ྉோ *bESP32 ൞ࠢӮ 2.4 GHz Wi-Fi ‫ބ‬ড࿩චଆ֥ֆྉோٚσđҐႨ෻ࠒ‫׈‬ +(TSMC) ӑ֮‫ ֥ݻۿ‬40 ବ૜‫۽‬ၜbESP32-PICO-D4 ଆቆၘࡼࣖᆒaflashaੲѯ‫׈‬ಸaRF ௄஥৽ਫ਼֩෮Ⴕຓຶ +ఖࡱ໭‫ࠢډ‬Ӯࣉ‫ٿ‬ልଽč࡮ᅣࢫ 6ğჰ৘๭Ďđ҂ᄜླေຓຶჭఖࡱࠧॖ‫۽‬ቔbՎൈđႮႿ໭ླຓຶఖࡱđଆቆ +‫ބࢤݯ‬ҩ൫‫ݖ‬ӱ္ॖၛх૧đၹՎ ESP32-PICO-D4 ॖၛննࢆ֮‫܂‬ႋ৽֥‫گ‬ᄖӱ؇ѩิശܵ॥ིੱb +ESP32-PICO-D4 ऎСุࠒࣅ՘aྟି఼࣑ࠣ‫֮֩ݻۿ‬หׄđൡႨႿ಩‫ࡗॢޅ‬Ⴕཋࠇ‫׈‬ӽ‫֥׈܂‬ഡСđбೂॖԬ +պഡСa၄ਏഡСaԮ‫ۋ‬ఖࠣః෰ IoT ഡСb + + ඪૼğ + * ۷‫؟‬Ⴕܱ ESP32 ֥ྐ༏đ౨ҕॉ uESP32 ࠯ඌܿ۬඀vb + +і 1 ਙԛਔ ESP32-PICO-D4 ֥Ӂ௖ܿ۬b + і 1: ESP32­PICO­D4 Ӂ௖ܿ۬ + +োљ ཛଢ Ӂ௖ܿ۬ +ಪᆣ ড࿩ಪᆣ BQB +Wi-Fi ླྀၰ 802.11 b/g/n (802.11n ֥෎؇ۚղ 150 Mbps) +ড࿩ ‫۽‬ቔྐ֡ᇏྏ௔ੱٓຶ ᆦӻ A-MPDU ‫ ބ‬A-MSDU ऊ‫ކ‬Ġᆦӻ 0.4 µs Ќ޹ࡗ‫ۯ‬ + ླྀၰ 2412 ~ 2484 MHz +႗ࡱ ড࿩ V4.2 BR/EDR ‫ݻۿ֮ބ‬ড࿩ѓሙ + ഝ௔ NZIF ࢤ൬ఖđਲૹ؇ղ⚶97 dBm + Class-1aClass-2 ‫ ބ‬Class-3 ‫ؿ‬ഝఖ + ၻ௔ AFH + CVSD ‫ ބ‬SBC + ଆቆࢤ१ ADCaDACaԨଃԮ‫ۋ‬ఖaSD/SDIO/MMC ᇶࠏ॥ᇅఖaSPIa + SDIO/SPI Ֆࠏ॥ᇅఖaEMACa‫ ࠏ׈‬PWMaLED PWMa + ோഈԮ‫ۋ‬ఖ UARTaI2CaI2Sa‫ޣ‬ຓჹӱ॥ᇅఖaGPIOaઝԊ࠹ඔఖa + ࠢӮࣖᆒ TWAI®č࡙ಸ ISO 11898-1 ླྀၰđࠧ CAN ܿٓ 2.0Ď + ࠢӮ SPI flash ࠉ‫غ‬Ԯ‫ۋ‬ఖ + ‫۽‬ቔ‫׈‬࿢/‫׈׈܂‬࿢ 40 MHz ࣖᆒ + ‫۽‬ቔ‫׈‬ੀ 4 MB + ‫׈׈܂‬ੀ 3.0 V ~ 3.6 V + ࡹၰ‫۽‬ቔߌ࣢໑؇ٓຶ ௜नğ80 mA + ‫ٿ‬ልԄժ ቋཬğ500 mA + Ӗുૹ‫ۋ‬؇֩ࠩ (MSL) ⚶40 °C ~ 85 °C + (7.000±0.100) mm×(7.000±0.100) mm×(0.940±0.100) mm + ֩ࠩ 3 + +ুᶈྐ༏॓࠯ 6 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 2 ܵ࢖‫ק‬ၬ + +2 ܵ࢖‫ק‬ၬ + +2.1 ܵ࢖҃अ + + 48 CAP1_NC + 47 CAP2_NC + 46 VDDA + 45 XTAL_P_NC + 44 XTAL_N_NC + 43 VDDA + 42 IO21 + 41 U0TXD + 40 U0RXD + 39 IO22 + 38 IO19 + 37 VDD3P3_CPU + + VDDA 1 49 GND 36 IO23 + LNA_IN 2 35 IO18 + VDDA3P3 3 34 IO5 + VDDA3P3 4 33 SD1 + SENSOR_VP 5 32 SD0 +SENSOR_CAPP 6 31 CLK +SENSOR_CAPN 7 30 CMD + SENSOR_VN 8 29 SD3 + 28 SD2 + EN 9 27 IO17 + IO34 10 26 VDD_SDIO + IO35 11 25 IO16 + IO32 12 + + IO33 13 + IO25 14 + IO26 15 + IO27 16 + IO14 17 + IO12 18 + VDD3P3_RTC 19 + IO13 20 + IO15 21 + + IO2 22 + IO0 23 + IO4 24 + + ๭ 1: ESP32­PICO­D4 ܵ࢖҃अč‫ڤ‬൪๭Ď + +2.2 ܵ࢖૭ඍ + +ESP32-PICO-D4 ଆቆ‫܋‬Ⴕ 48 ۱ܵ࢖đऎุ૭ඍҕ࡮і 2. + + і 2: ܵ࢖‫ק‬ၬ + +଀ӫ ྽‫ݼ‬ ো྘ ‫ିۿ‬ +VDDA 1 P ଆ୅‫׈‬ჷ (2.3 V ~ 3.6 V) +LNA_IN 2 I/O ഝ௔ൻೆൻԛ + +ুᶈྐ༏॓࠯ 7 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 2 ܵ࢖‫ק‬ၬ + +଀ӫ ྽‫ݼ‬ ো྘ ‫ିۿ‬ +VDDA3P3 3 P ଆ୅‫׈‬ჷ (2.3 V ~ 3.6 V) +VDDA3P3 4 P ଆ୅‫׈‬ჷ (2.3 V ~ 3.6 V) +SENSOR_VP 5 I GPIO36aADC1_CH0aRTC_GPIO0 +SENSOR_CAPP 6 I GPIO37aADC1_CH1aRTC_GPIO1 +SENSOR_CAPN 7 I GPIO38aADC1_CH2aRTC_GPIO2 +SENSOR_VN 8 I GPIO39aADC1_CH3aRTC_GPIO3 + ۚ‫׈‬௜ğଆቆ൐ିĠ +EN 9 I ֮‫׈‬௜ğଆቆܱоĠ + ᇿၩğ҂ିಞᆃ۱ܵ࢖‫ॢڜ‬b +IO34 10 I GPIO34aADC1_CH6aRTC_GPIO4 + I GPIO35aADC1_CH7aRTC_GPIO5 +IO35 11 I/O GPIO32a32K_XPč32.768 kHz ࣖᆒൻೆĎaADC1_CH4aTOUCH9a + RTC_GPIO9 +IO32 12 I/O GPIO33a32K_XNč32.768 kHz ࣖᆒൻԛĎaADC1_CH5aTOUCH8a + RTC_GPIO8 +IO33 13 I/O GPIO25aDAC_1aADC2_CH8aRTC_GPIO6aEMAC_RXD0 + I/O GPIO26aDAC_2aADC2_CH9aRTC_GPIO7aEMAC_RXD1 +IO25 14 I/O GPIO27aADC2_CH7aTOUCH7aRTC_GPIO17aEMAC_RX_DV + I/O GPIO14aADC2_CH6aTOUCH6aRTC_GPIO16aMTMSaHSPICLKa +IO26 15 HS2_CLKaSD_CLKaEMAC_TXD2 + I/O GPIO12aADC2_CH5aTOUCH5aRTC_GPIO15aMTDIaHSPIQa +IO27 16 P HS2_DATA2aSD_DATA2aEMAC_TXD3 + I/O RTC IO ‫׈‬ჷൻೆ (3.0 V ~ 3.6 V) +IO14 17 GPIO13aADC2_CH4aTOUCH4aRTC_GPIO14aMTCKaHSPIDa + I/O HS2_DATA3aSD_DATA3aEMAC_RX_ER +IO12 18 GPIO15aADC2_CH3aTOUCH3aRTC_GPIO13aMTDOaHSPICS0a + I/O HS2_CMDaSD_CMDaEMAC_RXD3 +VDD3P3_RTC 19 I/O GPIO2aADC2_CH2aTOUCH2aRTC_GPIO12aHSPIWPaHS2_DATA0a + SD_DATA0 +IO13 20 I/O GPIO0aADC2_CH1aTOUCH1aRTC_GPIO11aCLK_OUT1a + I/O EMAC_TX_CLK +IO15 21 P GPIO4aADC2_CH0aTOUCH0aRTC_GPIO10aHSPIHDaHS2_DATA1a + I/O SD_DATA1aEMAC_TX_ER +IO2 22 I/O GPIO16aHS1_DATA4aU2RXDaEMAC_CLK_OUT + I/O VDD3P3_RTC ‫׈‬ჷൻԛđ౨࡮і۬༯ٚඪૼ 1 +IO0 23 I/O GPIO17aHS1_DATA5aU2TXDaEMAC_CLK_OUT_180 + I/O GPIO9aSD_DATA2aSPIHDaHS1_DATA2aU1RXD +IO4 24 I/O GPIO10aSD_DATA3aSPIWPaHS1_DATA3aU1TXD + I/O GPIO11aSD_CMDaSPICS0aHS1_CMDaU1RTS +IO16 25 I/O GPIO6aSD_CLKaSPICLKaHS1_CLKaU1CTS + I/O GPIO7aSD_DATA0aSPIQaHS1_DATA0aU2RTS +VDD_SDIO 26 GPIO8aSD_DATA1aSPIDaHS1_DATA1aU2CTS + GPIO5aVSPICS0aHS1_DATA6aEMAC_RX_CLK +IO17 27 GPIO18aVSPICLKaHS1_DATA7 + +SD2 28 + +SD3 29 + +CMD 30 + +CLK 31 + +SD0 32 + +SD1 33 + +IO5 34 + +IO18 35 + +ুᶈྐ༏॓࠯ 8 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 2 ܵ࢖‫ק‬ၬ + +଀ӫ ྽‫ݼ‬ ো྘ ‫ିۿ‬ +IO23 36 I/O GPIO23aVSPIDaHS1_STROBE +VDD3P3_CPU 37 P CPU IO ‫׈‬ჷൻೆ (1.8 V ~ 3.6 V) +IO19 38 I/O GPIO19aVSPIQaU0CTSaEMAC_TXD0 +IO22 39 I/O GPIO22aVSPIWPaU0RTSaEMAC_TXD1 +U0RXD 40 I/O GPIO3aU0RXDaCLK_OUT2 +U0TXD 41 I/O GPIO1aU0TXDaCLK_OUT3aEMAC_RXD2 +IO21 42 I/O GPIO21aVSPIHDaEMAC_TX_EN +VDDA 43 P ଆ୅‫׈‬ჷ (2.3 V ~ 3.6 V) +XTAL_N_NC 44 - NC +XTAL_P_NC 45 - NC +VDDA 46 P ଆ୅‫׈‬ჷ (2.3 V ~ 3.6 V) +CAP2_NC 47 - NC +CAP1_NC 48 - NC + +ᇿၩğ + 1. ళೆൔ flash ৵ࢤᇀ VDD_SDIOđႮ VDD3P3_RTC ๙‫ݖ‬ჿ 6 Ω ‫׈‬ቅᆰࢤ‫׈܂‬bၹՎđVDD_SDIO ཌྷؓ VDD3P3_RTC + ߶Ⴕ၂‫׈ק‬࿢ࢆb + 2. IO16aIO17aCMDaCLKaSD0 ‫ ބ‬SD1 ႨႿ৵ࢤళೆൔ flashđ҂ॖႨႿః෰‫ିۿ‬bབྷ࡮ᅣࢫ 6 ჰ৘๭b + 3. ೂ‫ݔ‬ေຓࢤ PSRAMđ๷ࡩ൐Ⴈ SD3 (GPIO10) ႨႿ PSRAM_CSđ౨ҕॉᅣࢫ 7 ຓຶഡ࠹ჰ৘๭b + +2.3 Strapping ܵ࢖ + +ESP32 ‫܋‬Ⴕ 5 ۱ Strapping ܵ࢖đॖҕॉᅣࢫ 6 ‫׈‬ਫ਼ჰ৘๭ğ + • MTDI + • GPIO0 + • GPIO2 + • MTDO + • GPIO5 + +ೈࡱॖၛ‫؀‬౼࠷թఖoGPIO_STRAPPINGpᇏᆃ 5 ۱ܵ࢖ strapping ֥ᆴb +ᄝྉோ֥༢๤‫໊گ‬čഈ‫໊گ׈‬aRTC ु૊‫໊گܐ‬aఴ࿢‫໊گ‬Ď٢ष֥‫ݖ‬ӱᇏđStrapping ܵ࢖ؓ‫׈‬௜Ґဢѩթԥ +֞෭թఖᇏđ෭թູo0pࠇo1pđѩ၂ᆰЌӻ֞ྉோ‫ܱࠇ׈ו‬оb +ૄ၂۱ Strapping ܵ࢖‫߶׻‬৵ࢤଽ҆ഈঘ/༯ঘbೂ‫ݔ‬၂۱ Strapping ܵ࢖ીႵຓ҆৵ࢤࠇᆀ৵ࢤ֥ຓ҆ཌਫ਼ԩ +Ⴟۚቅॆሑ෿đଽ҆೐ഈঘ/༯ঘࡼथ‫ ק‬Strapping ܵ࢖ൻೆ‫׈‬௜֥ଏಪᆴb +ູ‫ڿ‬э Strapping ֥ᆴđႨ޼ॖၛႋႨຓ҆༯ঘ/ഈঘ‫׈‬ቅđࠇᆀႋႨᇶࠏ MCU ֥ GPIO ॥ᇅ ESP32 ഈ‫໊گ׈‬ +٢षൈ֥ Strapping ܵ࢖‫׈‬௜b +‫໊گ‬٢षުđStrapping ܵ࢖‫௴ބ‬๙ܵ࢖‫ିۿ‬ཌྷ๝b +஥ᇂ Strapping ܵ࢖֥བྷ༥ఓ‫׮‬ଆൔ౨ҕᄇі 3 b + +ুᶈྐ༏॓࠯ 9 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 2 ܵ࢖‫ק‬ၬ і 3: Strapping ܵ࢖ + + ܵ࢖ ଽᇂ LDO (VDD_SDIO) ‫׈‬࿢ + MTDI + ܵ࢖ ଏಪ 3.3 V 1.8 V + GPIO0 + GPIO2 ༯ঘ 0 1 + ܵ࢖ + MTDO ༢๤ఓ‫׮‬ଆൔ + + ܵ࢖ ଏಪ SPI ఓ‫׮‬ଆൔ ༯ᄛఓ‫׮‬ଆൔ + MTDO + GPIO5 ഈঘ 1 0 + + ༯ঘ ໭ܱཛ 0 + + ༢๤ఓ‫ݖ׮‬ӱᇏđ॥ᇅ U0TXD յႆ + + ଏಪ U0TXD ᆞӈյႆ U0TXD ഈ‫׈‬҂յႆ + + ഈঘ 1 0 + + SDIO Ֆࠏྐ‫ݼ‬ൻೆൻԛൈ྽ + + ༯ࢆခҐဢ ༯ࢆခҐဢ ഈശခҐဢ ഈശခҐဢ + + ଏಪ ༯ࢆခൻԛ ഈശခൻԛ ༯ࢆခൻԛ ഈശခൻԛ + + ഈঘ 0 0 1 1 + + ഈঘ 0 1 0 1 + +ඪૼğ + + • ‫ࡱܥ‬ॖၛ๙‫ݖ‬஥ᇂ၂ུ࠷թఖбห໊đᄝఓ‫ڿު׮‬эoଽᇂ LDO (VDD_SDIO) ‫׈‬࿢p‫ބ‬oSDIO Ֆࠏྐ‫ݼ‬ൻೆൻ + ԛൈ྽p֥ഡ‫ק‬b + + • ESP32-PICO-D4 ࠢӮ֥ຓ҆ SPI flash ‫۽‬ቔ‫׈‬࿢ູ 3.3 VđၹՎᄝഈ‫ݖ໊گ׈‬ӱᇏླЌӻ Strapping ܵ࢖ MTDI ູ + ֮‫׈‬௜b + +ুᶈྐ༏॓࠯ 10 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 3 ‫ିۿ‬૭ඍ + +3 ‫ିۿ‬૭ඍ + +Чᅣ૭ඍ ESP32-PICO-D4 ֥ऎุ‫ିۿ‬b + +3.1 CPU ‫ބ‬ோഈթԥ + +ESP32-PICO-D4 ձᄛ 2 ۱֮‫ ݻۿ‬Xtensa® 32-bit LX6 ັԩ৘ఖb +ESP32-PICO-D4 ோഈթԥЇওğ + + • 448 KB ֥ ROMđႨႿӱ྽ఓ‫ބ׮‬ଽ‫טିۿނ‬Ⴈ + • ႨႿඔऌ‫ބ‬ᆷ਷թԥ֥ 520 KB ோഈ SRAM + • RTC ॹ෎թԥఖđູ 8 KB ֥ SRAMđॖၛᄝ Deep-sleep ଆൔ༯ RTC ఓ‫׮‬ൈႨႿඔऌթԥၛࠣФᇶ + + CPU ٠໙ + • RTC ત෎թԥఖđູ 8 KB ֥ SRAMđॖၛᄝ Deep-sleep ଆൔ༯Фླྀԩ৘ఖ٠໙ + • 1 Kbit ֥ eFuseđఃᇏ 256 bit ູ༢๤ህႨčMAC ֹᆶ‫ބ‬ྉோഡᇂĎ; ఃჅ 768 bit Ќ਽۳Ⴈ޼ӱ྽, ᆃུ + + ӱ྽Їও flash ࡆૡ‫ބ‬ྉோ ID + +3.2 ຓ҆ Flash ‫ ބ‬SRAM + +ESP32 ᆦӻ‫؟‬۱ຓ҆ QSPI flash ‫࣡ބ‬෿ෛࠏթԥఖ (SRAM)bབྷ౦ॖҕॉuESP32 ࠯ඌҕॉ൭Ҩv ᇏ֥ SPI ᅣ +ࢫbESP32 ߎᆦӻࠎႿ AES ֥႗ࡱࡆࢳૡ‫ିۿ‬đՖ‫ط‬Ќ޹ष‫ؿ‬ᆀ flash ᇏ֥ӱ྽‫ބ‬ඔऌb +ESP32 ॖ๙‫ۚݖ‬෎ߏթ٠໙ຓ҆ QSPI flash ‫ ބ‬SRAMğ + + • ຓ҆ flash ॖၛ๝ൈ႘ഝ֞ CPU ᆷ਷‫ބ‬ᆺ‫؀‬ඔऌॢࡗb + – ֒႘ഝ֞ CPU ᆷ਷ॢࡗൈđ၂Ցቋ‫؟‬ॖ႘ഝ 11 MB + 248 KBbೂ‫ݔ‬၂Ց႘ഝӑ‫ ݖ‬3 MB + 248 KBđ + ᄵ cache ྟିॖିႮႿ CPU ֥๷ҩྟ‫؀‬౼‫֮ࢆط‬b + – ֒႘ഝ֞ᆺ‫؀‬ඔऌॢࡗൈđ၂Ցቋ‫؟‬ॖၛ႘ഝ 4 MBbᆦӻ 8-bita16-bit ‫ ބ‬32-bit ‫؀‬౼b + + • ຓ҆ SRAM ॖ႘ഝ֞ CPU ඔऌॢࡗb၂Ցቋ‫؟‬ॖ႘ഝ 4 MBbᆦӻ 8-bita16-bit ‫ ބ‬32-bit ٠໙b +ESP32-PICO-D4 ࠢӮਔ 4 MB ֥ຓ҆ SPI flashb + +3.3 ࣖᆒ + +ESP32-PICO-D4 ၘࠢӮ 40 MHz ࣖᆒb + +3.4 RTC ‫ܵݻۿ֮ބ‬৘ + +ESP32 ҐႨਔ༵ࣉ֥‫׈‬ჷܵ৘࠯ඌđॖၛᄝ҂๝֥‫ݻۿ‬ଆൔᆭࡗ్ߐb +ܱႿ ESP32 ᄝ҂๝֥‫ݻۿ‬ଆൔ༯֥‫׈‬ੀཨ‫ݻ‬đབྷ࡮uESP32 ࠯ඌܿ۬඀vᇏᅣࢫoRTC ‫ܵݻۿ֮ބ‬৘pb + +ুᶈྐ༏॓࠯ 11 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 4 ຓഡࢤ१‫ބ‬Ԯ‫ۋ‬ఖ + +4 ຓഡࢤ१‫ބ‬Ԯ‫ۋ‬ఖ + +བྷ࡮uESP32 ࠯ඌܿ۬඀vᇏຓഡࢤ१‫ބ‬Ԯ‫ۋ‬ఖᅣࢫb + ඪૼğ + • IO16aIO17aCMDaCLKaSD0 ‫ ބ‬SD1 ႨႿ৵ࢤళೆൔ flashđ҂ࡹၰႨႿః෰‫ିۿ‬bབྷ࡮ᅣࢫ 6 ჰ৘๭b + • ೂ‫ݔ‬ေຓࢤ PSRAMđ๷ࡩ൐Ⴈ SD3 (GPIO10) ႨႿ PSRAM_CSđ౨ҕॉᅣࢫ 7 ຓຶഡ࠹ჰ৘๭b + +ুᶈྐ༏॓࠯ 12 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 5 ‫׈‬గหྟ + +5 ‫׈‬గหྟ + +5.1 धؓቋն‫קح‬ᆴ + +ӑԛधؓቋն‫קح‬ᆴіॖି֝ᇁఖࡱႥࣲྟ෥ߊbᆃᆺ൞఼‫קح֥ט‬ᆴđ҂ടࠣఖࡱᄝᆃུࠇః෱่ࡱ༯ӑԛ +Ч࠯ඌܿ۬ᆷѓ֥‫ྟିۿ‬Ҡቔbࡹၰ‫۽‬ቔ่ࡱ౨ҕॉі 5b + + і 4: धؓቋն‫קح‬ᆴ + +‫ݼژ‬ ҕඔ ቋཬᆴ ቋնᆴ ֆ໊ +VDD33 ‫׈׈܂‬࿢ ⚶0.3 3.6 V +IO 1 IO ൻԛሹ‫׈‬ੀ - 1,100 mA +Tstore թԥ໑؇ ⚶40 85 °C + +1. ଆቆ֥ IO ൻԛሹ‫׈‬ੀ֥ҩ൫่ࡱູ 25 °C ߌ࣢໑؇đVDD3P3_RTC, VDD3P3_CPU, VDD_SDIO ೘۱‫׈‬ჷთ֥ܵ࢖ൻ + ԛۚ‫׈‬௜౏ᆰࢤࢤֹbՎൈଆቆᄝЌӻ‫۽‬ቔሑ෿ 24 ཬൈުđಯିᆞӈ‫۽‬ቔbఃᇏ VDD_SDIO ‫׈‬ჷთ֥ܵ࢖҂Їও৵ + ࢤ flash ‫ބ‬/ࠇ PSRAM ֥ܵ࢖b + +2. ܱႿ‫׈‬ჷთ౨ҕॉuESP32 ࠯ඌܿ۬඀v ‫ڸ‬੣ᇏі IO_MUXb + +5.2 ࡹၰ‫۽‬ቔ่ࡱ + + і 5: ࡹၰ‫۽‬ቔ่ࡱ + +‫ݼژ‬ ҕඔ ቋཬᆴ ‫྘ׅ‬ᆴ ቋնᆴ ֆ໊ +VDD33 ‫׈׈܂‬࿢ 3.0 3.3 3.6 V +IV DD ຓ҆‫׈‬ჷ֥‫׈׈܂‬ੀ 0.5 - - A +T ‫۽‬ቔߌ࣢໑؇ ⚶40 - 85 °C + +5.3 ᆰੀ‫׈‬గหྟ (3.3 V, 25 °C) + + і 6: ᆰੀ‫׈‬గหྟ (3.3 V, 25 °C) + +‫ݼژ‬ ҕඔ ቋཬᆴ ‫྘ׅ‬ᆴ ቋնᆴ ֆ໊ +CIN - 2 +VIH ܵ࢖‫׈‬ಸ 0.75×VDD1 - - pF +VIL ⚶0.3 - +IIH ۚ‫׈‬௜ൻೆ‫׈‬࿢ - - VDD1+0.3 V +IIL - - +VOH ֮‫׈‬௜ൻೆ‫׈‬࿢ 0.8×VDD1 - 0.25×VDD1 V +VOL - - + ۚ‫׈‬௜ൻೆ‫׈‬ੀ - 40 50 nA +IOH - 40 + ֮‫׈‬௜ൻೆ‫׈‬ੀ - 20 50 nA +IOL + ۚ‫׈‬௜ൻԛ‫׈‬࿢ - 28 - V + + ֮‫׈‬௜ൻԛ‫׈‬࿢ 0.1×VDD1 V + + ۚ‫׈‬௜ঘ‫׈‬ੀ VDD3P3_CPU ‫׈‬ჷთ 1, 2 - mA + + (VDD1 = 3.3 V, VOH >= 2.64 V, VDD3P3_RTC ‫׈‬ჷთ 1, 2 - mA + + ܵ࢖ൻԛ఼؇ഡູቋնᆴ) VDD_SDIO ‫׈‬ჷთ 1, 3 - mA + + ֮‫׈‬௜ܹ‫׈‬ੀ + + (VDD1 = 3.3 V, VOL = 0.495 V, - mA + ܵ࢖ൻԛ఼؇ഡູቋնᆴ) + +ুᶈྐ༏॓࠯ 13 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 5 ‫׈‬గหྟ + +‫ݼژ‬ ҕඔ ቋཬᆴ ‫྘ׅ‬ᆴ ቋնᆴ ֆ໊ +RP U ഈঘ‫׈‬ቅ - 45 - kΩ +RP D ༯ঘ‫׈‬ቅ - 45 - kΩ +VI L_nRS T CHIP_PU ܱоྉோ֥֮‫׈‬௜ൻೆ‫׈‬࿢ - - 0.6 V + +ඪૼğ + +1. VDD ൞ I/O ֥‫׈׈܂‬ჷbܱႿ‫׈‬ჷთ౨ҕॉuESP32 ࠯ඌܿ۬඀v ‫ڸ‬੣ᇏі IO_MUXb + +2. VDD3P3_CPU ‫ ބ‬VDD3P3_RTC ‫׈‬ჷთܵ࢖֥ֆ۱ܵ࢖֥ঘ‫׈‬ੀෛܵ࢖ඔਈᄹࡆ‫ཬࡨط‬đՖჿ 40 mA ࡨཬ֞ჿ 29 + mAb + +3. VDD_SDIO ‫׈‬ჷთ֥ܵ࢖҂Їও৵ࢤ flash ‫ބ‬/ࠇ PSRAM ֥ܵ࢖b + +5.4 Wi­Fi ഝ௔ і 7: Wi­Fi ഝ௔หྟ + + ҕඔ ቋཬᆴ ‫྘ׅ‬ᆴ ቋնᆴ ֆ໊ + ‫۽‬ቔྐ֡ᇏྏ௔ੱٓຶ 1 2412 - 2484 MHz + ൻԛቅॆ 2 - 50 - Ω + ൻԛ‫ ੱۿ‬3 + 72.2 Mbps PA ൻԛ‫ੱۿ‬ 13 14 15 dBm + 11b ଆൔ༯ PA ൻԛ‫ੱۿ‬ 19.5 20 20.5 dBm + + DSSSđ1 Mbps ਲૹ؇ ⚶98 - dBm + CCKđ11 Mbps - ⚶91 - dBm + OFDMđ6 Mbps - ⚶93 - dBm + OFDMđ54 Mbps - ⚶75 - dBm + HT20đMCS0 - ⚶93 - dBm + HT20đMCS7 - ⚶73 - dBm + HT40đMCS0 - ⚶90 - dBm + HT40đMCS7 - ⚶70 - dBm + MCS32 - ⚶89 - dBm + - + OFDMđ6 Mbps 37 - dB + OFDMđ54 Mbps ਣ֡ၝᇅ 21 - dB + HT20đMCS0 - 37 - dB + HT20đMCS7 - 20 - dB + - + - + +1. ‫۽‬ቔྐ֡ᇏྏ௔ੱٓຶႋ‫ֹࠇࡅݓކژ‬౵֥ܿٓѓሙbೈࡱॖၛ஥ᇂ‫۽‬ቔྐ֡ᇏྏ௔ੱٓຶb +2. ൐Ⴈຓ҆฿ཌ֥ଆቆൻԛቅॆູ 50 Ωđ҂൐Ⴈຓ҆฿ཌ֥ଆቆॖ໭ླܱᇿൻԛቅॆb +3. ۴ऌӁ௖ࠇಪᆣ֥ေ౰đႨ޼ॖၛ஥ᇂଢѓ‫ੱۿ‬b + +ুᶈྐ༏॓࠯ 14 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 5 ‫׈‬గหྟ + +5.5 ֮‫ݻۿ‬ড࿩ഝ௔ і 8: ֮‫ݻۿ‬ড࿩ࢤ൬ఖหྟ + +5.5.1 ࢤ൬ఖ ่ࡱ ቋཬᆴ ‫྘ׅ‬ᆴ ቋնᆴ ֆ໊ + - - ⚶97 - dBm + ҕඔ - 0 - - dBm + ਲૹ؇ @30.8% PER - - +10 - dB + ቋնࢤ൬ྐ‫@ ݼ‬30.8% PER F = F0 + 1 MHz - ⚶5 - dB + ‫֡ྐ܋‬ၝᇅб C/I F = F0 ⚶1 MHz - ⚶5 - dB + F = F0 + 2 MHz - ⚶25 - dB + ਣ֡ၝᇅб C/I F = F0 ⚶2 MHz - ⚶35 - dB + F = F0 + 3 MHz - ⚶25 - dB + ջຓቅೖ F = F0 ⚶3 MHz - ⚶45 - dB + ޺‫ט‬ 30 MHz ~ 2000 MHz ⚶10 - - dBm + 2000 MHz ~ 2400 MHz ⚶27 - - dBm + 2500 MHz ~ 3000 MHz ⚶27 - - dBm + 3000 MHz ~ 12.5 GHz ⚶10 - - dBm + - ⚶36 - - dBm + +5.5.2 ‫ؿ‬ഝఖ і 9: ֮‫ݻۿ‬ড࿩‫ؿ‬ഝఖหྟ + + ҕඔ ่ࡱ ቋཬᆴ ‫྘ׅ‬ᆴ ቋնᆴ ֆ໊ + ഝ௔‫ؿ‬ഝ‫ੱۿ‬ - - 0 - dBm + ᄹၭ॥ᇅ҄Ӊ - - 3 - dBm + ഝ௔‫ੱۿ‬॥ᇅٓຶ - ⚶12 - +9 dBm + F = F0 ± 2 MHz - ⚶52 - dBm + ਣ֡‫ؿ‬ഝ‫ੱۿ‬ F = F0 ± 3 MHz - ⚶58 - dBm + F = F0 ± > 3 MHz - ⚶60 - dBm + ∆ f 1avg - - - 265 kHz + ∆ f 2max - 247 - - kHz + ∆ f 2avg/∆ f 1avg - - ⚶0.92 - - + ICFT - - ⚶10 - kHz + ௎၍෎ੱ - - 0.7 - kHz/50 µs + ொ၍ - - 2 - kHz + +ুᶈྐ༏॓࠯ 15 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 5 ‫׈‬గหྟ + +5.6 ߭ੀ‫ݯ‬໑؇౷ཌ + +Ⴥଶ (℃) + +250 શ꧊Ⴥଶ + 235 ~ 250 ℃ + ᶼᅾ௤Ⴥ‫܄‬ ‫܄ܩٯ‬ + ࢧၞ‫܄‬ –1 ~ –5 ℃/s +217 150 ~ 200 ℃ 60 ~ 120 s !217 ℃ 60 ~ 90 s + +200 ᆄള෸ᳵ + > 30 s + + ‫܋‬Ⴥ‫܄‬ + 1 ~ 3 ℃/s +100 + +50 + +25 ෸ᳵ (s) + 250 +0 + + 0 50 100 150 200 + +‫܋‬Ⴥ‫ — ܄‬Ⴥଶғ25 ~ 150 ℃ ෸ᳵғ60 ~ 90 s ‫܋‬Ⴥෑሲғ1 ~ 3 ℃/s +ᶼᅾ௤Ⴥ‫ — ܄‬Ⴥଶғ150 ~ 200 ℃ ෸ᳵғ60 ~ 120 s +ࢧၞᆄള‫ — ܄‬Ⴥଶғ>217 ℃ ෸ᳵғ60 ~ 90 sҔશ꧊Ⴥଶғ235 ~ 250 ℃ ෸ᳵғ30 ~ 70 s +‫ — ܄ܩٯ‬Ⴥଶғશ꧊Ⴥଶ ~ 180 ℃ ᴳჅෑሲ–1 ~ –5 ℃/s +ᆄා — Ჟᱷᱞ‫ݳ‬ᰂ෫᱌ᆄා (SAC305) + + ๭ 2: ߭ੀ‫ݯ‬໑؇౷ཌ + +ඪૼğ +ࡹၰଆቆᆺ‫ݖ‬၂Ց߭ੀ‫ݯ‬b + +ুᶈྐ༏॓࠯ 16 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 6 ჰ৘๭ + +6 ჰ৘๭ + ๭ 3: ESP32­PICO­D4 ଆቆჰ৘๭ + +ুᶈྐ༏॓࠯ 17 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 7 ຓຶഡ࠹ჰ৘๭ + + 7 ຓຶഡ࠹ჰ৘๭ 5 4 3 2 1 + +D D + VDD33 + VDD33 + + C1 C2 IO21 JP2 + 10uF/6.3V(10%) 0.1uF/6.3V(10%) U0TXD 1 + U0RXD 21 + IO22 32 + IO19 43 + + 4 + + UART + + GND GND GND 49 GND + GND + VDD33 + 48 + CAP1_NC 47 VDD_SDIO + CAP2_NC 46 + C5 + VDDA 45 GND + XTAL_P_NC 44 + XTAL_N_NC 43 0.1uF/6.3V(10%) + + ANT 1 VDDA 42 36 IO23 PSRAM_CS 1 8 + IO21 41 IO23 35 + IO18 34 + U0TXD 40 + U0RXD 39 IO5 33 + SD1 32 + IO22 38 SD0 31 + IO19 37 CLK 30 + VDD3P3_CPU CMD 29 + SD3 28 + 1 ANT1 L1 TBD LAN_IN 2 VDDA SD2 27 IO18 SIO1 2 CS# VDD 7 SIO3 + IO17 26 +C 2 3 LNA_IN VDD_SDIO 25 IO5 SIO2 3 SO/SIO1 SIO3 6 SCLK C + C3 4 VDDA3P3 IO16 SIO0 4 SIO2 SCLK 5 SIO0 + C4 5 VDDA3P3 VSS SI/SIO0 + SENSOR_VP SIO2 + + TBD TBD SENSOR_CAPP 6 SENSOR_VP SCLK U2 pSRAM + + SENSOR_CAPN 7 SENSOR_CAPP SIO3 + 8 SENSOR_CAPN + SENSOR_VN PSRAM_CS GND + + GND GND GND EN 9 SENSOR_VN IO9 + IO34 10 EN + 11 IO34 SIO1 + + IO35 12 IO35 + + IO32 FLASH_CS + + IO32 + + 13 VDD_SDIO + 14 IO33 + 15 IO25 SPI/QPI ESP32-PICO-D4 Flash(3.3V) pSRAM(3.3V) + 16 IO26 + VDD33 17 IO27 Interface Signal Module Pin (Internal)Signal (External) Signal + 18 IO14 + U1 19 IO12 ESP32-PICO-D4 VDD33 Clock CLK CLK SCLK + 20 VDD3P3_RTC + 21 IO13 + 22 IO15 + 23 IO2 + 24 IO0 + + IO4 + + Flash Chip Select IO16 FLASH_CS - + + R2 + +B TBD pSRAM Chip Select SD3 - PSRAM_CS B + + SW1 + + SI/SIO[0] SD1 SI SIO0 + + R3 0R(1%) EN IO33 + IO25 + IO26 SO/SIO[1] IO17 SO SIO1 + IO27 + Reset Button IO14 + IO12 + C6 IO13 + IO15 + TBD IO2 + IO0 + IO4 + + JP3 JP1 WP/SIO[2] SD0 WP SIO2 + 1 1 + 21 HOLD/SIO[3] CMD HOLD SIO3 + 12 + 23 2 + 34 Boot Option + 4 + GND GND GND + JTAG + +A ๭ 4: ESP32­PICO­D4 ଆቆຓຶഡ࠹ჰ৘๭ A + + ඪૼğ + + ູಒЌྉோഈ‫׈‬ൈ֥‫׈܂‬ᆞӈđEN ܵ࢖ԩླေᄹࡆ RC ࿼Ӿ‫׈‬ਫ਼bRC ๙ӈࡹၰູ R = 10 kΩđC = 1 µFđ֌ऎุඔᆴಯ + ླ۴ऌ5ଆቆ‫׈‬ჷ֥ഈ‫׈‬ൈ྽‫ބ‬ྉ4ோ֥ഈ‫໊گ׈‬ൈ྽ࣉྛ‫ט‬ᆜ3 bྉோ֥ഈ‫໊گ׈‬ൈ྽๭2ॖҕॉuESP32 ࠯ඌܿ۬඀1 vᇏ + ֥‫׈‬ჷܵ৘ᅣࢫb + + ুᶈྐ༏॓࠯ 18 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 8 ‫ٿ‬ልྐ༏ + +8 ‫ٿ‬ልྐ༏ + + ๭ 5: ESP32­PICO­D4 ‫ٿ‬ልྐ༏ + +ুᶈྐ༏॓࠯ 19 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + 8 ‫ٿ‬ልྐ༏ + + 48 37 + +1 36 + + C0.5 GND Via Ø0.25 + + 49 0.50 + 2.10 + 4.00 + 4.50 + 6.73 + + 0.25 R0.05 + + 12 25 + +0.68 0.50 + 2.10 + 13 4.0024 + 4.50 + 6.73 + + 0.78 Copper + + 0.68 Solder mask opening + Via +Details of recommended copper-defined pad. +0.35 Unit: mm + 0.25 Tolerance: +/- 0.05 mm + +Notes: + 1. It is recommended to use copper-defined pad for Pin 1 to Pin 48 and + solder-mask-defined pad for Pin 49 (thermal pad). + 2. This drawing is subject to change without notice. + +ুᶈྐ༏॓࠯ ๭ 6: ESP32­PICO­D4 ‫ٿ‬ል๭ྙ ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + + 20 + ّঌ໓֖ၩ࡮ + 8 ‫ٿ‬ልྐ༏ + + 0.30 + 1.80 + 2.40 + 3.90 + 6.05 + 7.00 + 7.71 + + 0.30 + + 1.80 + + 2.40 + 3.90 + 6.05 + 7.00 + 7.71 + +Notes: Copper + 1. It is recommended to use a stencil of 80 um + thickness. Paste mask opening + 2. This drawing is subject to change without + notice. Recommended via drill size: 0.25 mm + Unit: mm + Tolerance: +/- 0.05 mm + +ুᶈྐ༏॓࠯ ๭ 7: ESP32­PICO­D4 STENCIL ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + + 21 + ّঌ໓֖ၩ࡮ + 9 ཌྷܱ໓֖‫ބ‬ሧჷ + +9 ཌྷܱ໓֖‫ބ‬ሧჷ + +ཌྷܱ໓֖ + + • uESP32 ࠯ඌܿ۬඀v – ิ‫ ܂‬ESP32 ྉோ֥႗ࡱ࠯ඌܿ۬b + • uESP32 ࠯ඌҕॉ൭Ҩv – ิ‫ ܂‬ESP32 ྉோ֥թԥఖ‫ބ‬ຓഡ֥བྷ༥൐Ⴈඪૼb + • uESP32 ႗ࡱഡ࠹ᆷଲv – ิ‫ࠎ܂‬Ⴟ ESP32 ྉோ֥Ӂ௖ഡ࠹ܿٓb + • uESP32 ा༂іࠣࢳथϷ‫م‬v – ิ‫ܱ܂‬Ⴟ ESP32 ྉோ֥ഡ࠹໙ี֥ඪૼ‫ࢳބ‬थٚσb + • ᆣ඀ + + https://espressif.com/zh-hans/support/documents/certificates + • ESP32 Ӂ௖/‫۽‬ၜэ۷๙ᆩ (PCN) + + https://espressif.com/zh-hans/support/documents/pcns + • ESP32 ‫܂ิ – ۡ܄‬Ⴕܱνಆabuga࡙ಸྟaఖࡱॖौྟ֥ྐ༏ + + https://espressif.com/zh-hans/support/documents/advisories + • ໓֖۷ྍ‫רބ‬ᄇ๙ᆩ + + https://espressif.com/zh-hans/support/download/documents + +ष‫ؿ‬ᆀഠ౵ + + • uESP32 ESP-IDF щӱᆷଲv – ESP-IDF ष‫֥ࡏॿؿ‬໓֖ᇏྏb + • ESP-IDF ࠣ GitHub ഈ֥ః෱ष‫ࡏॿؿ‬ + + https://github.com/espressif + • ESP32 ંฆ – ‫۽‬ӱഽؓ‫۽‬ӱഽ (E2E) ֥ഠ౵đଢ଼ॖၛᄝᆃ৚ิԛ໙ีaࢳथ໙ีa‫ٳ‬ཚᆩ്aฐ෬ܴׄb + + https://esp32.com/ + • The ESP Journal – ‫ٳ‬ཚুᶈ‫۽‬ӱഽ֥ቋࡄൌ࡬a࠯ඌ໓ᅣ‫۽ބ‬ቔෛгb + + https://blog.espressif.com/ + • SDK ‫ބ‬ဆൕaAppa‫۽‬ऎaAT ֩༯ᄛሧჷ + + https://espressif.com/zh-hans/support/download/sdks-demos + +Ӂ௖ + + • ESP32 ༢ਙྉோ – ESP32 ಆ༢ਙྉோb + https://espressif.com/zh-hans/products/socs?id=ESP32 + + • ESP32 ༢ਙଆቆ – ESP32 ಆ༢ਙଆቆb + https://espressif.com/zh-hans/products/modules?id=ESP32 + + • ESP32 ༢ਙष‫ؿ‬ϰ – ESP32 ಆ༢ਙष‫ؿ‬ϰb + https://espressif.com/zh-hans/products/devkits?id=ESP32 + + • ESP Product SelectorčুᶈӁ௖࿊྘‫۽‬ऎĎ– ๙‫ݖ‬ೱ࿊ྟିҕඔaࣉྛӁ௖ؓбॹ෎‫໊ק‬ଢ଼෮ླေ֥Ӂ௖b + https://products.espressif.com/#/product-selector?language=zh + +৳༢໡ૌ + + • അༀ໙ีa࠯ඌᆦӻa‫׈‬ਫ਼ჰ৘๭ & PCB ഡ࠹ബᄇa‫ܓ‬ઙဢ௖čཌഈഅ‫׋‬ĎaӮູ‫܂‬ႋഅaၩ࡮აࡹၰ + https://espressif.com/zh-hans/contact-us/sales-questions + +ুᶈྐ༏॓࠯ 22 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + ྩ‫ר‬৥ൎ + +ྩ‫ר‬৥ൎ + +ರ௹ ϱЧ ‫҃ؿ‬ඪૼ + ശࠩ໓֖۬ൔ +2022.04 v2.0 ۷ྍі 1 ᇏؓ TWAI® ֥૭ඍ + ۷ྍі 4 +2021.02 V1.9 ۷ྍ TWAI™ ູ TWAI® + ೷Ԣᅣࢫ 7ğຓຶഡ࠹ჰ৘๭ᇏ֥ VDD33 ٢‫׈׈‬ਫ਼๭‫׈໊گބ‬ਫ਼๭ +2020.11 V1.8 ۷ྍ๭ 2ğ߭ੀ‫ݯ‬໑؇౷ཌ༯֥ٚඪૼ + ᄝі 1 ᇏᄹࡆ TWAITMĠ +2019.12 V1.7 ۷ྍі 2Ġ + ۷ྍ RC ‫׈‬ਫ਼ᇏ֥‫׈‬ಸᆴູ 1 µFĠ +2019.09 V1.6 เࡆ๭ 6 ‫ބ‬๭ 7b +2019.01 V1.5 +2018.10 V1.4 • ࡼ VDD3P3_RTC ֥‫׈‬࿢ٓຶ‫ູڿ‬ა‫׈׈܂‬࿢ٓຶ၂ᇁb + • ᄝі 2.2 ༯ٚᄹࡆܱႿ VDD_SDIO ܵ࢖֥ඪૼb +2018.06 V1.3 • ᄝ๭ 2 ߭ੀ‫ݯ‬໑؇౷ཌ༯ٚᄹࡆ၂่ඪૼb + • ᄹࡆ໓ّ֖ঌ৽ࢤb + 2018.03 V1.2 + • ࡼ‫׈׈܂‬࿢ٓຶՖ 2.7 V ~ 3.6 V ‫ ູڿ‬3.0 V ~ 3.6 VĠ + 2017.09 V1.1 • ᄝі 1 ESP32-PICO-D4 Ӂ௖ܿ۬ᇏᄹࡆড࿩ಪᆣྐ༏‫ބ‬Ӗുૹ‫ۋ‬؇֩ࠩ +ুᶈྐ༏॓࠯ + (MSL) 3Ġ + • ᄝі 7 Wi-Fi ഝ௔หྟ༯ٚᄹࡆؓႿo‫۽‬ቔ௔ੱٓຶp‫ބ‬oൻԛ‫ੱۿ‬p֥ඪૼĠ + • ۷ྍᅣࢫ 7 ᇏຓຶჰ৘๭ѩᄹࡆ၂่ܱႿ RC ࿼Ӿ‫׈‬ਫ਼֥ඪૼb + ۷ྍі 2 ֥ඪૼ‫ބ‬ᅣࢫ 4 ֥ඪૼĠ + ۷ྍᅣࢫ 7 ຓຶഡ࠹ჰ৘๭đᄹࡆ ESP32-PICO-D4 ຓ‫ ܫ‬PSRAM ֥৵ࢤٚൔĠ + ࡼі 9 ᇏ֥oഝ௔‫ੱۿ‬॥ᇅٓຶpՖ⚶12 ~ +12 ‫⚶ູڿ‬12 ~ +9 dBmb + ೷Ԣі 1oESP32-PICO-D4 Ӂ௖ܿ۬pᇏೈࡱཌྷܱଽಸĠ + ᄝі 4oधؓቋն‫קح‬ᆴpᇏᄹࡆoIO ൻԛሹ‫׈‬ੀpĠ + ᄝі 6oDC ᆰੀ‫׈‬గหྟpᇏᄹࡆ۲۱‫׈‬ჷთ֥ঘ‫׈‬ੀ௜नᆴb + • ࡼі 2 ܵ࢖૭ඍᇏ VDD3P3_RTC ‫׈‬࿢ٓຶႮ 1.8-3.6V ‫ ູڿ‬2.3-3.6VĠ + • ࡼі 2 ܵ࢖૭ඍᇏ VDD_SDIO ‫׈‬࿢ٓຶႮo1.8V ࠇ VDD3P3_RTC ‫׈‬ჷൻ + + ԛp‫ູڿ‬oVDD3P3_RTC ‫׈‬ჷൻԛpĠ + • ೷ԢႵܱ໑؇Ԯ‫ۋ‬ఖaLNA భᇂ٢նఖ֥ଽಸĠ + • ۷ྍᅣࢫ 3 ‫ିۿ‬૭ඍĠ + • ۷ྍᅣࢫ 4 ຓഡࢤ१‫ބ‬Ԯ‫ۋ‬ఖᇏ֥ඪૼĠ + • ೷Ԣᅣࢫ 7 ຓຶഡ࠹ჰ৘๭ᇏܱႿܵ࢖ 49 ֥ඪૼđྍᄹਆ่ඪૼĠ + ‫׈‬గหྟཌྷܱ֥۷ྍğ + • ۷ྍі 4 धؓቋն‫קح‬ᆴĠ + • ᄹࡆі 5 ࡹၰ‫۽‬ቔ่ࡱĠ + • ᄹࡆі 6 DC ᆰੀ‫׈‬గหྟĠ + • ۷ྍі 9 ֮‫ݻۿ‬ড࿩‫ؿ‬ഝఖหྟᇏoᄹၭ॥ᇅ҄Ӊpđoਣ֡‫ؿ‬ഝ‫ੱۿ‬pҕඔb + + ۷ྍᅣࢫ 2.2 ᇏႵܱ VDD_SDIO ֥ܵ࢖૭ඍĠ + ۷ྍᅣࢫ 2.1 ᇏ֥ ESP32-PICO-D4 ܵ࢖҃अ๭Ġ + ۷ྍᅣࢫ 6 ᇏ֥ ESP32-PICO-D4 ଆቆჰ৘๭Ġ + ۷ྍᅣࢫ 7 ᇏ֥ ESP32-PICO-D4 ଆቆຓຶഡ࠹ҕॉ๭b + ۷ྍ‫۽‬ቔ‫׈‬࿢/‫׈׈܂‬࿢ٓຶູ 2.7V ~ 3.6VĠ + + 23 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + ྩ‫ר‬৥ൎ + +ರ௹ ϱЧ ‫҃ؿ‬ඪૼ + ۷ྍᅣࢫ 7đᄹࡆ၂่ඪૼb +2017.08 V1.0 ൮Ց‫҃ؿ‬b + +ুᶈྐ༏॓࠯ 24 ESP32-PICO-D4 ࠯ඌܿ۬඀ v2.0 + ّঌ໓֖ၩ࡮ + www.espressif.com ૧ᄳലૼ‫ބ‬ϱಃ‫ۡ܄‬ + + Ч໓֖ᇏ֥ྐ༏đЇও‫܂‬ҕॉ֥ URL ֹᆶđೂႵэ۷đඖ҂ਸ਼ྛ๙ᆩb + Ч໓֖ॖିႄႨਔֻ೘֥ٚྐ༏đ෮ႵႄႨ֥ྐ༏नູoοགྷሑpิ‫܂‬đুᶈ҂ؓྐ + ༏֥ሙಒྟaᆇൌྟቓ಩‫ޅ‬Ќᆣb + ুᶈ҂ؓЧ໓֖֥ଽಸቓ಩‫ޅ‬ЌᆣđЇওଽಸ֥ൡཧྟa൞‫ڎ‬ൡႨႿห‫ק‬Ⴈ๯đ္҂ + ิ‫܂‬಩‫ޅ‬ః෰ুᶈิσaܿ۬඀ࠇဢ௖ᄝ෰ԩิ֥֞಩‫ޅ‬Ќᆣb + ুᶈ҂ؓЧ໓֖൞‫ֻٕ౓ڎ‬೘ٚಃ০ቓ಩‫ޅ‬Ќᆣđ္҂ؓ൐ႨЧ໓֖ଽྐ༏֝ᇁ֥಩ + ‫ٕ౓ޅ‬ᆩ്Ӂಃ֥ྛູ‫ڵ‬ᄳbЧ໓֖ᄝՎໃၛ࣌ᆸّ࿽ࠇః෰ٚൔ൱Ⴭ಩‫ޅ‬ᆩ്Ӂಃ + ྸॖđ҂ܵ൞ૼൕྸॖߎ൞πൕྸॖb + Wi-Fi ৳ૐӮჴѓᆽ݂ Wi-Fi ৳ૐ෮Ⴕbড࿩ѓᆽ൞ Bluetooth SIG ֥ᇿҨഅѓb + ໓֖ᇏิ֥֞෮Ⴕഅѓ଀ӫaഅѓ‫ބ‬ᇿҨഅѓनඋః۲ሱ෮Ⴕᆀ֥ҍӁđหՎലૼb + ϱಃ݂ © 2022 ুᶈྐ༏॓࠯čഈ‫ݚ‬Ď‫ٺܢ‬Ⴕཋ‫܄‬ඳbЌ਽෮Ⴕಃ০b + diff --git a/3.Docs/esp32_technical_reference_manual_cn.pdf b/3.Docs/esp32_technical_reference_manual_cn.pdf new file mode 100644 index 0000000..f0c90b7 --- /dev/null +++ b/3.Docs/esp32_technical_reference_manual_cn.pdf @@ -0,0 +1,27295 @@ +ESP32 + +࠯ඌҕॉ൭Ҩ + + ϱЧ 4.7 + ুᶈྐ༏॓࠯ + ϱಃ © 2022 + + www.espressif.com + ܱႿЧ൭Ҩ + +uESP32 ࠯ඌҕॉ൭Ҩv֥ଢѓ‫؀‬ᆀಕุ൞൐Ⴈ ESP32 ྉோ֥ႋႨष‫۽ؿ‬ӱഽbЧ൭Ҩิ‫܂‬ਔܱႿ ESP32 ֥ + ऎุྐ༏đЇও۲۱‫ିۿ‬ଆॶ֥ଽ҆ࡏ‫ܒ‬a‫ିۿ‬૭ඍ‫࠷ބ‬թఖ஥ᇂ֩b + ྉோ֥ܵ࢖૭ඍa‫׈‬గหྟ‫ٿބ‬ልྐ༏֩ॖၛՖuESP32 ࠯ඌܿ۬඀vࠆ౼b + + ໓֖ϱЧ + + ౨ᇀুᶈܲຩ https://www.espressif.com/zh-hans/support/download/documents ༯ᄛቋྍϱЧ໓֖b + + ྩ‫ר‬৥ൎ + + ౨ᇀ໓֖ቋު်Ұुྩ‫ר‬৥ൎb + + ໓֖э۷๙ᆩ + + Ⴈ޼ॖၛ๙‫ুݖ‬ᶈܲຩ‫ר‬ᄇ်૫ www.espressif.com/zh-hans/subscribe ‫ר‬ᄇ࠯ඌ໓֖э۷֥‫׈‬ሰႯࡱ๙ + ᆩb + + ᆣ඀༯ᄛ + + Ⴈ޼ॖၛ๙‫ুݖ‬ᶈܲຩᆣ඀༯ᄛ်૫ www.espressif.com/zh-hans/certificates ༯ᄛӁ௖ᆣ඀b + ଢ੣ + +ଢ੣ + +1 ༢๤‫ބ‬թԥఖ 24 + 24 +1.1 ‫ۀ‬ඍ 24 +1.2 ᇶေหྟ 26 +1.3 ‫ିۿ‬૭ඍ 26 + 26 + 1.3.1 ֹᆶ႘ഝ 27 + 1.3.2 ோഈթԥఖ 27 + 27 + 1.3.2.1 Internal ROM 0 28 + 1.3.2.2 Internal ROM 1 28 + 1.3.2.3 Internal SRAM 0 28 + 1.3.2.4 Internal SRAM 1 29 + 1.3.2.5 Internal SRAM 2 29 + 1.3.2.6 DMA 29 + 1.3.2.7 RTC FAST Memory 29 + 1.3.2.8 RTC SLOW Memory 30 + 1.3.3 ோຓթԥఖ 32 + 1.3.4 Cache 32 + 1.3.5 ຓഡ 32 + 1.3.5.1 ҂ؓӫ PID Controller ຓഡ + 1.3.5.2 ҂৵࿃ຓഡֹᆶٓຶ 33 + 1.3.5.3 թԥఖ෎؇ 33 + 33 +2 ᇏ؎इᆔ (INTERRUPT) 33 + 33 +2.1 ‫ۀ‬ඍ 36 +2.2 ᇶေหྟ 36 +2.3 ‫ିۿ‬૭ඍ 37 + 37 + 2.3.1 ຓ҆ᇏ؎ჷ + 2.3.2 CPU ᇏ؎ 38 + 2.3.3 ‫ٳ‬஥ຓ҆ᇏ؎ჷᇀ CPU ຓ҆ᇏ؎ 38 + 2.3.4 ௠з CPU ֥ NMI ো྘ᇏ؎ 38 + 2.3.5 Ұ࿘ຓ҆ᇏ؎ჷ֒భ֥ᇏ؎ሑ෿ 38 + 39 +3 ‫ބ໊گ‬ൈᇒ 39 + 40 +3.1 System ‫໊گ‬ 40 + 3.1.1 ‫ۀ‬ඍ 41 + 3.1.2 ‫໊گ‬ჷ 41 + 41 +3.2 ༢๤ൈᇒ + 3.2.1 ‫ۀ‬ඍ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + 3.2.2 ൈᇒჷ + 3.2.3 CPU ൈᇒ + 3.2.4 ຓഡൈᇒ + 3.2.4.1 APB_CLK ჷ + 3.2.4.2 REF_TICK ჷ + +ুᶈྐ༏॓࠯ 3 + ّঌ໓֖ၩ࡮ + ଢ੣ + + 3.2.4.3 LEDC_SCLK ჷ 42 + + 3.2.4.4 APLL_SCLK ჷ 42 + + 3.2.4.5 PLL_D2_CLK ჷ 42 + + 3.2.4.6 ൈᇒჷᇿၩ൙ཛ 42 + + 3.2.5 Wi-Fi BT ൈᇒ 42 + + 3.2.6 RTC ൈᇒ 42 + + 3.2.7 ၻ௔ PLL 43 + +4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) 44 + +4.1 ‫ۀ‬ඍ 44 + +4.2 ๙‫ ݖ‬GPIO ࢌߐइᆔ֥ຓഡൻೆ 45 + + 4.2.1 ‫ۀ‬ඍ 45 + + 4.2.2 ‫ିۿ‬૭ඍ 45 + + 4.2.3 ࡥֆ GPIO ൻೆ 46 + +4.3 ๙‫ ݖ‬GPIO ࢌߐइᆔ֥ຓഡൻԛ 46 + + 4.3.1 ‫ۀ‬ඍ 46 + + 4.3.2 ‫ିۿ‬૭ඍ 46 + + 4.3.3 ࡥֆ GPIO ൻԛ 47 + +4.4 IO_MUX ֥ᆰࢤ I/O ‫ିۿ‬ 48 + + 4.4.1 ‫ۀ‬ඍ 48 + + 4.4.2 ‫ିۿ‬૭ඍ 48 + +4.5 RTC IO_MUX ֥֮‫ބݻۿ‬ଆ୅ I/O ‫ିۿ‬ 48 + + 4.5.1 ‫ۀ‬ඍ 48 + + 4.5.2 ‫ିۿ‬૭ඍ 48 + +4.6 Light-sleep ଆൔܵ࢖‫ିۿ‬ 48 + +4.7 Pad Hold หྟ 49 + +4.8 I/O Pad ‫׈܂‬ 49 + + 4.8.1 VDD_SDIO ‫׈‬ჷთ 50 + +4.9 ຓഡྐ‫ݼ‬ਙі 50 + +4.10 IO_MUX Pad ਙі 55 + +4.11 RTC_MUX ܵ࢖ౢֆ 56 + +4.12 ࠷թఖਙі 57 + + 4.12.1 GPIO ࢌߐइᆔ࠷թఖਙі 57 + + 4.12.2 IO MUX ࠷թఖਙі 58 + + 4.12.3 RTC IO MUX ࠷թఖਙі 59 + +4.13 ࠷թఖ 61 + + 4.13.1 GPIO ࢌߐइᆔ࠷թఖ 61 + + 4.13.2 IO MUX ࠷թఖ 69 + + 4.13.3 RTC IO MUX ࠷թఖ 70 + +5 DPort ࠷թఖ 82 + +5.1 ‫ۀ‬ඍ 82 + +5.2 ᇶေหྟ 82 + +5.3 ‫ିۿ‬૭ඍ 82 + + 5.3.1 ༢๤‫ބ‬թԥఖ࠷թఖ 82 + + 5.3.2 ‫ބ໊گ‬ൈᇒ࠷թఖ 82 + +ুᶈྐ༏॓࠯ 4 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + ଢ੣ + + 5.3.3 ᇏ؎इᆔ࠷թఖ 82 + 5.3.4 DMA ࠷թఖ 82 + 5.3.5 MPU/MMU ࠷թఖ 82 + 5.3.6 APP_CPU ॥ᇅఖ࠷թఖ 82 + 5.3.7 ຓഡൈᇒ૊॥‫໊گބ‬ 83 +5.4 ࠷թఖਙі 84 +5.5 ࠷թఖ 91 + +6 DMA ॥ᇅఖ (DMA) 107 + 107 +6.1 ‫ۀ‬ඍ 107 +6.2 หྟ 107 +6.3 ‫ିۿ‬૭ඍ 107 + 108 + 6.3.1 DMA ႄౣ֥ࡏ‫ܒ‬ 108 + 6.3.2 ৽і 110 +6.4 UART DMA (UDMA) ॥ᇅఖ 111 +6.5 SPI DMA ॥ᇅఖ +6.6 I2S DMA ॥ᇅఖ 112 + 112 +7 SPI ॥ᇅఖ (SPI) 112 + 113 +7.1 ‫ۀ‬ඍ 113 +7.2 SPI หᆘ 114 +7.3 GP-SPI ࢤ१ 114 + 115 + 7.3.1 GP-SPI ඹཌಆච‫۽‬ଆൔ 115 + 7.3.2 GP-SPI ඹཌ϶ච‫۽‬ଆൔ 115 + 7.3.3 GP-SPI ೘ཌ϶ච‫۽‬ଆൔ 116 + 7.3.4 GP-SPI ඔऌߏթ 117 +7.4 GP-SPI ൈᇒ॥ᇅ 117 + 7.4.1 GP-SPI ൈᇒࠞྟ‫ބ‬ൈᇒཌྷ໊ 118 + 7.4.2 GP-SPI ൈ྽ 118 +7.5 ѩྛ QSPI ࢤ१ 118 + 7.5.1 ѩྛ QSPI ࢤ१๙ྐ۬ൔ 119 +7.6 GP-SPI ᇏ؎႗ࡱ 121 + 7.6.1 SPI ᇏ؎ + 7.6.2 DMA ᇏ؎ 142 +7.7 ࠷թఖਙі 142 +7.8 ࠷թఖ 142 + 142 +8 SDIO Ֆࠏ॥ᇅఖ 142 + 142 +8.1 ‫ۀ‬ඍ 143 +8.2 ᇶေหྟ 143 +8.3 ‫ିۿ‬૭ඍ 144 + + 8.3.1 SDIO Slave ‫ॶିۿ‬๭ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + 8.3.2 SDIO ሹཌഈ֥ඔऌ‫ؿ‬ෂ‫ࢤބ‬൬ + 8.3.3 ࠷թఖ٠໙ + 8.3.4 DMA + 8.3.5 Ї֥‫ؿ‬ෂ‫ࢤބ‬൬ੀӱ + +ুᶈྐ༏॓࠯ 5 + ّঌ໓֖ၩ࡮ + ଢ੣ + + 8.3.5.1 Slave ཟ Host ‫ؿ‬ෂЇ 144 + 8.3.5.2 Slave Ֆ Host ࢤ൬Ї 146 + 8.3.6 SDIO ሹཌൈ྽ 147 + 8.3.7 ᇏ؎ 148 + 8.3.7.1 Host ҧᇏ؎ 148 + 8.3.7.2 Slave ҧᇏ؎ 148 +8.4 ࠷թఖਙі 149 +8.5 SLC ࠷թఖ 150 +8.6 SLC Host ࠷թఖ 159 +8.7 HINF ࠷թఖ 171 + +9 SD/MMC ᇶࠏ॥ᇅఖ 172 + 172 +9.1 ‫ۀ‬ඍ 172 +9.2 ᇶေหྟ 172 +9.3 SD/MMC ຓ҆ࢤ१ྐ‫ݼ‬ 173 +9.4 ‫ିۿ‬૭ඍ 173 + 174 + 9.4.1 SD/MMC ࡏ‫ܒ‬ 174 + 9.4.1.1 BIU ଆॶ 174 + 9.4.1.2 CIU ଆॶ 175 + 175 + 9.4.2 ଁ਷๙ਫ਼ 176 + 9.4.3 ඔऌ๙ਫ਼ 176 + 177 + 9.4.3.1 ඔऌ‫ؿ‬ෂ 177 + 9.4.3.2 ඔऌࢤ൬ 177 +9.5 CIU Ҡቔ֥ೈࡱཋᇅ 177 +9.6 ൬‫ؿ‬ඔऌ RAM 178 + 9.6.1 ‫ؿ‬ෂ RAM ଆॶ 180 + 9.6.2 ࢤ൬ RAM ଆॶ 180 +9.7 ৽іߌࢲ‫ܒ‬ 180 +9.8 ৽іࢲ‫ܒ‬ 181 +9.9 Ԛ൓߄ 181 + 9.9.1 DMAC Ԛ൓߄ 182 + 9.9.2 DMAC ඔऌ‫ؿ‬ෂԚ൓߄ 182 + 9.9.3 DMAC ඔऌࢤ൬Ԛ൓߄ 183 +9.10 ൈᇒཌྷ໊࿊ᄴ +9.11 ᇏ؎ 203 +9.12 ࠷թఖਙі 203 +9.13 ࠷թఖ 205 + 205 +10 ၛ෾ຩ (MAC) 205 + 206 +10.1 ‫ۀ‬ඍ 206 +10.2 EMAC_CORE 206 + + 10.2.1 ԮൻҠቔ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + 10.2.1.1 ‫ؿ‬ෂੀਈ॥ᇅ + 10.2.1.2 Ԋ๬௹ࡗ֥ᇗྍ‫ؿ‬ෂ + + 10.2.2 ࢤ൬Ҡቔ + 10.2.2.1 ࢤ൬ླྀၰ + +ুᶈྐ༏॓࠯ 6 + ّঌ໓֖ၩ࡮ + ଢ੣ + + 10.2.2.2 ࢤ൬ᆠ॥ᇅఖ 207 + 10.2.2.3 ࢤ൬ੀਈ॥ᇅ 207 + 10.2.2.4 ࢤ൬‫؟‬ᆠ֥Ҡቔԩ৘ 207 + 10.2.2.5 հ༂ԩ৘ 207 + 10.2.2.6 ࢤ൬ሑ෿ሳ 207 +10.3 MAC ᇏ؎॥ᇅఖ 208 +10.4 MAC ֹᆶ֥‫ݖ‬ੲ 208 + 10.4.1 ֆѬଢѓֹᆶ‫ݖ‬ੲ 208 + 10.4.2 ‫؟‬Ѭଢѓֹᆶ‫ݖ‬ੲ 208 + 10.4.3 ܼѬֹᆶ‫ݖ‬ੲ 208 + 10.4.4 ֆѬჷֹᆶ‫ݖ‬ੲ 208 + 10.4.5 ّཟ‫ݖ‬ੲҠቔ 208 + 10.4.6 ‫ؿ֥ݺ‬ෂᆠაࢤ൬ᆠ 210 +10.5 EMAC_MTLčMAC ԮൻҪĎ 210 +10.6 PHY ࢤ१ 210 + 10.6.1 MIIčࢺᇉ‫׿‬৫ࢤ१Ď 210 + 10.6.1.1 MII ა PHY ࡗ֥ࢤ१ྐ‫ݼ‬ 211 + 10.6.1.2 MII ൈᇒ 212 + 10.6.2 RMIIčࣚࡥࢺᇉ‫׿‬৫ࢤ१Ď 212 + 10.6.2.1 RMII ࢤ१ྐ‫ݼ‬૭ඍ 213 + 10.6.2.2 RMII ൈᇒ 213 + 10.6.3 Station Management Agent (SMA) ࢤ१ 214 + 10.6.4 RMII ࢤ१ൈ྽ေ౰ 214 +10.7 ၛ෾ຩ DMA หྟ 215 +10.8 ৽і૭ඍ‫ژ‬ 215 + 10.8.1 ‫ؿ‬ෂ૭ඍ‫ژ‬ 215 + 10.8.2 ࢤ൬૭ඍ‫ژ‬ 219 +10.9 ࠷թఖਙі 224 +10.10 ࠷թఖ 225 + +11 I2C ॥ᇅఖ (I2C) 260 + 260 +11.1 ‫ۀ‬ඍ 260 +11.2 ᇶေหྟ 260 +11.3 I2C ‫ିۿ‬૭ඍ 260 + 261 + 11.3.1 I2C ࡥࢺ 262 + 11.3.2 I2C ࡏ‫ܒ‬ 262 + 11.3.3 I2C ሹཌൈ྽ 263 + 11.3.4 I2C cmd ࢲ‫ܒ‬ 267 + 11.3.5 I2C ᇶࠏཿೆՖࠏ 269 + 11.3.6 I2C ᇶࠏ‫؀‬౼Ֆࠏ 269 + 11.3.7 ᇏ؎ 271 +11.4 ࠷թఖਙі +11.5 ࠷թఖ 281 + 281 +12 I2S ॥ᇅఖ (I2S) + ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) +12.1 ‫ۀ‬ඍ + +ুᶈྐ༏॓࠯ 7 + ّঌ໓֖ၩ࡮ + ଢ੣ + +12.2 ᇶေหྟ 282 +12.3 I2S ଆॶൈᇒ 283 +12.4 I2S ଆൔ 284 + 284 + 12.4.1 ᆦӻ֥ၻ௔ѓሙ 284 + 12.4.1.1 Philips ѓሙ 284 + 12.4.1.2 MSB ؓఊѓሙ 285 + 12.4.1.3 PCM ѓሙ 285 + 285 + 12.4.2 ଆॶ‫໊گ‬ 285 + 12.4.3 FIFO Ҡቔ 287 + 12.4.4 ‫ؿ‬ෂඔऌ 288 + 12.4.5 ࢤ൬ඔऌ 289 + 12.4.6 I2S ᇶࠏ/Ֆࠏଆൔ 290 + 12.4.7 I2S PDM ଆൔ 291 +12.5 Camera-LCD ॥ᇅఖ 291 + 12.5.1 LCD ᇶࠏ‫ؿ‬ෂଆൔ 292 + 12.5.2 Camera Ֆࠏࢤ൬ଆൔ 293 + 12.5.3 ADC/DAC ଆൔ 293 +12.6 I2S ᇏ؎ 294 + 12.6.1 FIFO ᇏ؎ 294 + 12.6.2 DMA ᇏ؎ 296 +12.7 ࠷թఖਙі +12.8 ࠷թఖ 313 + 313 +13 UART ॥ᇅఖ (UART) 313 + 313 +13.1 ‫ۀ‬ඍ 313 +13.2 ᇶေหྟ 314 +13.3 ‫ିۿ‬૭ඍ 315 + 315 + 13.3.1 UART ࡥࢺ 316 + 13.3.2 UART ࡏ‫ܒ‬ 316 + 13.3.3 UART RAM 317 + 13.3.4 ѯหੱ࡟ҩ 317 + 13.3.5 UART ඔऌᆠ 318 + 13.3.6 ੀ॥ 318 + 318 + 13.3.6.1 ႗ࡱੀ॥ 319 + 13.3.6.2 ೈࡱੀ॥ 319 + 13.3.7 UDMA 320 + 13.3.8 UART ᇏ؎ 322 + 13.3.9 UHCI ᇏ؎ +13.4 ࠷թఖਙі 349 + 13.4.1 UART ࠷թఖ 349 + 13.4.2 UHCI ࠷թఖ 349 +13.5 ࠷թఖ + ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) +14 LED PWM ॥ᇅఖ (LEDC) + +14.1 ‫ۀ‬ඍ +14.2 ‫ିۿ‬૭ඍ + +ুᶈྐ༏॓࠯ 8 + ّঌ໓֖ၩ࡮ + ଢ੣ 349 + 350 + 14.2.1 ࡏ‫ܒ‬ 351 + 14.2.2 ‫ٳ‬௔ఖ 352 + 14.2.3 ๙֡ 352 + 14.2.4 ᇏ؎ 355 +14.3 ࠷թఖਙі +14.4 ࠷թఖ 364 + 364 +15 ‫ޣ‬ຓဪ॥ (RMT) 364 + 364 +15.1 ‫ۀ‬ඍ 365 +15.2 ‫ିۿ‬૭ඍ 365 + 365 + 15.2.1 RMT ࡏ‫ܒ‬ 366 + 15.2.2 RMT RAM 366 + 15.2.3 ൈᇒ 366 + 15.2.4 ‫ؿ‬ഝఖ 367 + 15.2.5 ࢤ൬ఖ + 15.2.6 ᇏ؎ 372 +15.3 ࠷թఖਙі 372 +15.4 ࠷թఖ 372 + 374 +16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) 374 + 374 +16.1 ‫ۀ‬ඍ 374 +16.2 ᇶေหྟ 375 +16.3 ଆॶ 377 + 377 + 16.3.1 ଆॶ‫ۀ‬ඍ 377 + 16.3.1.1 ყ‫ٳ‬௔ఖଆॶ 377 + 16.3.1.2 ‫ק‬ൈఖଆॶ 378 + 16.3.1.3 Ҡቔఖଆॶ 382 + 16.3.1.4 ‫ܣ‬ᅰ࡟ҩଆॶ 382 + 16.3.1.5 ѽࠆଆॶ 382 + 383 + 16.3.2 PWM ‫ק‬ൈఖଆॶ 393 + 16.3.2.1 PWM ‫ק‬ൈఖଆॶ֥஥ᇂ 397 + 16.3.2.2 PWM ‫ק‬ൈఖ‫۽‬ቔଆൔ‫קބ‬ൈ൙ࡱളӮ 400 + 16.3.2.3 PWM ‫ק‬ൈఖ႕ሰ࠷թఖ 401 + 16.3.2.4 PWM ‫ק‬ൈఖ๝҄‫ބ‬෭ཌྷ 401 + 401 + 16.3.3 PWM Ҡቔఖଆॶ 402 + 16.3.3.1 PWM ളӮఖଆॶ 402 + 16.3.3.2 ඵ౵ളӮఖଆॶ 404 + 16.3.3.3 PWM ᄛѯଆॶ + 16.3.3.4 ‫ܣ‬ᅰԩ৘ఖଆॶ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + + 16.3.4 ѽࠆଆॶ + 16.3.4.1 ࢺക + 16.3.4.2 ѽࠆ‫ק‬ൈఖ + 16.3.4.3 ѽࠆ๙֡ + +16.4 ࠷թఖਙі +16.5 ࠷թఖ + +ুᶈྐ༏॓࠯ 9 + ّঌ໓֖ၩ࡮ + ଢ੣ + +17 ઝԊ࠹ඔఖ (PCNT) 448 + 448 +17.1 ‫ۀ‬ඍ 448 +17.2 ‫ିۿ‬૭ඍ 448 + 449 + 17.2.1 ࡏ‫ܒ‬๭ 449 + 17.2.2 ࠹ඔఖ๙֡ൻೆྐ‫ݼ‬ 449 + 17.2.3 ܴҳׄ 450 + 17.2.4 ई২ 450 + 17.2.5 ၮԛᇏ؎ 452 +17.3 ࠷թఖਙі +17.4 ࠷թఖ 457 + 457 +18 ‫ק‬ൈఖቆ (TIMG) 457 + 457 +18.1 ‫ۀ‬ඍ 457 +18.2 ‫ିۿ‬૭ඍ 458 + 458 + 18.2.1 16-bit ყ‫ٳ‬௔ఖ 458 + 18.2.2 64-bit ൈࠎ࠹ඔఖ 458 + 18.2.3 БࣞӁള 460 + 18.2.4 MWDT + 18.2.5 ᇏ؎ 467 +18.3 ࠷թఖਙі 467 +18.4 ࠷թఖ 467 + 467 +19 ु૊‫קܐ‬ൈఖ (WDT) 467 + 467 +19.1 ‫ۀ‬ඍ 468 +19.2 ᇶေหྟ 468 +19.3 ‫ିۿ‬૭ඍ 468 + + 19.3.1 ൈᇒ 469 + 19.3.2 ᄎྛ‫ݖ‬ӱ 469 + 19.3.3 ཿЌ޹ 469 + 19.3.4 Flash ఓ‫׮‬Ќ޹ 469 + 19.3.5 ࠷թఖ 469 + 470 +20 eFuse ॥ᇅఖ (eFuse) 470 + 471 +20.1 ‫ۀ‬ඍ 472 +20.2 ᇶေหྟ 472 +20.3 ‫ିۿ‬૭ඍ 475 + 476 + 20.3.1 ࢲ‫ܒ‬ 476 + 20.3.1.1 ༢๤ҕඔ efuse_wr_disable 477 + 20.3.1.2 ༢๤ҕඔ efuse_rd_disable + 20.3.1.3 ༢๤ҕඔ coding_scheme ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + 20.3.1.4 ༢๤ҕඔ BLK3_part_reserve + + 20.3.2 എཿ༢๤ҕඔ + 20.3.3 ೈࡱ‫؀‬౼༢๤ҕඔ + 20.3.4 ႗ࡱଆॶ൐Ⴈ༢๤ҕඔ + 20.3.5 ᇏ؎ +20.4 ࠷թఖਙі + +ুᶈྐ༏॓࠯ 10 + ّঌ໓֖ၩ࡮ + ଢ੣ + +20.5 ࠷թఖ 479 + +21 චཌచӚࢤ१ (TWAI) 490 + 490 +21.1 ‫ۀ‬ඍ 490 +21.2 ᇶေหྟ 490 +21.3 ‫ླྀྟିۿ‬ၰ 490 + 491 + 21.3.1 TWAI ྟି 492 + 21.3.2 TWAI Б໓ 494 + 495 + 21.3.2.1 ඔऌᆠ‫ބ‬ჹӱᆠ 496 + 21.3.2.2 հ༂ᆠ‫ݖބ‬ᄛᆠ 496 + 21.3.2.3 ᆠࡗए 496 + 21.3.3 TWAI հ༂ 496 + 21.3.3.1 հ༂ো྘ 497 + 21.3.3.2 հ༂ሑ෿ 497 + 21.3.3.3 հ༂࠹ඔ 498 + 21.3.4 TWAI ໊ൈ྽ 499 + 21.3.4.1 ଀ၬ໊ 499 + 21.3.4.2 ႗๝҄აᄜ๝҄ 500 +21.4 ࢲ‫ۀܒ‬ඍ 500 + 21.4.1 ࠷թఖଆॶ 500 + 21.4.2 ໊ੀԩ৘ఖ 500 + 21.4.3 հ༂ܵ৘આࠠ 500 + 21.4.4 ໊ൈ྽આࠠ 500 + 21.4.5 ࢤ൬ੲѯఖ 500 + 21.4.6 ࢤ൬ FIFO 501 +21.5 ‫ିۿ‬૭ඍ 501 + 21.5.1 ଆൔ 501 + 21.5.1.1 ‫໊گ‬ଆൔ 502 + 21.5.1.2 Ҡቔଆൔ 502 + 21.5.2 ໊ൈ྽ 502 + 21.5.3 ᇏ؎ܵ৘ 502 + 21.5.3.1 ࢤ൬ᇏ؎ (RXI) 503 + 21.5.3.2 ‫ؿ‬ෂᇏ؎ (TXI) 503 + 21.5.3.3 հ༂Бࣞᇏ؎ (EWI) 503 + 21.5.3.4 ඔऌၮԛᇏ؎ (DOI) 503 + 21.5.3.5 Ф‫׮‬հ༂ᇏ؎ (TXI) 503 + 21.5.3.6 ᇘҊ‫ש‬ാᇏ؎ (ALI) 503 + 21.5.3.7 ሹཌհ༂ᇏ؎ (BEI) 504 + 21.5.4 ‫ؿ‬ෂߏԊఖაࢤ൬ߏԊఖ 504 + 21.5.4.1 ߏԊఖ‫ۀ‬ඍ 505 + 21.5.4.2 ᆠྐ༏ 505 + 21.5.4.3 ᆠѓ്‫ژ‬ 506 + 21.5.4.4 ᆠඔऌ 506 + 21.5.5 ࢤ൬ FIFO ‫ބ‬ඔऌၮԛ + 21.5.6 ࢤ൬ੲѯఖ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + 21.5.6.1 ֆੲѯଆൔ + +ুᶈྐ༏॓࠯ 11 + ّঌ໓֖ၩ࡮ + ଢ੣ 507 + 507 + 21.5.6.2 චੲѯଆൔ 509 + 21.5.7 հ༂ܵ৘ 509 + 509 + 21.5.7.1 հ༂Бࣞཋᇅ 509 + 21.5.7.2 Ф‫׮‬հ༂ 510 + 21.5.7.3 ৖ཌሑ෿ა৖ཌ߫‫گ‬ 511 + 21.5.8 հ༂ѽሚ 512 + 21.5.9 ᇘҊ‫ש‬ാѽሚ +21.6 ࠷թఖਙі 524 +21.7 ࠷թఖ 524 + 524 +22 AES ࡆ෎ఖ (AES) 524 + 524 +22.1 ‫ۀ‬ඍ 524 +22.2 ᇶေหྟ 524 +22.3 ‫ିۿ‬૭ඍ 527 + 527 + 22.3.1 ᄎෘଆൔ 527 + 22.3.2 ૡᄂaૼ໓aૡ໓ 528 + 22.3.3 ሳࢫ྽ + 22.3.4 ࡆૡაࢳૡᄎෘ 530 + 22.3.5 ᄎྛིੱ 530 +22.4 ࠷թఖਙі 530 +22.5 ࠷թఖ 530 + 530 +23 SHA ࡆ෎ఖ (SHA) 530 + 530 +23.1 ‫ۀ‬ඍ 531 +23.2 ᇶေหྟ 531 +23.3 ‫ିۿ‬૭ඍ 533 + + 23.3.1 แԉࢳ༅ྐ༏ 538 + 23.3.2 ྐ༏ᅋေ 538 + 23.3.3 ‫ݗ‬༐ᄎෘ 538 + 23.3.4 ᄎྛིੱ 538 +23.4 ࠷թఖਙі 538 +23.5 ࠷թఖ 538 + 539 +24 RSA ࡆ෎ఖ (RSA) 540 + 541 +24.1 ‫ۀ‬ඍ 542 +24.2 ᇶေหྟ +24.3 ‫ିۿ‬૭ඍ 544 + 544 + 24.3.1 Ԛ൓߄ + 24.3.2 նඔଆૢᄎෘ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + 24.3.3 նඔଆӰᄎෘ + 24.3.4 նඔӰ‫م‬ᄎෘ +24.4 ࠷թఖਙі +24.5 ࠷թఖ + +25 ෛࠏඔ‫ؿ‬ളఖ (RNG) + +25.1 ‫ۀ‬ඍ + +ুᶈྐ༏॓࠯ 12 + ّঌ໓֖ၩ࡮ + ଢ੣ 544 + 544 +25.2 ᇶေหྟ 544 +25.3 ‫ିۿ‬૭ඍ 545 +25.4 щӱᆷଲ 545 +25.5 ࠷թఖਙі +25.6 ࠷թఖ 546 + 546 +26 ோຓթԥఖࡆૡაࢳૡ (FLASH) 546 + 546 +26.1 ‫ۀ‬ඍ 547 +26.2 ᇶေหྟ 547 +26.3 ‫ିۿ‬૭ඍ 548 + 548 + 26.3.1 Key Generator ଆॶ 548 + 26.3.2 Flash Encryption ଆॶ + 26.3.3 Flash Decryption ଆॶ 550 +26.4 ࠷թఖਙі 550 +26.5 ࠷թఖ 550 + 550 +27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) 550 + 550 +27.1 ‫ۀ‬ඍ 550 +27.2 ᇶေหྟ 557 +27.3 ‫ିۿ‬૭ඍ 562 + + 27.3.1 PID ॥ᇅఖ 564 + 27.3.2 MPU/MMU 564 + 564 + 27.3.2.1 ళೆൔթԥఖ 564 + 27.3.2.2 ோຓթԥఖ 564 + 27.3.2.3 ຓഡ 565 + 567 +28 PID ॥ᇅఖ (PID) 568 + 570 +28.1 ‫ۀ‬ඍ +28.2 ᇶေหྟ 574 +28.3 ‫ିۿ‬૭ඍ 574 + 574 + 28.3.1 ᇏ؎്љ 574 + 28.3.2 ྐ༏࠺੣ 574 + 28.3.3 ࣉӱᇶ‫ࣉߐ్׮‬ӱ 575 +28.4 ࠷թఖਙі 575 +28.5 ࠷թఖ 575 + 577 +29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ 577 + +29.1 ‫ۀ‬ඍ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) +29.2 ‫׈‬ಸൔԨଃԮ‫ۋ‬ఖ + + 29.2.1 ࡥࢺ + 29.2.2 ᇶေหྟ + 29.2.3 ॖႨ๙Ⴈൻೆൻԛࢤ१ + 29.2.4 ‫ିۿ‬૭ඍ + 29.2.5 Ԩ‫ؿ‬Ԯ‫ۋ‬ఖ֥ሑ෿ࠏ +29.3 SAR ADC + 29.3.1 ࡥࢺ + +ুᶈྐ༏॓࠯ 13 + ّঌ໓֖ၩ࡮ + ଢ੣ + + 29.3.2 ᇶေหྟ 578 + 29.3.3 ‫ۀିۿ‬ঃ 578 + 29.3.4 RTC SAR ADC ॥ᇅఖ 580 + 29.3.5 DIG SAR ADC ॥ᇅఖ 580 +29.4 ࠉ‫غ‬Ԯ‫ۋ‬ఖ 582 + 29.4.1 ࡥࢺ 582 + 29.4.2 ᇶေหྟ 582 + 29.4.3 ‫ିۿ‬૭ඍ 582 +29.5 ඔሳଆ୅ሇߐఖ 583 + 29.5.1 ࡥࢺ 583 + 29.5.2 ᇶေหྟ 583 + 29.5.3 ࢲ‫ܒ‬ 583 + 29.5.4 Ⴥ༿ѯྙളӮఖ 584 + 29.5.5 ᆦӻ DMA 584 +29.6 ࠷թఖਙі 585 + 29.6.1 Ԯ‫ۋ‬ఖ 585 + 29.6.2 ຓຶሹཌ 586 + 29.6.3 RTC I/O 586 +29.7 ࠷թఖ 587 + 29.7.1 Ԯ‫ۋ‬ఖ 587 + 29.7.2 ۚࠩຓຶሹཌ 596 + 29.7.3 RTC I/O 600 + +30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) 601 + 601 +30.1 ‫ۀ‬ඍ 601 +30.2 ᇶေหྟ 602 +30.3 ‫ିۿ‬૭ඍ 602 +30.4 ᆷ਷ࠢ 602 + 603 + 30.4.1 ALU - ෘඔაઆࠠᄎෘ 603 + 30.4.1.1 ؓ࠷թఖඔᆴ֥ᄎෘ 604 + 30.4.1.2 ؓᆷ਷৫ࠧᆴ֥ᄎෘ 605 + 30.4.1.3 ؓࢨ‫࠹؍‬ඔఖ࠷թఖඔᆴ֥ᄎෘ 605 + 606 + 30.4.2 ST ⚶թԥඔऌᇀଽթ 606 + 30.4.3 LD ⚶Ֆଽթࡆᄛඔऌ 607 + 30.4.4 JUMP ⚶๋ሇᇀधֹؓᆶ 607 + 30.4.5 JUMPR ⚶๋ሇᇀཌྷֹؓᆶčࠎႿ R0 ࠷թఖ஑؎Ď 607 + 30.4.6 JUMPS ⚶๋ሇᇀཌྷֹؓᆶčࠎႿࢨ‫࠹؍‬ඔఖ࠷թఖ஑؎Ď 608 + 30.4.7 HALT ⚶ࢲඏӱ྽ 608 + 30.4.8 WAKE ⚶ߒྜྉோ 608 + 30.4.9 SLEEP ⚶ഡᇂ႗ࡱ࠹ൈఖ֥ߒྜᇛ௹ 609 + 30.4.10 WAIT ⚶֩ր೏‫ۄ‬۱ᇛ௹ 609 + 30.4.11 ADC ⚶ؓ ADC ࣉྛҩਈ 610 + 30.4.12 I2C_RD / I2C_WR ⚶‫ ؀‬/ ཿ I²C 610 + 30.4.13 REG_RD ⚶Ֆຓຶ࠷թఖ‫؀‬౼ + 30.4.14 REG_WR ⚶ཿೆຓຶ࠷թఖ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) +30.5 ULP ླྀԩ৘ఖӱ྽֥ᆳྛ + +ুᶈྐ༏॓࠯ 14 + ّঌ໓֖ၩ࡮ + ଢ੣ + +30.6 RTC_I2C ॥ᇅఖ 612 + + 30.6.1 ஥ᇂ RTC_I2C 612 + + 30.6.2 ൐Ⴈ RTC_I2C 613 + + 30.6.2.1 I2C_RD - ‫؀‬౼ֆ۱ሳࢫ 613 + + 30.6.2.2 I2C_WR - ཿೆֆ۱ሳࢫ 613 + + 30.6.2.3 ࡟ҩհ༂่ࡱ 614 + + 30.6.2.4 ৵ࢤ I²C ྐ‫ݼ‬ 614 + +30.7 ࠷թఖਙі 614 + + 30.7.1 SENS_ULP ֹᆶॢࡗ 614 + + 30.7.2 RTC_I2C ֹᆶॢࡗ 615 + +30.8 ࠷թఖ 615 + + 30.8.1 SENS_ULP ֹᆶॢࡗ 615 + + 30.8.2 RTC_I2C ֹᆶॢࡗ 618 + +31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) 624 + +31.1 ‫ۀ‬ඍ 624 + +31.2 ᇶေหྟ 624 + +31.3 ‫ିۿ‬૭ඍ 624 + + 31.3.1 ࡥࢺ 625 + + 31.3.2 ඔሳଽ‫טނ‬࿢ఖ 625 + + 31.3.3 ֮‫טݻۿ‬࿢ఖ 625 + + 31.3.4 Flash ‫ט‬࿢ఖ 626 + + 31.3.5 ఴ࿢࡟ҩఖ 627 + + 31.3.6 RTC ଆॶ 627 + + 31.3.7 ֮‫ݻۿ‬ൈᇒ 628 + + 31.3.8 ‫׈‬ჷ૊॥֥ൌགྷ 630 + + 31.3.9 ყഡ‫ݻۿ‬ଆൔ 631 + + 31.3.10 ߒྜჷ 633 + + 31.3.11 RTC ࠹ൈఖ 633 + + 31.3.12 RTC Boot 633 + +31.4 ࠷թఖਙі 635 + +31.5 ࠷թఖ 637 + +Ս߸ਙі 661 + +ຓഡཌྷܱՍ߸ 661 + +࠷թఖཌྷܱՍ߸ 661 + +ྩ‫ר‬৥ൎ 662 + +ুᶈྐ༏॓࠯ 15 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + і۬ + +і۬ + +1-1 ֹᆶ႘ഝ 26 + +1-2 ோഈ࠷թఖֹᆶ႘ഝ 27 + +1-3 ऎႵ DMA ‫֥ିۿ‬ଆॶ 29 + +1-4 ோຓթԥఖֹᆶ႘ഝ 29 + +1-5 Cache memory ଆൔ 30 + +1-6 ຓഡֹᆶ႘ഝ 31 + +2-1 PRO_CPUaAPP_CPU ຓ҆ᇏ؎஥ᇂ࠷թఖaຓ҆ᇏ؎ჷᇏ؎ሑ෿࠷թఖaຓ҆ᇏ؎ჷ 34 + +2-2 CPU ᇏ؎ 36 + +3-1 PRO_CPU ‫ ބ‬APP_CPU ‫໊گ‬ჷ 38 + +3-2 CPU_CLK ჷ 40 + +3-3 CPU_CLK ჷ 40 + +3-4 ຓഡൈᇒႨ‫م‬ 41 + +3-5 APB_CLK ჷ 41 + +3-6 REF_TICK ჷ 41 + +3-7 LEDC_SCLK ჷ 42 + +4-1 IO_MUX Light-sleep ܵ࢖‫࠷ିۿ‬թఖ 48 + +4-2 GPIO ࢌߐइᆔຓഡྐ‫ݼ‬ 50 + +4-3 IO_MUX Pad ਙі 55 + +4-4 RTC_MUX ܵ࢖ౢֆ 56 + +7-1 ܵ࢖‫ݼྐିۿ‬აሹཌྐ‫ݼ‬႘ഝܱ༢ 112 + +7-2 Ֆࠏଁ਷૭ඍ 114 + +7-3 ᇶࠏଆൔൈᇒࠞྟ‫ބ‬ཌྷ໊॥ᇅ࠷թఖᆴ 116 + +7-4 Ֆࠏଆൔൈᇒࠞྟ‫ބ‬ཌྷ໊॥ᇅ࠷թఖᆴ 116 + +9-1 SD/MMC ܵ࢖૭ඍ 173 + +9-2 DES0 ৽і૭ඍ 178 + +9-3 DES1 179 + +9-4 DES2 180 + +9-5 DES3 180 + +10-1 ଢѓֹᆶ‫ݖ‬ੲ 209 + +10-2 ჷֹᆶ‫ݖ‬ੲ 209 + +10-3 ࢤ൬ඔऌൈ྽ေ౰ 214 + +10-4 ‫ؿ‬ෂඔऌൈ྽ေ౰ 215 + +10-5 ‫ؿ‬ෂ૭ඍ‫ ژ‬0 (TDES0) 216 + +10-6 ‫ؿ‬ෂ૭ඍ‫ ژ‬1 (TDES1) 218 + +10-7 ‫ؿ‬ෂ૭ඍ‫ ژ‬2 (TDES2) 219 + +10-8 ‫ؿ‬ෂ૭ඍ‫ ژ‬3 (TDES3) 219 + +10-9 ‫ؿ‬ෂ૭ඍ‫ ژ‬6 (TDES6) 219 + +10-10 ‫ؿ‬ෂ૭ඍ‫ ژ‬7 (TDES7) 219 + +10-11 ࢤ൬૭ඍ‫ ژ‬0 (RDES0) 220 + +10-12 ࢤ൬૭ඍ‫ ژ‬1 (RDES1) 221 + +10-13 ࢤ൬૭ඍ‫ ژ‬2 (RDES2) 222 + +10-14 ࢤ൬૭ඍ‫ ژ‬3 (RDES3) 222 + +10-15 ࢤ൬૭ඍ‫ ژ‬4 (RDES4) 222 + +ুᶈྐ༏॓࠯ 16 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + і۬ + +10-16 ࢤ൬૭ඍ‫ ژ‬6 (RDES6) 223 +10-17 ࢤ൬૭ඍ‫ ژ‬7 (RDES7) 224 +11-1 SCL ௔ੱ஥ᇂ 262 +12-1 I2S ྐ‫ݼ‬ሹཌ૭ඍ 282 +12-2 ࠷թఖ஥ᇂ 286 +12-3 ‫ؿ‬ෂ๙֡ଆൔ 286 +12-4 ࢤ൬ඔऌཿೆ FIFO ଆൔ‫ؓބ‬ႋ࠷թఖ஥ᇂ 287 +12-5 4 ᇕଆൔؓႋ࠷թఖ஥ᇂ 288 +12-6 ‫ݖ‬Ґဢੱ஥ᇂ 289 +12-7 ༯Ґဢ஥ᇂ 290 +14-1 ӈႨ஥ᇂ௔ੱࠣࣚ؇ 350 +16-1 Ҡቔఖଆॶ֥஥ᇂҕඔ 376 +16-2 PWM ളӮఖᇏ֥෮Ⴕ‫ק‬ൈ൙ࡱ 384 +16-3 PWM ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđ‫ק‬ൈ൙ࡱ֥Ⴊ༵ࠩ 384 +16-4 PWM ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđ‫ק‬ൈ൙ࡱ֥Ⴊ༵ࠩ 385 +16-5 ॥ᇅඵ౵ൈࡗളӮఖषܱ֥࠷թఖ 394 +16-6 ඵ౵ളӮఖ֥‫྘ׅ‬Ҡቔଆൔ 395 +20-1 ༢๤ҕඔ 469 +20-2 BLOCK1/2/3 щ઒ 471 +20-3 എཿ࠷թఖ 472 +20-4 ൈ྽஥ᇂ 474 +20-5 ೈࡱ‫؀‬౼࠷թఖ 475 +21-1 SFF ‫ ބ‬EFF ᇏ֥ඔऌᆠ‫ބ‬ჹӱᆠ 493 +21-2 հ༂ᆠ 494 +21-3 ‫ݖ‬ᄛᆠ 495 +21-4 ᆠࡗए 495 +21-5 ଀ၬ໊ൈ྽ᇏЇ‫؍֥ݣ‬ 498 +21-6 TWAI_CLOCK_DIVIDER_REG ֥ bit ྐ༏; TWAI ֹᆶ 0x18 501 +21-7 TWAI_BUS_TIMING_1_REG ֥ bit ྐ༏; TWAI ֹᆶ 0x1c 501 +21-8 SFF ა EFF ֥ߏԊఖ҃अ 503 +21-9 TX/RX ᆠྐ༏ (SFF/EFF)ĠTWAI ֹᆶ 0x40 504 +21-10 TX/RX ѓ്‫ ژ‬1 (SFF); TWAI ֹᆶ 0x44 505 +21-11 TX/RX ѓ്‫ ژ‬2 (SFF); TWAI ֹᆶ 0x48 505 +21-12 TX/RX ѓ്‫ ژ‬1 (EFF); TWAI ֹᆶ 0x44 505 +21-13 TX/RX ѓ്‫ ژ‬2 (EFF); TWAI ֹᆶ 0x48 505 +21-14 TX/RX ѓ്‫ ژ‬3 (EFF); TWAI ֹᆶ 0x4c 505 +21-15 TX/RX ѓ്‫ ژ‬4 (EFF); TWAI ֹᆶ 0x50 505 +21-16 TWAI_ERR_CODE_CAP_REG ֥ bit ྐ༏; TWAI ֹᆶ 0x30 509 +21-17 SEG.4 - SEG.0 ໊֥ྐ༏ 510 +21-18 TWAI_ARB LOST CAP_REG ᇏ໊֥ྐ༏; TWAI ֹᆶ 0x2c 511 +22-1 ᄎෘଆൔ 524 +22-2 AES ໓Чሳࢫ྽ 525 +22-3 AES-128 ૡᄂሳࢫ྽ 526 +22-4 AES-192 ૡᄂሳࢫ྽ 526 +22-5 AES-256 ૡᄂሳࢫ྽ 526 +27-1 ோഈթԥఖ֥ MPU ‫ ބ‬MMU ࢲ‫ܒ‬ 551 + +ুᶈྐ༏॓࠯ 17 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + і۬ + +27-2 ܵ৘ RTC FAST Memory ֥ MPU 551 + +27-3 ܵ৘ RTC SLOW Memory ֥ MPU 551 + +27-4 ܵ৘ோഈ SRAM 0 ‫ ބ‬SRAM2 ഺჅ 128 KB ֥ MMU ်ଆൔ 552 + +27-5 SRAM0 MMU ်шࢸֹᆶ 553 + +27-6 SRAM2 MMU ်шࢸֹᆶ 554 + +27-7 DPORT_DMMU_TABLEn_REG ‫ ބ‬DPORT_IMMU_TABLEn_REG 555 + +27-8 ᆌؓ DMA ֥ MPU ഡᇂ 556 + +27-9 ோຓթԥఖ֥ྴֹᆶ 557 + +27-10 PRO_CPU ֥ MMU ஥ᇂཛ‫ݼ‬ 558 + +27-11 APP_CPU ֥ MMU ஥ᇂཛ‫ݼ‬ 558 + +27-12 PRO_CPU ֥ MMU ஥ᇂཛ‫ݼ‬čห൹ଆൔĎ 558 + +27-13 APP_CPU ֥ MMU ஥ᇂཛ‫ݼ‬čห൹ଆൔĎ 559 + +27-14 ோຓ SRAM ֥ྴ୅ֹᆶଆൔ 560 + +27-15 ோຓ SRAM ֥ྴֹᆶčᆞӈଆൔĎ 560 + +27-16 ோຓ SRAM ֥ྴֹᆶč֮-ۚଆൔĎ 560 + +27-17 ோຓ SRAM ֥ྴֹᆶč୽-అଆൔĎ 561 + +27-18 ோຓ RAM ֥ MMU ஥ᇂཛ‫ݼ‬ 561 + +27-19 ܵ৘ຓഡ֥ MPU 562 + +27-20 DPORT_AHBLITE_MPU_TABLE_X_REG 563 + +28-1 ᇏ؎ཟਈೆ१ֹᆶ 565 + +28-2 PIDCTRL_LEVEL_REG 565 + +28-3 PIDCTRL_FROM_n_REG 566 + +29-1 ESP32 ‫׈‬ಸൔԨଃԮ‫ۋ‬ఖ֥ܵ࢖ 575 + +29-2 SAR ADC ֥ྐ‫ݼ‬ൻೆ 579 + +29-3 ESP32 ֥ SAR ADC ॥ᇅఖ 579 + +29-4 ဢൔі࠷թఖ֥ሳ‫ྐ؍‬༏ 581 + +29-5 I ྘ DMA ඔऌ۬ൔ 582 + +29-6 II ྘ DMA ඔऌ۬ൔ 582 + +30-1 ؓ࠷թఖඔᆴ֥ ALU ᄎෘ 603 + +30-2 ؓᆷ਷৫ࠧᆴ֥ ALU ᄎෘ 604 + +30-3 ؓࢨ‫࠹؍‬ඔఖ࠷թఖ֥ ALU ᄎෘ 604 + +30-4 ADC ᆷ਷֥ൻೆྐ‫ݼ‬ 608 + +31-1 RTC ‫׈‬ჷთ 630 + +31-2 ߒྜჷ 633 + +ুᶈྐ༏॓࠯ 18 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + Ҭ๭ + +Ҭ๭ 25 + 25 + 1-1 ༢๤ࢲ‫ܒ‬ 30 + 1-2 ֹᆶ႘ഝࢲ‫ܒ‬ 33 + 1-3 Cache ༢๤ॿ๭ 38 + 2-1 ᇏ؎इᆔࢲ‫ܒ‬๭ 39 + 3-1 ༢๤‫໊گ‬ 44 + 3-2 ༢๤ൈᇒ 45 + 4-1 IO_MUXaRTC IO_MUX ‫ ބ‬GPIO ࢌߐइᆔࢲ‫ॿܒ‬๭ 47 + 4-2 ๙‫ ݖ‬IO_MUXaGPIO ࢌߐइᆔ֥ຓഡൻೆ 49 + 4-3 ๙‫ ݖ‬GPIO ࢌߐइᆔൻԛྐ‫ݼ‬ 50 + 4-4 ESP32 I/O Pad ‫׈܂‬ჷčQFN 6*6đ‫פ‬൪๭Ď 107 + 4-5 ESP32 I/O Pad ‫׈܂‬ჷčQFN 5*5đ‫פ‬൪๭Ď 108 + 6-1 DMA ႄౣ֥ࡏ‫ܒ‬ 109 + 6-2 ৽іࢲ‫ܒ‬๭ 110 + 6-3 UDMA ଆൔඔऌԮൻ 112 + 6-4 SPI DMA 113 + 7-1 SPI ༢๤ॿ๭ 115 + 7-2 SPI ඹཌಆච‫۽‬/϶ච‫۽‬๙ྐ 117 + 7-3 SPI ඔऌߏթ 118 + 7-4 GP-SPI Ֆࠏඔऌൻԛ 118 + 7-5 ѩྛ QSPI ࢤ१ 142 + 7-6 ѩྛ QSPI ࢤ१֥๙ྐଆൔ 143 + 8-1 SDIO Slave ‫ॶିۿ‬๭ 143 + 8-2 SDIO ሹཌഈඔऌԮൻ 143 + 8-3 CMD53 ଽಸ 144 + 8-4 SDIO Slave DMA ৽іࢲ‫ܒ‬ 145 + 8-5 ৽іԱ 146 + 8-6 Slave ཟ Host ‫ؿ‬ෂЇ֥ੀӱ 147 + 8-7 Slave Ֆ Host ࢤ൬Ї֥ੀӱ 147 + 8-8 Slave CPU ‫ܫ‬ᄛ buffer ֥ੀӱ 148 + 8-9 Ґဢൈ྽๭ 172 + 8-10 ൻԛൈ྽๭ 173 + 9-1 SD/MMC ຓഡ৵ࢤ֥ຉ௪ࢲ‫ܒ‬ 173 + 9-2 SD/MMC ຓ҆ࢤ१ྐ‫ݼ‬ 175 + 9-3 SD/MMC ࠎЧࡏ‫ܒ‬ 175 + 9-4 ଁ਷๙ਫ਼ሑ෿ࠏ 176 + 9-5 ඔऌԮൻሑ෿ࠏ 178 + 9-6 ඔऌࢤ൬ሑ෿ࠏ 178 + 9-7 ৽іߌࢲ‫ܒ‬ 181 + 9-8 ৽іࢲ‫ܒ‬ 203 + 9-9 ൈᇒཌྷ໊࿊ᄴ 205 + 10-1 Ethernet MAC ‫ۀିۿ‬ඍ 211 + 10-2 Ethernet ‫ॿିۿ‬๭ + 10-3 MII ࢤ१ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + +ুᶈྐ༏॓࠯ 19 + ّঌ໓֖ၩ࡮ + Ҭ๭ + +10-4 MII ൈᇒ 212 +10-5 RMII ࢤ१ 213 +10-6 RMII ൈᇒ 214 +10-7 ࢤ൬ඔऌൈ྽๭ 214 +10-8 ‫ؿ‬ෂඔऌൈ྽๭ 215 +10-9 ‫ؿ‬ෂ૭ඍ‫ژ‬ 215 +10-10 ࢤ൬৽іࢲ‫ܒ‬ 219 +11-1 I2C Master ࠎЧࡏ‫ܒ‬ 261 +11-2 I2C Slave ࠎЧࡏ‫ܒ‬ 261 +11-3 I2C ൈ྽๭ 262 +11-4 I2C ଁ਷࠷թఖࢲ‫ܒ‬ 263 +11-5 I2C Master ཿ 7-bit ֹᆶ Slave 264 +11-6 I2C Master ཿ 10-bit ֹᆶ Slave 265 +11-7 I2C Master ཿ 7-bit ֹᆶ Slave ֥ M ֹᆶ RAM 265 +11-8 I2C Master ‫؍ٳ‬ཿ 7-bit ֹᆶ Slave 266 +11-9 I2C Master ‫ ؀‬7-bit ֹᆶ Slave 267 +11-10 I2C Master ‫ ؀‬10-bit ֹᆶ Slave 267 +11-11 I2C Master Ֆ 7-bit ֹᆶ Slave ֥ M ֹᆶ‫؀‬౼ N ۱ඔऌ 268 +11-12 I2C Master ‫ ؀؍ٳ‬7-bit ֹᆶ Slave 269 +12-1 I2S ༢๤ॿ๭ 281 +12-2 I2S ൈᇒ 283 +12-3 Philips ѓሙ 284 +12-4 MSB ؓఊѓሙ 284 +12-5 PCM ѓሙ 285 +12-6 ‫ؿ‬ෂ FIFO ඔऌଆൔ 286 +12-7 ֻ၂ࢨ‫ࢤ؍‬൬ඔऌ 287 +12-8 ࢤ൬ඔऌཿೆ FIFO ଆൔ 288 +12-9 PDM ‫ؿ‬ෂଆॶ 289 +12-10 PDM ‫ؿ‬ෂྐ‫ݼ‬ 290 +12-11 PDM ࢤ൬ྐ‫ݼ‬ 290 +12-12 PDM ࢤ൬ଆॶ 290 +12-13 LCD ᇶࠏ‫ؿ‬ෂଆൔ 291 +12-14 LCD ᇶࠏ‫ؿ‬ෂඔऌᆠ۬ൔ 1 291 +12-15 LCD ᇶࠏ‫ؿ‬ෂඔऌᆠ۬ൔ 2 291 +12-16 Camera Ֆࠏࢤ൬ଆൔ 292 +12-17 I2S ֥ ADC ࢤ१ 292 +12-18 I2S ֥ DAC ࢤ१ 293 +12-19 I2S DAC ࢤ१ඔऌൻೆ 293 +13-1 UART ࠎЧࡏ‫ܒ‬๭ 314 +13-2 UART ‫܋‬ཚ RAM ๭ 315 +13-3 UART ඔऌᆠࢲ‫ܒ‬ 316 +13-4 AT_CMD ሳ‫۬ژ‬ൔ 316 +13-5 ႗ࡱੀ॥๭ 317 +14-1 LED_PWM ࡏ‫ܒ‬ 349 +14-2 LED_PWM ۚ෎๙֡ॿ๭ 349 +14-3 LED_PWM ‫ٳ‬௔ఖ 350 + +ুᶈྐ༏॓࠯ 20 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + Ҭ๭ + +14-4 LED_PWM ൻԛྐ‫ݼ‬๭ 351 + +14-5 ࡶэᅝॢбൻԛྐ‫ݼ‬๭ 351 + +15-1 RMT ࡏ‫ܒ‬ 364 + +15-2 ඔऌࢲ‫ܒ‬ 365 + +16-1 MCPWM ຓഡ‫ۀ‬ফ 372 + +16-2 ყ‫ٳ‬௔ఖଆॶ 374 + +16-3 ‫ק‬ൈఖଆॶ 374 + +16-4 Ҡቔఖଆॶ 375 + +16-5 ‫ܣ‬ᅰ࡟ҩଆॶ 377 + +16-6 ѽࠆଆॶ 377 + +16-7 ‫־‬ᄹ࠹ඔଆൔѯྙ 378 + +16-8 ‫࠹ࡨ־‬ඔଆൔѯྙ 379 + +16-9 ‫־‬ᄹ‫ࡨ־‬࿖ߌଆൔѯྙđ๝҄൙ࡱު‫ࡨ־‬ 379 + +16-10 ‫־‬ᄹ‫ࡨ־‬࿖ߌଆൔѯྙđ๝҄൙ࡱު‫־‬ᄹ 379 + +16-11 ‫־‬ᄹଆൔᇏളӮ֥ UTEP ‫ ބ‬UTEZ 380 + +16-12 ‫ࡨ־‬ଆൔᇏളӮ֥ UTEP ‫ ބ‬UTEZ 381 + +16-13 ‫־‬ᄹ‫ࡨ־‬ଆൔᇏളӮ֥ UTEP ‫ ބ‬UTEZ 382 + +16-14 PWM Ҡቔఖ֥ሰଆॶ 383 + +16-15 ‫־‬ᄹ‫ࡨ־‬ଆൔ༯֥ؓӫѯྙ 386 + +16-16 ‫־‬ᄹ࠹ඔଆൔđֆш҂ؓӫѯྙđPWMxA ‫ ބ‬PWMxB ‫׿‬৫‫ט‬ᇅ⚶ۚ‫׈‬௜ 387 + +16-17 ‫־‬ᄹ࠹ඔଆൔđઝԊ໊ᇂ҂ؓӫѯྙđPWMxA ‫׿‬৫‫ט‬ᇅ 388 + +16-18 ‫־‬ᄹ‫ࡨ־‬࿖ߌ࠹ඔଆൔđචခؓӫѯྙđᄝ PWMxA ‫ ބ‬PWMxB ഈ‫׿‬৫‫ט‬ᇅ⚶ۚ‫׈‬௜Ⴕི 389 + +16-19 ‫־‬ᄹ‫ࡨ־‬࿖ߌ࠹ඔଆൔđචခؓӫѯྙđᄝ PWMxA ‫ ބ‬PWMxB ഈ‫׿‬৫‫ט‬ᇅ⚶޺Ҁ 390 + +16-20 NCI ᄝ PWMxA ൻԛഈೈࡱ఼ᇅ൙ࡱൕ২ 391 + +16-21 CNTU ᄝ PWMxB ൻԛഈೈࡱ఼ᇅ൙ࡱൕ২ 392 + +16-22 ඵ౵ଆॶ֥षܱຉ௪ 394 + +16-23 ۚ‫׈‬௜Ⴕི޺Ҁ (AHC) ඵ౵ѯྙ 395 + +16-24 ֮‫׈‬௜Ⴕི޺Ҁ (ALC) ඵ౵ѯྙ 395 + +16-25 ۚ‫׈‬௜Ⴕི (AH) ඵ౵ѯྙ 396 + +16-26 ֮‫׈‬௜Ⴕི (AL) ඵ౵ѯྙ 396 + +16-27 PWM ᄛѯҠቔ֥ѯྙൕ২ 398 + +16-28 ᄛѯଆॶֻ֥၂۱ઝԊ‫ބ‬ᆭުӻ࿃֥ઝԊൕ২ 399 + +16-29 PWM ᄛѯଆॶᇏӻ࿃ઝԊ֥ 7 ᇕᅝॢбഡᇂ 400 + +17-1 PULSE_CNT ֆჭࠎЧࡏ‫ܒ‬๭ 448 + +17-2 PULSE_CNT ‫־‬ᄹ࠹ඔ๭ 450 + +17-3 PULSE_CNT ‫࠹ࡨ־‬ඔ๭ 450 + +21-1 ඔऌᆠ‫ބ‬ჹӱᆠᇏ໊֥თ 492 + +21-2 հ༂ᆠᇏ໊֥თ 494 + +21-3 ‫ݖ‬ᄛᆠᇏ໊֥თ 494 + +21-4 ᆠࡗएᇏ֥თ 495 + +21-5 ໊ൈ྽‫ܒ‬Ӯ 498 + +21-6 TWAI ‫੻ۀ‬๭ 499 + +21-7 ࢤ൬ੲѯఖ 506 + +21-8 ֆੲѯଆൔ 507 + +21-9 චੲѯଆൔ 508 + +21-10 հ༂ሑ෿э߄ 508 + +ুᶈྐ༏॓࠯ 21 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + Ҭ๭ + +21-11 ‫ש‬ാᇘҊ֥ bit ໊ᇂ 511 +25-1 ᄮലჷ 544 +26-1 Flash ࡆࢳૡଆॶࡏ‫ܒ‬ 546 +27-1 MMU ٠໙ൕ২ 552 +28-1 ᇏ؎ళส 567 +29-1 ԨଃԮ‫ۋ‬ఖ 574 +29-2 ԨଃԮ‫ۋ‬ఖ֥ଽ҆ࢲ‫ܒ‬ 575 +29-3 ԨଃԮ‫ۋ‬ఖ֥‫۽‬ቔੀӱ 576 +29-4 FSM ֥ଽ҆ࢲ‫ܒ‬ 577 +29-5 SAR ADC ֥‫ۀ‬ঃ 577 +29-6 SAR ADC ֥‫ۀିۿ‬ঃ 578 +29-7 RTC SAR ADC ֥‫ۀିۿ‬ঃ 580 +29-8 DIG SAR ADC ॥ᇅఖ֥‫ۀ‬ঃ 581 +29-9 ࠉ‫غ‬Ԯ‫ۋ‬ఖ֥ࢲ‫ܒ‬ 583 +29-10 DAC ֥‫ۀିۿ‬ঃ 584 +29-11 Ⴥ༿ѯྙളӮఖ֥‫۽‬ቔੀӱ 585 +30-1 ULP ླྀԩ৘ఖࠎЧࡏ‫ܒ‬ 601 +30-2 ULP ླྀԩ৘ఖ֥ᆷ਷۬ൔ 602 +30-3 ᆷ਷ো྘ - ؓ࠷թఖඔᆴ֥ ALU ᄎෘ 603 +30-4 ᆷ਷ো྘ - ؓᆷ਷৫ࠧᆴ֥ ALU ᄎෘ 603 +30-5 ᆷ਷ো྘ - ؓࢨ‫࠹؍‬ඔఖ࠷թఖ֥ ALU ᄎෘ 604 +30-6 ᆷ਷ো྘ - ST 605 +30-7 ᆷ਷ো྘ - LD 605 +30-8 ᆷ਷ো྘ - JUMP 606 +30-9 ᆷ਷ো྘ - JUMPR 606 +30-10 ᆷ਷ো྘ - JUMPS 607 +30-11 ᆷ਷ো྘ - HALT 607 +30-12 ᆷ਷ো྘ - WAKE 607 +30-13 ᆷ਷ো྘ - SLEEP 608 +30-14 ᆷ਷ো྘ - WAIT 608 +30-15 ᆷ਷ো྘ - ADC 608 +30-16 ᆷ਷ো྘ - I²C 609 +30-17 ᆷ਷ো྘ - REG_RD 609 +30-18 ᆷ਷ো྘ - REG_WR 610 +30-19 ULP ླྀԩ৘ఖӱ྽ॿ๭ 611 +30-20 ULP ླྀԩ৘ఖӱ྽ੀ॥๭ 612 +30-21 I2C ‫؀‬Ҡቔ 613 +30-22 I²C ཿҠቔ 614 +31-1 ESP32 ‫ݻۿ‬॥ᇅൕၩ๭ 624 +31-2 ඔሳଽ‫טނ‬࿢ఖ 625 +31-3 ֮‫טݻۿ‬࿢ఖ 626 +31-4 Flash ‫ט‬࿢ఖ 627 +31-5 ఴ࿢࡟ҩఖ 627 +31-6 RTC ࢲ‫ܒ‬๭ 628 +31-7 RTC ֮‫ݻۿ‬ൈᇒ 629 +31-8 ඔሳ֮‫ݻۿ‬ൈᇒ 629 + +ুᶈྐ༏॓࠯ 22 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + Ҭ๭ + +31-9 RTC ሑ෿ 630 + +31-10 ‫ݻۿ‬ଆൔ 632 + +31-11 ESP32 ఓ‫׮‬ੀӱ๭ 634 + +ুᶈྐ༏॓࠯ 23 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 1 ༢๤‫ބ‬թԥఖ + + 1 ༢๤‫ބ‬թԥఖ + + 1.1 ‫ۀ‬ඍ + + ESP32 ҐႨਆ۱‫ ܒࢲڍݗ‬Xtensa LX6 CPU ‫ܒ‬Ӯච‫ނ‬༢๤b෮Ⴕ֥ோഈթԥఖaோຓթԥఖၛࠣຓഡ‫҃ٳ׻‬ᄝ + ਆ۱ CPU ֥ඔऌሹཌ‫ބ‬Ĕࠇᆷ਷ሹཌഈb + Ԣ༯໓ਙԛ֥۱љ౦ঃຓđਆ۱ CPU ֹ֥ᆶ႘ഝӯؓӫࢲ‫ܒ‬đࠧ൐Ⴈཌྷ๝ֹ֥ᆶ٠໙๝၂ଢѓb༢๤ᇏ‫؟‬۱ຓ + ഡି‫ܔ‬๙‫ ݖ‬DMA ٠໙ோഈթԥఖb + ਆ۱ CPU ֥଀ӫ‫ٳ‬љ൞oPRO_CPUp‫ބ‬oAPP_CPUpbPRO սіoprotocolčླྀၰĎpđAPP սіoapplication +čႋႨĎpbᄝն‫؟‬ඔ౦ঃ༯đਆ۱ CPU ֥‫ିۿ‬൞ཌྷ๝֥b + + 1.2 ᇶေหྟ + + • ֹᆶॢࡗ + – ؓӫֹᆶ႘ഝ + – ඔऌሹཌაᆷ਷ሹཌ‫ٳ‬љႵ 4 GB (32-bit) ֹᆶॢࡗ + – 1296 KB ோഈթԥఖֹᆶॢࡗ + – 19704 KB ோຓթԥఖֹᆶॢࡗ + – 512 KB ຓഡֹᆶॢࡗ + – ҆‫ٳ‬ோഈթԥఖაோຓթԥఖ࠻ିФඔऌሹཌ္ିФᆷ਷ሹཌ٠໙ + – 328 KB DMA ֹᆶॢࡗ + + • ோഈթԥఖ + – 448 KB Internal ROM + – 520 KB Internal SRAM + – 8 KB RTC FAST Memory + – 8 KB RTC SLOW Memory + + • ோຓթԥఖ + ோຓ SPI թԥఖॖቔູோຓթԥఖФ႘ഝ֞ॖႨֹ֥ᆶॢࡗb҆‫ٳ‬ோഈթԥఖॖႨቔோຓթԥఖ֥ + Cacheb + – ቋնᆦӻ 16 MB ோຓ SPI Flash + – ቋնᆦӻ 8 MB ோຓ SPI SRAM + + • ຓഡ + – 41 ۱ຓഡଆॶ + + • DMA + – 13 ۱ऎႵ DMA ‫֥ିۿ‬ଆॶ + +ুᶈྐ༏॓࠯ 24 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 1 ༢๤‫ބ‬թԥఖ +๭ 1-1 ૭ඍਔ༢๤ࢲ‫ܒ‬b๭ 1-2 ૭ඍਔֹᆶ႘ഝࢲ‫ܒ‬b + + ๭ 1­1. ༢๤ࢲ‫ܒ‬ + + ๭ 1­2. ֹᆶ႘ഝࢲ‫ܒ‬ + +ুᶈྐ༏॓࠯ 25 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 1 ༢๤‫ބ‬թԥఖ + +1.3 ‫ିۿ‬૭ඍ + +1.3.1 ֹᆶ႘ഝ + +๝‫ܒ‬ච‫ނ‬༢๤Ⴎਆ۱‫ ܒࢲڍݗ‬Xtensa LX6 CPU ‫ܒ‬Ӯđૄ۱ CPU ‫׻‬ऎႵ 4 GBč32-bitĎֹ֥ᆶॢࡗbਆ۱ CPU +ֹ֥ᆶ႘ഝ൞ؓӫ֥b + +ֹᆶ 0x4000_0000 ၛ༯֥҆‫ٳ‬උႿඔऌሹཌֹ֥ᆶٓຶđֹᆶ 0x4000_0000 ~ 0x4FFF_FFFF ҆‫ູٳ‬ᆷ਷ሹཌ +ֹ֥ᆶٓຶđֹᆶ 0x5000_0000 ࠣၛഈ֥҆‫ٳ‬൞ඔऌሹཌაᆷ਷ሹཌ‫܋‬Ⴈֹ֥ᆶٓຶb + +CPU ֥ඔऌሹཌაᆷ਷ሹཌ‫ཬູ׻‬؊྽bࠧሳࢫֹᆶ 0x0a0x1a0x2a0x3 ٠໙֥ሳࢫ‫ٳ‬љ൞ 0x0 ٠໙֥ +32-bit ሳᇏ֥ቋ֮aՑ֮aՑۚaቋۚሳࢫbCPU ॖၛ๙‫ݖ‬ඔऌሹཌοᅶሳࢫa϶ሳaሳࣉྛؓఊა٤ؓఊ֥ +ඔऌ٠໙bCPU ॖၛ๙‫ݖ‬ᆷ਷ሹཌࣉྛඔऌ٠໙đ֌сྶ൞ሳؓఊٚൔĠ٤ؓఊඔऌ٠໙߶֝ᇁ CPU ‫۽‬ቔၳ +ӈb + +ਆ۱ CPU ‫ܔି׻‬൐Ⴈඔऌሹཌაᆷ਷ሹཌᆰࢤ٠໙ோഈթԥఖa൐Ⴈ Cache ‫ ބ‬MMU ᆰࢤ٠໙႘ഝֹ֞ᆶॢ +ࡗ֥ோຓթԥఖa൐Ⴈᆷ਷ሹཌᆰࢤ٠໙ຓഡb֒ਆ۱ CPU ٠໙๝၂ଢѓൈđః൐Ⴈཌྷ๝ֹ֥ᆶđᆜ۱༢๤֥ +ֹᆶ႘ഝӯؓӫࢲ‫ܒ‬bі 1-1 ૭ඍਔਆ۱ CPU ֥ඔऌሹཌაᆷ਷ሹཌᇏ֥۲‫ֹ؍‬ᆶ෮ି٠໙֥ଢѓb + +༢๤ᇏ҆‫ٳ‬ோഈթԥఖა҆‫ٳ‬ோຓթԥఖ࠻ॖၛФඔऌሹཌ٠໙္ॖၛФᆷ਷ሹཌ٠໙đᆃᇕ౦ঃ༯đਆ۱ +CPU ‫׻‬ॖၛႨ‫؟‬۱ֹᆶ٠໙֞๝၂ଢѓb + + і 1­1. ֹᆶ႘ഝ + +ሹཌো྘ шࢸֹᆶ ಸਈ ଢѓ + +ඔऌ ֹ໊֮ᆶ ֹ໊ۚᆶ 4 MB Ќ਽ +ඔऌ 4 MB ோຓթԥఖ + 0x0000_0000 0x3F3F_FFFF 3 MB ோຓթԥఖ +ඔऌ 512 KB Ќ਽ +ඔऌ 0x3F40_0000 0x3F7F_FFFF 512 KB ຓഡ +ᆷ਷ 776 KB ோഈթԥఖ +ᆷ਷ 0x3F80_0000 0x3FBF_FFFF 11512 KB ோഈթԥఖ + 244 MB ோຓթԥఖ +ඔऌĔᆷ਷ 0x3FC0_0000 0x3FEF_FFFF 8 KB Ќ਽ + ோഈթԥఖ + 0x3FF0_0000 0x3FF7_FFFF Ќ਽ + + 0x3FF8_0000 0x3FFF_FFFF + + 0x4000_0000 0x400C_1FFF + + 0x400C_2000 0x40BF_FFFF + + 0x40C0_0000 0x4FFF_FFFF + + 0x5000_0000 0x5000_1FFF + + 0x5000_2000 0xFFFF_FFFF + +1.3.2 ோഈթԥఖ + +ோഈթԥఖ‫ ູٳ‬Internal ROMaInternal SRAMaRTC FAST MemoryaRTC SLOW Memory ඹ۱҆‫ٳ‬đఃಸਈ‫ٳ‬ +љູ 448 KBa520 KBa8 KBa8 KBbఃᇏ 448 KB Internal ROM ‫ ູٳ‬384 KB Internal ROM 0a64 KB Internal +ROM 1 ਆ҆‫ٳ‬Ġ520 KB Internal SRAM ‫ ູٳ‬192 KB Internal SRAM 0a128 KB Internal SRAM 1a200 KB +Internal SRAM 2 ೘҆‫ٳ‬b + +RTC FAST Memory ა RTC SLOW Memory ‫ ູ׻‬SRAMb + +і 1-2 ਙԛਔ෮Ⴕோഈթԥఖၛࠣோഈթԥఖ֥ඔऌሹཌაᆷ਷ሹཌֹᆶ‫؍‬b + +ুᶈྐ༏॓࠯ 26 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 1 ༢๤‫ބ‬թԥఖ + + і 1­2. ோഈ࠷թఖֹᆶ႘ഝ + +ሹཌো྘ шࢸֹᆶ ಸਈ ଢѓ Сᇿ +ඔऌ PRO_CPU Only + ֹ໊֮ᆶ ֹ໊ۚᆶ 8 KB RTC FAST Memory +ඔऌ 56 KB Ќ਽ DMA + 0x3FF8_0000 0x3FF8_1FFF 64 KB Internal ROM 1 DMA +ඔऌ 56 KB Ќ਽ Сᇿ +ඔऌ 0x3FF8_2000 0x3FF8_FFFF 200 KB Internal SRAM 2 Remap +ሹཌো྘ 128 KB Internal SRAM 1 +ᆷ਷ 0x3FF9_0000 0x3FF9_FFFF Cache +ᆷ਷ ಸਈ ଢѓ + 0x3FFA_0000 0x3FFA_DFFF Remap +ᆷ਷ 32 KB Internal ROM 0 PRO_CPU Only +ᆷ਷ 0x3FFA_E000 0x3FFD_FFFF 352 KB Internal ROM 0 Сᇿ +ᆷ਷ 64 KB Ќ਽ +ᆷ਷ 0x3FFE_0000 0x3FFF_FFFF 64 KB Internal SRAM 0 +ᆷ਷ 128 KB Internal SRAM 0 +ᆷ਷ шࢸֹᆶ 64 KB Internal SRAM 1 +ሹཌো྘ 32 KB Internal SRAM 1 +ඔऌᆷ਷ ֹ໊֮ᆶ ֹ໊ۚᆶ 32 KB Internal SRAM 1 + 8 KB RTC FAST Memory + 0x4000_0000 0x4000_7FFF + ಸਈ ଢѓ + 0x4000_8000 0x4005_FFFF + 8 KB RTC SLOW Memory + 0x4006_0000 0x4006_FFFF + + 0x4007_0000 0x4007_FFFF + + 0x4008_0000 0x4009_FFFF + + 0x400A_0000 0x400A_FFFF + + 0x400B_0000 0x400B_7FFF + + 0x400B_8000 0x400B_FFFF + + 0x400C_0000 0x400C_1FFF + + шࢸֹᆶ + + ֹ໊֮ᆶ ֹ໊ۚᆶ + + 0x5000_0000 0x5000_1FFF + +1.3.2.1 Internal ROM 0 + +Internal ROM 0 ֥ಸਈູ 384 KBđॖၛФਆ۱ CPU ๙‫ݖ‬ᆷ਷ሹཌ 0x4000_0000 ~ 0x4005_FFFF ‫؀‬౼b +٠໙ ROM 0 ֥๨ 32 KB ֹ֥ᆶč0x4000_0000 ~ 0x4000_7FFFĎॖၛФᇗྍ႘ഝ֞ Internal SRAM 1 ᇏ֥၂҆ +‫ٳ‬đᆃ҆‫ٳ‬ჰЧФֹᆶ 0x400B_0000 ~ 0x400B_7FFF ٠໙bᇗ႘ഝൈđᆃ 32 KB SRAM ҂ିᄜФֹᆶ +0x400B_0000 ~ 0x400B_7FFF ٠໙đ֌൞ॖၛФඔऌሹཌ (0x3FFE_8000 ~ 0x3FFE_FFFFĎ٠໙bൌགྷٚൔ൞ +‫ٳ‬љູਆ۱ CPU ஥ᇂ၂۱࠷թఖđູࠧ PRO_CPU ᇂ໊ DPORT_PRO_BOOT_REMAP_CTRL_REG ࠷թఖ֥ +bit 0 ࠇᆀູ APP_CPU ᇂ໊ DPORT_APP_BOOT_REMAP_CTRL_REG ࠷թఖ֥ bit 0b + +1.3.2.2 Internal ROM 1 + +Internal ROM 1 ֥ಸਈູ 64 KBđఃॖၛФਆ۱ CPU ๙‫ݖ‬ඔऌሹཌ 0x3FF9_0000 ~ 0x3FF9_FFFF ‫؀‬౼b + +1.3.2.3 Internal SRAM 0 + +Internal SRAM 0 ֥ಸਈູ 192 KBđ๙‫ݖ‬஥ᇂđ႗ࡱ֥๨ 64 KB ॖၛቔູ Cache টߏթோຓթԥఖb҂ቔູ +Cache ൐Ⴈൈđ๨ 64 KB ॖၛФਆ۱ CPU ๙‫ݖ‬ᆷ਷ሹཌ 0x4007_0000 ~ 0x4007_FFFF ‫؀‬ཿđఃჅ 128 KB ॖ +ၛФਆ۱ CPU ๙‫ݖ‬ᆷ਷ሹཌ 0x4008_0000 ~ 0x4009_FFFF ‫؀‬ཿb + +ুᶈྐ༏॓࠯ 27 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 1 ༢๤‫ބ‬թԥఖ + +1.3.2.4 Internal SRAM 1 + +Internal SRAM 1 ֥ಸਈູ 128 KBđః࠻ॖၛФਆ۱ CPU ๙‫ݖ‬ඔऌሹཌ 0x3FFE_0000 ~ 0x3FFF_FFFF ‫؀‬ཿđ +္ॖၛФਆ۱ CPU ๙‫ݖ‬ᆷ਷ሹཌ 0x400A_0000 ~ 0x400B_FFFF ‫؀‬ཿb + +ᆷ਷ሹཌֹᆶ‫ބ‬ඔऌሹཌֹᆶ٠໙֥ word ൞୉྽֥bֹࠧᆶğ +0x3FFE_0000 ა 0x400B_FFFC ٠໙֞ཌྷ๝֥ word +0x3FFE_0004 ა 0x400B_FFF8 ٠໙֞ཌྷ๝֥ word +0x3FFE_0008 ა 0x400B_FFF4 ٠໙֞ཌྷ๝֥ word +ll +0x3FFF_FFF4 ა 0x400A_0008 ٠໙֞ཌྷ๝֥ word +0x3FFF_FFF8 ა 0x400A_0004 ٠໙֞ཌྷ๝֥ word +0x3FFF_FFFC ა 0x400A_0000 ٠໙֞ཌྷ๝֥ word + +CPU ֥ඔऌሹཌაᆷ਷ሹཌ‫׻‬൞ཬ؊྽bၹՎֹᆶॢࡗ٠໙ૄ۱ word ֥ሳࢫඨ྽҂൞୉྽֥bֹࠧᆶğ +0x3FFE_0000 ٠໙֥ሳࢫ֩๝Ⴟ 0x400B_FFFC ٠໙֥ word ᇏ֥ቋ֮ሳࢫ +0x3FFE_0001 ٠໙֥ሳࢫ֩๝Ⴟ 0x400B_FFFC ٠໙֥ word ᇏ֥Ց֮ሳࢫ +0x3FFE_0002 ٠໙֥ሳࢫ֩๝Ⴟ 0x400B_FFFC ٠໙֥ word ᇏ֥Ցۚሳࢫ +0x3FFE_0003 ٠໙֥ሳࢫ֩๝Ⴟ 0x400B_FFFC ٠໙֥ word ᇏ֥ቋۚሳࢫ +0x3FFE_0004 ٠໙֥ሳࢫ֩๝Ⴟ 0x400B_FFF8 ٠໙֥ word ᇏ֥ቋ֮ሳࢫ +0x3FFE_0005 ٠໙֥ሳࢫ֩๝Ⴟ 0x400B_FFF8 ٠໙֥ word ᇏ֥Ց֮ሳࢫ +0x3FFE_0006 ٠໙֥ሳࢫ֩๝Ⴟ 0x400B_FFF8 ٠໙֥ word ᇏ֥Ցۚሳࢫ +0x3FFE_0007 ٠໙֥ሳࢫ֩๝Ⴟ 0x400B_FFF8 ٠໙֥ word ᇏ֥ቋۚሳࢫ +ll +0x3FFF_FFF8 ٠໙֥ሳࢫ֩๝Ⴟ 0x400A_0004 ٠໙֥ word ᇏ֥ቋ֮ሳࢫ +0x3FFF_FFF9 ٠໙֥ሳࢫ֩๝Ⴟ 0x400A_0004 ٠໙֥ word ᇏ֥Ց֮ሳࢫ +0x3FFF_FFFA ٠໙֥ሳࢫ֩๝Ⴟ 0x400A_0004 ٠໙֥ word ᇏ֥Ցۚሳࢫ +0x3FFF_FFFB ٠໙֥ሳࢫ֩๝Ⴟ 0x400A_0004 ٠໙֥ word ᇏ֥ቋۚሳࢫ +0x3FFF_FFFC ٠໙֥ሳࢫ֩๝Ⴟ 0x400A_0000 ٠໙֥ word ᇏ֥ቋ֮ሳࢫ +0x3FFF_FFFD ٠໙֥ሳࢫ֩๝Ⴟ 0x400A_0000 ٠໙֥ word ᇏ֥Ց֮ሳࢫ +0x3FFF_FFFE ٠໙֥ሳࢫ֩๝Ⴟ 0x400A_0000 ٠໙֥ word ᇏ֥Ցۚሳࢫ +0x3FFF_FFFF ٠໙֥ሳࢫ֩๝Ⴟ 0x400A_0000 ٠໙֥ word ᇏ֥ቋۚሳࢫ + +҆‫ٳ‬թԥఖॖၛФᇗྍ႘ഝ֞ ROM 0 ֹ֥ᆶॢࡗbབྷ༥ྐ༏౨ҕ࡮ Internal Rom 0b + +1.3.2.5 Internal SRAM 2 + +Internal SRAM 2 ֥ಸਈູ 200 KBđఃॖၛФਆ۱ CPU ๙‫ݖ‬ඔऌሹཌ 0x3FFA_E000 ~ 0x3FFD_FFFF ‫؀‬ +ཿb + +1.3.2.6 DMA + +DMA ൐Ⴈა CPU ඔऌሹཌປಆཌྷ๝ֹ֥ᆶ‫؀‬ཿ Internal SRAM 1 ა Internal SRAM 2bࠧ DMA ൐Ⴈֹᆶ +0x3FFE_0000 ~ 0x3FFF_FFFF ‫؀‬ཿ Internal SRAM 1đ൐Ⴈֹᆶ 0x3FFA_E000 ~ 0x3FFD_FFFF ‫؀‬ཿ Internal +SRAM 2b + +༢๤ᇏऎႵ DMA ‫֥ିۿ‬ଆॶሹ‫܋‬Ⴕ 13 ۱bі 1-3 ਙԛਔ෮ႵऎႵ DMA ‫֥ିۿ‬ଆॶb + +ুᶈྐ༏॓࠯ 28 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 1 ༢๤‫ބ‬թԥఖ + + і 1­3. ऎႵ DMA ‫֥ିۿ‬ଆॶ + + UART0 UART1 UART2 + + SPI1 SPI2 SPI3 + + I2S0 I2S1 + + SDIO Slave SDMMC + + EMAC + + BT WIFI + +1.3.2.7 RTC FAST Memory + +RTC FAST Memory ູ 8 KB SRAMđఃᆺିФ PRO_CPU ๙‫ݖ‬ඔऌሹཌ 0x3FF8_0000 ~ 0x3FF8_1FFF ‫؀‬ཿđࠇ +Ф PRO_CPU ๙‫ݖ‬ᆷ਷ሹཌ 0x400C_0000 ~ 0x400C_1FFF ‫؀‬ཿbაః෰թԥఖ҂๝đAPP_CPU ҂ି٠໙ +RTC FAST Memoryb + +PRO_CPU ֥ᆃਆ‫ֹ؍‬ᆶ๝྽٠໙ RTC FAST Memorybֹࠧᆶ 0x3FF8_0000 ა 0x400C_0000 ٠໙֞ཌྷ๝֥ +wordđ0x3FF8_0004 ა 0x400C_0004 ٠໙֞ཌྷ๝֥ wordđ0x3FF8_0008 ა 0x400C_0008 ٠໙֞ཌྷ๝֥ +wordđၛՎো๷bAPP_CPU ֥ᆃਆ‫ֹ؍‬ᆶ҂ି٠໙֞ RTC FAST Memoryđ္҂ି٠໙֞ః෰಩‫ޅ‬ଢѓb + +1.3.2.8 RTC SLOW Memory + +RTC SLOW Memory ູ 8 KB SRAMđఃॖၛФਆ۱ CPU ๙‫ݖ‬ඔऌሹཌაᆷ਷ሹཌ‫܋‬Ⴈֹᆶ‫ ؍‬0x5000_0000 ~ +0x5000_1FFF ‫؀‬ཿb + +1.3.3 ோຓթԥఖ + +ESP32 ࡼ External Flash ა External SRAM ቔູோຓթԥఖbі 1-4 ਙԛਔਆ۱ CPU ֥ඔऌሹཌაᆷ਷ሹཌᇏ +֥۲‫ֹ؍‬ᆶ๙‫ ݖ‬Cache ა MMU ෮ି٠໙֥ோຓթԥఖbਆ۱ CPU ๙‫ ݖ‬Cache ა MMU ؓோຓթԥఖࣉྛ٠ +໙ൈđCache ࡼ۴ऌ MMU ᇏ֥ഡᇂϜ CPU ֹ֥ᆶэߐູ External Flash ა External SRAM ֥ൌֹᆶbࣜ‫ݖ‬э +ߐᆭު֥ൌֹᆶቋնᆦӻ 16 MB ֥ External Flash ა 8 MB ֥ External SRAMb + + і 1­4. ோຓթԥఖֹᆶ႘ഝ + +ሹཌো྘ шࢸֹᆶ ಸਈ ଢѓ Сᇿ +ඔऌ 4 MB External Flash ‫؀‬ +ඔऌ ֹ໊֮ᆶ ֹ໊ۚᆶ 4 MB External SRAM ‫؀‬Ĕཿ +ሹཌো྘ ಸਈ ଢѓ Сᇿ +ᆷ਷ 0x3F40_0000 0x3F7F_FFFF 11512 KB External Flash ‫؀‬ + + 0x3F80_0000 0x3FBF_FFFF + + шࢸֹᆶ + + ֹ໊֮ᆶ ֹ໊ۚᆶ + + 0x400C_2000 0x40BF_FFFF + +1.3.4 Cache + +ೂ༯๭ 1-3 ෮ൕđESP32 ֥ 2 ۱ CPU ۲Ⴕ၂ቆնཬູ 32 KB ֥ cacheđႨၛ٠໙ຓ҆թԥఖbPRO CPU ‫ބ‬ +APP CPU ‫ٳ‬љ൐Ⴈ DPORT_PRO_CACHE_CTRL_REG ֥ PRO_CACHE_ENABLE ໊‫ބ‬ +DPORT_APP_CACHE_CTRL_REG ֥ APP_CACHE_ENABLE ໊൐ି Cache ‫ିۿ‬b + +ESP32 Cache ҐႨਆਫ਼ቆཌྷ৵֥႘ഝٚൔb֒ᆺႵ PRO CPU ൐Ⴈ Cache ࠇᆺႵ APP CPU ൐Ⴈ Cache ൈđॖ +ၛ๙‫ݖ‬஥ᇂ࠷թఖ DPORT_CACHE_MUX_MODE_REG ֥ CACHE_MUX_MODE[1:0] ໊đ࿊ᄴ൐Ⴈ Internal + +ুᶈྐ༏॓࠯ 29 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 1 ༢๤‫ބ‬թԥఖ + + ๭ 1­3. Cache ༢๤ॿ๭ + +SRAM0 ֥ POOL0 ࠇ POOL1 ቔູ cache memoryb֒ PRO CPU ‫ ބ‬APP CPU ‫׻‬൐Ⴈ Cache ൈđInternal +SRAM0 ֥ POOL0 ‫ ބ‬POOL1 ॖၛ‫گ‬Ⴈቔູ cache memorybབྷ࡮і 1-5b + + і 1­5. Cache memory ଆൔ + + CACHE_MUX_MODE POOL0 POOL1 + 0 PRO CPU APP CPU + 1 PRO CPU/APP CPU + 2 - + 3 - PRO CPU/APP CPU + APP CPU + PRO CPU + +Ⴎі 1-5 ॖᆩđ֒ CACHE_MUX_MODE ູ 1 ࠇ 2 ൈđPRO CPU ‫ ބ‬APP CPU ҂ॖ๝ൈषఓ Cache ‫ିۿ‬bषఓ +Cache ‫ުିۿ‬đPOOL0 ࠇᆀ POOL1 ᆺቔູ cache memory ൐Ⴈđ҂ି‫گ‬Ⴈቔູᆷ਷ሹཌ֥٠໙౵თb + +ESP32 Cache ऎႵ Flush ‫ିۿ‬bླေᇿၩ֥൞đ֒൐Ⴈ Flush ‫ିۿ‬ൈđཿೆ cache ֥ඔऌࡼФ‫ש‬ఙđѩ҂߶ཿ +߭֞ External SRAM ᇏbൌགྷ flush Ҡቔ֥ٚ‫ູم‬ğ༵ࡼ DPORT_x_CACHE_CTRL_REG ֥ +x_CACHE_FLUSH_ENA ໊ౢ 0đᄜࡼ‫໊ھ‬ᇂ 1bՎުđ༢๤႗ࡱ߶ࡼ࠷թఖᇏ֥ x_CACHE_FLUSH_DONE ໊ +ᇂູ 1 ൈđіૼ cache flush ҠቔၘࣜປӮđఃᇏ x іൕoPROpࠇoAPPpb + +ESP32 Cache ֹ֥ᆶ႘ഝབྷ࡮ோഈթԥఖᅣࢫ‫ބ‬ோຓթԥఖᅣࢫb + +1.3.5 ຓഡ + +ESP32 ‫܋‬Ⴕ 41 ۱ຓഡଆॶbі 1-6 བྷ༥૭ඍਔਆ۱ CPU ֥ඔऌሹཌᇏ֥۲‫ֹ؍‬ᆶ෮ି٠໙֥۲۱ຓഡଆॶb +Ԣਔ PID Controller ၛຓđఃჅຓഡଆॶ‫׻‬ॖၛФਆ۱ CPU Ⴈཌྷ๝ֹᆶ٠໙֞b + +ুᶈྐ༏॓࠯ 30 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 1 ༢๤‫ބ‬թԥఖ + + і 1­6. ຓഡֹᆶ႘ഝ + +ሹཌো྘ ሹཌো྘ ಸਈ ଢѓ Сᇿ +ඔऌ ૄ۱ CPU ֆ‫׿‬ຓഡ +ඔऌ ֹ໊֮ᆶ ֹ໊ۚᆶ 4 KB DPort Register +ඔऌ 4 KB AES Accelerator ೘۱҆‫ٳ‬ᆭ၂ +ඔऌ 0x3FF0_0000 0x3FF0_0FFF 4 KB RSA Accelerator ೘۱҆‫ٳ‬ᆭ၂ +ඔऌ 4 KB SHA Accelerator ೘۱҆‫ٳ‬ᆭ၂ + 0x3FF0_1000 0x3FF0_1FFF 4 KB Secure Boot +ඔऌ 44 KB Ќ਽ + 0x3FF0_2000 0x3FF0_2FFF 16 KB Cache MMU Table +ඔऌ 44 KB Ќ਽ + 0x3FF0_3000 0x3FF0_3FFF 4 KB PID Controller +ඔऌ 128 KB Ќ਽ + 0x3FF0_4000 0x3FF0_4FFF 4 KB UART0 +ඔऌ 4 KB Ќ਽ +ඔऌ 0x3FF0_5000 0x3FF0_FFFF 4 KB SPI1 +ඔऌ 4 KB SPI0 + 0x3FF1_0000 0x3FF1_3FFF 4 KB GPIO +ඔऌ 12 KB Ќ਽ +ඔऌ 0x3FF1_4000 0x3FF1_EFFF 4 KB RTC + 4 KB IO MUX +ඔऌ 0x3FF1_F000 0x3FF1_FFFF 4 KB Ќ਽ +ඔऌ 4 KB SDIO Slave + 0x3FF2_0000 0x3FF3_FFFF 4 KB UDMA1 +ඔऌ 8 KB Ќ਽ +ඔऌ 0x3FF4_0000 0x3FF4_0FFF 4 KB I2S0 + 4 KB UART1 +ඔऌ 0x3FF4_1000 0x3FF4_1FFF 8 KB Ќ਽ +ඔऌ 4 KB I2C0 +ඔऌ 0x3FF4_2000 0x3FF4_2FFF 4 KB UDMA0 +ඔऌ 4 KB SDIO Slave +ඔऌ 0x3FF4_3000 0x3FF4_3FFF 4 KB RMT +ඔऌ 4 KB PCNT +ඔऌ 0x3FF4_4000 0x3FF4_4FFF 4 KB SDIO Slave +ඔऌ 4 KB LED PWM +ඔऌ 0x3FF4_5000 0x3FF4_7FFF 4 KB Efuse Controller + 4 KB Flash Encryption +ඔऌ 0x3FF4_8000 0x3FF4_8FFF 8 KB Ќ਽ +ඔऌ 4 KB MCPWM0 +ඔऌ 0x3FF4_9000 0x3FF4_9FFF 4 KB TIMG0 + 4 KB TIMG1 +ඔऌ 0x3FF4_A000 0x3FF4_AFFF 12 KB Ќ਽ +ඔऌ 4 KB SPI2 + 0x3FF4_B000 0x3FF4_BFFF 4 KB SPI3 + + 0x3FF4_C000 0x3FF4_CFFF + + 0x3FF4_D000 0x3FF4_EFFF + + 0x3FF4_F000 0x3FF4_FFFF + + 0x3FF5_0000 0x3FF5_0FFF + + 0x3FF5_1000 0x3FF5_2FFF + + 0x3FF5_3000 0x3FF5_3FFF + + 0x3FF5_4000 0x3FF5_4FFF + + 0x3FF5_5000 0x3FF5_5FFF + + 0x3FF5_6000 0x3FF5_6FFF + + 0x3FF5_7000 0x3FF5_7FFF + + 0x3FF5_8000 0x3FF5_8FFF + + 0x3FF5_9000 0x3FF5_9FFF + + 0x3FF5_A000 0x3FF5_AFFF + + 0x3FF5_B000 0x3FF5_BFFF + + 0x3FF5_C000 0x3FF5_DFFF + + 0x3FF5_E000 0x3FF5_EFFF + + 0x3FF5_F000 0x3FF5_FFFF + + 0x3FF6_0000 0x3FF6_0FFF + + 0x3FF6_1000 0x3FF6_3FFF + + 0x3FF6_4000 0x3FF6_4FFF + + 0x3FF6_5000 0x3FF6_5FFF + +ুᶈྐ༏॓࠯ 31 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 1 ༢๤‫ބ‬թԥఖ + +ሹཌো྘ ሹཌো྘ ಸਈ ଢѓ Сᇿ + +ඔऌ ֹ໊֮ᆶ ֹ໊ۚᆶ 4 KB SYSCON +ඔऌ 4 KB I2C1 +ඔऌ 0x3FF6_6000 0x3FF6_6FFF 4 KB SDMMC +ඔऌ 8 KB EMAC +ඔऌ 0x3FF6_7000 0x3FF6_7FFF 4KB TWAI +ඔऌ 4 KB MCPWM1 +ඔऌ 0x3FF6_8000 0x3FF6_8FFF 4 KB I2S1 +ඔऌ 4 KB UART2 +ඔऌ 0x3FF6_9000 0x3FF6_AFFF 4 KB Ќ਽ +ඔऌ 4 KB Ќ਽ + 0x3FF6_B000 0x3FF6_BFFF 16 KB Ќ਽ +ඔऌ 4 KB RNG + 0x3FF6_C000 0x3FF6_CFFF 40 KB Ќ਽ + + 0x3FF6_D000 0x3FF6_DFFF + + 0x3FF6_E000 0x3FF6_EFFF + + 0x3FF6_F000 0x3FF6_FFFF + + 0x3FF7_0000 0x3FF7_0FFF + + 0x3FF7_1000 0x3FF7_4FFF + + 0x3FF7_5000 0x3FF7_5FFF + + 0x3FF7_6000 0x3FF7_FFFF + +ᇿၩğ + + • ൐Ⴈ 0x3FF40000 ~ 0x3FF7FFFF ֹᆶॢࡗ (DPORT) ٠໙֥ຓഡđCPU ္ॖၛ൐Ⴈ 0x60000000 ~ + 0x6003FFFF ֹᆶॢࡗ (AHB) ٠໙bࠧ൐Ⴈ (0x3FF40000 + n) ֹᆶ‫ބ‬൐Ⴈ (0x60000000 + n) ֹᆶ٠໙֥ଽ + ಸ൞ཌྷ๝֥đఃᇏ n = 0 ~ 0x3FFFFb + + • ཌྷбႿ๙‫ ݖ‬AHB ٠໙ຓഡđCPU ๙‫ ݖ‬DPORT ٠໙ຓഡིੱ۷ۚb֌൞ DPORT Ⴕყҩྟ‫( ؀‬speculative + read) ֥หׄđ҂ିЌᆣૄ၂Ց֥‫؀‬٠໙‫׻‬൞ᆇൌႵི֥bਸ਼ຓđDPORT ߶յ੹ሹཌഈ֥‫؀‬ཿҠቔ֥༵ު + ඨ྽ၛิശྟିđᆃॖି߶֝ᇁؓ‫؀‬ཿҠቔ֥༵ުඨ྽Ⴕ࿸۬ေ౰֥ӱ྽‫ؿ‬ളЩ঎bՎຓ൐Ⴈ AHB ሹཌ + ‫ ؀‬FIFO ߶ԛགྷ໭‫م‬ყᆩ֥հ༂bၹՎ൐Ⴈൈ౨࿸۬቎࿖ uESP32 ा༂іࠣࢳथϷ‫م‬vᇏֻ 3.3a3.10a + 3.16 ‫ ބ‬3.17 ᅣࢫ֥૭ඍb + +1.3.5.1 ҂ؓӫ PID Controller ຓഡ + +༢๤ᇏႵਆ۱ PID Controller ‫ٳ‬љ‫ڛ‬ༀႿ PRO_CPU ‫ ބ‬APP_CPUbPRO_CPU ‫ ބ‬APP_CPU ‫׻‬ᆺି٠໙ሱ֥࠭ +PID Controllerđ҂ି٠໙֥ؓٚ PID Controllerbਆ۱ CPU ‫׻‬൐Ⴈඔऌሹཌ 0x3FF1_F000 ~ 3FF1_FFFF ٠໙ +ሱ֥࠭ PID Controllerb + +1.3.5.2 ҂৵࿃ຓഡֹᆶٓຶ + +ຓഡଆॶ SDIO Slave Ф߃‫ູٳ‬೘҆‫ٳ‬bਆ۱ CPU ٠໙ᆃ೘҆‫ֹ֥ٳ‬ᆶ൞҂৵࿃֥bᆃ೘҆‫ٳٳ‬љФਆ۱ CPU +֥ඔऌሹཌ 0x3FF4_B000 ~ 3FF4_BFFFa0x3FF5_5000 ~ 3FF5_5FFFa0x3FF5_8000 ~ 3FF5_8FFF ٠໙b‫ބ‬ః +෰ຓഡ၂ဢđSDIO Slave ିФਆ۱ CPU ٠໙b + +1.3.5.3 թԥఖ෎؇ + +ROM ‫ ބ‬SRAM ֥ൈᇒჷ‫׻‬൞ CPU_CLKđCPU ॖᄝֆ۱ൈᇒᇛ௹ଽ٠໙ᆃਆ۱թԥఖbႮႿ RTC FAST +Memory ֥ൈᇒჷ൞ APB_CLOCKđRTC SLOW Memory ֥ൈᇒჷ൞ FAST_CLOCKđ෮ၛ CPU ٠໙ᆃਆ۱թ +ԥఖ֥෎؇഍તbDMA ᄝ APB_CLK ൈᇒ༯٠໙թԥఖb + +SRAM ૄ 32K ູ၂۱ॶbᆺေ๝ൈ٠໙֥൞҂๝֥ॶđପહ CPU ‫ ބ‬DMA ॖၛ๝ൈၛቋॹ෎؇٠໙ +SRAMb + +ুᶈྐ༏॓࠯ 32 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 2 ᇏ؎इᆔ (INTERRUPT) + +2 ᇏ؎इᆔ (INTERRUPT) + +2.1 ‫ۀ‬ඍ + +ESP32 ᇏ؎इᆔࡼ಩၂ຓ҆ᇏ؎ჷֆ‫ٳ׿‬஥֞ૄ۱ CPU ֥಩၂ຓ҆ᇏ؎ഈbᆃิ‫܂‬ਔ఼ն֥ਲࠃྟđିൡႋ +҂๝֥ႋႨླ౰b + +2.2 ᇶေหྟ + + • ࢤ൳ 71 ۱ຓ҆ᇏ؎ჷቔູൻೆ + • ູਆ۱ CPU ‫ٳ‬љളӮ 26 ۱ຓ҆ᇏ؎čሹ‫ ܋‬52 ۱Ďቔູൻԛ + • ௠з CPU ֥ NMI ো྘ᇏ؎ + • Ұ࿘ຓ҆ᇏ؎ჷ֒భ֥ᇏ؎ሑ෿ +ᇏ؎इᆔ֥ࢲ‫ܒ‬ೂ๭ 2-1 ෮ൕb + + ๭ 2­1. ᇏ؎इᆔࢲ‫ܒ‬๭ + +2.3 ‫ିۿ‬૭ඍ + +2.3.1 ຓ҆ᇏ؎ჷ + +ESP32 ሹ‫܋‬Ⴕ 71 ۱ຓ҆ᇏ؎ჷbі 2-1 ਙԛਔ෮Ⴕຓ҆ᇏ؎ჷbESP32 ᇏ֥ 71 ۱ຓ҆ᇏ؎ჷᇏႵ 67 ۱ॖၛ +‫ٳ‬஥۳ਆ۱ CPUbఃჅ֥ 4 ۱ຓ҆ᇏ؎ჷᆺି‫ٳ‬஥۳ห‫ ֥ק‬CPUđૄ۱ CPU 2 ۱bGPIO_INTERRUPT_PRO +‫ ބ‬GPIO_INTERRUPT_PRO_NMI ᆺॖၛ‫ٳ‬஥۳ PRO_CPUđGPIO_INTERRUPT_APP ‫ބ‬ +GPIO_INTERRUPT_APP_NMI ᆺॖၛ‫ٳ‬஥۳ APP_CPUbၹՎđPRO_CPU ა APP_CPU ۲ॖၛ‫ٳ‬஥֞ 69 ۱ຓ +҆ᇏ؎ჷb + +ুᶈྐ༏॓࠯ 33 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + ুᶈྐ༏॓࠯ і 2­1. PRO_CPUaAPP_CPU ຓ҆ᇏ؎஥ᇂ࠷թఖaຓ҆ᇏ؎ჷᇏ؎ሑ෿࠷թఖaຓ҆ᇏ؎ჷ 2 ᇏ؎इᆔ (INTERRUPT) + + PRO_CPU APP_CPU + + Peripheral Interrupt Status Register Peripheral Interrupt Source Status Register Peripheral Interrupt + Name + Configuration Register Bit Name No. No. Name Bit Configuration Register + + DPORT_PRO_MAC_INTR_MAP_REG 0 0 MAC_INTR 0 0 DPORT_APP_MAC_INTR_MAP_REG + + DPORT_PRO_MAC_NMI_MAP_REG 1 1 MAC_NMI 1 1 DPORT_APP_MAC_NMI_MAP_REG + + DPORT_PRO_BB_INT_MAP_REG 2 2 BB_INT 2 2 DPORT_APP_BB_INT_MAP_REG + + DPORT_PRO_BT_MAC_INT_MAP_REG 3 3 BT_MAC_INT 3 3 DPORT_APP_BT_MAC_INT_MAP_REG + + DPORT_PRO_BT_BB_INT_MAP_REG 4 4 BT_BB_INT 4 4 DPORT_APP_BT_BB_INT_MAP_REG + + DPORT_PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 DPORT_APP_BT_BB_NMI_MAP_REG + + DPORT_PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 DPORT_APP_RWBT_IRQ_MAP_REG + + DPORT_PRO_RWBLE_IRQ_MAP_REG 7 7 RWBLE_IRQ 7 7 DPORT_APP_RWBLE_IRQ_MAP_REG + + DPORT_PRO_RWBT_NMI_MAP_REG 8 8 RWBT_NMI 8 8 DPORT_APP_RWBT_NMI_MAP_REG + + DPORT_PRO_RWBLE_NMI_MAP_REG 9 9 RWBLE_NMI 9 9 DPORT_APP_RWBLE_NMI_MAP_REG + + DPORT_PRO_SLC0_INTR_MAP_REG 10 10 SLC0_INTR 10 10 DPORT_APP_SLC0_INTR_MAP_REG + + DPORT_PRO_SLC1_INTR_MAP_REG 11 11 SLC1_INTR 11 11 DPORT_APP_SLC1_INTR_MAP_REG + + DPORT_PRO_UHCI0_INTR_MAP_REG 12 12 UHCI0_INTR 12 12 DPORT_APP_UHCI0_INTR_MAP_REG + + DPORT_PRO_UHCI1_INTR_MAP_REG 13 13 UHCI1_INTR 13 13 DPORT_APP_UHCI1_INTR_MAP_REG + + DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG 14 14 TG_T0_LEVEL_INT 14 14 DPORT_APP_TG_T0_LEVEL_INT_MAP_REG + + DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG 15 DPORT_PRO_INTR_STATUS_REG_0_REG 15 TG_T1_LEVEL_INT 15 DPORT_APP_INTR_STATUS_REG_0_REG 15 DPORT_APP_TG_T1_LEVEL_INT_MAP_REG + DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG TG_WDT_LEVEL_INT DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG + 16 16 16 16 + + DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG 17 17 TG_LACT_LEVEL_INT 17 17 DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG + + DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG 18 18 TG1_T0_LEVEL_INT 18 18 DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG + + DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG 19 19 TG1_T1_LEVEL_INT 19 19 DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG + + 34 DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG 20 20 TG1_WDT_LEVEL_INT 20 20 DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG +ّঌ໓֖ၩ࡮ + DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG 21 21 TG1_LACT_LEVEL_INT 21 21 DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG + + DPORT_PRO_GPIO_INTERRUPT_MAP_REG 22 22 GPIO_INTERRUPT_PRO GPIO_INTERRUPT_APP 22 22 DPORT_APP_GPIO_INTERRUPT_MAP_REG + + DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG 23 23 GPIO_INTERRUPT_PRO_NMI GPIO_INTERRUPT_APP_NMI 23 23 DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG + + DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG 24 24 CPU_INTR_FROM_CPU_0 24 24 DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG + + DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG 25 25 CPU_INTR_FROM_CPU_1 25 25 DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG + + DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG 26 26 CPU_INTR_FROM_CPU_2 26 26 DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG + + DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG 27 27 CPU_INTR_FROM_CPU_3 27 27 DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG + + DPORT_PRO_SPI_INTR_0_MAP_REG 28 28 SPI_INTR_0 28 28 DPORT_APP_SPI_INTR_0_MAP_REG + + DPORT_PRO_SPI_INTR_1_MAP_REG 29 29 SPI_INTR_1 29 29 DPORT_APP_SPI_INTR_1_MAP_REG + + DPORT_PRO_SPI_INTR_2_MAP_REG 30 30 SPI_INTR_2 30 30 DPORT_APP_SPI_INTR_2_MAP_REG + + DPORT_PRO_SPI_INTR_3_MAP_REG 31 31 SPI_INTR_3 31 31 DPORT_APP_SPI_INTR_3_MAP_REG + + DPORT_PRO_I2S0_INT_MAP_REG 0 32 I2S0_INT 32 0 DPORT_APP_I2S0_INT_MAP_REG + + DPORT_PRO_I2S1_INT_MAP_REG 1 33 I2S1_INT 33 1 DPORT_APP_I2S1_INT_MAP_REG + + DPORT_PRO_UART_INTR_MAP_REG 2 34 UART_INTR 34 2 DPORT_APP_UART_INTR_MAP_REG + + DPORT_PRO_UART1_INTR_MAP_REG 3 35 UART1_INTR 35 3 DPORT_APP_UART1_INTR_MAP_REG + + DPORT_PRO_UART2_INTR_MAP_REG 4 36 UART2_INTR 36 4 DPORT_APP_UART2_INTR_MAP_REG + +ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG 5 37 SDIO_HOST_INTERRUPT 37 5 DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG + + DPORT_PRO_EMAC_INT_MAP_REG 6 38 EMAC_INT 38 6 DPORT_APP_EMAC_INT_MAP_REG + + DPORT_PRO_PWM0_INTR_MAP_REG 7 39 PWM0_INTR 39 7 DPORT_APP_PWM0_INTR_MAP_REG + + DPORT_PRO_PWM1_INTR_MAP_REG 8 40 PWM1_INTR 40 8 DPORT_APP_PWM1_INTR_MAP_REG + + Reserved 9 41 Reserved 41 9 Reserved + + Reserved 10 DPORT_PRO_INTR_STATUS_REG_1_REG 42 Reserved 42 DPORT_APP_INTR_STATUS_REG_1_REG 10 Reserved + + DPORT_PRO_LEDC_INT_MAP_REG 11 43 LEDC_INT 43 11 DPORT_APP_LEDC_INT_MAP_REG + + DPORT_PRO_EFUSE_INT_MAP_REG 12 44 EFUSE_INT 44 12 DPORT_APP_EFUSE_INT_MAP_REG + + DPORT_PRO_TWAI_INT_MAP_REG 13 45 TWAI_INT 45 13 DPORT_APP_TWAI_INT_MAP_REG + + DPORT_PRO_RTC_CORE_INTR_MAP_REG 14 46 RTC_CORE_INTR 46 14 DPORT_APP_RTC_CORE_INTR_MAP_REG + + DPORT_PRO_RMT_INTR_MAP_REG 15 47 RMT_INTR 47 15 DPORT_APP_RMT_INTR_MAP_REG + + DPORT_PRO_PCNT_INTR_MAP_REG 16 48 PCNT_INTR 48 16 DPORT_APP_PCNT_INTR_MAP_REG + + DPORT_PRO_I2C_EXT0_INTR_MAP_REG 17 49 I2C_EXT0_INTR 49 17 DPORT_APP_I2C_EXT0_INTR_MAP_REG + + DPORT_PRO_I2C_EXT1_INTR_MAP_REG 18 50 I2C_EXT1_INTR 50 18 DPORT_APP_I2C_EXT1_INTR_MAP_REG + + DPORT_PRO_RSA_INTR_MAP_REG 19 51 RSA_INTR 51 19 DPORT_APP_RSA_INTR_MAP_REG + + DPORT_PRO_SPI1_DMA_INT_MAP_REG 20 52 SPI1_DMA_INT 52 20 DPORT_APP_SPI1_DMA_INT_MAP_REG + ুᶈྐ༏॓࠯ PRO_CPU APP_CPU 2 ᇏ؎इᆔ (INTERRUPT) + + Peripheral Interrupt Status Register No. Peripheral Interrupt Source No. Status Register Peripheral Interrupt + Configuration Register Configuration Register + Bit Name Name Name Bit + DPORT_PRO_SPI2_DMA_INT_MAP_REG DPORT_APP_SPI2_DMA_INT_MAP_REG + DPORT_PRO_SPI3_DMA_INT_MAP_REG 21 53 SPI2_DMA_INT 53 21 DPORT_APP_SPI3_DMA_INT_MAP_REG + SPI3_DMA_INT + DPORT_PRO_WDG_INT_MAP_REG 22 54 54 22 DPORT_APP_WDG_INT_MAP_REG + DPORT_PRO_TIMER_INT1_MAP_REG WDG_INT DPORT_APP_TIMER_INT1_MAP_REG + DPORT_PRO_TIMER_INT2_MAP_REG 23 55 TIMER_INT1 55 23 DPORT_APP_TIMER_INT2_MAP_REG + DPORT_PRO_TG_T0_EDGE_INT_MAP_REG TIMER_INT2 DPORT_APP_TG_T0_EDGE_INT_MAP_REG + DPORT_PRO_TG_T1_EDGE_INT_MAP_REG 24 56 TG_T0_EDGE_INT 56 24 DPORT_APP_TG_T1_EDGE_INT_MAP_REG + DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG TG_T1_EDGE_INT DPORT_APP_TG_WDT_EDGE_INT_MAP_REG + DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG 25 57 TG_WDT_EDGE_INT 57 25 DPORT_APP_TG_LACT_EDGE_INT_MAP_REG + DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG TG_LACT_EDGE_INT DPORT_APP_TG1_T0_EDGE_INT_MAP_REG + DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG 26 DPORT_PRO_INTR_STATUS_REG_1_REG 58 TG1_T0_EDGE_INT 58 DPORT_APP_INTR_STATUS_REG_1_REG 26 DPORT_APP_TG1_T1_EDGE_INT_MAP_REG + DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG TG1_T1_EDGE_INT DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG + DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG 27 59 TG1_WDT_EDGE_INT 59 27 DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG + DPORT_PRO_MMU_IA_INT_MAP_REG TG1_LACT_EDGE_INT DPORT_APP_MMU_IA_INT_MAP_REG + DPORT_PRO_MPU_IA_INT_MAP_REG 28 60 MMU_IA_INT 60 28 DPORT_APP_MPU_IA_INT_MAP_REG + DPORT_PRO_CACHE_IA_INT_MAP_REG MPU_IA_INT DPORT_APP_CACHE_IA_INT_MAP_REG + 29 61 CACHE_IA_INT 61 29 + + 30 62 62 30 + + 31 63 63 31 + + 0 64 64 0 + + 1 65 65 1 + + 2 DPORT_PRO_INTR_STATUS_REG_2_REG 66 66 DPORT_APP_INTR_STATUS_REG_2_REG 2 + + 3 67 67 3 + + 4 68 68 4 + + 35 +ّঌ໓֖ၩ࡮ + +ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + 2 ᇏ؎इᆔ (INTERRUPT) + +2.3.2 CPU ᇏ؎ + +ਆ۱ CPUčPRO_CPU ‫ ބ‬APP_CPUĎ۲Ⴕ 32 ۱ᇏ؎đఃᇏ 26 ۱ູຓ҆ᇏ؎bі 2-2 ਙԛਔૄ۱ CPU ෮Ⴕ֥ +ᇏ؎b + + і 2­2. CPU ᇏ؎ + +щ‫ݼ‬ োљ ᇕো Ⴊ༵ࠩ +0 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +1 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +2 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +3 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +4 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +5 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +6 ଽ҆ᇏ؎ ‫ק‬ൈఖ 0 1 +7 ଽ҆ᇏ؎ ೈࡱ 1 +8 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +9 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +10 ຓ҆ᇏ؎ шခԨ‫ؿ‬ 1 +11 ଽ҆ᇏ؎ ࢳ༅ 3 +12 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +13 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +14 ຓ҆ᇏ؎ NMI NMI +15 ଽ҆ᇏ؎ ‫ק‬ൈఖ 1 3 +16 ଽ҆ᇏ؎ ‫ק‬ൈఖ 2 5 +17 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +18 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 1 +19 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 2 +20 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 2 +21 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 2 +22 ຓ҆ᇏ؎ шခԨ‫ؿ‬ 3 +23 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 3 +24 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 4 +25 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 4 +26 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 5 +27 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 3 +28 ຓ҆ᇏ؎ шခԨ‫ؿ‬ 4 +29 ଽ҆ᇏ؎ ೈࡱ 3 +30 ຓ҆ᇏ؎ шခԨ‫ؿ‬ 4 +31 ຓ҆ᇏ؎ ‫׈‬௜Ԩ‫ؿ‬ 5 + +2.3.3 ‫ٳ‬஥ຓ҆ᇏ؎ჷᇀ CPU ຓ҆ᇏ؎ + +ᄝЧཬࢫᇏğ + + • ࠺‫ ݼ‬Source_X սіଖ۱ຓ҆ᇏ؎ჷb + + • ࠺‫ ݼ‬PRO_X_MAP_REGčࠇ APP_X_MAP_REGĎіൕ PRO_CPUčࠇ APP_CPUĎ֥ଖ۱ຓ҆ᇏ؎஥ᇂ + +ুᶈྐ༏॓࠯ 36 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 2 ᇏ؎इᆔ (INTERRUPT) + + ࠷թఖđ౏Վຓ҆ᇏ؎஥ᇂ࠷թఖაຓ҆ᇏ؎ჷ Source_X ཌྷؓႋbࠧі 2-1 ᇏoPRO_CPUčAPP_CPUĎ + - Peripheral Interrupt Configuration Registerp၂ਙᇏაoPeripheral Interrupt Source - Namep၂ਙᇏ֥ଖ + ۱ຓ҆ᇏ؎ჷԩႿ๝၂ྛ֥࠷թఖb + + • ࠺‫ ݼ‬Interrupt_P іൕ CPU ᇏ؎྽‫ ູݼ‬Num_P ֥ຓ҆ᇏ؎đNum_P ֥౼ᆴٓຶູ 0 ~ 5a8 ~ 10a12 ~ + 14a17 ~ 28a30 ~ 31b + + • ࠺‫ ݼ‬Interrupt_I іൕ CPU ᇏ؎྽‫ ູݼ‬Num_I ֥ଽ҆ᇏ؎đNum_I ֥౼ᆴٓຶູ 6a7a11a15a16a29b + +ࢹᇹၛഈඌეđॖၛᆃဢ૭ඍᇏ؎इᆔ॥ᇅఖҠቔğ + + • ࡼຓ҆ᇏ؎ჷ Source_X ‫ٳ‬஥֞ CPUčPRO_CPU ࠇ APP_CPUĎ + ࡼ࠷թఖ PRO_X_MAP_REGčAPP_X_MAP_REGĎ஥Ӯ Num_PbNum_P ॖၛ౼಩ၩ CPU ຓ҆ᇏ؎ᆴb + CPU ᇏ؎ॖၛФ‫؟‬۱ຓഡ‫܋‬ཚč࡮༯໓Ďb + + • ܱо CPUčPRO_CPU ࠇ APP_CPUĎຓ҆ᇏ؎ჷ Source_X + ࡼ࠷թఖ PRO_X_MAP_REGčAPP_X_MAP_REGĎ஥Ӯ಩ၩ Num_IbႮႿ಩‫ޅ‬Ф஥Ӯ Num_I ֥ᇏ؎‫׻‬ી + Ⴕ৵ࢤ֞ 2 ۱ CPU ഈđ࿊ᄴห‫ק‬ଽ҆ᇏ؎ᆴ҂߶ᄯӮ႕ཙb + + • ࡼ‫؟‬۱ຓ҆ᇏ؎ჷ Source_Xn ORed ‫ٳ‬஥֞ PRO_CPUčAPP_CPUĎ֥ຓ҆ᇏ؎ + ࡼ۲۱࠷թఖ PRO_Xn_MAP_REG (APP_Xn_MAP_REG) ‫׻‬஥Ӯ๝ဢ֥ Num_Pbᆃུຓഡᇏ؎‫߶׻‬Ԩ‫ؿ‬ + CPU Interrupt_Pb + +2.3.4 ௠з CPU ֥ NMI ো྘ᇏ؎ + +ᇏ؎इᆔି‫ܔ‬۴ऌྐ‫ ݼ‬PRO_CPU NMI Interrupt Maskčࠇ APP_CPU NMI Interrupt MaskĎᄠൈ௠з෮ႵФ‫ٳ‬஥ +֞ PRO_CPUčࠇ APP_CPUĎ֥ຓ҆ᇏ؎ჷ֥ NMI ᇏ؎bྐ‫ ݼ‬PRO_CPU NMI Interrupt Mask ‫ ބ‬APP_CPU +NMI Interrupt Mask ‫ٳ‬љটሱຓഡ PID Controllerb + +2.3.5 Ұ࿘ຓ҆ᇏ؎ჷ֒భ֥ᇏ؎ሑ෿ + +‫࠷؀‬թఖ PRO_INTR_STATUS_REG_nčAPP_INTR_STATUS_REG_nĎᇏ֥ห‫ ק‬Bit ᆴࣼॖၛࠆᆩຓ҆ᇏ؎ჷ֒ +భ֥ᇏ؎ሑ෿b࠷թఖ PRO_INTR_STATUS_REG_nčAPP_INTR_STATUS_REG_nĎაຓ҆ᇏ؎ჷ֥ؓႋܱ༢ +ೂі 2-1 ෮ൕb + +ুᶈྐ༏॓࠯ 37 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 3 ‫ބ໊گ‬ൈᇒ + +3 ‫ބ໊گ‬ൈᇒ + +3.1 System ‫໊گ‬ + +3.1.1 ‫ۀ‬ඍ + +༢๤ิ‫܂‬೘ᇕࠩљ֥‫໊گ‬ٚൔđ‫ٳ‬љ൞ CPU ‫໊گ‬đଽ‫໊گނ‬đ༢๤‫໊گ‬b +෮Ⴕ֥‫׻໊گ‬҂߶႕ཙ MEM ᇏ֥ඔऌb๭ 3-1 ᅚൕਔᆜ۱ሰ༢๤֥ࢲ‫ܒ‬ၛࠣૄᇕ‫໊گ‬ٚൔğ + + ๭ 3­1. ༢๤‫໊گ‬ + +• CPU ‫໊گ‬ğᆺ‫ ໊گ‬CPU ֥෮Ⴕ࠷թఖb +• ଽ‫໊گނ‬ğԢਔ RTCđ߶Ϝᆜ۱ digital ֥࠷թఖಆ҆‫໊گ‬đЇও CPUa෮Ⴕຓഡ‫ބ‬ඔሳ GPIOb +• ༢๤‫໊گ‬ğ߶‫໊گ‬ᆜ۱ྉோ෮Ⴕ֥࠷թఖđЇও RTCb + +3.1.2 ‫໊گ‬ჷ + +ն‫؟‬ඔ౦ঃ༯đAPP_CPU ‫ ބ‬PRO_CPU ࡼФ৫ख़‫໊گ‬đႵུ‫໊گ‬ჷᆺି‫໊گ‬ఃᇏ၂۱bAPP_CPU ‫ބ‬ +PRO_CPU ֥‫໊گ‬ჰၹ္۲ሱ҂๝ğ֒༢๤‫໊گ‬ఏটᆭުđPRO_CPU ॖၛ๙‫؀ݖ‬౼࠷թఖ +RTC_CNTL_RESET_CAUSE_PROCPU টࠆ౼‫໊گ‬ჷđAPP_CPU ᄵॖၛ๙‫؀ݖ‬౼࠷թఖ +RTC_CNTL_RESET_CAUSE_APPCPU টࠆ౼‫໊گ‬ჷb + +і 3-1 ਙԛਔՖᆃུ࠷թఖᇏॖି‫؀‬ԛ֥‫໊گ‬ჷb + + і 3­1. PRO_CPU ‫ ބ‬APP_CPU ‫໊گ‬ჷ + +PRO APP ჷ ‫໊گ‬ٚൔ ᇿ൤ +0x01 0x01 ྉோഈ‫໊گ׈‬ ༢๤‫໊گ‬ - +0x10 0x10 RWDT ༢๤‫໊گ‬ ༢๤‫໊گ‬ བྷ࡮ WDT ᅣࢫ +0x0F 0x0F ఴ࿢‫໊گ‬ ༢๤‫໊گ‬ བྷ࡮ Power Management ᅣࢫ +0x03 0x03 ೈࡱ༢๤‫໊گ‬ ଽ‫໊گނ‬ ஥ᇂ RTC_CNTL_SW_SYS_RST ࠷թఖ +0x05 0x05 Deep Sleep Reset ଽ‫໊گނ‬ བྷ࡮ Power Management ᅣࢫ +0x07 0x07 MWDT0 ಆअ‫໊گ‬ ଽ‫໊گނ‬ བྷ࡮ WDT ᅣࢫ + +ুᶈྐ༏॓࠯ 38 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 3 ‫ބ໊گ‬ൈᇒ + +PRO APP ჷ ‫໊گ‬ٚൔ ᇿ൤ +0x08 0x08 MWDT1 ಆअ‫໊گ‬ ଽ‫໊گނ‬ +0x09 0x09 RWDT ଽ‫໊گނ‬ ଽ‫໊گނ‬ བྷ࡮ WDT ᅣࢫ +0x0B - MWDT0 CPU ‫໊گ‬ CPU ‫໊گ‬ +0x0C - ೈࡱ CPU ‫໊گ‬ CPU ‫໊گ‬ བྷ࡮ WDT ᅣࢫ +- 0x0B MWDT1 CPU ‫໊گ‬ CPU ‫໊گ‬ +- 0x0C ೈࡱ CPU ‫໊گ‬ CPU ‫໊گ‬ བྷ࡮ WDT ᅣࢫ +0x0D 0x0D RWDT CPU ‫໊گ‬ CPU ‫໊گ‬ + ஥ᇂ RTC_CNTL_SW_APPCPU_RST ࠷թఖ +- 0xE PRO CPU ‫໊گ‬ CPU ‫໊گ‬ + བྷ࡮ WDT ᅣࢫ + + ஥ᇂ RTC_CNTL_SW_APPCPU_RST ࠷թఖ + + བྷ࡮ WDT ᅣࢫ + + іૼ PRO CPU ି‫ܔ‬๙‫ݖ‬஥ᇂ + + DPORT_APPCPU_RESETTING ࠷ թ ఖ ֆ ‫໊ گ ׿‬ + + APP CPU + +3.2 ༢๤ൈᇒ + +3.2.1 ‫ۀ‬ඍ + +ESP32 ิ‫܂‬ਔ‫؟‬ᇕ҂๝௔ੱ֥ൈᇒ࿊ᄴđॖၛਲࠃ֥஥ᇂ CPUđຓഡđၛࠣ RTC ֥‫۽‬ቔ௔ੱđၛડቀ҂๝‫ۿ‬ +‫ླିྟބݻ‬౰b༯๭ 3-2 ູ༢๤ൈᇒࢲ‫ܒ‬b + +5&B)$67B&/. + + 5&B6/2:B&/. 57&B6/2:B&/. +5&B)$67B',9B&/. 57&B)$67B&/. + + ;7$/B',9B&/. ๭ 3­2. ༢๤ൈᇒ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + +ুᶈྐ༏॓࠯ 39 + ّঌ໓֖ၩ࡮ + 3 ‫ބ໊گ‬ൈᇒ + +3.2.2 ൈᇒჷ + +ESP32 ֥ൈᇒჷ‫ٳ‬љটሱຓ҆ࣖᆒaଽ҆ PLL ࠇᆑ֕‫׈‬ਫ਼bऎֹุඪđᆃུൈᇒჷູğ + • ॹ෎ൈᇒ + – PLL_CLKđ320 MHz ࠇ 480 MHz ଽ҆ PLL ൈᇒ + – XTL_CLKđ2 ~ 40 MHz ຓ҆ࣖᆒൈᇒ + • ֮‫ݻۿ‬ત෎ൈᇒ + – XTL32K_CLKđ32 KHz ຓ҆ࣖᆒൈᇒ + – FOSC_CLKđ8 MHz ଽ҆ൈᇒđ௔ੱॖ‫ט‬ + – RC_FAST_DIV_CLK Ⴎ FOSC_CLK ࣜ 256 ‫ٳ‬௔෮֤đ௔ੱູčFOSC_CLK/256Ďb֒ FOSC_CLK ֥ + Ԛ൓௔ੱູ 8 MHz ൈđ‫ھ‬ൈᇒၛ 31.250 KHz ֥௔ੱᄎྛb + – RC_SLOW_CLKđ150 KHz ଽ֮҆‫ݻۿ‬ൈᇒđ௔ੱॖ‫ט‬ + • ၻ௔ൈᇒ + – APLL_CLKđ16 ~ 128 MHz ଽ҆ Audio PLL ൈᇒ + +3.2.3 CPU ൈᇒ + +ೂ๭ 3-2 ෮ൕđCPU_CLK ູ CPU ᇶൈᇒđ෱ᄝིۚ‫۽‬ቔଆൔ༯đᇶ௔ॖၛղ֞ 240 MHzb๝ൈđCPU ି‫ܔ‬ᄝ +ӑ֮௔༯‫۽‬ቔđၛࡨഒ‫ݻۿ‬b + +CPU_CLK Ⴎ RTC_CNTL_SOC_CLK_SEL ট࿊ᄴൈᇒჷđᄍྸ࿊ᄴ PLL_CLKđAPLL_CLKđFOSC_CLKđ +XTL_CLK ቔູ CPU_CLK ֥ൈᇒჷbऎุ౨ҕॉі 3-2 ‫ބ‬і 3-3b + + і 3­2. CPU_CLK ჷ + + RTC_CNTL_SOC_CLK_SEL ᆴ ൈᇒჷ + 0 XTL_CLK + 1 PLL_CLK + 2 FOSC_CLK + 3 APLL_CLK + + і 3­3. CPU_CLK ჷ + +ൈᇒჷ *SEL_0 *SEL_1 CPU ൈᇒ +XTL_CLK 0 - CPU_CLK = XTL_CLK / (APB_CTRL_PRE_DIV_CNT+1) +PLL_CLK (320 MHz) 1 0 APB_CTL_PRE_DIV_CNT ଏಪᆴູ 0đٓຶ 0 ~ 1023 +PLL_CLK (320 MHz) 1 1 CPU_CLK = PLL_CLK / 4 +PLL_CLK (480 MHz) 1 2 CPU_CLK ௔ੱູ 80 MHz +FOSC_CLK 2 - CPU_CLK = PLL_CLK / 2 + CPU_CLK ௔ੱູ 160 MHz + CPU_CLK = PLL_CLK / 2 + CPU_CLK ௔ੱູ 240 MHz + CPU_CLK = FOSC_CLK / (APB_CTRL_PRE_DIV_CNT+1) + APB_CTL_PRE_DIV_CNT ଏಪᆴູ 0đٓຶ 0 ~ 1023 + +ুᶈྐ༏॓࠯ 40 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 3 ‫ބ໊گ‬ൈᇒ + +APLL_CLK 3 0 CPU_CLK = APLL_CLK / 4 +APLL_CLK + 3 1 CPU_CLK = APLL_CLK / 2 + +*SEL_0ğ࠷թఖ RTC_CNTL_SOC_CLK_SEL ֥ᆴ +*SEL_1ğ࠷թఖ CPU_CPUPERIOD_SEL ֥ᆴ + +3.2.4 ຓഡൈᇒ + +ຓഡ෮ླေ֥ൈᇒЇও APB_CLKđREF_TICKđLEDC_SCLKđAPLL_CLK ‫ ބ‬PLL_D2_CLKb +༯і 3-4 ູࢤೆ۲۱ຓഡ֥ൈᇒb + + і 3­4. ຓഡൈᇒႨ‫م‬ + +ຓഡ APB_CLK REF_TICK LEDC_SCLK APLL_CLK PLL_D2_CLK +EMAC Y N N Y N +TIMG Y N N N N +I2S Y N N Y Y +UART Y Y N N N +RMT Y Y N N N +LED PWM Y Y Y N N +PWM Y N N N N +I2C Y N N N N +SPI Y N N N N +PCNT Y N N N N +Efuse Controller Y N N N N +SDIO Slave Y N N N N +SDMMC Y N N N N + +3.2.4.1 APB_CLK ჷ + +ೂі 3-5 ෮ൕđAPB_CLK Ⴎ CPU_CLK Ӂളđ‫ٳ‬௔༢ඔႮ CPU_CLK ჷथ‫ק‬ğ + + і 3­5. APB_CLK ჷ + + CPU_CLK ჷ APB_CLK + PLL_CLK 80 MHz + APLL_CLK CPU_CLK / 2 + XTAL_CLK CPU_CLK + FOSC_CLK CPU_CLK + +3.2.4.2 REF_TICK ჷ + +REF_TICK Ⴎ APB_CLK ‫ٳ‬௔Ӂളđ‫ٳ‬௔ᆴႮ APB_CLK ჷ‫ ބ‬CPU_CLK ჷ‫܋‬๝थ‫ק‬bႨ޼๙‫ݖ‬஥ᇂ‫ކ‬৘֥‫ٳ‬௔ +༢ඔđॖၛЌᆣ REF_TICK ᄝ APB_CLK ్ߐൈົӻ௔ੱ҂эb࠷թఖ஥ᇂೂі 3-6 ෮ൕğ + + і 3­6. REF_TICK ჷ + + CPU_CLK & APB_CLK ჷ ൈᇒ‫ٳ‬௔࠷թఖ + + PLL_CLK APB_CTRL_PLL_TICK_NUM + +ুᶈྐ༏॓࠯ 41 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 3 ‫ބ໊گ‬ൈᇒ + + XTAL_CLK APB_CTRL_XTAL_TICK_NUM + APLL_CLK APB_CTRL_APLL_TICK_NUM + FOSC_CLK APB_CTRL_CK8M_TICK_NUM + +3.2.4.3 LEDC_SCLK ჷ + +LEDC_SCLK ൈᇒჷႮ࠷թఖ LEDC_APB_CLK_SEL थ‫ק‬đೂі 3-7 ෮ൕb + + і 3­7. LEDC_SCLK ჷ + + LEDC_APB_CLK_SEL ᆴ LEDC_SCLK ჷ + 0 FOSC_CLK + 1 APB_CLK + +3.2.4.4 APLL_SCLK ჷ + +APLL_CLK টሱଽ҆ PLL_CLKđఃൻԛ௔ੱ๙‫ݖ‬൐Ⴈ APLL ஥ᇂ࠷թఖট஥ᇂb + +3.2.4.5 PLL_D2_CLK ჷ + +PLL_D2_CLK ൞ PLL_CLK ֥‫ٳؽ‬௔ൈᇒb + +3.2.4.6 ൈᇒჷᇿၩ൙ཛ + +ն‫؟‬ඔຓഡ၂Ϯᄝ࿊ᄴ PLL_CLK ൈᇒჷ֥౦ঃ༯‫۽‬ቔb೏௔ੱ‫ؿ‬ളэ߄đຓഡླေ๙‫ڿྩݖ‬஥ᇂҌିၛ๝ဢ +֥௔ੱ‫۽‬ቔbࢤೆ REF_TICK ֥ຓഡᄍྸᄝ్ߐൈᇒჷ֥౦ঃ༯đ҂ྩ‫ڿ‬ຓഡ஥ᇂࠧॖ‫۽‬ቔbབྷ౦౨ҕॉі +3-4b +LED PWM ଆॶିࡼ FOSC_CLK ቔູൈᇒჷ൐Ⴈđࠧᄝ APB_CLK ܱо֥ൈީđLED PWM ္ॖ‫۽‬ቔbߐ‫ط‬࿽ +ᆭđ֒༢๤ԩႿ֮‫ݻۿ‬ଆൔൈčҕॉᅣࢫ ֮‫ܵݻۿ‬৘Ďđ෮Ⴕᆞӈຓഡ‫ࡼ׻‬๔ᆸ‫۽‬ቔčAPB_CLK ܱоĎđ֌൞ +LED PWM ಯಖॖၛ๙‫ ݖ‬FOSC_CLK টᆞӈ‫۽‬ቔb + +3.2.5 Wi­Fi BT ൈᇒ + +Wi-Fi ‫ ބ‬BT сྶᄝ APB_CLK ൈᇒჷ࿊ᄴ PLL_CLK ༯Ҍି‫۽‬ቔbᆺႵ֒ Wi-Fi ‫ ބ‬BT ๝ൈࣉೆ֮‫ݻۿ‬ଆൔൈđ +Ҍିᄠൈܱо PLL_CLKb +LOW_POWER_CLK ᄍྸ࿊ᄴ RC_SLOW_CLKaRTC_SLOW_CLKaFOSC_CLK ࠇ XTL_CLKđႨႿ Wi-Fi ‫ބ‬ +BT ֥֮‫ݻۿ‬ଆൔb + +3.2.6 RTC ൈᇒ + +RTC_SLOW_CLK ‫ ބ‬RTC_FAST_CLK ֥ൈᇒჷູ֮௔ൈᇒbRTC ଆॶି‫ܔ‬ᄝն‫؟‬ඔൈᇒჷܱо֥ሑ෿༯‫۽‬ +ቔb +RTC_SLOW_CLK ᄍྸ࿊ᄴ RC_SLOW_CLKđXTL32K_CLK ࠇ RC_FAST_DIV_CLKđႨႿ౺‫ ׮‬Power +Management ଆॶb +RTC_FAST_CLK ᄍྸ࿊ᄴ XTL_CLK ֥‫ٳ‬௔ൈᇒࠇ FOSC_CLKđႨႿ౺‫ ׮‬On-chip Sensor ଆॶb + +ুᶈྐ༏॓࠯ 42 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 3 ‫ބ໊گ‬ൈᇒ + +3.2.7 ၻ௔ PLL + +ၻ௔ႋႨ‫ބ‬ః෰ؓႿඔऌԮൻൈིྟေ౰‫֥ۚޓ‬ႋႨ‫ླ׻‬ေۚ؇ॖ஥ᇂa֮‫׮׵‬ѩ౏ࣚಒ֥ൈᇒჷbটሱ༢๤ +ൈᇒ֥ൈᇒჷॖି߶ེջ‫׮׵‬đѩ౏҂ᆦӻۚࣚ؇֥ൈᇒ௔ੱ஥ᇂb + +ູਔ๙‫ࠢݖ‬Ӯ֥ࣚૡൈᇒჷটቋնཋ؇ֹࢆ֮༢๤ӮЧđESP32 ࠢӮਔၻ௔ PLLbAudio PLL ‫܄‬ൔೂ༯ğ + +f = out fxtal (sdm2+ sdm1 + sdm0 +4) + 28 216 + + 2(odiv+2) + +ఃᇏđ + +• fxtalğࣖᆒ௔ੱđ๙ӈູ 40 MHz +• sdm0ğॖ஥ҕඔ 0 ~ 255 + +• sdm1ğॖ஥ҕඔ 0 ~ 255 + +• sdm2ğॖ஥ҕඔ 0 ~ 63 + +• odivğॖ஥ҕඔ 0 ~ 31 + +• ‫܄‬ൔ֥‫ٳ‬ሰ௔ੱ‫۽‬ቔٓຶᄝ 350 MHz ~ 500 MHz + +350M Hz < fxtal(sdm2 + sdm1 + sdm0 + 4) < 500M Hz + 28 216 + +ᇿၩğsdm1 ‫ ބ‬sdm0 ᄝ ESP32 ֥ revision0 ϱЧᇏ҂ᆦӻb۷‫ܱ؟‬Ⴟ ESP32 ϱЧ֥ྐ༏đॖᄝ uESP32 Bug +૭ඍࠣࢳथٚ‫م‬vᇏҰुb + +Audio PLL ॖ๙࠷թఖ RTC_CNTL_PLLA_FORCE_PU ఼ྛյषđࠇᆀ๙‫࠷ݖ‬թఖ +RTC_CNTL_PLLA_FORCE_PD ఼ྛܱоđܱоႪ༵ࠩնႿյषႪ༵ࠩb֒ RTC_CNTL_PLLA_FORCE_PU ‫ބ‬ +RTC_CNTL_PLLA_FORCE_PD ๝ൈູ 0 ֥ൈީđPLL ߶۵ෛ༢๤ሑ෿đ֒༢๤ࣉೆඤ૤ଆൔ֥ൈީሱ‫ܱ׮‬оđ +༢๤Фߒྜ֥ൈީሱ‫׮‬յषb + +ুᶈྐ༏॓࠯ 43 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +4.1 ‫ۀ‬ඍ + +ESP32 ྉோႵ 34 ۱໾৘ GPIO padbૄ۱ pad ‫׻‬ॖႨቔ၂۱๙Ⴈ IOđࠇ৵ࢤ၂۱ଽ֥҆ຓഡྐ‫ݼ‬bIO_MUXa +RTC IO_MUX ‫ ބ‬GPIO ࢌߐइᆔႨႿࡼྐ‫ݼ‬ՖຓഡԮൻᇀ GPIO padbᆃུଆॶ‫܋‬๝ቆӮਔྉோ֥ IO ॥ +ᇅb +ᇿၩğᆃ 34 ۱໾৘ GPIO pad ֥྽ਙ‫ູݼ‬ğ0­19, 21­23, 25­27, 32­39bఃᇏ GPIO 34­39 ࣇႨቔൻೆܵ࢖đ +ః෰֥࠻ॖၛቔູൻೆႻॖၛቔູൻԛܵ࢖b + +Чᅣ૭ඍਔඔሳ padč॥ᇅྐ‫ݼ‬ğFUN_SELaIEaOEaWPUaWDU ֩Ď‫ ބ‬162 ۱ຓഡൻೆၛࠣ 176 ۱ຓഡൻ +ԛྐ‫ݼ‬č॥ᇅྐ‫ݼ‬ğSIG_IN_SELaSIG_OUT_SELaIEaOE ֩Ď‫ॹބ‬෎ຓഡൻೆĔൻԛྐ‫ݼ‬č॥ᇅྐ‫ݼ‬ğIEa +OE ֩Ďၛࠣ RTC IO_MUX ᆭࡗ֥ྐ‫ݼ‬࿊ᄴ‫ބ‬৵ࢤܱ༢b + + ๭ 4­1. IO_MUXaRTC IO_MUX ‫ ބ‬GPIO ࢌߐइᆔࢲ‫ॿܒ‬๭ + +1. IO_MUX ᇏૄ۱ GPIO pad Ⴕ၂ቆ࠷թఖbૄ۱ pad ॖၛ஥ᇂӮ GPIO ‫ିۿ‬č৵ࢤ GPIO ࢌߐइᆔĎࠇᆀ + ᆰ৵‫ିۿ‬čகਫ਼ GPIO ࢌߐइᆔđॹ෎ྐ‫ݼ‬ೂၛ෾ຩaSDIOaSPIaJTAGaUART ֩߶கਫ਼ GPIO ࢌߐइ + ᆔၛൌགྷ۷‫֥ۚݺ‬௔ඔሳหྟb෮ၛۚ෎ྐ‫߶ݼ‬ᆰࢤ๙‫ ݖ‬IO_MUX ൻೆ‫ބ‬ൻԛbĎ + ᅣࢫ 4.10 ਙԛਔ෮Ⴕ GPIO pad ֥ IO_MUX ‫ିۿ‬b + +2. GPIO ࢌߐइᆔ൞ຓഡൻೆ‫ބ‬ൻԛྐ‫ ބݼ‬pad ᆭࡗ֥ಆࢌߐइᆔb + • ྉோൻೆٚཟğ162 ۱ຓഡൻೆྐ‫׻ݼ‬ॖၛ࿊ᄴ಩ၩ၂۱ GPIO pad ֥ൻೆྐ‫ݼ‬b + • ྉோൻԛٚཟğૄ۱ GPIO pad ֥ൻԛྐ‫ݼ‬ॖটሱ 176 ۱ຓഡൻԛྐ‫ݼ‬ᇏ֥಩ၩ၂۱b + + ᅣࢫ 4.9 ਙԛਔ GPIO ࢌߐइᆔ֥ຓഡྐ‫ݼ‬b +3. RTC IO_MUX ႨႿ॥ᇅ GPIO pad ֥֮‫ބݻۿ‬ଆ୅‫ିۿ‬bᆺႵ҆‫ ٳ‬GPIO pad ऎႵᆃུ‫ିۿ‬b + + ᅣࢫ 4.11 ਙԛਔ RTC IO_MUX ‫ିۿ‬b + +ুᶈྐ༏॓࠯ 44 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +4.2 ๙‫ ݖ‬GPIO ࢌߐइᆔ֥ຓഡൻೆ + +4.2.1 ‫ۀ‬ඍ + +ູൌགྷ๙‫ ݖ‬GPIO ࢌߐइᆔࢤ൬ຓഡൻೆྐ‫ݼ‬đླေ஥ᇂ GPIO ࢌߐइᆔՖ 34 ۱ GPIOč0-19đ21-23đ25-27đ +32-39Ďᇏࠆ౼ຓഡൻೆྐ‫֥ݼ‬෬ႄ‫ݼ‬č0-18đ23-36đ39-58đ61-90đ95-124đ140-155đ164-181đ190-195đ +198-206Ďb + +ൻೆྐ‫ݼ‬๙‫ ݖ‬IO_MUX Ֆ GPIO pad ᇏ‫؀‬౼bIO_MUX сྶഡᇂཌྷႋ pad ູ GPIO ‫ିۿ‬bᆃဢ GPIO pad ֥ൻೆ +ྐ‫ࣼݼ‬ॖࣉೆ GPIO ࢌߐइᆔಖު๙‫ ݖ‬GPIO ࢌߐइᆔࣉೆ࿊ᄴ֥ຓഡൻೆb + +4.2.2 ‫ିۿ‬૭ඍ + +๭ 4-2 ູ๙‫ ݖ‬GPIO ࢌߐइᆔ֥ຓഡൻೆ֥ൕၩ๭b + + ๭ 4­2. ๙‫ ݖ‬IO_MUXaGPIO ࢌߐइᆔ֥ຓഡൻೆ + +Ϝଖ۱ຓഡྐ‫ ݼ‬Y Ͼ‫֞ק‬ଖ۱ GPIO pad X ֥஥ᇂ‫ݖ‬ӱູğ + 1. ᄝ GPIO ࢌߐइᆔᇏ஥ᇂຓഡྐ‫ ݼ‬Y ֥ GPIO_FUNCy_IN_SEL_CFG ࠷թఖğ + • ᇂ໊ GPIO_SIGy_IN_SEL ࿊ᄴ๙‫ ݖ‬GPIO ࢌߐइᆔࢤ൬ຓ҆ൻೆྐ‫ݼ‬Ġ + • ഡᇂ GPIO_FUNCy_IN_SEL ሳ‫ູ؍‬ေ‫؀‬౼֥ GPIO pad X ֥ᆴb + 2. ᄝ GPIO ࢌߐइᆔᇏ஥ᇂ GPIO pad X ֥ GPIO_FUNCx_OUT_SEL_CFG ࠷թఖaౢਬ + GPIO_ENABLE_DATA[x] ሳ‫؍‬ğ + • ေ఼ᇅܵ࢖֥ൻԛሑ෿൓ᇔႮ GPIO_ENABLE_DATA[x] ሳ‫؍‬थ‫ק‬đᄵࡼ + GPIO_FUNCx_OUT_SEL_CFG ࠷թఖ֥ GPIO_FUNCx_OEN_SEL ሳ‫໊؍‬ᇂູ 1b + • GPIO_ENABLE_DATA[x] ሳ‫؍‬ᄝ GPIO_ENABLE_REG (GPIOs 0-31) ࠇ GPIO_ENABLE1_REG (GPIOs + 32-39) ᇏđౢਬՎ໊ॖၛܱо GPIO pad ֥ൻԛb + + 3. ஥ᇂ IO_MUX ࠷թఖট࿊ᄴ GPIO ࢌߐइᆔb஥ᇂ GPIO pad X ֥ IO_MUX_x_REG ֥‫ݖ‬ӱೂ༯ğ + • ഡᇂ‫ିۿ‬ሳ‫( ؍‬MCU_SEL) ູ GPIO X ֥ IO_MUX ‫ିۿ‬č෮Ⴕܵ࢖֥ Function 2đඔᆴູ 2Ďb + • ᇂ໊ FUN_IE ൐ିൻೆb + +ুᶈྐ༏॓࠯ 45 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + • ᇂ໊ࠇౢਬ FUN_WPU ‫ ބ‬FUN_WPD ໊đ൐ିࠇܱоଽ҆ഈঘ/༯ঘ‫׈‬ቅఖb +ඪૼğ + + • ๝၂۱ൻೆ pad ഈॖၛ๝ൈϾ‫؟ק‬۱ଽ҆ input_signalsb + • ᇂ໊ GPIO_FUNCy_IN_INV_SEL ॖၛϜൻೆ֥ྐ‫ݼ‬౼ّb + • ໭ླࡼൻೆྐ‫ݼ‬Ͼ‫֞ק‬၂۱ pad ္ॖၛ൐ຓഡ‫؀‬౼‫׈ۚޚࠇ֮ޚ‬௜֥ൻೆᆴbൌགྷٚൔູ࿊ᄴห‫֥ק‬ + + GPIO_FUNCy_IN_SEL ൻೆᆴ‫ط‬҂൞၂۱ GPIO ྽‫ݼ‬ğ + – ֒ GPIO_FUNCy_IN_SEL ൞ 0x30 ൈđinput_signal_x ൓ᇔູ 0b + – ֒ GPIO_FUNCy_IN_SEL ൞ 0x38 ൈđinput_signal_x ൓ᇔູ 1b + +২ೂđေϜ RMT ຓഡ๙֡ 0 ֥ൻೆྐ‫ ݼ‬RMT_SIG_IN0_IDXčྐ‫ݼ‬෬ႄ‫ ݼ‬83ĎϾ‫ ֞ק‬GPIO15đ౨οᅶၛ༯҄ +ᇧҠቔč౨ᇿၩ GPIO15 ္ࢡቓ MTDO ܵ࢖Ďğ + + 1. ࡼ GPIO_FUNC83_IN_SEL_CFG ࠷թఖ֥ GPIO_FUNC83_IN_SEL ሳ‫؍‬ഡᇂູ 15b + 2. ၹູՎྐ‫ݼ‬൞Ղൻೆྐ‫ݼ‬đᇂ໊ GPIO_FUNC15_OUT_SEL_CFG_REG ࠷թఖᇏ֥ + + GPIO_FUNC15_OEN_SEL ໊b + 3. ౢਬ GPIO_ENABLE_REG ࠷թఖ֥ bit 15čGPIO_ENABLE_DATA[15] ሳ‫؍‬Ďb + 4. ஥ᇂ IO_MUX_GPIO15 ࠷թఖ֥ MCU_SEL ሳ‫ ູ؍‬2 (GPIO function)đ๝ൈᇂ໊ FUN_IEč൐ିൻೆଆൔĎb + +4.2.3 ࡥֆ GPIO ൻೆ + +GPIO_IN_REG/GPIO_IN1_REG ࠷թఖթԥሢૄ၂۱ GPIO pad ֥ൻೆᆴb +಩ၩ GPIO pin ֥ൻೆᆴ‫׻‬ॖၛෛൈ‫؀‬౼‫ط‬໭ླູଖ၂۱ຓഡྐ‫ݼ‬஥ᇂ GPIO ࢌߐइᆔb֌൞ླေູ pad X ֥ +IO_MUX_x_REG ࠷թఖ஥ᇂ FUN_IE ໊ၛ൐ିൻೆđೂᅣࢫ 4.2.2 ෮ඍb + +4.3 ๙‫ ݖ‬GPIO ࢌߐइᆔ֥ຓഡൻԛ + +4.3.1 ‫ۀ‬ඍ + +ູൌགྷ๙‫ ݖ‬GPIO ࢌߐइᆔൻԛຓഡྐ‫ݼ‬đླေ஥ᇂ GPIO ࢌߐइᆔࡼൻԛ෬ႄ‫ ູݼ‬0-18đ23-37đ61-121đ +140-215đ224-228 ֥ຓഡྐ‫ݼ‬ൻԛ֞ 28 ۱ GPIO (0-19, 21-23, 25-27, 32-33)b +ൻԛྐ‫ݼ‬Ֆຓഡൻԛ֞ GPIO ࢌߐइᆔđಖު֞ղ IO_MUXbIO_MUX сྶഡᇂཌྷႋ pad ູ GPIO ‫ିۿ‬bᆃဢൻ +ԛ GPIO ྐ‫ିࣼݼ‬৵ࢤ֞ཌྷႋ padb + + ඪૼğ + ൻԛ෬ႄ‫ ູݼ‬224-228 ֥ຓഡྐ‫ݼ‬đॖ஥ᇂູՖ၂۱ GPIO ܵ࢖ൻೆުđᆰࢤႮਸ਼၂۱ GPIO ܵ࢖ൻԛb + +4.3.2 ‫ିۿ‬૭ඍ + +๭ 4-3 ෮ൕູ 176 ۱ൻԛྐ‫ݼ‬ᇏ֥ଖ၂۱ྐ‫ݼ‬๙‫ ݖ‬GPIO ࢌߐइᆔ֞ղ IO_MUX ಖު৵ࢤ֞ଖ۱ padb + +ুᶈྐ༏॓࠯ 46 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + In GPIO matrix In IO MUX + + GPIO_FUNCx_OUT_SEL + + signal0_out 0 MCU_SEL + + signal1_out 1 + + signal2_out 2 + + signal3_out 3 + + GPIO X out 0 (FUNC) I/O Pad x + 1 (FUNC) + 2 (GPIO) + + 228 GPIOx_out + + signal228_out + + FUN_OE = 1 + +GPIO_OUT_DATA bit x 256 (0x100) + + 256sdfsdfasdfgas + + ๭ 4­3. ๙‫ ݖ‬GPIO ࢌߐइᆔൻԛྐ‫ݼ‬ + +ൻԛຓഡྐ‫ ݼ‬Y ֞ଖ၂ GPIO pad X ֥҄ᇧູğ + 1. ᄝ GPIO ࢌߐइᆔ৚஥ᇂ GPIO X ֥ GPIO_FUNCx_OUT_SEL_CFG ࠷թఖ‫ ބ‬GPIO_ENABLE_DATA[x] ሳ + ‫؍‬ğ + + • ഡᇂ GPIO_FUNCx_OUT_SEL_CFG ࠷թఖ֥ GPIO_FUNCx_OUT_SEL ሳ‫ູ؍‬ຓഡൻԛྐ‫ ݼ‬Y ֥෬ + ႄ‫( ݼ‬Y)b + + • ေࡼྐ‫఼ݼ‬ᇅ൐ିູൻԛଆൔđࡼ GPIO pad X ֥ GPIO_FUNCx_OUT_SEL_CFG ࠷թఖ֥ + GPIO_FUNCx_OEN_SEL ᇂ໊đѩ౏ࡼ GPIO_ENABLE_REG ࠷թఖ֥ GPIO_ENABLE_DATA[x] ሳ‫؍‬ + ᇂ໊bࠇᆀđࡼ GPIO_FUNCx_OEN_SEL ౢਬđՎൈൻԛ൐ିྐ‫ݼ‬Ⴎଽ҆આࠠ‫ିۿ‬थ‫ק‬b + + • GPIO_ENABLE_DATA[x] ሳ‫؍‬ᄝ GPIO_ENABLE_REG (GPIOs 0-31) ࠇ GPIO_ENABLE1_REG (GPIOs + 32-39) ᇏđౢਬՎ໊ॖၛܱо GPIO pad ֥ൻԛb + + 2. ေ࿊ᄴၛष੐ٚൔൻԛđॖၛഡᇂ GPIO X ֥ GPIO_PINx ࠷թఖᇏ֥ GPIO_PINx_PAD_DRIVER ໊b + 3. ஥ᇂ IO_MUX ࠷թఖট࿊ᄴ GPIO ࢌߐइᆔb஥ᇂ GPIO pad X ֥ IO_MUX_x_REG ֥‫ݖ‬ӱೂ༯ğ + + • ഡᇂ‫ିۿ‬ሳ‫( ؍‬MCU_SEL) ູ GPIO X ֥ IO_MUX ‫ିۿ‬č෮Ⴕܵ࢖֥ Function 2đඔᆴູ 2Ďb + • ഡᇂ FUN_DRV ሳ‫ູ؍‬ห‫֥ק‬ൻԛ఼؇ᆴ (0-3)đᆴᄀնđൻԛ౺‫ି׮‬৯ᄀ఼b + + • ᄝष੐ଆൔ༯đ๙‫ݖ‬ᇂ໊/ౢਬ FUN_WPU ‫ ބ‬FUN_WPD ൐ିࠇܱоഈঘ/༯ঘ‫׈‬ቅఖb +ඪૼğ + + • ଖ၂۱ຓഡ֥ൻԛྐ‫ݼ‬ॖၛ๝ൈՖ‫؟‬۱ pad ൻԛb + + • ᆺႵ 28 ۱ GPIO ܵ࢖ॖႨႿൻԛྐ‫ݼ‬b + + • ᇂ໊ GPIO_FUNCx_OUT_INV_SEL ॖၛϜൻԛ֥ྐ‫ݼ‬౼ّb + +4.3.3 ࡥֆ GPIO ൻԛ + +GPIO ࢌߐइᆔ္ॖၛႨႿࡥֆ GPIO ൻԛbഡᇂ GPIO_OUT_DATA ࠷թఖᇏଖ၂໊֥ᆴॖၛཿೆؓႋ֥ GPIO +padb + +ুᶈྐ༏॓࠯ 47 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + ູൌགྷଖ၂ pad ֥ GPIO ൻԛđഡᇂ GPIO ࢌߐइᆔ GPIO_FUNCx_OUT_SEL ࠷թఖູห‫֥ק‬ຓഡ෬ႄᆴ 256 +č0x100Ďb + +4.4 IO_MUX ֥ᆰࢤ I/O ‫ିۿ‬ + +4.4.1 ‫ۀ‬ඍ + +ॹ෎ྐ‫ݼ‬ೂၛ෾ຩaSDIOaSPIaJTAGaUART ֩߶கਫ਼ GPIO ࢌߐइᆔၛൌགྷ۷‫֥ۚݺ‬௔ඔሳหྟb෮ၛۚ෎ +ྐ‫߶ݼ‬ᆰࢤ๙‫ ݖ‬IO_MUX ൻೆ‫ބ‬ൻԛb + +ᆃဢб൐Ⴈ GPIO ࢌߐइᆔ֥ਲࠃ؇ေ֮đࠧૄ۱ GPIO pad ֥ IO_MUX ࠷թఖᆺႵࢠഒ֥‫ିۿ‬࿊ᄴđ֌ॖၛ +ൌགྷ۷‫֥ۚݺ‬௔ඔሳหྟb + +4.4.2 ‫ିۿ‬૭ඍ + +ູൌགྷຓഡ I/O கਫ਼ GPIO ࢌߐइᆔсྶ஥ᇂਆ۱࠷թఖğ + + 1. GPIO pad ֥ IO_MUX сྶഡᇂູཌྷႋ֥ pad ‫ିۿ‬đᅣࢫ 4.10 ਙԛਔ pad ‫ିۿ‬b + + 2. ؓႿൻೆྐ‫ݼ‬đсྶౢਬ SIG_IN_SEL ࠷թఖđᆰࢤࡼൻೆྐ‫ݼ‬ൻԛ֞ຓഡb + +4.5 RTC IO_MUX ֥֮‫ބݻۿ‬ଆ୅ I/O ‫ିۿ‬ + +4.5.1 ‫ۀ‬ඍ + +18 ۱ GPIO ܵ࢖ऎႵ֮‫ݻۿ‬č֮‫ ݻۿ‬RTCĎྟି‫ބ‬ଆ୅‫ିۿ‬đႮ ESP32 ֥ RTC ሰ༢๤॥ᇅbᆃུ‫ିۿ‬҂൐Ⴈ +IO_MUX ‫ ބ‬GPIO ࢌߐइᆔđ‫ط‬൞൐Ⴈ RTC_MUX ࡼ I/O ᆷཟ RTC ሰ༢๤b + +֒ᆃུܵ࢖Ф஥ᇂູ RTC GPIO ܵ࢖đቔູൻԛܵ࢖ൈಯಖି‫ܔ‬ᄝྉோԩႿ Deep-sleep ඤ૤ଆൔ༯Ќӻൻԛ +‫׈‬௜ᆴࠇᆀቔູൻೆܵ࢖൐ႨൈॖၛࡼྉோՖ Deep-sleep ᇏߒྜb + +ᅣࢫ 4.11 ਙԛਔ RTC_MUX ܵ࢖‫ିۿބ‬b + +4.5.2 ‫ିۿ‬૭ඍ + +ૄ۱ pad ֥ଆ୅‫ ބ‬RTC ‫ିۿ‬൞Ⴎ RTC_GPIO_PINx ࠷թఖᇏ֥ RTC_IO_TOUCH_PADx_TO_GPIO ໊॥ᇅ֥b +Վ໊ଏಪᇂູ 1đ๙‫ ݖ‬IO_MUX ሰ༢๤ൻೆൻԛྐ‫ݼ‬đೂభ໓෮ඍb + +ೂ‫ݔ‬ౢਬ RTC_IO_TOUCH_PADx_TO_GPIO ໊đᄵൻೆൻԛྐ‫ ݖࣜ߶ݼ‬RTC ሰ༢๤bᄝᆃᇕଆൔ༯đ +RTC_GPIO_PINx ࠷թఖႨႿඔሳ I/Ođpad ֥ଆ୅‫္ିۿ‬ॖၛൌགྷbᅣࢫ 4.11 ਙԛਔ RTC ܵ࢖֥‫ିۿ‬b + +і 4.11 ਙԛਔ GPIO pad აཌྷႋ֥ RTC ܵ࢖‫ބ‬ଆ୅‫֥ିۿ‬႘ഝܱ༢b౨ᇿၩ RTC_IO_PINx ࠷թఖ൐Ⴈ֥൞ +RTC GPIO ܵ࢖֥྽‫ݼ‬đ҂൞ GPIO pad ֥྽‫ݼ‬b + +4.6 Light­sleep ଆൔܵ࢖‫ିۿ‬ + +֒ ESP32 ԩႿ Light-sleep ଆൔൈܵ࢖ॖၛႵ҂๝֥‫ିۿ‬bೂ‫ݔ‬ଖ၂ GPIO pad ֥ IO_MUX ࠷թఖᇏ SLP_SEL +໊ᇂູ 1đྉோԩႿ Light-sleep ଆൔ༯ࡼႮਸ਼၂ቆ҂๝֥࠷թఖ॥ᇅ padb + + і 4­1. IO_MUX Light­sleep ܵ࢖‫࠷ିۿ‬թఖ + +IO_MUX ‫ିۿ‬ ᆞӈ‫۽‬ቔଆൔࠇᆀ SLP_SEL = 0 Light-sleep ଆൔѩ౏ SLP_SEL = 1 +Output Drive Strength FUN_DRV MCU_DRV +Pull-up Resistor FUN_WPU MCU_WPU +Pull-down Resistor FUN_WPD MCU_WPD +Output Enable (From GPIO Matrix _OEN field) MCU_OE + +ুᶈྐ༏॓࠯ 48 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +ೂ‫ ݔ‬SLP_SEL ᇂູ 0đᄵྉோᄝᆞӈ‫۽‬ቔ‫ ބ‬Light-sleep ଆൔ༯đܵ࢖֥‫ିۿ‬၂ဢb + +4.7 Pad Hold หྟ + +ૄ۱ IO padčЇও RTC padĎ‫׻‬Ⴕֆ‫ ֥׿‬hold ‫ିۿ‬đႮ RTC ࠷թఖ॥ᇅbpad ֥ hold ‫ିۿ‬Фᇂഈުđpad ᄝ +ᇂഈ hold ପ၂ख़֥ሑ෿Ф఼ᇅЌӻđ໭ંଽ҆ྐ‫ݼ‬ೂ‫ޅ‬э߄đྩ‫ ڿ‬IO_MUX ஥ᇂࠇᆀ GPIO ஥ᇂđ‫׻‬҂߶‫ڿ‬э +pad ֥ሑ෿bႋႨೂ‫ݔ‬༐ຬᄝु૊‫ܐ‬ӑൈԨ‫ؿ‬ଽ‫ބ໊گނ‬༢๤‫໊گ‬ൈࠇᆀ Deep-sleep ൈ pad ֥ሑ෿҂Ф‫ڿ‬эđ +ࣼླေิభϜ hold ᇂഈb + + ඪૼğ + • ؓႿඔሳ pad ‫ط‬࿽, ೏ေᄝധ؇ඤ૤‫׈ו‬ᆭުЌӻ pad ൻೆൻԛ֥ሑ෿ᆴđླေᄝ‫׈ו‬ᆭభϜ࠷թఖ + REG_DG_PAD_FORCE_UNHOLD ഡᇂӮ 0bؓႿ RTC pad ‫ط‬࿽đpad ֥ൻೆൻԛᆴđႮ࠷թఖ + RTC_CNTL_HOLD_FORCE_REG ᇏཌྷႋ໊֥ট॥ᇅ Hold ‫ ބ‬Unhold pad ֥ᆴb + • ᄝྉோФߒྜᆭުđ೏ေܱо Hold ‫ିۿ‬đࡼ࠷թఖ REG_DG_PAD_FORCE_UNHOLD ഡᇂӮ 1b೏མ࠿࿃Ќӻ + pad ֥ᆴđॖϜ RTC_CNTL_HOLD_FORCE_REG ࠷թఖᇏཌྷႋ໊֥ഡᇂӮ 1b + +4.8 I/O Pad ‫׈܂‬ + +IO pad ‫׈܂‬ೂ๭ 4-4 ‫ބ‬๭ 4-5 ෮ൕb + + 48 CAP1 + 47 CAP2 + 46 VDDA + 45 XTAL_P + 44 XTAL_N + 43 VDDA + 42 GPIO21 + 41 U0TXD + 40 U0RXD + 39 GPIO22 + 38 GPIO19 + 37 VDD3P3_CPU + + VDDA 1 ESP32 36 GPIO23 + LNA_IN 2 49 GND 35 GPIO18 + VDD3P3 3 34 GPIO5 + VDD3P3 4 33 SD_DATA_1 + SENSOR_VP 5 32 SD_DATA_0 + SENSOR_CAPP 6 31 SD_CLK + SENSOR_CAPN 7 30 SD_CMD + SENSOR_VN 8 29 SD_DATA_3 + CHIP_PU 9 28 SD_DATA_2 + VDET_1 10 27 GPIO17 + VDET_2 11 26 VDD_SDIO + 32K_XP 12 25 GPIO16 + + 32K_XN 13 + GPIO25 14 + GPIO26 15 + GPIO27 16 + + MTMS 17 + MTDI 18 + + VDD3P3_RTC 19 + MTCK 20 + MTDO 21 + GPIO2 22 + GPIO0 23 + GPIO4 24 + Analog pads + Pads powered by VDD3P3_CPU + Pads powered by VDD_SDIO + Pads powered by VDD3P3_RTC + + ๭ 4­4. ESP32 I/O Pad ‫׈܂‬ჷčQFN 6*6đ‫פ‬൪๭Ď + +ুᶈྐ༏॓࠯ 49 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + 48 CAP1 + 47 CAP2 + 46 VDDA + 45 XTAL_P + 44 XTAL_N + 43 VDDA + 42 GPIO21 + 41 U0TXD + 40 U0RXD + 39 GPIO22 + + VDDA 1 ESP32 38 GPIO19 + LNA_IN 2 49 GND 37 VDD3P3_CPU + VDD3P3 3 36 GPIO23 + VDD3P3 4 35 GPIO18 + SENSOR_VP 5 34 GPIO5 + SENSOR_CAPP 6 33 SD_DATA_1 + SENSOR_CAPN 7 32 SD_DATA_0 + SENSOR_VN 8 31 SD_CLK + CHIP_PU 9 30 SD_CMD + VDET_1 10 29 SD_DATA_3 + VDET_2 11 28 SD_DATA_2 + 32K_XP 12 27 GPIO17 + 32K_XN 13 26 VDD_SDIO + GPIO25 14 25 GPIO16 + + GPIO26 15 Analog pads + GPIO27 16 Pads powered by VDD3P3_CPU + Pads powered by VDD_SDIO + MTMS 17 Pads powered by VDD3P3_RTC + MTDI 18 + + VDD3P3_RTC 19 + MTCK 20 + MTDO 21 + GPIO2 22 + GPIO0 23 + GPIO4 24 + + ๭ 4­5. ESP32 I/O Pad ‫׈܂‬ჷčQFN 5*5đ‫פ‬൪๭Ď + + • ড೤֥ pad ູ RTC padđ෱ૌ‫׻‬ջႵ၂ᇕࠇࠫᇕଆ୅‫ିۿ‬đ္ॖၛႨቔູᆞӈඔሳ IO pad ൐Ⴈđབྷ࡮ᅣ + ࢫ 4.11b + + • ߛ೤‫ބ‬ੳ೤֥ pad ᆺႵඔሳ IO ֥‫ିۿ‬b + + • ੳ೤֥ pad ॖၛ๙‫ ݖ‬VDD_SDIO Ⴎຓ҆‫္׈܂‬ॖႮྉோଽ҆‫׈܂‬čབྷ࡮༯໓Ďb + +4.8.1 VDD_SDIO ‫׈‬ჷთ + +VDD_SDIO ॖၛঘ‫׈‬ੀ‫׈ܹބ‬ੀđၹՎ VDD_SDIO ‫׈‬ჷთॖႮຓ҆ࠇଽ҆‫׈܂‬b೏൐Ⴈຓ҆‫׈܂‬đсྶ൐Ⴈ‫ބ‬ +VDD3P3_RTC ཌྷ๝֥‫׈‬ჷb + +ೂ‫ݔ‬ຓ҆҂‫׈܂‬đᄵଽ҆ཌྟ໗࿢ఖ߶۳ VDD_SDIO ‫׈܂‬bVDD_SDIO ‫׈‬࿢ॖၛູ 1.8V ࠇა VDD3P3_RTC ၂ +ᇁđᆃ౼थႿ MTDI pad ᄝ‫໊گ‬ൈ֥ሑ෿iiۚ‫׈‬௜ൈູ 1.8Vđ֮‫׈‬௜ൈູა VDD3P3_RTC ၂ᇁbeFuse bit +ᇂഈުॖ఼ᇅथ‫ ק‬VDD_SDIO ֥ଏಪ‫׈‬࿢bՎຓđೈࡱఓ‫ު׮‬ೈࡱߎॖၛ஥ᇂ࠷թఖট఼ᇅ‫ڿ‬э VDD_SDIO ֥ +‫׈‬࿢b + +4.9 ຓഡྐ‫ݼ‬ਙі + +і 4-2 ਙԛਔ GPIO ࢌߐइᆔ֥ຓഡൻೆĔൻԛྐ‫ݼ‬b + + і 4­2. GPIO ࢌߐइᆔຓഡྐ‫ݼ‬ + +Signal Input Signal Output Signal Direct I/O in IO_MUX +0 SPICLK_in SPICLK_out YES +1 SPIQ_in SPIQ_out YES +2 SPID_in SPID_out YES + +ুᶈྐ༏॓࠯ 50 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +Signal Input Signal Output Signal Direct I/O in IO_MUX +3 SPIHD_in SPIHD_out YES +4 SPIWP_in SPIWP_out YES +5 SPICS0_in SPICS0_out YES +6 SPICS1_in SPICS1_out - +7 SPICS2_in SPICS2_out - +8 HSPICLK_in HSPICLK_out YES +9 HSPIQ_in HSPIQ_out YES +10 HSPID_in HSPID_out YES +11 HSPICS0_in HSPICS0_out YES +12 HSPIHD_in HSPIHD_out YES +13 HSPIWP_in HSPIWP_out YES +14 U0RXD_in U0TXD_out YES +15 U0CTS_in U0RTS_out YES +16 U0DSR_in U0DTR_out - +17 U1RXD_in U1TXD_out YES +18 U1CTS_in U1RTS_out YES +23 I2S0O_BCK_in I2S0O_BCK_out - +24 I2S1O_BCK_in I2S1O_BCK_out - +25 I2S0O_WS_in I2S0O_WS_out - +26 I2S1O_WS_in I2S1O_WS_out - +27 I2S0I_BCK_in I2S0I_BCK_out - +28 I2S0I_WS_in I2S0I_WS_out - +29 I2CEXT0_SCL_in I2CEXT0_SCL_out - +30 I2CEXT0_SDA_in I2CEXT0_SDA_out - +31 pwm0_sync0_in sdio_tohost_int_out - +32 pwm0_sync1_in pwm0_out0a - +33 pwm0_sync2_in pwm0_out0b - +34 pwm0_f0_in pwm0_out1a - +35 pwm0_f1_in pwm0_out1b - +36 pwm0_f2_in pwm0_out2a - +37 - pwm0_out2b - +39 pcnt_sig_ch0_in0 - - +40 pcnt_sig_ch1_in0 - - +41 pcnt_ctrl_ch0_in0 - - +42 pcnt_ctrl_ch1_in0 - - +43 pcnt_sig_ch0_in1 - - +44 pcnt_sig_ch1_in1 - - +45 pcnt_ctrl_ch0_in1 - - +46 pcnt_ctrl_ch1_in1 - - +47 pcnt_sig_ch0_in2 - - +48 pcnt_sig_ch1_in2 - - +49 pcnt_ctrl_ch0_in2 - - +50 pcnt_ctrl_ch1_in2 - - + +ুᶈྐ༏॓࠯ 51 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +Signal Input Signal Output Signal Direct I/O in IO_MUX +51 pcnt_sig_ch0_in3 - - +52 pcnt_sig_ch1_in3 - - +53 pcnt_ctrl_ch0_in3 - - +54 pcnt_ctrl_ch1_in3 - - +55 pcnt_sig_ch0_in4 - - +56 pcnt_sig_ch1_in4 - - +57 pcnt_ctrl_ch0_in4 - - +58 pcnt_ctrl_ch1_in4 - - +61 HSPICS1_in HSPICS1_out - +62 HSPICS2_in HSPICS2_out - +63 VSPICLK_in VSPICLK_out_mux YES +64 VSPIQ_in VSPIQ_out YES +65 VSPID_in VSPID_out YES +66 VSPIHD_in VSPIHD_out YES +67 VSPIWP_in VSPIWP_out YES +68 VSPICS0_in VSPICS0_out YES +69 VSPICS1_in VSPICS1_out - +70 VSPICS2_in VSPICS2_out - +71 pcnt_sig_ch0_in5 ledc_hs_sig_out0 - +72 pcnt_sig_ch1_in5 ledc_hs_sig_out1 - +73 pcnt_ctrl_ch0_in5 ledc_hs_sig_out2 - +74 pcnt_ctrl_ch1_in5 ledc_hs_sig_out3 - +75 pcnt_sig_ch0_in6 ledc_hs_sig_out4 - +76 pcnt_sig_ch1_in6 ledc_hs_sig_out5 - +77 pcnt_ctrl_ch0_in6 ledc_hs_sig_out6 - +78 pcnt_ctrl_ch1_in6 ledc_hs_sig_out7 - +79 pcnt_sig_ch0_in7 ledc_ls_sig_out0 - +80 pcnt_sig_ch1_in7 ledc_ls_sig_out1 - +81 pcnt_ctrl_ch0_in7 ledc_ls_sig_out2 - +82 pcnt_ctrl_ch1_in7 ledc_ls_sig_out3 - +83 rmt_sig_in0 ledc_ls_sig_out4 - +84 rmt_sig_in1 ledc_ls_sig_out5 - +85 rmt_sig_in2 ledc_ls_sig_out6 - +86 rmt_sig_in3 ledc_ls_sig_out7 - +87 rmt_sig_in4 rmt_sig_out0 - +88 rmt_sig_in5 rmt_sig_out1 - +89 rmt_sig_in6 rmt_sig_out2 - +90 rmt_sig_in7 rmt_sig_out3 - +91 - rmt_sig_out4 - +92 - rmt_sig_out5 - +93 - rmt_sig_out6 - +94 - rmt_sig_out7 - +95 I2CEXT1_SCL_in I2CEXT1_SCL_out - + +ুᶈྐ༏॓࠯ 52 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +Signal Input Signal Output Signal Direct I/O in IO_MUX +96 I2CEXT1_SDA_in +97 host_card_detect_n_1 I2CEXT1_SDA_out - +98 host_card_detect_n_2 +99 host_card_write_prt_1 host_ccmd_od_pullup_en_n - +100 host_card_write_prt_2 +101 host_card_int_n_1 host_rst_n_1 - +102 host_card_int_n_2 +103 pwm1_sync0_in host_rst_n_2 - +104 pwm1_sync1_in +105 pwm1_sync2_in gpio_sd0_out - +106 pwm1_f0_in +107 pwm1_f1_in gpio_sd1_out - +108 pwm1_f2_in +109 pwm0_cap0_in gpio_sd2_out - +110 pwm0_cap1_in +111 pwm0_cap2_in gpio_sd3_out - +112 pwm1_cap0_in +113 pwm1_cap1_in gpio_sd4_out - +114 pwm1_cap2_in +115 - gpio_sd5_out - +116 - +117 - gpio_sd6_out - +118 - +119 - gpio_sd7_out - +120 - +121 - pwm1_out0a - +122 - +123 - pwm1_out0b - +124 - +140 I2S0I_DATA_in0 pwm1_out1a - +141 I2S0I_DATA_in1 +142 I2S0I_DATA_in2 pwm1_out1b - +143 I2S0I_DATA_in3 +144 I2S0I_DATA_in4 pwm1_out2a - +145 I2S0I_DATA_in5 +146 I2S0I_DATA_in6 pwm1_out2b - +147 I2S0I_DATA_in7 +148 I2S0I_DATA_in8 - - +149 I2S0I_DATA_in9 +150 I2S0I_DATA_in10 - - +151 I2S0I_DATA_in11 +152 I2S0I_DATA_in12 - - +153 I2S0I_DATA_in13 + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + I2S0O_DATA_out0 - + + I2S0O_DATA_out1 - + + I2S0O_DATA_out2 - + + I2S0O_DATA_out3 - + + I2S0O_DATA_out4 - + + I2S0O_DATA_out5 - + + I2S0O_DATA_out6 - + + I2S0O_DATA_out7 - + + I2S0O_DATA_out8 - + + I2S0O_DATA_out9 - + + I2S0O_DATA_out10 - + + I2S0O_DATA_out11 - + + I2S0O_DATA_out12 - + + I2S0O_DATA_out13 - + +ুᶈྐ༏॓࠯ 53 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +Signal Input Signal Output Signal Direct I/O in IO_MUX +154 I2S0I_DATA_in14 I2S0O_DATA_out14 - +155 I2S0I_DATA_in15 I2S0O_DATA_out15 - +156 - I2S0O_DATA_out16 - +157 - I2S0O_DATA_out17 - +158 - I2S0O_DATA_out18 - +159 - I2S0O_DATA_out19 - +160 - I2S0O_DATA_out20 - +161 - I2S0O_DATA_out21 - +162 - I2S0O_DATA_out22 - +163 - I2S0O_DATA_out23 - +164 I2S1I_BCK_in I2S1I_BCK_out - +165 I2S1I_WS_in I2S1I_WS_out - +166 I2S1I_DATA_in0 I2S1O_DATA_out0 - +167 I2S1I_DATA_in1 I2S1O_DATA_out1 - +168 I2S1I_DATA_in2 I2S1O_DATA_out2 - +169 I2S1I_DATA_in3 I2S1O_DATA_out3 - +170 I2S1I_DATA_in4 I2S1O_DATA_out4 - +171 I2S1I_DATA_in5 I2S1O_DATA_out5 - +172 I2S1I_DATA_in6 I2S1O_DATA_out6 - +173 I2S1I_DATA_in7 I2S1O_DATA_out7 - +174 I2S1I_DATA_in8 I2S1O_DATA_out8 - +175 I2S1I_DATA_in9 I2S1O_DATA_out9 - +176 I2S1I_DATA_in10 I2S1O_DATA_out10 - +177 I2S1I_DATA_in11 I2S1O_DATA_out11 - +178 I2S1I_DATA_in12 I2S1O_DATA_out12 - +179 I2S1I_DATA_in13 I2S1O_DATA_out13 - +180 I2S1I_DATA_in14 I2S1O_DATA_out14 - +181 I2S1I_DATA_in15 I2S1O_DATA_out15 - +182 - I2S1O_DATA_out16 - +183 - I2S1O_DATA_out17 - +184 - I2S1O_DATA_out18 - +185 - I2S1O_DATA_out19 - +186 - I2S1O_DATA_out20 - +187 - I2S1O_DATA_out21 - +188 - I2S1O_DATA_out22 - +189 - I2S1O_DATA_out23 - +190 I2S0I_H_SYNC - - +191 I2S0I_V_SYNC - - +192 I2S0I_H_ENABLE - - +193 I2S1I_H_SYNC - - +194 I2S1I_V_SYNC - - +195 I2S1I_H_ENABLE - - +196 - - - + +ুᶈྐ༏॓࠯ 54 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +Signal Input Signal Output Signal Direct I/O in IO_MUX +197 - - - +198 U2RXD_in U2TXD_out YES +199 U2CTS_in U2RTS_out YES +200 emac_mdc_i emac_mdc_o - +201 emac_mdi_i emac_mdo_o - +202 emac_crs_i emac_crs_o - +203 emac_col_i emac_col_o - +204 pcmfsync_in bt_audio0_irq - +205 pcmclk_in bt_audio1_irq - +206 pcmdin bt_audio2_irq - +207 - ble_audio0_irq - +208 - ble_audio1_irq - +209 - ble_audio2_irq - +210 - pcmfsync_out - +211 - pcmclk_out - +212 - pcmdout - +213 - ble_audio_sync0_p - +214 - ble_audio_sync1_p - +215 - ble_audio_sync2_p - +224 - sig_in_func224 - +225 - sig_in_func225 - +226 - sig_in_func226 - +227 - sig_in_func227 - +228 - sig_in_func228 - + +Direct I/O in IO_MUX ”YES” ᆷՎྐ‫္ݼ‬ॖၛ๙‫ ݖ‬IO_MUX ᆰࢤ৵ࢤ padbೂ‫ݔ‬ᆃུྐ‫ݼ‬ေ൐Ⴈ GPIO ࢌߐइ +ᆔđᄵсྶࡼཌྷႋ֥ SIG_IN_SEL ࠷թఖౢਬb + +4.10 IO_MUX Pad ਙі + +і 4-3 ਙԛਔૄ۱ I/O pad ֥ IO_MUX ‫ିۿ‬b + + і 4­3. IO_MUX Pad ਙі + +GPIO Pad Name Function 0 Function 1 Function 2 Function 3 Function 4 Function 5 Reset Notes +0 GPIO0 GPIO0 CLK_OUT1 GPIO0 - - EMAC_TX_CLK 3 R +1 U0TXD U0TXD CLK_OUT3 GPIO1 - - EMAC_RXD2 3 - +2 GPIO2 GPIO2 HSPIWP GPIO2 HS2_DATA0 SD_DATA0 - 2 R +3 U0RXD U0RXD CLK_OUT2 GPIO3 - - - 3 - +4 GPIO4 GPIO4 HSPIHD GPIO4 HS2_DATA1 SD_DATA1 EMAC_TX_ER 2 R +5 GPIO5 GPIO5 VSPICS0 GPIO5 HS1_DATA6 - EMAC_RX_CLK 3 - +6 SD_CLK SD_CLK SPICLK GPIO6 HS1_CLK U1CTS - 3 - +7 SD_DATA_0 SD_DATA0 SPIQ GPIO7 HS1_DATA0 U2RTS - 3 - +8 SD_DATA_1 SD_DATA1 SPID GPIO8 HS1_DATA1 U2CTS - 3 - +9 SD_DATA_2 SD_DATA2 SPIHD GPIO9 HS1_DATA2 U1RXD - 3 - +10 SD_DATA_3 SD_DATA3 SPIWP GPIO10 HS1_DATA3 U1TXD - 3 - +11 SD_CMD SD_CMD SPICS0 GPIO11 HS1_CMD U1RTS - 3 - +12 MTDI MTDI HSPIQ GPIO12 HS2_DATA2 SD_DATA2 EMAC_TXD3 2 R +13 MTCK MTCK HSPID GPIO13 HS2_DATA3 SD_DATA3 EMAC_RX_ER 2 R + +ুᶈྐ༏॓࠯ 55 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +GPIO Pad Name Function 0 Function 1 Function 2 Function 3 Function 4 Function 5 Reset Notes +14 HSPICLK GPIO14 EMAC_TXD2 3 R +15 MTMS MTMS HSPICS0 GPIO15 HS2_CLK SD_CLK EMAC_RXD3 3 R +16 - GPIO16 EMAC_CLK_OUT 1 - +17 MTDO MTDO - GPIO17 HS2_CMD SD_CMD EMAC_CLK_180 1 - +18 VSPICLK GPIO18 - 1 - +19 GPIO16 GPIO16 VSPIQ GPIO19 HS1_DATA4 U2RXD EMAC_TXD0 1 - +21 VSPIHD GPIO21 EMAC_TX_EN 1 - +22 GPIO17 GPIO17 VSPIWP GPIO22 HS1_DATA5 U2TXD EMAC_TXD1 1 - +23 VSPID GPIO23 - 1 - +25 GPIO18 GPIO18 - GPIO25 HS1_DATA7 - EMAC_RXD0 0 R +26 - GPIO26 EMAC_RXD1 0 R +27 GPIO19 GPIO19 - GPIO27 U0CTS - EMAC_RX_DV 0 R +32 - GPIO32 - 0 R +33 GPIO21 GPIO21 - GPIO33 - - - 0 R +34 - GPIO34 - 0 R, I +35 GPIO22 GPIO22 - GPIO35 U0RTS - - 0 R, I +36 - GPIO36 - 0 R, I +37 GPIO23 GPIO23 - GPIO37 HS1_STROBE - - 0 R, I +38 - GPIO38 - 0 R, I +39 GPIO25 GPIO25 - GPIO39 - - - 0 R, I + + GPIO26 GPIO26 - - + + GPIO27 GPIO27 - - + + 32K_XP GPIO32 - - + + 32K_XN GPIO33 - - + + VDET_1 GPIO34 - - + + VDET_2 GPIO35 - - + + SENSOR_VP GPIO36 - - + + SENSOR_CAPP GPIO37 - - + + SENSOR_CAPN GPIO38 - - + + SENSOR_VN GPIO39 - - + + ‫໊گ‬஥ᇂ +oResetp၂ণ൞ૄ۱ pad ‫֥ު໊گ‬ଏಪ஥ᇂb + + • 0 - IE=0čൻೆܱоĎ + • 1 - IE=1čൻೆ൐ିĎ + • 2 - IE=1, WPD=1čൻೆ൐ିđ༯ঘ‫׈‬ቅĎ + • 3 - IE=1, WPU=1čൻೆ൐ିđഈঘ‫׈‬ቅĎ + ඪૼ + • R - Pad ๙‫ ݖ‬RTC_MUX ऎႵ RTC Ĕଆ୅‫ିۿ‬b + • I - Pad ᆺି஥ᇂູൻೆ GPIObՎো Pad ҂ऎСൻԛ౺‫ࠇ׮‬ଽᇂഈঘ/༯ঘ‫׈‬ਫ਼b + ౨ҕॉ uESP32 ࠯ඌܿ۬඀v֥‫ڸ‬੣Ұुܵ࢖‫֥ିۿ‬ປᆜі۬b + +4.11 RTC_MUX ܵ࢖ౢֆ + +і 4-4 ਙԛਔ RTC ܵ࢖‫ؓބ‬ႋ GPIO padb + + і 4­4. RTC_MUX ܵ࢖ౢֆ + + Analog Function RTC Function + +RTC GPIO Num GPIO Num Pad Name 0 1 2 Function 0 Function 1 + + (FUN_SEL = 0) (FUN_SEL = 3) + + 0 36 SENSOR_VP ADC_H ADC1_CH0 - RTC_GPIO0 - + + 1 37 SENSOR_CAPP ADC_H ADC1_CH1 - RTC_GPIO1 - + + 2 38 SENSOR_CAPN ADC_H ADC1_CH2 - RTC_GPIO2 - + + 3 39 SENSOR_VN ADC_H ADC1_CH3 - RTC_GPIO3 - + + 4 34 VDET_1 - ADC1_CH6 - RTC_GPIO4 - + +ুᶈྐ༏॓࠯ 56 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Analog Function RTC Function + +RTC GPIO Num GPIO Num Pad Name 0 1 2 Function 0 Function 1 + + VDET_2 - (FUN_SEL = 0) (FUN_SEL = 3) + GPIO25 - +5 35 GPIO26 - ADC1_CH7 - RTC_GPIO5 - + 32K_XN DAC_1 ADC2_CH8 TOUCH8 +6 25 32K_XP DAC_2 ADC2_CH9 TOUCH9 RTC_GPIO6 - + GPIO4 XTAL_32K_N ADC1_CH5 TOUCH0 +7 26 GPIO0 XTAL_32K_P ADC1_CH4 TOUCH1 RTC_GPIO7 - + GPIO2 ADC2_CH0 TOUCH2 +8 33 MTDO - ADC2_CH1 TOUCH3 RTC_GPIO8 - + MTCK - ADC2_CH2 TOUCH4 +9 32 - ADC2_CH3 TOUCH5 RTC_GPIO9 - + MTDI - ADC2_CH4 TOUCH6 +10 4 MTMS - ADC2_CH5 TOUCH7 RTC_GPIO10 I2C_SCL∗ + GPIO27 - ADC2_CH6 +11 0 - ADC2_CH7 RTC_GPIO11 I2C_SDA∗ + - +12 2 RTC_GPIO12 I2C_SCL∗ + +13 15 RTC_GPIO13 I2C_SDA∗ + +14 13 RTC_GPIO14 - + +15 12 RTC_GPIO15 - + +16 14 RTC_GPIO16 - + +17 27 RTC_GPIO17 - + +ඪૼğ +Ⴕܱ RTC I2C ֥஥ᇂྐ༏đ౨ҕॉᅣࢫ 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP)ğRTC I2C ॥ᇅఖb + +4.12 ࠷թఖਙі + +4.12.1 GPIO ࢌߐइᆔ࠷թఖਙі + +଀ӫ ૭ඍ ֹᆶ ٠໙ +GPIO_OUT_REG GPIO 0-31 ൻԛ࠷թఖ 0x3FF44004 ‫؀‬/ཿ +GPIO_OUT_W1TS_REG GPIO 0-31 ൻԛ࠷թఖ _WITS 0x3FF44008 ᆺཿ +GPIO_OUT_W1TC_REG GPIO 0-31 ൻԛ࠷թఖ _WITC 0x3FF4400C ᆺཿ +GPIO_OUT1_REG GPIO 32-39 ൻԛ࠷թఖ 0x3FF44010 ‫؀‬/ཿ +GPIO_OUT1_W1TS_REG GPIO 32-39 ൻԛᇂ໊࠷թఖ 0x3FF44014 ᆺཿ +GPIO_OUT1_W1TC_REG GPIO 32-39 ൻԛౢԢ࠷թఖ 0x3FF44018 ᆺཿ +GPIO_ENABLE_REG GPIO 0-31 ൻԛ൐ି࠷թఖ 0x3FF44020 ‫؀‬/ཿ +GPIO_ENABLE_W1TS_REG GPIO 0-31 ൻԛ൐ି࠷թఖ _W1TS 0x3FF44024 ᆺཿ +GPIO_ENABLE_W1TC_REG GPIO 0-31 ൻԛ൐ି࠷թఖ _W1TC 0x3FF44028 ᆺཿ +GPIO_ENABLE1_REG GPIO 32-39 ൻԛ൐ି࠷թఖ 0x3FF4402C ‫؀‬/ཿ +GPIO_ENABLE1_W1TS_REG GPIO 32-39 ൻԛ൐ିᇂ໊࠷թఖ 0x3FF44030 ᆺཿ +GPIO_ENABLE1_W1TC_REG GPIO 32-39 ൻԛ൐ିౢԢ࠷թఖ 0x3FF44034 ᆺཿ +GPIO_STRAP_REG Bootstrap ܵ࢖ᆴ࠷թఖ 0x3FF44038 ᆺ‫؀‬ +GPIO_IN_REG GPIO 0-31 ൻೆ࠷թఖ 0x3FF4403C ᆺ‫؀‬ +GPIO_IN1_REG GPIO 32-39 ൻೆ࠷թఖ 0x3FF44040 ᆺ‫؀‬ +GPIO_STATUS_REG GPIO 0-31 ᇏ؎ሑ෿࠷թఖ 0x3FF44044 ‫؀‬/ཿ +GPIO_STATUS_W1TS_REG GPIO 0-31 ᇏ؎ሑ෿࠷թఖ _W1TS 0x3FF44048 ᆺཿ +GPIO_STATUS_W1TC_REG GPIO 0-31 ᇏ؎ሑ෿࠷թఖ _W1TC 0x3FF4404C ᆺཿ +GPIO_STATUS1_REG GPIO 32-39 ᇏ؎ሑ෿࠷թఖ 1 0x3FF44050 ‫؀‬/ཿ +GPIO_STATUS1_W1TS_REG GPIO 32-39 ᇏ؎ሑ෿ᇂ໊࠷թఖ 0x3FF44054 ᆺཿ + +ুᶈྐ༏॓࠯ 57 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +଀ӫ ૭ඍ ֹᆶ ٠໙ + 0x3FF44058 ᆺཿ +GPIO_STATUS1_W1TC_REG GPIO 32-39 ᇏ؎ሑ෿ౢԢ࠷թఖ 0x3FF44060 ᆺ‫؀‬ + 0x3FF44064 ᆺ‫؀‬ +GPIO_ACPU_INT_REG GPIO 0-31 APP_CPU ᇏ؎ሑ෿ 0x3FF44068 ᆺ‫؀‬ + 0x3FF4406C ᆺ‫؀‬ +GPIO_ACPU_NMI_INT_REG GPIO 0-31 APP_CPU ٤௠зᇏ؎ሑ෿ 0x3FF44074 ᆺ‫؀‬ + 0x3FF44078 ᆺ‫؀‬ +GPIO_PCPU_INT_REG GPIO 0-31 PRO_CPU ᇏ؎ሑ෿ 0x3FF4407C ᆺ‫؀‬ + 0x3FF44080 ᆺ‫؀‬ +GPIO_PCPU_NMI_INT_REG GPIO 0-31 PRO_CPU ٤௠зᇏ؎ሑ෿ 0x3FF44088 ‫؀‬/ཿ + 0x3FF4408C ‫؀‬/ཿ +GPIO_ACPU_INT1_REG GPIO 31-39 APP_CPU ᇏ؎ሑ෿ 0x3FF44090 ‫؀‬/ཿ + ... ... +GPIO_ACPU_NMI_INT1_REG GPIO 32-39 APP_CPU ٤௠зᇏ؎ሑ෿ 0x3FF44120 ‫؀‬/ཿ + 0x3FF44124 ‫؀‬/ཿ +GPIO_PCPU_INT1_REG GPIO 32-39 PRO_CPU ᇏ؎ሑ෿ 0x3FF44130 ‫؀‬/ཿ + 0x3FF44134 ‫؀‬/ཿ +GPIO_PCPU_NMI_INT1_REG GPIO 32-39 PRO_CPU ٤௠зᇏ؎ሑ෿ ... ... + 0x3FF44528 ‫؀‬/ཿ +GPIO_PIN0_REG ஥ᇂ GPIO ܵ࢖ 0 0x3FF4452C ‫؀‬/ཿ + 0x3FF44530 ‫؀‬/ཿ +GPIO_PIN1_REG ஥ᇂ GPIO ܵ࢖ 1 0x3FF44534 ‫؀‬/ཿ + ... ... +GPIO_PIN2_REG ஥ᇂ GPIO ܵ࢖ 2 0x3FF445C8 ‫؀‬/ཿ + 0x3FF445CC ‫؀‬/ཿ +... ... + +GPIO_PIN38_REG ஥ᇂ GPIO ܵ࢖ 38 + +GPIO_PIN39_REG ஥ᇂ GPIO ܵ࢖ 39 + +GPIO_FUNC0_IN_SEL_CFG_REG ຓഡ‫ ିۿ‬0 ൻೆ࿊ᄴ࠷թఖ + +GPIO_FUNC1_IN_SEL_CFG_REG ຓഡ‫ ିۿ‬1 ൻೆ࿊ᄴ࠷թఖ + +... ... + +GPIO_FUNC254_IN_SEL_CFG_REG ຓഡ‫ ିۿ‬254 ൻೆ࿊ᄴ࠷թఖ + +GPIO_FUNC255_IN_SEL_CFG_REG ຓഡ‫ ିۿ‬255 ൻೆ࿊ᄴ࠷թఖ + +GPIO_FUNC0_OUT_SEL_CFG_REG GPIO0 ֥ຓഡൻԛ࿊ᄴ + +GPIO_FUNC1_OUT_SEL_CFG_REG GPIO1 ֥ຓഡൻԛ࿊ᄴ + +... ... + +GPIO_FUNC38_OUT_SEL_CFG_REG GPIO38 ֥ຓഡൻԛ࿊ᄴ + +GPIO_FUNC39_OUT_SEL_CFG_REG GPIO39 ֥ຓഡൻԛ࿊ᄴ + +4.12.2 IO MUX ࠷թఖਙі + +଀ӫ ૭ඍ ֹᆶ ٠໙ +IO_MUX_PIN_CTRL ຓഡൈᇒ஥ᇂ࠷թఖ 0x3FF49000 ‫؀‬/ཿ +IO_MUX_GPIO36_REG ܵ࢖ GPIO36 ֥஥ᇂ࠷թఖ 0x3FF49004 ‫؀‬/ཿ +IO_MUX_GPIO37_REG ܵ࢖ GPIO37 ֥஥ᇂ࠷թఖ 0x3FF49008 ‫؀‬/ཿ +IO_MUX_GPIO38_REG ܵ࢖ GPIO38 ֥஥ᇂ࠷թఖ 0x3FF4900C ‫؀‬/ཿ +IO_MUX_GPIO39_REG ܵ࢖ GPIO39 ֥஥ᇂ࠷թఖ 0x3FF49010 ‫؀‬/ཿ +IO_MUX_GPIO34_REG ܵ࢖ GPIO34 ֥஥ᇂ࠷թఖ 0x3FF49014 ‫؀‬/ཿ +IO_MUX_GPIO35_REG ܵ࢖ GPIO35 ֥஥ᇂ࠷թఖ 0x3FF49018 ‫؀‬/ཿ +IO_MUX_GPIO32_REG ܵ࢖ GPIO32 ֥஥ᇂ࠷թఖ 0x3FF4901C ‫؀‬/ཿ +IO_MUX_GPIO33_REG ܵ࢖ GPIO33 ֥஥ᇂ࠷թఖ 0x3FF49020 ‫؀‬/ཿ +IO_MUX_GPIO25_REG ܵ࢖ GPIO25 ֥஥ᇂ࠷թఖ 0x3FF49024 ‫؀‬/ཿ +IO_MUX_GPIO26_REG ܵ࢖ GPIO26 ֥஥ᇂ࠷թఖ 0x3FF49028 ‫؀‬/ཿ +IO_MUX_GPIO27_REG ܵ࢖ GPIO27 ֥஥ᇂ࠷թఖ 0x3FF4902C ‫؀‬/ཿ +IO_MUX_MTMS_REG ܵ࢖ MTMS ֥஥ᇂ࠷թఖ 0x3FF49030 ‫؀‬/ཿ +IO_MUX_MTDI_REG ܵ࢖ MTDI ֥஥ᇂ࠷թఖ 0x3FF49034 ‫؀‬/ཿ +IO_MUX_MTCK_REG ܵ࢖ MTCK ֥஥ᇂ࠷թఖ 0x3FF49038 ‫؀‬/ཿ + +ুᶈྐ༏॓࠯ 58 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +଀ӫ ૭ඍ ֹᆶ ٠໙ +IO_MUX_MTDO_REG ܵ࢖ MTDO ֥஥ᇂ࠷թఖ 0x3FF4903C ‫؀‬/ཿ +IO_MUX_GPIO2_REG ܵ࢖ GPIO2 ֥஥ᇂ࠷թఖ 0x3FF49040 ‫؀‬/ཿ +IO_MUX_GPIO0_REG ܵ࢖ GPIO0 ֥஥ᇂ࠷թఖ 0x3FF49044 ‫؀‬/ཿ +IO_MUX_GPIO4_REG ܵ࢖ GPIO4 ֥஥ᇂ࠷թఖ 0x3FF49048 ‫؀‬/ཿ +IO_MUX_GPIO16_REG ܵ࢖ GPIO16 ֥஥ᇂ࠷թఖ 0x3FF4904C ‫؀‬/ཿ +IO_MUX_GPIO17_REG ܵ࢖ GPIO17 ֥஥ᇂ࠷թఖ 0x3FF49050 ‫؀‬/ཿ +IO_MUX_SD_DATA2_REG ܵ࢖ SD_DATA2 ֥஥ᇂ࠷թఖ 0x3FF49054 ‫؀‬/ཿ +IO_MUX_SD_DATA3_REG ܵ࢖ SD_DATA3 ֥஥ᇂ࠷թఖ 0x3FF49058 ‫؀‬/ཿ +IO_MUX_SD_CMD_REG ܵ࢖ SD_CMD ֥஥ᇂ࠷թఖ 0x3FF4905C ‫؀‬/ཿ +IO_MUX_SD_CLK_REG ܵ࢖ SD_CLK ֥஥ᇂ࠷թఖ 0x3FF49060 ‫؀‬/ཿ +IO_MUX_SD_DATA0_REG ܵ࢖ SD_DATA0 ֥஥ᇂ࠷թఖ 0x3FF49064 ‫؀‬/ཿ +IO_MUX_SD_DATA1_REG ܵ࢖ SD_DATA1 ֥஥ᇂ࠷թఖ 0x3FF49068 ‫؀‬/ཿ +IO_MUX_GPIO5_REG ܵ࢖ GPIO5 ֥஥ᇂ࠷թఖ 0x3FF4906C ‫؀‬/ཿ +IO_MUX_GPIO18_REG ܵ࢖ GPIO18 ֥஥ᇂ࠷թఖ 0x3FF49070 ‫؀‬/ཿ +IO_MUX_GPIO19_REG ܵ࢖ GPIO19 ֥஥ᇂ࠷թఖ 0x3FF49074 ‫؀‬/ཿ +IO_MUX_GPIO20_REG ܵ࢖ GPIO20 ֥஥ᇂ࠷թఖ 0x3FF49078 ‫؀‬/ཿ +IO_MUX_GPIO21_REG ܵ࢖ GPIO21 ֥஥ᇂ࠷թఖ 0x3FF4907C ‫؀‬/ཿ +IO_MUX_GPIO22_REG ܵ࢖ GPIO22 ֥஥ᇂ࠷թఖ 0x3FF49080 ‫؀‬/ཿ +IO_MUX_U0RXD_REG ܵ࢖ U0RXD ֥஥ᇂ࠷թఖ 0x3FF49084 ‫؀‬/ཿ +IO_MUX_U0TXD_REG ܵ࢖ U0TXD ֥஥ᇂ࠷թఖ 0x3FF49088 ‫؀‬/ཿ +IO_MUX_GPIO23_REG ܵ࢖ GPIO23 ֥஥ᇂ࠷թఖ 0x3FF4908C ‫؀‬/ཿ +IO_MUX_GPIO24_REG ܵ࢖ GPIO24 ֥஥ᇂ࠷թఖ 0x3FF49090 ‫؀‬/ཿ + +4.12.3 RTC IO MUX ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + + ଀ӫ RTC GPIO ൻԛ࠷թఖ 0x3FF48400 ‫؀‬/ཿ + GPIO ஥ᇂĔඔऌ࠷թఖ RTC GPIO ൻԛᇂ໊࠷թఖ 0x3FF48404 ᆺཿ + RTCIO_RTC_GPIO_OUT_REG RTC GPIO ൻԛౢԢ࠷թఖ 0x3FF48408 ᆺཿ + RTCIO_RTC_GPIO_OUT_W1TS_REG RTC GPIO ൻԛ൐ି࠷թఖ 0x3FF4840C ‫؀‬/ཿ + RTCIO_RTC_GPIO_OUT_W1TC_REG RTC GPIO ൻԛ൐ିᇂ໊࠷թఖ 0x3FF48410 ᆺཿ + RTCIO_RTC_GPIO_ENABLE_REG RTC GPIO ൻԛ൐ିౢԢ࠷թఖ 0x3FF48414 ᆺཿ + RTCIO_RTC_GPIO_ENABLE_W1TS_REG RTC GPIO ᇏ؎ሑ෿࠷թఖ 0x3FF48418 ‫؀‬/ཿ + RTCIO_RTC_GPIO_ENABLE_W1TC_REG RTC GPIO ᇏ؎ሑ෿ᇂ໊࠷թఖ 0x3FF4841C ᆺཿ + RTCIO_RTC_GPIO_STATUS_REG RTC GPIO ᇏ؎ሑ෿ౢԢ࠷թఖ 0x3FF48420 ᆺཿ + RTCIO_RTC_GPIO_STATUS_W1TS_REG RTC GPIO ൻೆ࠷թఖ 0x3FF48424 ᆺ‫؀‬ + RTCIO_RTC_GPIO_STATUS_W1TC_REG ஥ᇂ RTC ܵ࢖ 0 0x3FF48428 ‫؀‬/ཿ + RTCIO_RTC_GPIO_IN_REG ஥ᇂ RTC ܵ࢖ 1 0x3FF4842C ‫؀‬/ཿ + RTCIO_RTC_GPIO_PIN0_REG ஥ᇂ RTC ܵ࢖ 2 0x3FF48430 ‫؀‬/ཿ + RTCIO_RTC_GPIO_PIN1_REG ஥ᇂ RTC ܵ࢖ 3 0x3FF48434 ‫؀‬/ཿ + RTCIO_RTC_GPIO_PIN2_REG ஥ᇂ RTC ܵ࢖ 4 0x3FF48438 ‫؀‬/ཿ + RTCIO_RTC_GPIO_PIN3_REG ஥ᇂ RTC ܵ࢖ 5 0x3FF4843C ‫؀‬/ཿ + RTCIO_RTC_GPIO_PIN4_REG ஥ᇂ RTC ܵ࢖ 6 0x3FF48440 ‫؀‬/ཿ + RTCIO_RTC_GPIO_PIN5_REG + RTCIO_RTC_GPIO_PIN6_REG + +ুᶈྐ༏॓࠯ 59 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +଀ӫ ૭ඍ ֹᆶ ٠໙ +RTCIO_RTC_GPIO_PIN7_REG ஥ᇂ RTC ܵ࢖ 7 0x3FF48444 ‫؀‬/ཿ +RTCIO_RTC_GPIO_PIN8_REG ஥ᇂ RTC ܵ࢖ 8 0x3FF48448 ‫؀‬/ཿ +RTCIO_RTC_GPIO_PIN9_REG ஥ᇂ RTC ܵ࢖ 9 0x3FF4844C ‫؀‬/ཿ +RTCIO_RTC_GPIO_PIN10_REG ஥ᇂ RTC ܵ࢖ 10 0x3FF48450 ‫؀‬/ཿ +RTCIO_RTC_GPIO_PIN11_REG ஥ᇂ RTC ܵ࢖ 11 0x3FF48454 ‫؀‬/ཿ +RTCIO_RTC_GPIO_PIN12_REG ஥ᇂ RTC ܵ࢖ 12 0x3FF48458 ‫؀‬/ཿ +RTCIO_RTC_GPIO_PIN13_REG ஥ᇂ RTC ܵ࢖ 13 0x3FF4845C ‫؀‬/ཿ +RTCIO_RTC_GPIO_PIN14_REG ஥ᇂ RTC ܵ࢖ 14 0x3FF48460 ‫؀‬/ཿ +RTCIO_RTC_GPIO_PIN15_REG ஥ᇂ RTC ܵ࢖ 15 0x3FF48464 ‫؀‬/ཿ +RTCIO_RTC_GPIO_PIN16_REG ஥ᇂ RTC ܵ࢖ 16 0x3FF48468 ‫؀‬/ཿ +RTCIO_RTC_GPIO_PIN17_REG ஥ᇂ RTC ܵ࢖ 17 0x3FF4846C ‫؀‬/ཿ +RTCIO_DIG_PAD_HOLD_REG RTC GPIO Hold ࠷թఖ 0x3FF48474 ‫؀‬/ཿ +GPIO RTC ‫ିۿ‬஥ᇂ࠷թఖ +RTCIO_HALL_SENS_REG ࠉ‫غ‬Ԯ‫ۋ‬ఖ஥ᇂ 0x3FF48478 ‫؀‬/ཿ +RTCIO_SENSOR_PADS_REG Ԯ‫ۋ‬ఖܵ࢖஥ᇂ࠷թఖ +RTCIO_ADC_PAD_REG ADC ஥ᇂ࠷թఖ 0x3FF4847C ‫؀‬/ཿ +RTCIO_PAD_DAC1_REG DAC1 ஥ᇂ࠷թఖ +RTCIO_PAD_DAC2_REG DAC2 ஥ᇂ࠷թఖ 0x3FF48480 ‫؀‬/ཿ +RTCIO_XTAL_32K_PAD_REG 32 KHz ࣖᆒܵ࢖஥ᇂ࠷թఖ +RTCIO_TOUCH_CFG_REG ԨଃԮ‫ۋ‬ఖ஥ᇂ࠷թఖ 0x3FF48484 ‫؀‬/ཿ +RTCIO_TOUCH_PAD0_REG Ԩଃܵ࢖஥ᇂ࠷թఖ +... ... 0x3FF48488 ‫؀‬/ཿ +RTCIO_TOUCH_PAD9_REG Ԩଃܵ࢖஥ᇂ࠷թఖ +RTCIO_EXT_WAKEUP0_REG ຓ҆ߒྜ஥ᇂ࠷թఖ 0x3FF4848C ‫؀‬/ཿ +RTCIO_XTL_EXT_CTR_REG ࣖᆒ؎‫ ׈‬GPIO ൐ିჷ +RTCIO_SAR_I2C_IO_REG RTC I2C ܵ࢖࿊ᄴ 0x3FF48490 ‫؀‬/ཿ + + 0x3FF48494 ‫؀‬/ཿ + + ... ... + + 0x3FF484B8 ‫؀‬/ཿ + + 0x3FF484BC ‫؀‬/ཿ + + 0x3FF484C0 ‫؀‬/ཿ + + 0x3FF484C4 ‫؀‬/ཿ + +ুᶈྐ༏॓࠯ 60 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + +4.13 ࠷թఖ + +4.13.1 GPIO ࢌߐइᆔ࠷թఖ + +Чཬࢫও‫ݼ‬ᇏֹ֥ᆶनູཌྷؓႿ GPIO ࠎֹᆶֹ֥ᆶொ၍ਈčཌྷֹؓᆶĎđऎุࠎֹᆶ࡮ᅣࢫ 1 ༢๤‫ބ‬թԥఖ +ᇏ֥і 1-6 ຓഡֹᆶ႘ഝb࠷թఖधֹؓᆶ࡮ᅣࢫ 4.12.1 GPIO ࢌߐइᆔ࠷թఖਙіb + + Register 4.1. GPIO_OUT_REG (0x0004) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_OUT_REG GPIO0-31 ൻԛᆴbč‫؀‬/ཿĎ + + Register 4.2. GPIO_OUT_W1TS_REG (0x0008) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_OUT_W1TS_REG GPIO0-31 ൻԛᇂ໊࠷թఖbૄ၂໊ᇂ 1đᄵ GPIO_OUT_REG ᇏ֥ཌྷႋ໊ + ္߶ᇂ 1bčᆺཿĎ + + Register 4.3. GPIO_OUT_W1TC_REG (0x000c) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_OUT_W1TC_REG GPIO0-31 ൻԛౢਬ࠷թఖbૄ၂໊ᇂ 1đᄵ GPIO_OUT_REG ᇏ֥ཌྷႋ໊ + ߶ౢਬbčᆺཿĎ + + Register 4.4. GPIO_OUT1_REG (0x0010) + + (reserved) GPIO_OUT_DATA + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_OUT_DATA GPIO32-39 ൻԛᆴbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 61 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.5. GPIO_OUT1_W1TS_REG (0x0014) + + (reserved) GPIO_OUT_DATA + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_OUT_DATA GPIO32-39 ൻԛᆴᇂ໊࠷թఖbૄ၂໊ᇂ 1đᄵ GPIO_OUT1_DATA ᇏ֥ཌྷႋ໊ + ္߶ᇂ 1bčᆺ‫؀‬Ď + + Register 4.6. GPIO_OUT1_W1TC_REG (0x0018) + + (reserved) GPIO_OUT_DATA + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_OUT_DATA GPIO32-39 ൻԛᆴౢਬ࠷թఖbૄ၂໊ᇂ 1đᄵ GPIO_OUT1_DATA ᇏ֥ཌྷႋ໊ + ߶ౢਬbčᆺཿĎ + + Register 4.7. GPIO_ENABLE_REG (0x0020) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_ENABLE_REG GPIO0-31 ൻԛ൐ିbč‫؀‬/ཿĎ + + Register 4.8. GPIO_ENABLE_W1TS_REG (0x0024) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_ENABLE_W1TS_REG GPIO0-31 ൻԛ൐ିᇂ໊࠷թఖbૄ၂໊ᇂ 1đᄵ GPIO_ENABLE ᇏ֥ + ཌྷႋ္໊ᇂ 1bčᆺཿĎ + +ুᶈྐ༏॓࠯ 62 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.9. GPIO_ENABLE_W1TC_REG (0x0028) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_ENABLE_W1TC_REG GPIO0-31 ൻԛ൐ିౢਬ࠷թఖbૄ၂໊ᇂ 1đᄵ GPIO_ENABLE ᇏ + ֥ཌྷႋ໊߶ౢਬbčᆺཿĎ + + Register 4.10. GPIO_ENABLE1_REG (0x002c) + + (reserved) GPIO_ENABLE_DATA + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_ENABLE_DATA GPIO32-39 ൻԛ൐ିbč‫؀‬/ཿĎ + + Register 4.11. GPIO_ENABLE1_W1TS_REG (0x0030) + + (reserved) GPIO_ENABLE_DATA + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_ENABLE_DATA GPIO32-39 ൻԛ൐ିᇂ໊࠷թఖbૄ၂໊ᇂ 1đᄵ GPIO_ENABLE1 ᇏ֥ཌྷ + ႋ္໊ᇂ 1bčᆺཿĎ + + Register 4.12. GPIO_ENABLE1_W1TC_REG (0x0034) + + (reserved) GPIO_ENABLE_DATA + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_ENABLE_DATA GPIO32-39 ൻԛ൐ିౢਬ࠷թఖbૄ၂໊ᇂ 1đᄵ GPIO_ENABLE1 ᇏ֥ཌྷ + ႋ໊߶ౢਬbčᆺཿĎ + +ুᶈྐ༏॓࠯ 63 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.13. GPIO_STRAP_REG (0x0038) + + (reserved) GPIO_STRAPPING + +31 16 15 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x Reset + + GPIO_STRAPPING GPIO strapping ࢲ‫ݔ‬ğboot_sel_chip[5:0] ֥ bit5 ֞ bit0 ‫ٳ‬љؓႋ MTDI, GPIO0, + GPIO2, GPIO4, MTDO, GPIO5b + + Register 4.14. GPIO_IN_REG (0x003c) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_IN_REG GPIO0-31 ൻೆᆴbૄ۱ bit սі pad ֥ோຓൻೆᆴđбೂோຓႄ࢖ູۚ‫׈‬௜đՎ bit + ᆴႋູ 1đோຓႄ࢖ູ֮‫׈‬௜đՎ bit ᆴႋູ 0bčᆺ‫؀‬Ď + + Register 4.15. GPIO_IN1_REG (0x0040) + + (reserved) GPIO_IN_DATA_NEXT + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_IN_DATA_NEXT GPIO32-39 ൻೆᆴbૄ۱ bit սі pad ֥ோຓൻೆᆴbčᆺ‫؀‬Ď + + Register 4.16. GPIO_STATUS_REG (0x0044) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_STATUS_REG GPIO0-31 ᇏ؎ሑ෿࠷թఖbૄ۱ bit ‫׻‬ॖၛቔູਆ۱ CPU ֥ਆᇕᇏ؎ჷđ๝ൈ + ႋ‫ھ‬Ϝ GPIO_PINn_REG ֥ 0-4 bit ཌྷႋ֥ GPIO_STATUS_INTERRUPT ֥൐ି໊ᇂູ 1bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 64 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.17. GPIO_STATUS_W1TS_REG (0x0048) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_STATUS_W1TS_REG GPIO0-31 ᇏ ؎ ሑ ෿ ᇂ ໊ ࠷ թ ఖb ૄ ၂ ໊ ᇂ 1đ ᄵ + GPIO_STATUS_INTERRUPT ᇏ֥ཌྷႋ္໊ᇂ 1bčᆺ‫؀‬Ď + + Register 4.18. GPIO_STATUS_W1TC_REG (0x004c) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_STATUS_W1TC_REG GPIO0-31 ᇏ ؎ ሑ ෿ ౢ Ԣ ࠷ թ ఖb ૄ ၂ ໊ ᇂ 1đ ᄵ + GPIO_STATUS_INTERRUPT ᇏ֥ཌྷႋ໊߶ౢਬbčᆺཿĎ + + Register 4.19. GPIO_STATUS1_REG (0x0050) + + (reserved) GPIO_STATUS_INTERRUPT + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_STATUS_INTERRUPT GPIO32-39 ᇏ؎ሑ෿bč‫؀‬/ཿĎ + + Register 4.20. GPIO_STATUS1_W1TS_REG (0x0054) + + (reserved) GPIO_STATUS_INTERRUPT + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_STATUS_INTERRUPT GPIO32-39 ᇏ ؎ ሑ ෿ ᇂ ໊ ࠷ թ ఖb ૄ ၂ ໊ ᇂ 1đ ᄵ + GPIO_STATUS_INTERRUPT1 ᇏ֥ཌྷႋ္໊ᇂ 1bčᆺཿĎ + +ুᶈྐ༏॓࠯ 65 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.21. GPIO_STATUS1_W1TC_REG (0x0058) + + (reserved) GPIO_STATUS_INTERRUPT + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_STATUS_INTERRUPT GPIO32-39 ᇏ ؎ ሑ ෿ ౢ Ԣ ࠷ թ ఖb ૄ ၂ ໊ ᇂ 1đ ᄵ + GPIO_STATUS_INTERRUPT1 ᇏ֥ཌྷႋ໊߶ౢਬbčᆺཿĎ + + Register 4.22. GPIO_ACPU_INT_REG (0x0060) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_ACPU_INT_REG GPIO0-31 APP CPU ᇏ؎ሑ෿࠷թఖbčᆺ‫؀‬Ď + + Register 4.23. GPIO_ACPU_NMI_INT_REG (0x0064) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_ACPU_NMI_INT_REG GPIO0-31 APP CPU ٤௠зᇏ؎ሑ෿࠷թఖbčᆺ‫؀‬Ď + + Register 4.24. GPIO_PCPU_INT_REG (0x0068) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_PCPU_INT_REG GPIO0-31 PRO CPU ᇏ؎ሑ෿࠷թఖbčᆺ‫؀‬Ď + + Register 4.25. GPIO_PCPU_NMI_INT_REG (0x006c) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + GPIO_PCPU_NMI_INT_REG GPIO0-31 PRO CPU ٤௠зᇏ؎ሑ෿࠷թఖbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 66 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.26. GPIO_ACPU_INT1_REG (0x0074) + + (reserved) GPIO_APPCPU_INT + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_APPCPU_INT GPIO32-39 APP CPU ᇏ؎ሑ෿࠷թఖbčᆺ‫؀‬Ď + + Register 4.27. GPIO_ACPU_NMI_INT1_REG (0x0078) + + (reserved) GPIO_APPCPU_NMI_INT + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_APPCPU_NMI_INT GPIO32-39 APP CPU ٤௠зᇏ؎ሑ෿࠷թఖbčᆺ‫؀‬Ď + + Register 4.28. GPIO_PCPU_INT1_REG (0x007c) + + (reserved) GPIO_PROCPU_INT + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_PROCPU_INT GPIO32-39 PRO CPU ᇏ؎ሑ෿࠷թఖbčᆺ‫؀‬Ď + + Register 4.29. GPIO_PCPU_NMI_INT1_REG (0x0080) + + (reserved) GPIO_PROCPU_NMI_INT + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_PROCPU_NMI_INT GPIO32-39 PRO CPU ٤௠зᇏ؎ሑ෿࠷թఖbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 67 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.30. GPIO_PINn_REG (n: 0­39) (0x88+0x4*n) + + (reserved) GPIO_PINn_INT_EN(AreservedG) PIO_PINnG_WPIAOK_EPUINPn__EINNTA_BTLYE(PreEserved) GPIO_PI(Nrens_ePrAveDd_)DRIVER + +31 18 17 13 12 11 10 9 76 321 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x 0 0 x x x x 0 0 0 0 x 0 0 Reset + + GPIO_PINn_INT_ENA bit0ğAPP CPU ᇏ؎൐ିĠč‫؀‬/ཿĎ + bit1ğAPP CPU ٤௠зᇏ؎൐ିĠ + bit2ğPRO CPU ᇏ؎൐ିĠ + bit3ğPRO CPU ٤௠зᇏ؎൐ିb + + GPIO_PINn_WAKEUP_ENABLE GPIO ߒྜ൐ିbᆺିࡼ CPU Ֆ Light-sleep ᇏߒྜbč‫؀‬/ཿĎ + + GPIO_PINn_INT_TYPE 0: GPIO ᇏ؎ো྘Ġč‫؀‬/ཿĎ + 1ğഈശခԨ‫ؿ‬Ġ + 2ğ༯ࢆခԨ‫ؿ‬Ġ + 3ğ಩၂ခԨ‫ؿ‬Ġ + 4ğ֮‫׈‬௜Ԩ‫ؿ‬Ġ + 5ğۚ‫׈‬௜Ԩ‫ؿ‬b + + GPIO_PINn_PAD_DRIVER 0ğᆞӈൻԛĠ1ğष੐ٚൔൻԛbč‫؀‬/ཿĎ + + Register 4.31. GPIO_FUNCy_IN_SEL_CFG_REG (y: 0­255) (0x130+0x4*y) + + (reserved) GPIO_GSPIGIOy__FINU_NSCEyL_IN_INGVP_SIOE_LFUNCy_IN_SEL + +31 87 65 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset + + GPIO_SIGy_IN_SEL கਫ਼ GPIO ࢌߐइᆔb1ğ๙‫ ݖ‬GPIO ࢌߐइᆔĠ0ğᆰࢤ๙‫ ݖ‬IO_MUX ৵ࢤྐ + ‫ݼ‬აຓഡbč‫؀‬/ཿĎ + + GPIO_FUNCy_IN_INV_SEL ّሇൻೆᆴb1: ّሇĠ0: ҂ّሇbč‫؀‬/ཿĎ + + GPIO_FUNCy_IN_SEL ຓഡൻೆ y ࿊ᄴ॥ᇅbՎ໊࿊ᄴ 1 ۱ GPIO ࢌߐइᆔൻೆܵ࢖ᇏაྐ‫ݼ‬৵ࢤđ + ࠇᆀ࿊ᄴ 0x38 ა‫׈ۚޚ‬௜ൻೆྐ‫ݼ‬৵ࢤࠇᆀ࿊ᄴ 0x30 ა‫׈֮ޚ‬௜ൻೆྐ‫ݼ‬৵ࢤbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 68 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.32. GPIO_FUNCn_OUT_SEL_CFG_REG (n: 0­19, 21­23, 25­27, 32­33) (0x530+0x4*n) + + (reserved) GPIO_GFPUIONC_GFnPU_IOONC_EFNnU__ONINCEVNn___SOSEEULLT_INV_SEGL PIO_FUNCn_OUT_SEL + +31 12 11 10 9 8 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x Reset + + GPIO_FUNCn_OEN_INV_SEL 1ğّሇൻԛ൐ିྐ‫ݼ‬Ġ0ğ҂ّሇൻԛ൐ିྐ‫ݼ‬bč‫؀‬/ཿĎ + + GPIO_FUNCn_OEN_SEL 1ğ఼ᇅՖ GPIO_ENABLE_REG bit n ᇏ࿊౼ൻԛ൐ିྐ‫ݼ‬b0ğ൐ႨՖຓ + ഡ࿊౼֥ൻԛ൐ିྐ‫ݼ‬bč‫؀‬/ཿĎ + + GPIO_FUNCn_OUT_INV_SEL 1ğّሇൻԛᆴĠ0ğ҂ّሇൻԛᆴbč‫؀‬/ཿĎ + + GPIO_FUNCn_OUT_SEL GPIO ൻ ԛ n ֥ ࿊ ᄴ ॥ ᇅb ᆴ ູ s (0<=s<256) ৵ ࢤ ຓ ഡ + ൻ ԛ s ა GPIO ൻ ԛ nb ᆴ ູ 256 ࿊ ᄴ GPIO_OUT_REG/GPIO_OUT1_REG ‫ބ‬ + GPIO_ENABLE_REG/GPIO_ENABLE1_REG ֥ bit n ቓູൻԛᆴ‫ބ‬ൻԛ൐ିbč‫؀‬/ཿĎ + +4.13.2 IO MUX ࠷թఖ + +Чཬࢫও‫ݼ‬ᇏֹ֥ᆶनູཌྷؓႿ IO MUX ࠎֹᆶֹ֥ᆶொ၍ਈčཌྷֹؓᆶĎđऎุࠎֹᆶ࡮ᅣࢫ 1 ༢๤‫ބ‬թԥఖ +ᇏ֥і 1-6 ຓഡֹᆶ႘ഝb࠷թఖधֹؓᆶ࡮ᅣࢫ 4.12.2 IO MUX ࠷թఖਙіb + + Register 4.33. IO_MUX_PIN_CTRL (0x3FF49000) + + (reserved) PIN_CTRL_CLK3 PIN_CTRL_CLK2 PIN_CTRL_CLK1 + +31 12 11 87 43 0 + + 0x0 0x0 0x0 0x0 Reset + + ေࡼ I2S0 ຓഡൈᇒ (I2S0_CLK) ൻԛ֞ğ + CLK_OUT1đ஥ᇂ PIN_CTRL[3:0] = 0x0Ġ + CLK_OUT2đ஥ᇂ PIN_CTRL[3:0] = 0x0 ౏ PIN_CTRL[7:4] = 0x0Ġ + CLK_OUT3đ஥ᇂ PIN_CTRL[3:0] = 0x0 ౏ PIN_CTRL[11:8] = 0x0b + ေࡼ I2S1 ຓഡൈᇒ (I2S1_CLK) ൻԛ֞ğ + CLK_OUT1đ஥ᇂ PIN_CTRL[3:0] = 0xFĠ + CLK_OUT2đ஥ᇂ PIN_CTRL[3:0] = 0xF ౏ PIN_CTRL[7:4] = 0x0Ġ + CLK_OUT3đ஥ᇂ PIN_CTRL[3:0] = 0xF ౏ PIN_CTRL[11:8] = 0x0b + + ေࡼ APLL ൻԛ֞ + CLK_OUT1đ஥ᇂ PIN_CTRL[3:0] = 0x6Ġ + CLK_OUT2đ஥ᇂ PIN_CTRL[3:0] = 0x6 ౏ PIN_CTRL[7:4] = 0x6Ġ + CLK_OUT3đ஥ᇂ PIN_CTRL[3:0] = 0x6 ౏ PIN_CTRL[11:8] = 0x6bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 69 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + ඪૼğ + • ࣇᆦӻഈඍ஥ᇂቆ‫ކ‬đࠧĠ + – ࣇᆦӻൻԛൈᇒğI2S0/1_CLK ‫ ބ‬APLL; + – ࣇᆦӻൻԛܵ࢖ğCLK_OUT1-3 + • CLK_OUT1-3 ॖᄝ IO_MUX Pad ਙіᇏҰ࿘b + + Register 4.34. IO_MUX_x_REG (x: GPIO0­GPIO39) (0x10+4*x) + + (reserved) MCU_SEL FUN_DRFVUN_IFEUN_WFUPNU_WPMDCU_DRMVCU_MIECU_MWCPUU_SWLPP_DSMECLU_OE + +31 15 14 12 11 10 9 8 7 6 54 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x2 0 0 0 0x0 0 0 0 0 0 Reset + + MCU_SEL ູྐ‫ݼ‬࿊ᄴ IO_MUX ‫ିۿ‬b0ğ࿊ᄴ‫ ିۿ‬0Ġ1ğ࿊ᄴ‫ ିۿ‬1ĠၛՎো๷bč‫؀‬/ཿĎ + FUN_DRV ࿊ᄴ౺‫఼׮‬؇đᆴᄀնđ఼؇ᄀնbؓႿ GPIO34-39đFUN_DRV ‫ ູޚ‬0bऎุ౺‫఼׮‬؇ + + ౨ҕॉuESP32 ࠯ඌܿ۬඀vᇏoܵ࢖ౢֆඪૼpֻ֥ 8 ่bč‫؀‬/ཿĎ + FUN_IE pad ֥ൻೆ൐ିb1ğൻೆ൐ିĠ0ğൻೆܱоbč‫؀‬/ཿĎ + FUN_WPU pad ֥ഈঘ൐ିb1ğଽ҆ഈঘ൐ିĠ0ğଽ҆ഈঘܱоbႮႿ GPIO34-39 ࣇॖႨቔൻೆ + + ܵ࢖đ҂ऎСൻԛ౺‫ࠇ׮‬ଽᇂഈঘ/༯ঘ‫׈‬ਫ਼đၹՎᆃུܵ࢖֥ FUN_WPU ‫ ູޚ‬0bč‫؀‬/ཿĎ + FUN_WPD pad ֥༯ঘ൐ିb1ğଽ҆༯ঘ൐ିĠ0ğଽ҆༯ঘܱоbႮႿ GPIO34-39 ࣇॖႨቔൻ + + ೆđ҂ऎСൻԛ౺‫ࠇ׮‬ଽᇂഈঘ/༯ঘ‫׈‬ਫ਼đၹՎᆃུܵ࢖֥ FUN_WPD ‫ ູޚ‬0bč‫؀‬/ཿĎ + MCU_DRV ඤ૤ଆൔ༯࿊ᄴ pad ֥౺‫఼׮‬؇đᆴᄀնđ఼؇ᄀնbč‫؀‬/ཿĎ + MCU_IE ඤ૤ଆൔ༯ pad ֥ൻೆ൐ିb1ğൻೆ൐ିĠ0ğൻೆܱоbč‫؀‬/ཿĎ + MCU_WPU ඤ૤ଆൔ༯ pad ֥ഈঘ൐ିb1ğଽ҆ഈঘ൐ିĠ0ğଽ҆ഈঘܱоbč‫؀‬/ཿĎ + MCU_WPD ඤ૤ଆൔ༯ pad ֥༯ঘ൐ିb1ğଽ҆༯ঘ൐ିĠ0ğଽ҆༯ঘܱоbč‫؀‬/ཿĎ + SLP_SEL pad ֥ඤ૤ଆൔ࿊ᄴbᇂ 1 ࡼ൐ିඤ૤ଆൔbč‫؀‬/ཿĎ + MCU_OE ඤ૤ଆൔ༯ pad ֥ൻԛ൐ିb1: ൻԛ൐ିĠ2: ൻԛܱоbč‫؀‬/ཿĎ + +4.13.3 RTC IO MUX ࠷թఖ + +Чཬࢫও‫ݼ‬ᇏֹ֥ᆶनູཌྷؓႿ (RTC ࠎֹᆶ + 0x0400) ֹ֥ᆶொ၍ਈčཌྷֹؓᆶĎbRTC ࠎֹᆶ࡮ᅣࢫ 1 ༢๤ +‫ބ‬թԥఖ ᇏ֥і 1-6 ຓഡֹᆶ႘ഝb࠷թఖधֹؓᆶ࡮ᅣࢫ 4.12.3 RTC IO MUX ࠷թఖਙіb + +ুᶈྐ༏॓࠯ 70 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.35. RTCIO_RTC_GPIO_OUT_REG (0x0000) + + RTCIO_RTC_GPIO_OUT_DATA (reserved) + +31 14 13 0 + +x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_RTC_GPIO_OUT_DATA GPIO0-17 ൻԛ࠷թఖbBit14 ൞ GPIO[0]đbit15 ൞ GPIO[1]đၛՎ + ো๷bč‫؀‬/ཿĎ + + Register 4.36. RTCIO_RTC_GPIO_OUT_W1TS_REG (0x0004) + + RTCIO_RTC_GPIO_OUT_DATA_W1TS (reserved) + +31 14 13 0 + +x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_RTC_GPIO_OUT_DATA_W1TS GPIO0-17 ൻ ԛ ഡ ᇂ ࠷ թ ఖb ૄ ၂ ໊ ᇂ 1đ ᄵ RT- + CIO_RTC_GPIO_OUT ᇏ֥ཌྷႋ္໊߶ᇂ 1bčᆺཿĎ + + Register 4.37. RTCIO_RTC_GPIO_OUT_W1TC_REG (0x0008) + + RTCIO_RTC_GPIO_OUT_DATA_W1TC (reserved) + +31 14 13 0 + +x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_RTC_GPIO_OUT_DATA_W1TC GPIO0-17 ൻ ԛ ౢ Ԣ ࠷ թ ఖb ૄ ၂ ໊ ᇂ 1đ ᄵ RT- + CIO_RTC_GPIO_OUT ᇏ֥ཌྷႋ໊߶ౢਬbčᆺཿĎ + +ুᶈྐ༏॓࠯ 71 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.38. RTCIO_RTC_GPIO_ENABLE_REG (0x000C) + + RTCIO_RTC_GPIO_ENABLE (reserved) + +31 14 13 0 + +x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_RTC_GPIO_ENABLE GPIO0-17 ൻԛ൐ିbBit14 ൞ GPIO[0]đbit15 ൞ GPIO[1]đၛՎো๷b + 1 սіՎ GPIO ູൻԛ१bč‫؀‬/ཿĎ + + Register 4.39. RTCIO_RTC_GPIO_ENABLE_W1TS_REG (0x0010) + + RTCIO_RTC_GPIO_ENABLE_W1TS (reserved) + +31 14 13 0 + +x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_RTC_GPIO_ENABLE_W1TS GPIO0-17 ൻ ԛ ൐ ି ഡ ᇂ ࠷ թ ఖb ૄ ၂ ໊ ᇂ 1đ ᄵ RT- + CIO_RTC_GPIO_ENABLE ᇏ֥ཌྷႋ္໊߶ᇂ 1bčᆺཿĎ + + Register 4.40. RTCIO_RTC_GPIO_ENABLE_W1TC_REG (0x0014) + + RTCIO_RTC_GPIO_ENABLE_W1TC (reserved) + +31 14 13 0 + +x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_RTC_GPIO_ENABLE_W1TC GPIO0-17 ൻ ԛ ൐ ି ౢ Ԣ ࠷ թ ఖb ૄ ၂ ໊ ᇂ 1đ ᄵ RT- + CIO_RTC_GPIO_ENABLE ᇏ֥ཌྷႋ໊߶ౢਬbčᆺཿĎ + +ুᶈྐ༏॓࠯ 72 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.41. RTCIO_RTC_GPIO_STATUS_REG (0x0018) + + RTCIO_RTC_GPIO_STATUS_INT (reserved) + +31 14 13 0 + +x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_RTC_GPIO_STATUS_INT GPIO0-17 ᇏ؎ሑ෿bBit14 ൞ GPIO[0]đbit15 ൞ GPIO[1]đၛՎ + ো๷bՎ࠷թఖႋ๝ൈ‫ ބ‬RTCIO_RTC_GPIO_PINn_REG ֥ RTCIO_RTC_GPIO_PINn_INT_TYPE + ᇏ؎ো྘஥‫ކ‬൐Ⴈđ1 սіႵཌྷႋᇏ؎đ0 սіીႵᇏ؎bč‫؀‬/ཿĎ + + Register 4.42. RTCIO_RTC_GPIO_STATUS_W1TS_REG (0x001C) + + RTCIO_RTC_GPIO_STATUS_INT_W1TS (reserved) + +31 14 13 0 + +x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_RTC_GPIO_STATUS_INT_W1TS GPIO0-17 ᇏ ؎ ഡ ᇂ ࠷ թ ఖb ૄ ၂ ໊ ᇂ 1đ ᄵ RT- + CIO_RTC_GPIO_STATUS_INT ᇏ֥ཌྷႋ္໊߶ᇂ 1bčᆺཿĎ + + Register 4.43. RTCIO_RTC_GPIO_STATUS_W1TC_REG (0x0020) + + RTCIO_RTC_GPIO_STATUS_INT_W1TC (reserved) + +31 14 13 0 + +x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_RTC_GPIO_STATUS_INT_W1TC GPIO0-17 ᇏ ؎ ౢ Ԣ ࠷ թ ఖb ૄ ၂ ໊ ᇂ 1đ ᄵ RT- + CIO_RTC_GPIO_STATUS_INT ᇏ֥ཌྷႋ໊߶ౢਬbčᆺཿĎ + +ুᶈྐ༏॓࠯ 73 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.44. RTCIO_RTC_GPIO_IN_REG (0x0024) + + RTCIO_RTC_GPIO_IN_NEXT (reserved) + +31 14 13 0 + +x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_RTC_GPIO_IN_NEXT GPIO0-17 ൻೆᆴbBit14 ൞ GPIO[0]đbit15 ൞ GPIO[1]đၛՎো๷b + ૄ۱ bit սі pad ֥ோຓൻೆᆴđбೂோຓႄ࢖ູۚ‫׈‬௜đՎ bit ᆴႋູ 1đோຓႄ࢖ູ֮‫׈‬௜đ + Վ bit ᆴႋູ 0bčᆺ‫؀‬Ď + + Register 4.45. RTCIO_RTC_GPIO_PINn_REG (n: 0­17) (28+4*n) + + (reserved) RTCIO_RTCR_TGCPIOIO__RPTICN_nG_WPIAOK_(EPreUINsPen_r_vEIeNNdTA)_BTLYEPRETCIO_R(rTeCse_rGvePdIO) _PINn_PAD_DRIVER + +31 11 10 9 76 321 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 0 0 0 x 0 0 Reset + + RTCIO_RTC_GPIO_PINn_WAKEUP_ENABLE GPIO ߒྜ൐ିbᆺିࡼԩႿ Light-sleep ֥ ESP32 + ߒྜbč‫؀‬/ཿĎ + + RTCIO_RTC_GPIO_PINn_INT_TYPE GPIO ᇏ؎ো྘࿊ᄴbč‫؀‬/ཿĎ + 0ğGPIO ᇏ؎ܱоĠ + 1ğഈശခԨ‫ؿ‬Ġ + 2ğ༯ࢆခԨ‫ؿ‬Ġ + 3ğ಩၂ခԨ‫ؿ‬Ġ + 4ğ֮‫׈‬௜Ԩ‫ؿ‬Ġ + 5ğۚ‫׈‬௜Ԩ‫ؿ‬b + + RTCIO_RTC_GPIO_PINn_PAD_DRIVER Pad ౺‫׮‬ఖ࿊ᄴb0ğᆞӈൻԛĠ1ğष੐ଆൔbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 74 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.46. RTCIO_DIG_PAD_HOLD_REG (0x0074) + +31 0 + + 0 Reset + +RTCIO_DIG_PAD_HOLD_REG ࿊ᄴଧ၂۱ඔሳ pad ᇂႿ hold ሑ෿b0: ᄍྸᆞӈҠቔĠ1: ᇂႿ hold + ሑ෿bč‫؀‬/ཿĎ + + ଀ӫ ૭ඍ + Bit[0] pad U0RTD Hold ‫ିۿ‬൐ି໊ + Bit[1] pad U0TXD Hold ‫ିۿ‬൐ି໊ + Bit[2] pad SD_CLK Hold ‫ିۿ‬൐ି໊ + Bit[3] pad SD_DATA0 Hold ‫ିۿ‬൐ି໊ + Bit[4] pad SD_DATA1 Hold ‫ିۿ‬൐ି໊ + Bit[5] pad SD_DATA2 Hold ‫ିۿ‬൐ି໊ + Bit[6] pad SD_DATA3 Hold ‫ିۿ‬൐ି໊ + Bit[7] pad SD_CMD Hold ‫ିۿ‬൐ି໊ + Bit[8] pad GPIO5 Hold ‫ିۿ‬൐ି໊ + Bit[9] pad GPIO16 Hold ‫ିۿ‬൐ି໊ + Bit[10] pad GPIO17 Hold ‫ିۿ‬൐ି໊ + Bit[11] pad GPIO18 Hold ‫ିۿ‬൐ି໊ + Bit[12] pad GPIO19 Hold ‫ିۿ‬൐ି໊ + Bit[13] pad GPIO20 Hold ‫ିۿ‬൐ି໊ + Bit[14] pad GPIO21 Hold ‫ିۿ‬൐ି໊ + Bit[15] pad GPIO22 Hold ‫ିۿ‬൐ି໊ + Bit[16] pad GPIO23 Hold ‫ିۿ‬൐ି໊ + + Register 4.47. RTCIO_HALL_SENS_REG (0x0078) + +RTCIOR_THCAIOLL__HXAPLDL__HPHALALSE (reserved) + +31 30 29 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +RTCIO_HALL_XPD_HALL ۳ࠉ‫غ‬Ԯ‫ۋ‬ఖഈ‫׈‬đ৵ࢤ VP ‫ ބ‬VNbč‫؀‬/ཿĎ +RTCIO_HALL_PHASE ّሇࠉ‫غ‬Ԯ‫ۋ‬ఖ֥ࠞྟbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 75 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.48. RTCIO_SENSOR_PADS_REG (0x007C) + +RTCIOR_TSCEIONRS_TSOCERIONR_S_STSOECENRIONRS_S_STESOEC1ENR_IONHRS_S_SOTESOEC2LENR_DIONHRS_S_SOTESOEC3LENR_DIONHRS_S_SOTESOEC4LENR_DIONHS_S_SOESOER1LENR_TDNMCS_SSEIUOOE2X_NR__SMRS_SESTEEUNEC3LXSN_I_OOMRSS_RTEEUSC_4LXES_I_ONMERSS_NTEUSOCSLXEREI_ON_1SS_S_ESOFERLEUNRTNNCS_SS_EIOOSE1_ENR_SSLRS_ELSTENPEC1S_N_IOSOSRSE_LRTESLPC_1E_S_IONIFEREUS_NTSONCSER_EIONI_2ES_S_SOFEREUNRTNNCS_SS_EIOOSE2_ENR_SSLRS_ELSTENPEC2S_N_IOSOSRSE_LRTESLPC_2E_S_IONIFEREUS_NTSONCSER_EIONI_3ES_S_SOFEREUNRTNNCS_SS_EIOOSE3_ENR_SSLRS_ELSTENPEC3S_N_IOSOSRSE_LRTESLPC_3E_S_IONIFEREUS_NTSONCSER_EIONI_4ES_S_SOFEEUNRNNS_SS_EOSE(4reENR_sSLS_eLSErPvE4e_N_dSSS)ELELP4__IFEUN_IE + +31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 5 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +RTCIO_SENSOR_SENSEn_HOLD ᇂ 1 ЌӻԮ‫ۋ‬ఖ n ֥ൻԛᆴb0: ᆞӈҠቔbč‫؀‬/ཿĎ +RTCIO_SENSOR_SENSEn_MUX_SEL 1ğ৵ࢤԮ‫ۋ‬ఖ n ა RTC ଆॶĠ0ğ৵ࢤԮ‫ۋ‬ఖ n აඔሳ + + IO_MUXbč‫؀‬/ཿĎ + +RTCIO_SENSOR_SENSEn_FUN_SEL ࿊ᄴ RTC IO_MUX ‫ିۿ‬b0ğ࿊ᄴ Function 0bč‫؀‬/ཿĎ +RTCIO_SENSOR_SENSEn_SLP_SEL pad ֥ඤ૤ଆൔ࿊ᄴྐ‫ݼ‬bpad ࣉೆඤ૤ଆൔൈႋࡼՎ bit ᇂ + + 1 bč‫؀‬/ཿĎ + +RTCIO_SENSOR_SENSEn_SLP_IE ඤ૤ଆൔ༯ pad ֥ൻೆ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ +RTCIO_SENSOR_SENSEn_FUN_IE pad ֥ൻೆ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ + + Register 4.49. RTCIO_ADC_PAD_REG (0x0080) + +RTCIOR_TACDIOCR__TAACDDIOCCR__1TAA_CDDHIOCCO__2LAA_RDDDHTCCOC_1ILOA_D_DMACRUD2TXC_C_M_SIOAREU_DLTXACC_D1SIOC_RE_F_LTAUACDDNIOCC__S_1AAE_RDDSLTCLCCP_1IOA__S_DSAELCRLDP1TC__CIF_EIOUAR_DNTAC_CDI2EIOC_R_F_TAUACDDNIOCC__S_2AAE_DDSLCLCP_2A__SDSELCLP2__IFEUN_IE (reserved) + +31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +RTCIO_ADC_ADCn_HOLD ᇂ 1 ࡼЌ਽ pad ֥ൻԛᆴđ0: ᆞӈҠቔbč‫؀‬/ཿĎ +RTCIO_ADC_ADCn_MUX_SEL 0ğ৵ࢤ pad აඔሳ IO_MUXb1ğ৵ࢤ pad ა RTC ଆॶbč‫؀‬/ཿĎ +RTCIO_ADC_ADCn_FUN_SEL ࿊ᄴ RTC ‫ିۿ‬b0ğ࿊ᄴ Function 0Ġ3ğ࿊ᄴ Function 1bč‫؀‬/ཿĎ +RTCIO_ADC_ADCn_SLP_SEL pad ֥ඤ૤ଆൔ࿊ᄴྐ‫ݼ‬bᇂ 1 pad ࡼࣉೆඤ૤ଆൔbč‫؀‬/ཿĎ +RTCIO_ADC_ADCn_SLP_IE ඤ૤ଆൔ༯ pad ֥ൻೆ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ +RTCIO_ADC_ADCn_FUN_IE pad ֥ൻೆ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 76 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.50. RTCIO_PAD_DAC1_REG (0x0084) + +RTCIO_PRATDC_IPORD_TPACACIDO1R___TPPDCADRIDOAV_C_PP1AD_DHA_COP1LD_DRADCE1_RUERTCIO_PAD_PDAC1_DACRTCIOR_TPCAIDO__PPRADTDAC_CIPO1D__PXARAPCTDD1C___IPDOMRDA_UTPACCXAC_IDO1SR___ETPPFLCUADIDONAR_C__TPPS1CADE_IDOSLARL_C_TPPP1CAD__ISDOSAEL_C_LPPP1AD__IDSAEL_CPP1D__OFAUECN1__IDEAC_XPD(r_eFseOrRveCdE) + +31 30 29 28 27 26 19 18 17 16 15 14 13 12 11 10 9 0 + +2 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +RTCIO_PAD_PDAC1_DRV ࿊ᄴ pad ֥౺‫఼׮‬؇bč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_HOLD ᇂ 1 ࡼЌ਽ pad ֥ൻԛᆴđ0: ᆞӈҠቔbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_RDE 1ğ༯ঘ൐ିĠ0: ༯ঘܱоbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_RUE 1ğഈঘ൐ିĠ0: ഈঘܱоbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_DAC PAD DAC1 ൻԛᆴbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_XPD_DAC ۳ DAC1 ഈ‫׈‬b၂Ϯ‫ط‬࿽đDAC ഈ‫׈‬ൈđPDAC1 ႋ‫ھ‬ᇂູ೘෿đ + + ࠧ IE=0aOE=0aRDE=0aRUE=0bč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_MUX_SEL 0ğ৵ࢤ pad აඔሳ IO_MUXb1ğ৵ࢤ RTC ଆॶbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_FUN_SEL pad ֥‫ିۿ‬࿊ᄴྐ‫ݼ‬bč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_SLP_SEL pad ֥ඤ૤ଆൔ࿊ᄴྐ‫ݼ‬bᇂ 1 ᄵ pad ࣉೆඤ૤ଆൔbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_SLP_IE ඤ૤ଆൔ༯ pad ֥ൻೆ൐ିb1: ൐ିĠ0: ܱоbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_SLP_OE pad ֥ൻԛ൐ିb1: ൐ିĠ0: ܱоbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_FUN_IE pad ֥ൻೆ൐ିb1: ൐ିĠ0: ܱоbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC1_DAC_XPD_FORCE ۳ DAC1 ഈ‫׈‬b၂Ϯ‫ط‬࿽đDAC ഈ‫׈‬ൈđPDAC1 ႋ‫ھ‬ᇂ + + ູ೘෿đࠧ IE=0aOE=0aRDE=0aRUE=0bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 77 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.51. RTCIO_PAD_DAC2_REG (0x0088) + +RTCIO_PRATDC_IPORD_TPACACIDO2R___TPPDCADRIDOAV_C_PP2AD_DHA_COP2LD_DRADCE2_RUERTCIO_PAD_PDAC2_DACRTCIOR_TPCAIDO__PPRADTDAC_CIPO2D__PXARAPCTDD2C___IPDOMRDA_UTPACCXAC_IDO2SR___ETPPFLCUADIDONAR_C__TPPS2CADE_IDOSLARL_C_TPPP2CAD__ISDOSAEL_C_LPPP2AD__IDSAEL_CPP2D__OFAUECN2__IDEAC_XPD(r_eFseOrRveCdE) + +31 30 29 28 27 26 19 18 17 16 15 14 13 12 11 10 9 0 + +2 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +RTCIO_PAD_PDAC2_DRV ࿊ᄴ pad ֥౺‫఼׮‬؇bč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_HOLD ᇂ 1 ࡼЌ਽ pad ֥ൻԛᆴđ0ğᆞӈҠቔbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_RDE 1ğ༯ঘ൐ିĠ0ğ༯ঘܱоbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_RUE 1ğഈঘ൐ିĠ0ğഈঘܱоbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_DAC PAD DAC2 ൻԛᆴbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_XPD_DAC ۳ DAC2 ഈ‫׈‬b၂Ϯ‫ط‬࿽đDAC ഈ‫׈‬ൈđPDAC2 ႋ‫ھ‬ᇂູ೘෿đ + + ࠧ IE=0, OE=0, RDE=0, RUE=0bč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_MUX_SEL 0ğ৵ࢤ pad აඔሳ IO_MUXb1ğ৵ࢤ RTC ଆॶbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_FUN_SEL ࿊ᄴ pad ֥ RTC ‫ିۿ‬đ0ğ࿊ᄴ Function 0bč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_SLP_SEL pad ֥ඤ૤ଆൔ࿊ᄴྐ‫ݼ‬bᇂ 1 ᄵ pad ࣉೆඤ૤ଆൔbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_SLP_IE ඤ૤ଆൔ༯ pad ֥ൻೆ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_SLP_OE pad ֥ൻԛ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_FUN_IE pad ֥ൻೆ൐ିb1ğ൐ିĠ0: ܱоbč‫؀‬/ཿĎ +RTCIO_PAD_PDAC2_DAC_XPD_FORCE ۳ DAC2 ഈ‫׈‬b၂Ϯ‫ط‬࿽đDAC ഈ‫׈‬ൈđPDAC2 ႋ‫ھ‬ᇂ + + ູ೘෿đࠧ IE=0, OE=0, RDE=0, RUE=0bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 78 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.52. RTCIO_XTAL_32K_PAD_REG (0x008C) + +RTCIO_XRTTACLI_ORX_3TX2CTNIAOR_L_DT_XRCXT3VIAO2L_N_XR_XTH3TA2OCLNIL_O_XD_R3XD2RTNETAC_LRI_OURX_3ETX2CTPIAO_RLD_T_XRCXTV3IAO2L_P_X_RXTH3TAO2CLPLI_O_DXR_3XD2RTPETA_CLRI_OURD_ETAXCCTIA_ORXL_TT_XACXTLPIAO_DL3___X2RXXTKT3TAA2CLLNI_O__X3_M32X2RUKTPTAX_C_LMSI_ORXUE_3TLXX2C_TNSIAOR_EL_FLT_XUCXTN3IAO2R_L_SNT_XE_CXTSL3IAOL2LP_N_X_R_XTSS3TAEL2CLLPNI_O__XI_SE3XL2RTPNTA_C_LOFI_OUERX_N3TX2_CTIPIEAO_RLF_T_XUCXTN3IAO_2RLS_PT_XE_CXTSL3IAOL2LP_P_X__RXSTS3TAEL2CLLPPI_O__XIS_E3XL2TPPA__RLOFT_UECDNIRO_EI_ESX(_rTeXAsTLeA_rvLDe_Bd3I)2AKS_XTAL_32K + +31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 6 54 32 10 + +2 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset + +RTCIO_XTAL_X32N_DRV ࿊ᄴ pad ֥౺‫఼׮‬؇bč‫؀‬/ཿĎ +RTCIO_XTAL_X32N_HOLD ᇂ 1 ࡼЌ਽ pad ֥ൻԛᆴđ0ğᆞӈҠቔbč‫؀‬/ཿĎ +RTCIO_XTAL_X32N_RDE 1ğ༯ঘ൐ିĠ0: ༯ঘܱоbč‫؀‬/ཿĎ +RTCIO_XTAL_X32N_RUE 1ğഈঘ൐ିĠ0: ഈঘܱоbč‫؀‬/ཿĎ +RTCIO_XTAL_X32P_DRV ࿊ᄴ pad ֥౺‫఼׮‬؇bč‫؀‬/ཿĎ +RTCIO_XTAL_X32P_HOLD ᇂ 1 ࡼЌ਽ pad ֥ൻԛᆴđ0ğᆞӈҠቔbč‫؀‬/ཿĎ +RTCIO_XTAL_X32P_RDE 1ğ༯ঘ൐ିĠ0ğ༯ঘܱоbč‫؀‬/ཿĎ +RTCIO_XTAL_X32P_RUE 1ğഈঘ൐ିĠ0ğഈঘܱоbč‫؀‬/ཿĎ +RTCIO_XTAL_DAC_XTAL_32K 32K XTAL ொᇂ‫׈‬ੀ DAC ᆴbč‫؀‬/ཿĎ +RTCIO_XTAL_XPD_XTAL_32K ۳ 32 kHz ࣖᆒ๙‫׈‬bč‫؀‬/ཿĎ +RTCIO_XTAL_X32N_MUX_SEL 0: ৵ࢤ X32N აඔሳ IO_MUXĠ1ğ৵ࢤ RTC ଆॶbč‫؀‬/ཿĎ +RTCIO_XTAL_X32P_MUX_SEL 0ğ৵ࢤ X32P pad აඔሳ IO_MUXĠ1ğ৵ࢤ RTC ଆॶbč‫؀‬/ཿĎ +RTCIO_XTAL_X32N_FUN_SEL ࿊ᄴ pad ֥ RTC ‫ିۿ‬đ0ğ࿊ᄴ Function 0bč‫؀‬/ཿĎ +RTCIO_XTAL_X32N_SLP_SEL pad ֥ඤ૤ଆൔ࿊ᄴྐ‫ݼ‬bᇂ 1 ᄵ pad ࣉೆඤ૤ଆൔbč‫؀‬/ཿĎ +RTCIO_XTAL_X32N_SLP_IE ඤ૤ଆൔ༯ pad ֥ൻೆ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ +RTCIO_XTAL_X32N_SLP_OE pad ֥ൻԛ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ +RTCIO_XTAL_X32N_FUN_IE pad ֥ൻೆ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ +RTCIO_XTAL_X32P_FUN_SEL ࿊ᄴ pad ֥ RTC ‫ିۿ‬đ0ğ࿊ᄴ Function 0Ġ1ğ࿊ᄴ Function + + 1bč‫؀‬/ཿĎ +RTCIO_XTAL_X32P_SLP_SEL ඤ૤ଆൔ࿊ᄴđᇂ 1 ᄵ pad ࣉೆඤ૤ଆൔbč‫؀‬/ཿĎ +RTCIO_XTAL_X32P_SLP_IE ඤ૤ଆൔ༯ pad ֥ൻೆ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ +RTCIO_XTAL_X32P_SLP_OE ඤ૤ଆൔ༯ pad ֥ൻԛ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ +RTCIO_XTAL_X32P_FUN_IE pad ֥ൻೆ൐ିb1ğ൐ିĠ0ğܱоbč‫؀‬/ཿĎ +RTCIO_XTAL_DRES_XTAL_32K 32K XTAL ‫׈‬ቅொᇂ॥ᇅbč‫؀‬/ཿĎ +RTCIO_XTAL_DBIAS_XTAL_32K 32K XTAL ሱொᇂҕॉ॥ᇅbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 79 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.53. RTCIO_TOUCH_CFG_REG (0x0090) + +RTCIO_TROTUCCIOH__TXOPUDRCT_BHCI_IAODS_RTEOFURHCTHC_IOD_RTEOFURLCTHC_IOD_RTAONUGCEH_DCUR (reserved) + +31 30 29 28 27 26 25 24 23 22 0 + +0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_TOUCH_XPD_BIAS ԨଃԮ‫ۋ‬ఖொᇂഈ‫໊׈‬b1ğഈ‫׈‬Ġ0ğ؎‫׈‬bč‫؀‬/ཿĎ + RTCIO_TOUCH_DREFH ԨଃԮ‫ۋ‬ఖѯ‫׈פ‬࿢bč‫؀‬/ཿĎ + RTCIO_TOUCH_DREFL ԨଃԮ‫ۋ‬ఖѯָ‫׈‬࿢bč‫؀‬/ཿĎ + RTCIO_TOUCH_DRANGE ԨଃԮ‫ۋ‬ఖ‫׈‬࿢э‫ຶٓ׮‬bč‫؀‬/ཿĎ + RTCIO_TOUCH_DCUR ԨଃԮ‫ۋ‬ఖொᇂ‫׈‬ੀb֒ BIAS_SLEEP ൐ିൈđॖၛࣉྛഡᇂbč‫؀‬/ཿĎ + + Register 4.54. RTCIO_TOUCH_PADn_REG (n: 0­9) (94+4*n) + + (reserved) RTCIO_TOURCTHC_IOPR_ATTDCOnIOU_RD_CTTAHCOC_IOUPR_CATTDHCOn_IOU_PS_CATTDRHOAnT_RU_PCTTCAIOIDHE__n_TO_POXAPPUDTDCn_HT_OP_AGDPn_IOFUN_SEL (reserved) + +31 26 25 23 22 21 20 19 18 17 16 0 + +0 0 0 0 0 0 0x4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_TOUCH_PADn_DAC ԨଃԮ‫ۋ‬ఖོੱ॥ᇅbૄ۱Ԩଃ pad ູ 3-bitđଏಪູ 100bč‫؀‬/ཿĎ + RTCIO_TOUCH_PADn_START ఓ‫׮‬ԨଃԮ‫ۋ‬ఖbč‫؀‬/ཿĎ + RTCIO_TOUCH_PADn_TIE_OPT ଏಪԨଃԮ‫ۋ‬ఖԚ൓‫׈‬࿢໊b0ğ0VĠ1ğVDD_RTC ֥‫׈‬࿢bč‫؀‬/ཿĎ + RTCIO_TOUCH_PADn_XPD ԨଃԮ‫ۋ‬ఖഈ‫׈‬bč‫؀‬/ཿĎ + RTCIO_TOUCH_PADn_TO_GPIO ৵ࢤ RTC pad ൻೆაඔሳ pad ൻೆđॖၛᇂ 0bč‫؀‬/ཿĎ + RTCIO_TOUCH_PADn_FUN_SEL ࿊ᄴ RTC pad ֥‫ିۿ‬b0ğRTC Function 0bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 80 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) + + Register 4.55. RTCIO_EXT_WAKEUP0_REG (0x00BC) + + RTCIO_EXT_WAKEUP0_SEL (reserved) + +31 27 26 0 + + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_EXT_WAKEUP0_SEL GPIO[0-17] ॖၛႨႿࡼྉோՖඤ૤ଆൔᇏߒྜbՎ࠷թఖ࿊ᄴ pad + ჷࡼྉோՖ Deep/Light-sleep ଆൔᇏߒྜb0ğ࿊ᄴ GPIO0Ġ1ğ࿊ᄴ GPIO2đၛՎো๷bč‫؀‬/ཿĎ + + Register 4.56. RTCIO_XTL_EXT_CTR_REG (0x00C0) + + RTCIO_XTL_EXT_CTR_SEL (reserved) + +31 27 26 0 + + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_XTL_EXT_CTR_SEL ࿊ᄴඤ૤ଆൔ༯ຓ҆ࣖᆒ؎‫׈‬൐ିჷb0ğ࿊ᄴ GPIO0Ġ1ğ࿊ᄴ GPIO2đ + ၛՎো๷bФ࿊ᄴܵ࢖֥ᆴၳࠇ RTC_CNTL_XTL_EXT_CTR_LV ഈ֥આࠠᆴ൞ࣖᆒ؎‫׈‬൐ିྐ + ‫ݼ‬bč‫؀‬/ཿĎ + + Register 4.57. RTCIO_SAR_I2C_IO_REG (0x00C4) + + RTCIO_SARR_TI2CCIO__SSDAAR__SIE2CL _SCL_SEL (reserved) + +31 30 29 28 27 0 + + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTCIO_SAR_I2C_SDA_SEL ࿊ᄴਸ਼၂۱ pad ቔູ RTC I2C SDA ྐ‫ݼ‬b0ğ࿊ᄴ TOUCH_PAD[1]Ġ1ğ + ࿊ᄴ TOUCH_PAD[3]bଏಪᆴູ 0bč‫؀‬/ཿĎ + + RTCIO_SAR_I2C_SCL_SEL ࿊ᄴਸ਼၂۱ pad ቔູ RTC I2C SCL signalb0ğ࿊ᄴ TOUCH_PAD[0]Ġ + 1ğ࿊ᄴ TOUCH_PAD[2]bଏಪᆴູ 0bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 81 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + +5 DPort ࠷թఖ + +5.1 ‫ۀ‬ඍ + +ESP32 ࠢӮਔ‫֥ڶپ‬ຓഡđ๙‫ ݖ‬DPort ࠷թఖ॥ᇅൈᇒ૊॥đ‫ܵݻۿ‬৘đຓഡၛࠣ༢๤‫ྏނ‬ଆॶ֥஥ᇂđॖၛ +൐֤༢๤ᄝЌӻቋࡄྟି֥๝ൈࡼ‫֞ࢆݻۿ‬ቋ֮b༢๤๙‫ ݖ‬DPort ࠷թఖᇏ֥஥ᇂ࠷թఖؓ۲۱ଆॶࣉྛ஥ +ᇂb + +5.2 ᇶေหྟ + +DPort ࠷թఖЇ‫ݣ‬ਔ‫؟‬۱ؓႋຓഡ‫ބ‬ଆॶ֥࠷թఖğ + • ༢๤‫ބ‬թԥఖ + • ‫ބ໊گ‬ൈᇒ + • ᇏ؎इᆔ + + • DMA + + • MPU/MMU + • APP_CPU ॥ᇅఖ + • ຓഡൈᇒ૊॥‫໊گބ‬ + +5.3 ‫ିۿ‬૭ඍ + +5.3.1 ༢๤‫ބ‬թԥఖ࠷թఖ + +༢๤‫ބ‬թԥఖ࠷թఖč࡮і 5.4ĎႨႿ༢๤‫ބ‬թԥఖđ২ೂ cache ஥ᇂ‫ބ‬թԥఖ႘ഝb࠷թఖ૭ඍབྷ࡮ᅣࢫ༢ +๤‫ބ‬թԥఖb + +5.3.2 ‫ބ໊گ‬ൈᇒ࠷թఖ + +‫ބ໊گ‬ൈᇒ࠷թఖč࡮і 5.4ĎႨႿ‫ބ໊گ‬ൈᇒb࠷թఖ૭ඍབྷ࡮ᅣࢫ‫ބ໊گ‬ൈᇒb + +5.3.3 ᇏ؎इᆔ࠷թఖ + +ᇏ؎इᆔ࠷թఖč࡮і 5.4ĎႨႿ๙‫ݖ‬ᇏ؎इᆔ஥ᇂ‫ބ‬႘ഝᇏ؎b࠷թఖ૭ඍབྷ࡮ᅣࢫᇏ؎इᆔ +(INTERRUPT)b + +5.3.4 DMA ࠷թఖ + +DMA ࠷թఖč࡮і 5.4ĎႨႿ SPI DMA ஥ᇂb࠷թఖ૭ඍབྷ࡮ᅣࢫ DMA ॥ᇅఖ (DMA)b + +5.3.5 MPU/MMU ࠷թఖ + +MPU/MMU ࠷թఖč࡮і 5.4ĎႨႿ MPU/MMU ஥ᇂაҠቔ॥ᇅb࠷թఖ૭ඍབྷ࡮ᅣࢫ թԥఖܵ৘‫ބ‬Ќ޹ֆჭ +(MMU, MPU)b + +5.3.6 APP_CPU ॥ᇅఖ࠷թఖ + +APP_CPU ॥ᇅఖ࠷թఖč࡮і 5.4ĎॖႨႿ APP_CPU ֥ࠎЧ஥ᇂđ২ೂᄠ๔಩ༀ֥ᆳྛđၛࠣഡᇂՖ ROM +code ఓ‫๋֥ު׮‬ሇֹᆶb࠷թఖ૭ඍབྷ࡮ᅣࢫ 5.5bླေᇿၩ֥൞đ‫࠷໊گ‬թఖ໭‫م‬๙‫ݖ‬႗ࡱౢԢb + +ুᶈྐ༏॓࠯ 82 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + +5.3.7 ຓഡൈᇒ૊॥‫໊گބ‬ + +ຓഡൈᇒ૊॥‫࠷໊گބ‬թఖč࡮і 5.4Ďनູۚ‫׈‬௜Ⴕིb࠷թఖ૭ඍབྷ࡮ᅣࢫ 5.5bླေᇿၩ֥൞đ‫࠷໊گ‬թ +ఖ໭‫م‬๙‫ݖ‬႗ࡱౢԢb + +ুᶈྐ༏॓࠯ 83 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + +5.4 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + + ଀ӫ PRO_CPU թԥఖᇗ႘ഝଆൔ 0x3FF00000 ‫؀‬/ཿ + ༢๤‫ބ‬թԥఖ࠷թఖ APP_CPU թԥఖᇗ႘ഝଆൔ 0x3FF00004 ‫؀‬/ཿ + DPORT_PRO_BOOT_REMAP_CTRL_REG ਆ۱ cache ๝ൈᅝႨଽթ֥ + DPORT_APP_BOOT_REMAP_CTRL_REG ଆൔ 0x3FF0007C ‫؀‬/ཿ + + DPORT_CACHE_MUX_MODE_REG ࿊ᄴ CPU ൈᇒ 0x3FF0003C ‫؀‬/ཿ + + ‫ބ໊گ‬ൈᇒ࠷թఖ ਆ۱ CPU ֥ Interrupt 0 0x3FF000DC ‫؀‬/ཿ + DPORT_CPU_PER_CONF_REG ਆ۱ CPU ֥ Interrupt 1 0x3FF000E0 ‫؀‬/ཿ + ᇏ؎इᆔ࠷թఖ ਆ۱ CPU ֥ Interrupt 2 0x3FF000E4 ‫؀‬/ཿ + DPORT_CPU_INTR_FROM_CPU_0_REG ਆ۱ CPU ֥ Interrupt 3 0x3FF000E8 ‫؀‬/ཿ + DPORT_CPU_INTR_FROM_CPU_1_REG PRO_CPU ᇏ؎ሑ෿ 0 0x3FF000EC ᆺ‫؀‬ + DPORT_CPU_INTR_FROM_CPU_2_REG PRO_CPU ᇏ؎ሑ෿ 1 0x3FF000F0 ᆺ‫؀‬ + DPORT_CPU_INTR_FROM_CPU_3_REG PRO_CPU ᇏ؎ሑ෿ 2 0x3FF000F4 ᆺ‫؀‬ + DPORT_PRO_INTR_STATUS_REG_0_REG APP_CPU ᇏ؎ሑ෿ 0 0x3FF000F8 ᆺ‫؀‬ + DPORT_PRO_INTR_STATUS_REG_1_REG APP_CPU ᇏ؎ሑ෿ 1 0x3FF000FC ᆺ‫؀‬ + DPORT_PRO_INTR_STATUS_REG_2_REG APP_CPU ᇏ؎ሑ෿ 2 0x3FF00100 ᆺ‫؀‬ + DPORT_APP_INTR_STATUS_REG_0_REG ᇏ؎႘ഝ 0x3FF00104 ‫؀‬/ཿ + DPORT_APP_INTR_STATUS_REG_1_REG ᇏ؎႘ഝ 0x3FF00108 ‫؀‬/ཿ + DPORT_APP_INTR_STATUS_REG_2_REG ᇏ؎႘ഝ 0x3FF0010C ‫؀‬/ཿ + DPORT_PRO_MAC_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF00110 ‫؀‬/ཿ + DPORT_PRO_MAC_NMI_MAP_REG ᇏ؎႘ഝ 0x3FF00114 ‫؀‬/ཿ + DPORT_PRO_BB_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00118 ‫؀‬/ཿ + DPORT_PRO_BT_MAC_INT_MAP_REG ᇏ؎႘ഝ 0x3FF0011C ‫؀‬/ཿ + DPORT_PRO_BT_BB_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00120 ‫؀‬/ཿ + DPORT_PRO_BT_BB_NMI_MAP_REG ᇏ؎႘ഝ 0x3FF00124 ‫؀‬/ཿ + DPORT_PRO_RWBT_IRQ_MAP_REG ᇏ؎႘ഝ 0x3FF00128 ‫؀‬/ཿ + DPORT_PRO_RWBLE_IRQ_MAP_REG ᇏ؎႘ഝ 0x3FF0012C ‫؀‬/ཿ + DPORT_PRO_RWBT_NMI_MAP_REG ᇏ؎႘ഝ 0x3FF00130 ‫؀‬/ཿ + DPORT_PRO_RWBLE_NMI_MAP_REG ᇏ؎႘ഝ 0x3FF00134 ‫؀‬/ཿ + DPORT_PRO_SLC0_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF00138 ‫؀‬/ཿ + DPORT_PRO_SLC1_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF0013C ‫؀‬/ཿ + DPORT_PRO_UHCI0_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF00140 ‫؀‬/ཿ + DPORT_PRO_UHCI1_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF00144 ‫؀‬/ཿ + DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00148 ‫؀‬/ཿ + DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF0014C ‫؀‬/ཿ + DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00150 ‫؀‬/ཿ + DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00154 ‫؀‬/ཿ + DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00158 ‫؀‬/ཿ + DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF0015C ‫؀‬/ཿ + DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00160 ‫؀‬/ཿ + DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG + DPORT_PRO_GPIO_INTERRUPT_MAP_REG + DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG + +ুᶈྐ༏॓࠯ 84 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + +଀ӫ ૭ඍ ֹᆶ ٠໙ +DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG ᇏ؎႘ഝ 0x3FF00164 ‫؀‬/ཿ +DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG ᇏ؎႘ഝ 0x3FF00168 ‫؀‬/ཿ +DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG ᇏ؎႘ഝ 0x3FF0016C ‫؀‬/ཿ +DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG ᇏ؎႘ഝ 0x3FF00170 ‫؀‬/ཿ +DPORT_PRO_SPI_INTR_0_MAP_REG ᇏ؎႘ഝ 0x3FF00174 ‫؀‬/ཿ +DPORT_PRO_SPI_INTR_1_MAP_REG ᇏ؎႘ഝ 0x3FF00178 ‫؀‬/ཿ +DPORT_PRO_SPI_INTR_2_MAP_REG ᇏ؎႘ഝ 0x3FF0017C ‫؀‬/ཿ +DPORT_PRO_SPI_INTR_3_MAP_REG ᇏ؎႘ഝ 0x3FF00180 ‫؀‬/ཿ +DPORT_PRO_I2S0_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00184 ‫؀‬/ཿ +DPORT_PRO_I2S1_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00188 ‫؀‬/ཿ +DPORT_PRO_UART_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF0018C ‫؀‬/ཿ +DPORT_PRO_UART1_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF00190 ‫؀‬/ཿ +DPORT_PRO_UART2_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF00194 ‫؀‬/ཿ +DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG ᇏ؎႘ഝ 0x3FF00198 ‫؀‬/ཿ +DPORT_PRO_EMAC_INT_MAP_REG ᇏ؎႘ഝ 0x3FF0019C ‫؀‬/ཿ +DPORT_PRO_PWM0_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF001A0 ‫؀‬/ཿ +DPORT_PRO_PWM1_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF001A4 ‫؀‬/ཿ +DPORT_PRO_LEDC_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001B0 ‫؀‬/ཿ +DPORT_PRO_EFUSE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001B4 ‫؀‬/ཿ +DPORT_PRO_TWAI_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001B8 ‫؀‬/ཿ +DPORT_PRO_RTC_CORE_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF001BC ‫؀‬/ཿ +DPORT_PRO_RMT_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF001C0 ‫؀‬/ཿ +DPORT_PRO_PCNT_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF001C4 ‫؀‬/ཿ +DPORT_PRO_I2C_EXT0_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF001C8 ‫؀‬/ཿ +DPORT_PRO_I2C_EXT1_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF001CC ‫؀‬/ཿ +DPORT_PRO_RSA_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF001D0 ‫؀‬/ཿ +DPORT_PRO_SPI1_DMA_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001D4 ‫؀‬/ཿ +DPORT_PRO_SPI2_DMA_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001D8 ‫؀‬/ཿ +DPORT_PRO_SPI3_DMA_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001DC ‫؀‬/ཿ +DPORT_PRO_WDG_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001E0 ‫؀‬/ཿ +DPORT_PRO_TIMER_INT1_MAP_REG ᇏ؎႘ഝ 0x3FF001E4 ‫؀‬/ཿ +DPORT_PRO_TIMER_INT2_MAP_REG ᇏ؎႘ഝ 0x3FF001E8 ‫؀‬/ཿ +DPORT_PRO_TG_T0_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001EC ‫؀‬/ཿ +DPORT_PRO_TG_T1_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001F0 ‫؀‬/ཿ +DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001F4 ‫؀‬/ཿ +DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001F8 ‫؀‬/ཿ +DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF001FC ‫؀‬/ཿ +DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00200 ‫؀‬/ཿ +DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00204 ‫؀‬/ཿ +DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00208 ‫؀‬/ཿ +DPORT_PRO_MMU_IA_INT_MAP_REG ᇏ؎႘ഝ 0x3FF0020C ‫؀‬/ཿ +DPORT_PRO_MPU_IA_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00210 ‫؀‬/ཿ +DPORT_PRO_CACHE_IA_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00214 ‫؀‬/ཿ + +ুᶈྐ༏॓࠯ 85 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + +଀ӫ ૭ඍ ֹᆶ ٠໙ +DPORT_APP_MAC_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF00218 ‫؀‬/ཿ +DPORT_APP_MAC_NMI_MAP_REG ᇏ؎႘ഝ 0x3FF0021C ‫؀‬/ཿ +DPORT_APP_BB_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00220 ‫؀‬/ཿ +DPORT_APP_BT_MAC_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00224 ‫؀‬/ཿ +DPORT_APP_BT_BB_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00228 ‫؀‬/ཿ +DPORT_APP_BT_BB_NMI_MAP_REG ᇏ؎႘ഝ 0x3FF0022C ‫؀‬/ཿ +DPORT_APP_RWBT_IRQ_MAP_REG ᇏ؎႘ഝ 0x3FF00230 ‫؀‬/ཿ +DPORT_APP_RWBLE_IRQ_MAP_REG ᇏ؎႘ഝ 0x3FF00234 ‫؀‬/ཿ +DPORT_APP_RWBT_NMI_MAP_REG ᇏ؎႘ഝ 0x3FF00238 ‫؀‬/ཿ +DPORT_APP_RWBLE_NMI_MAP_REG ᇏ؎႘ഝ 0x3FF0023C ‫؀‬/ཿ +DPORT_APP_SLC0_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF00240 ‫؀‬/ཿ +DPORT_APP_SLC1_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF00244 ‫؀‬/ཿ +DPORT_APP_UHCI0_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF00248 ‫؀‬/ཿ +DPORT_APP_UHCI1_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF0024C ‫؀‬/ཿ +DPORT_APP_TG_T0_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00250 ‫؀‬/ཿ +DPORT_APP_TG_T1_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00254 ‫؀‬/ཿ +DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00258 ‫؀‬/ཿ +DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF0025C ‫؀‬/ཿ +DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00260 ‫؀‬/ཿ +DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00264 ‫؀‬/ཿ +DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00268 ‫؀‬/ཿ +DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG ᇏ؎႘ഝ 0x3FF0026C ‫؀‬/ཿ +DPORT_APP_GPIO_INTERRUPT_MAP_REG ᇏ؎႘ഝ 0x3FF00270 ‫؀‬/ཿ +DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG ᇏ؎႘ഝ 0x3FF00274 ‫؀‬/ཿ +DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG ᇏ؎႘ഝ 0x3FF00278 ‫؀‬/ཿ +DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG ᇏ؎႘ഝ 0x3FF0027C ‫؀‬/ཿ +DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG ᇏ؎႘ഝ 0x3FF00280 ‫؀‬/ཿ +DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG ᇏ؎႘ഝ 0x3FF00284 ‫؀‬/ཿ +DPORT_APP_SPI_INTR_0_MAP_REG ᇏ؎႘ഝ 0x3FF00288 ‫؀‬/ཿ +DPORT_APP_SPI_INTR_1_MAP_REG ᇏ؎႘ഝ 0x3FF0028C ‫؀‬/ཿ +DPORT_APP_SPI_INTR_2_MAP_REG ᇏ؎႘ഝ 0x3FF00290 ‫؀‬/ཿ +DPORT_APP_SPI_INTR_3_MAP_REG ᇏ؎႘ഝ 0x3FF00294 ‫؀‬/ཿ +DPORT_APP_I2S0_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00298 ‫؀‬/ཿ +DPORT_APP_I2S1_INT_MAP_REG ᇏ؎႘ഝ 0x3FF0029C ‫؀‬/ཿ +DPORT_APP_UART_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002A0 ‫؀‬/ཿ +DPORT_APP_UART1_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002A4 ‫؀‬/ཿ +DPORT_APP_UART2_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002A8 ‫؀‬/ཿ +DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG ᇏ؎႘ഝ 0x3FF002AC ‫؀‬/ཿ +DPORT_APP_EMAC_INT_MAP_REG ᇏ؎႘ഝ 0x3FF002B0 ‫؀‬/ཿ +DPORT_APP_PWM0_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002B4 ‫؀‬/ཿ +DPORT_APP_PWM1_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002B8 ‫؀‬/ཿ +DPORT_APP_LEDC_INT_MAP_REG ᇏ؎႘ഝ 0x3FF002C4 ‫؀‬/ཿ +DPORT_APP_EFUSE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF002C8 ‫؀‬/ཿ + +ুᶈྐ༏॓࠯ 86 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ ૭ඍ ֹᆶ ٠໙ + ᇏ؎႘ഝ 0x3FF002CC ‫؀‬/ཿ + ଀ӫ ᇏ؎႘ഝ 0x3FF002D0 ‫؀‬/ཿ + DPORT_APP_TWAI_INT_MAP_REG ᇏ؎႘ഝ 0x3FF002D4 ‫؀‬/ཿ + DPORT_APP_RTC_CORE_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002D8 ‫؀‬/ཿ + DPORT_APP_RMT_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002DC ‫؀‬/ཿ + DPORT_APP_PCNT_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002E0 ‫؀‬/ཿ + DPORT_APP_I2C_EXT0_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002E4 ‫؀‬/ཿ + DPORT_APP_I2C_EXT1_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002E8 ‫؀‬/ཿ + DPORT_APP_RSA_INTR_MAP_REG ᇏ؎႘ഝ 0x3FF002EC ‫؀‬/ཿ + DPORT_APP_SPI1_DMA_INT_MAP_REG ᇏ؎႘ഝ 0x3FF002F0 ‫؀‬/ཿ + DPORT_APP_SPI2_DMA_INT_MAP_REG ᇏ؎႘ഝ 0x3FF002F4 ‫؀‬/ཿ + DPORT_APP_SPI3_DMA_INT_MAP_REG ᇏ؎႘ഝ 0x3FF002F8 ‫؀‬/ཿ + DPORT_APP_WDG_INT_MAP_REG ᇏ؎႘ഝ 0x3FF002FC ‫؀‬/ཿ + DPORT_APP_TIMER_INT1_MAP_REG ᇏ؎႘ഝ 0x3FF00300 ‫؀‬/ཿ + DPORT_APP_TIMER_INT2_MAP_REG ᇏ؎႘ഝ 0x3FF00304 ‫؀‬/ཿ + DPORT_APP_TG_T0_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00308 ‫؀‬/ཿ + DPORT_APP_TG_T1_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF0030C ‫؀‬/ཿ + DPORT_APP_TG_WDT_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00310 ‫؀‬/ཿ + DPORT_APP_TG_LACT_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00314 ‫؀‬/ཿ + DPORT_APP_TG1_T0_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00318 ‫؀‬/ཿ + DPORT_APP_TG1_T1_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF0031C ‫؀‬/ཿ + DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00320 ‫؀‬/ཿ + DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00324 ‫؀‬/ཿ + DPORT_APP_MMU_IA_INT_MAP_REG ᇏ؎႘ഝ 0x3FF00328 ‫؀‬/ཿ + DPORT_APP_MPU_IA_INT_MAP_REG + DPORT_APP_CACHE_IA_INT_MAP_REG ࿊ᄴ SPI1, SPI2, SPI3 ֥ 0x3FF005A8 ‫؀‬/ཿ + DMA ࠷թఖ DMA ྐ֡ + + DPORT_SPI_DMA_CHAN_SEL_REG External SRAM ֥ྴ୅ֹᆶଆ 0x3FF00040 ‫؀‬/ཿ + ൔ + MPU/MMU ࠷թఖ External SRAM ֥ྴ୅ֹᆶଆ 0x3FF00058 ‫؀‬/ཿ + ൔ + DPORT_PRO_CACHE_CTRL_REG Internal SRAM 0 ֥ MMU ် 0x3FF00080 ‫؀‬/ཿ + նཬ + DPORT_APP_CACHE_CTRL_REG Internal SRAM 2 ֥ MMU ် 0x3FF00084 ‫؀‬/ཿ + նཬ 0x3FF000B4 ‫؀‬/ཿ + DPORT_IMMU_PAGE_MODE_REG ஥ᇂ DMA ֥ MPU 0x3FF000B8 ‫؀‬/ཿ + ஥ᇂ DMA ֥ MPU 0x3FF0032C ‫؀‬/ཿ + DPORT_DMMU_PAGE_MODE_REG ຓഡ MPU 0x3FF00330 ‫؀‬/ཿ + ຓഡ MPU 0x3FF00334 ‫؀‬/ཿ + DPORT_AHB_MPU_TABLE_0_REG ຓഡ MPU 0x3FF00338 ‫؀‬/ཿ + DPORT_AHB_MPU_TABLE_1_REG ຓഡ MPU 0x3FF00348 ‫؀‬/ཿ + DPORT_AHBLITE_MPU_TABLE_UART_REG ຓഡ MPU + DPORT_AHBLITE_MPU_TABLE_SPI1_REG + DPORT_AHBLITE_MPU_TABLE_SPI0_REG + DPORT_AHBLITE_MPU_TABLE_GPIO_REG + DPORT_AHBLITE_MPU_TABLE_RTC_REG + +ুᶈྐ༏॓࠯ 87 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + +଀ӫ ૭ඍ ֹᆶ ٠໙ +DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG ຓഡ MPU 0x3FF0034C ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_HINF_REG ຓഡ MPU 0x3FF00354 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_UHCI1_REG ຓഡ MPU 0x3FF00358 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_I2S0_REG ຓഡ MPU 0x3FF00364 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_UART1_REG ຓഡ MPU 0x3FF00368 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG ຓഡ MPU 0x3FF00374 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_UHCI0_REG ຓഡ MPU 0x3FF00378 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG ຓഡ MPU 0x3FF0037C ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_RMT_REG ຓഡ MPU 0x3FF00380 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_PCNT_REG ຓഡ MPU 0x3FF00384 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_SLC_REG ຓഡ MPU 0x3FF00388 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_LEDC_REG ຓഡ MPU 0x3FF0038C ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_EFUSE_REG ຓഡ MPU 0x3FF00390 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG ຓഡ MPU 0x3FF00394 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_PWM0_REG ຓഡ MPU 0x3FF0039C ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG ຓഡ MPU 0x3FF003A0 ‫؀‬/ཿ + + ຓഡ MPU 0x3FF003A4 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG + +DPORT_AHBLITE_MPU_TABLE_SPI2_REG ຓഡ MPU 0x3FF003A8 ‫؀‬/ཿ + 0x3FF003AC ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_SPI3_REG ຓഡ MPU 0x3FF003B0 ‫؀‬/ཿ + 0x3FF003B4 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG ຓഡ MPU 0x3FF003B8 ‫؀‬/ཿ + 0x3FF003BC ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG ຓഡ MPU 0x3FF003C4 ‫؀‬/ཿ + 0x3FF003C8 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG ຓഡ MPU 0x3FF003CC ‫؀‬/ཿ + 0x3FF003E4 ‫؀‬/ཿ +DPORT_AHBLITE_MPU_TABLE_EMAC_REG ຓഡ MPU + +DPORT_AHBLITE_MPU_TABLE_PWM1_REG ຓഡ MPU + +DPORT_AHBLITE_MPU_TABLE_I2S1_REG ຓഡ MPU + +DPORT_AHBLITE_MPU_TABLE_UART2_REG ຓഡ MPU + +DPORT_AHBLITE_MPU_TABLE_PWR_REG ຓഡ MPU + +DPORT_IMMU_TABLE0_REG ஥ᇂ Internal SRAM 0 ֥ 0x3FF00504 ‫؀‬/ཿ + MMU + +DPORT_IMMU_TABLE1_REG ஥ᇂ Internal SRAM 0 ֥ 0x3FF00508 ‫؀‬/ཿ + MMU + +DPORT_IMMU_TABLE2_REG ஥ᇂ Internal SRAM 0 ֥ 0x3FF0050C ‫؀‬/ཿ + MMU + +DPORT_IMMU_TABLE3_REG ஥ᇂ Internal SRAM 0 ֥ 0x3FF00510 ‫؀‬/ཿ + MMU + +DPORT_IMMU_TABLE4_REG ஥ᇂ Internal SRAM 0 ֥ 0x3FF00514 ‫؀‬/ཿ + MMU + +DPORT_IMMU_TABLE5_REG ஥ᇂ Internal SRAM 0 ֥ 0x3FF00518 ‫؀‬/ཿ + MMU + +DPORT_IMMU_TABLE6_REG ஥ᇂ Internal SRAM 0 ֥ 0x3FF0051C ‫؀‬/ཿ + MMU + +DPORT_IMMU_TABLE7_REG ஥ᇂ Internal SRAM 0 ֥ 0x3FF00520 ‫؀‬/ཿ + MMU + +ুᶈྐ༏॓࠯ 88 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ ૭ඍ ֹᆶ ٠໙ + ஥ᇂ Internal SRAM 0 ֥ + ଀ӫ MMU 0x3FF00524 ‫؀‬/ཿ + DPORT_IMMU_TABLE8_REG ஥ᇂ Internal SRAM 0 ֥ + DPORT_IMMU_TABLE9_REG MMU 0x3FF00528 ‫؀‬/ཿ + DPORT_IMMU_TABLE10_REG ஥ᇂ Internal SRAM 0 ֥ + DPORT_IMMU_TABLE11_REG MMU 0x3FF0052C ‫؀‬/ཿ + DPORT_IMMU_TABLE12_REG ஥ᇂ Internal SRAM 0 ֥ + DPORT_IMMU_TABLE13_REG MMU 0x3FF00530 ‫؀‬/ཿ + DPORT_IMMU_TABLE14_REG ஥ᇂ Internal SRAM 0 ֥ + DPORT_IMMU_TABLE15_REG MMU 0x3FF00534 ‫؀‬/ཿ + DPORT_DMMU_TABLE0_REG ஥ᇂ Internal SRAM 0 ֥ + DPORT_DMMU_TABLE1_REG MMU 0x3FF00538 ‫؀‬/ཿ + DPORT_DMMU_TABLE2_REG ஥ᇂ Internal SRAM 0 ֥ + DPORT_DMMU_TABLE3_REG MMU 0x3FF0053C ‫؀‬/ཿ + DPORT_DMMU_TABLE4_REG ஥ᇂ Internal SRAM 0 ֥ + DPORT_DMMU_TABLE5_REG MMU 0x3FF00540 ‫؀‬/ཿ + DPORT_DMMU_TABLE6_REG ஥ᇂ Internal SRAM 2 ֥ + DPORT_DMMU_TABLE7_REG MMU 0x3FF00544 ‫؀‬/ཿ + DPORT_DMMU_TABLE8_REG ஥ᇂ Internal SRAM 2 ֥ + DPORT_DMMU_TABLE9_REG MMU 0x3FF00548 ‫؀‬/ཿ + DPORT_DMMU_TABLE10_REG ஥ᇂ Internal SRAM 2 ֥ + DPORT_DMMU_TABLE11_REG MMU 0x3FF0054C ‫؀‬/ཿ + DPORT_DMMU_TABLE12_REG ஥ᇂ Internal SRAM 2 ֥ + DPORT_DMMU_TABLE13_REG MMU 0x3FF00550 ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ +ুᶈྐ༏॓࠯ MMU 0x3FF00554 ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ + MMU 0x3FF00558 ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ + MMU 0x3FF0055C ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ + MMU 0x3FF00560 ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ + MMU 0x3FF00564 ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ + MMU 0x3FF00568 ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ + MMU 0x3FF0056C ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ + MMU 0x3FF00570 ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ + MMU 0x3FF00574 ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ + MMU 0x3FF00578 ‫؀‬/ཿ + + 89 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ ૭ඍ ֹᆶ ٠໙ + ஥ᇂ Internal SRAM 2 ֥ + ଀ӫ MMU 0x3FF0057C ‫؀‬/ཿ + ஥ᇂ Internal SRAM 2 ֥ + DPORT_DMMU_TABLE14_REG MMU 0x3FF00580 ‫؀‬/ཿ + + DPORT_DMMU_TABLE15_REG APP_CPU ‫໊گ‬ 0x3FF0002C ‫؀‬/ཿ + APP_CPU ൈᇒ૊॥ 0x3FF00030 ‫؀‬/ཿ + APP_CPU ॥ᇅఖ࠷թఖ APP_CPU ᄠ๔ (stall) 0x3FF00034 ‫؀‬/ཿ + DPORT_APPCPU_CTRL_REG_A_REG APP_CPU ఓ‫ֹ׮‬ᆶ 0x3FF00038 ‫؀‬/ཿ + DPORT_APPCPU_CTRL_REG_B_REG + DPORT_APPCPU_CTRL_REG_C_REG ຓഡൈᇒ૊॥ 0x3FF0001C ‫؀‬/ཿ + DPORT_APPCPU_CTRL_REG_D_REG ຓഡ‫໊گ‬ 0x3FF00020 ‫؀‬/ཿ + ຓഡൈᇒ૊॥‫࠷໊گބ‬թఖ ຓഡൈᇒ૊॥ 0x3FF000C0 ‫؀‬/ཿ + DPORT_PERI_CLK_EN_REG ຓഡ‫໊گ‬ 0x3FF000C4 ‫؀‬/ཿ + DPORT_PERI_RST_EN_REG Wi-Fi ൈᇒ૊॥ 0x3FF000CC ‫؀‬/ཿ + DPORT_PERIP_CLK_EN_REG Wi-Fi ‫໊گ‬ 0x3FF000D0 ‫؀‬/ཿ + DPORT_PERIP_RST_EN_REG + DPORT_WIFI_CLK_EN_REG + DPORT_WIFI_RST_EN_REG + +ুᶈྐ༏॓࠯ 90 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + +5.5 ࠷թఖ + + Register 5.1. DPORT_PRO_BOOT_REMAP_CTRL_REG (0x000) + + (reserved) DPORT_PRO_BOOT_REMAP + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_PRO_BOOT_REMAP PRO_CPU ֥թԥఖᇗ႘ഝଆൔbč‫؀‬ĔཿĎ + + Register 5.2. DPORT_APP_BOOT_REMAP_CTRL_REG (0x004) + + (reserved) DPORT_APP_BOOT_REMAP + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_APP_BOOT_REMAP APP_CPU ֥թԥఖᇗ႘ഝଆൔbč‫؀‬ĔཿĎ + + Register 5.3. DPORT_PERI_CLK_EN_REG (0x01C) + + (reserved) DPORDTP_OPERDRTPI__OPEERNRT_I_R_PESENAR_IS_HENA_AES + +31 32 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_PERI_EN_RSA ᇂ໊൐ି RSA ଆॶ֥ൈᇒbౢਬܱо RSA ଆॶ֥ൈᇒbč‫؀‬ĔཿĎ + DPORT_PERI_EN_SHA ᇂ໊൐ି SHA ଆॶ֥ൈᇒbౢਬܱо SHA ଆॶ֥ൈᇒbč‫؀‬ĔཿĎ + DPORT_PERI_EN_AES ᇂ໊൐ି AES ଆॶ֥ൈᇒbౢਬܱо AES ଆॶ֥ൈᇒbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 91 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.4. DPORT_PERI_RST_EN_REG (0x020) + + (reserved) DPORDTP_OPERDRTPI__OPRERSRTTI___PRRESSRATI__SRHSAT_AES + +31 32 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_PERI_RST_RSA ᇂ໊‫ ໊گ‬RSA ଆॶ֥ൈᇒbౢਬܱо RSA ଆॶ֥ൈᇒbč‫؀‬ĔཿĎ + DPORT_PERI_RST_SHA ᇂ໊‫ ໊گ‬SHA ଆॶ֥ൈᇒbౢਬܱо SHA ଆॶ֥ൈᇒbč‫؀‬ĔཿĎ + DPORT_PERI_RST_AES ᇂ໊‫ ໊گ‬AES ଆॶ֥ൈᇒbౢਬܱо AES ଆॶ֥ൈᇒbč‫؀‬ĔཿĎ + + Register 5.5. DPORT_APPCPU_CTRL_REG_A_REG (0x02C) + + (reserved) DPORT_APPCPU_RESETTING + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset + + DPORT_APPCPU_RESETTING ᇂ໊‫ ໊گ‬APP_CPUbౢਬ൤٢ APP_CPUbč‫؀‬ĔཿĎ + + Register 5.6. DPORT_APPCPU_CTRL_REG_B_REG (0x030) + + (reserved) DPORT_APPCPU_CLKGATE_EN + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_APPCPU_CLKGATE_EN ᇂ໊൐ି APP_CPU ֥ൈᇒbౢਬܱо APP_CPU ֥ൈᇒbč‫؀‬ + ĔཿĎ + +ুᶈྐ༏॓࠯ 92 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.7. DPORT_APPCPU_CTRL_REG_C_REG (0x034) + + (reserved) DPORT_APPCPU_RUNSTALL + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_APPCPU_RUNSTALL ᇂ໊൐ି APP_CPU ֥ᄠ๔ (stall) ሑ෿bౢਬ൤٢ APP_CPU ֥ᄠ + ๔ (stall) ሑ෿bč‫؀‬ĔཿĎ + + Register 5.8. DPORT_APPCPU_CTRL_REG_D_REG (0x038) + +31 0 + + 0x000000000 Reset + + DPORT_APPCPU_CTRL_REG_D_REG APP_CPU Ֆ ROM code ఓ‫׮‬ᆭުđ߶๋ሇ֞‫࠷ھ‬թఖᇏ + ֹ֥ᆶbč‫؀‬ĔཿĎ + + Register 5.9. DPORT_CPU_PER_CONF_REG (0x03C) + + (reserved) DPORT_CPU_CPUPERIOD_SEL + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_CPU_CPUPERIOD_SEL ࿊ᄴ CPU ൈᇒbབྷ౦౨ҕॉі 3-3bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 93 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.10. DPORT_PRO_CACHE_CTRL_REG (0x040) + + (reserved) DPORT_PRO_(rDeRseArMve_dH) L DPORDTP_OPRROT__PDRROA_M(rSe_IsNSePGrvLLeIETd_)IRAMD_PEONRADTP_OPRRDOTP__OPCRRAOTC__HPCERA_(OrCFe_LsHCUeErAS_vCHeFdLH_)UDESO_HENN_EEANBALE + +31 17 16 15 12 11 10 9 65 4 32 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset + + DPORT_PRO_DRAM_HL External SRAM ֥ྴ୅ֹᆶଆൔbč‫؀‬ĔཿĎ + DPORT_PRO_DRAM_SPLIT External SRAM ֥ྴ୅ֹᆶଆൔbč‫؀‬ĔཿĎ + DPORT_PRO_SINGLE_IRAM_ENA PRO_CPU ٠໙ external flash ֥ห൹ଆൔbč‫؀‬ĔཿĎ + DPORT_PRO_CACHE_FLUSH_DONE ౢԢ PRO_CPU cache ປӮѓᆽbčᆺ‫؀‬Ď + DPORT_PRO_CACHE_FLUSH_ENA ౢԢ PRO_CPU cachebč‫؀‬ĔཿĎ + DPORT_PRO_CACHE_ENABLE ൐ି PRO_CPU cachebč‫؀‬ĔཿĎ + + Register 5.11. DPORT_APP_CACHE_CTRL_REG (0x058) + + (reserved) DPORT_(ArePsPe_rvDeRdDA) PMO_RHDTLP_OAPRPT__DAPRPA_M(Sr_eINSsePGrLvLIeETd_)IRAMD_PEONRADTP_OAPRDPTP__OCAPARPCT__HCAEPA_(PCrFe_LHsCUeEASr_vCHFeLdH_UD)ESO_HENN_EEANBALE + +31 15 14 13 12 11 10 9 65 4 32 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset + + DPORT_APP_DRAM_HL External SRAM ֥ྴ୅ֹᆶଆൔbč‫؀‬ĔཿĎ + DPORT_APP_DRAM_SPLIT External SRAM ֥ྴ୅ֹᆶଆൔbč‫؀‬ĔཿĎ + DPORT_APP_SINGLE_IRAM_ENA APP_CPU ٠໙ external flash ֥ห൹ଆൔbč‫؀‬ĔཿĎ + DPORT_APP_CACHE_FLUSH_DONE ౢԢ APP_CPU cache ປӮѓᆽbčᆺ‫؀‬Ď + DPORT_APP_CACHE_FLUSH_ENA ౢԢ APP_CPU cachebč‫؀‬ĔཿĎ + DPORT_APP_CACHE_ENABLE ൐ି APP_CPU cachebč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 94 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.12. DPORT_CACHE_MUX_MODE_REG (0x07C) + + (reserved) DPORT_CACHE_MUX_MODE + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_CACHE_MUX_MODE ਆ۱ cache ‫܋‬Ⴈଽթ֥ଆൔbč‫؀‬ĔཿĎ + + Register 5.13. DPORT_IMMU_PAGE_MODE_REG (0x080) + + (reserved) DPORT_(IrMesMeUrv_ePdA) GE_MODE + +31 32 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_IMMU_PAGE_MODE Internal SRAM 0 ֥ MMU ်նཬbč‫؀‬ĔཿĎ + + Register 5.14. DPORT_DMMU_PAGE_MODE_REG (0x084) + + (reserved) DPORT_(DreMseMrvUe_dP)AGE_MODE + +31 32 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_DMMU_PAGE_MODE Internal SRAM 2 ֥ MMU ်նཬbč‫؀‬ĔཿĎ + + Register 5.15. DPORT_AHB_MPU_TABLE_0_REG (0x0B4) 0 + +31 Reset + + 0xFFFFFFFF + + DPORT_AHB_MPU_TABLE_0_REG ஥ᇂ DMA ֥ MPUbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 95 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.16. DPORT_AHB_MPU_TABLE_1_REG (0x0B8) + + (reserved) DPORT_AHB_ACCESS_GRANT_1 + +31 98 0 + +00000000000000000000000 0x1FF Reset + + DPORT_AHB_ACCESS_GRANT_1 ஥ᇂ DMA ֥ MPUbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 96 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.17. DPORT_PERIP_CLK_EN_REG (0x0C0) + + (reserved) (reserv(reeds)ervDePdO) RDTP_OUARDRTP_TOU_MARDRTEP_TMOS2_P_RCDCIT_LPL_DKOKI2M__RSEADET1N_NP__COPCLWRLKDKTM_P__E1OETN_WNRCDTALP_IK_OI2C_RCEDLT_NKP_E_OPXEWRTND1TMP__C0OS_LPRCDKIT3LP___KEOTCN_IRMLEDKTNEP__ROEEGFNRDURTPSO_OTEUI_RMPDCT1EPL__RKOUCG_HRLEDRKTCNPO__I1OLEU_ENRPCDDT_LPC_CKOP_L_CCRKEDLNT_NPK_ETOR_N_ECMRDNLTTPK__OU_CEHRLDNKTCP__I0OIE2_NRCCDT_LP_EKOSX_PRTEDI0T2NP___COUCLARL(KrRKTe__T_sEIE1e2NN_rSvDC0ePL_dOKC) _RLDEKTNP__OEUNAR(rRTe_TsS_eCPrvILe0Kd1_)_ECNLK_EN + +31 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 11111 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 Reset + + ᇂ໊ၛ༯ሳ‫؍‬൐ିཌྷႋຓഡ֥ൈᇒbౢਬܱоཌྷႋຓഡ֥ൈᇒb + DPORT_UART_MEM_CLK_EN UART0 ~ 2 ‫܋‬Ⴈ֥թԥఖbč‫؀‬/ཿĎ + DPORT_UART2_CLK_EN UART2 ଆॶbč‫؀‬/ཿĎ + DPORT_SPI_DMA_CLK_EN SPI_DMA ଆॶbč‫؀‬/ཿĎ + DPORT_I2S1_CLK_EN I2S1 ଆॶbč‫؀‬/ཿĎ + DPORT_PWM1_CLK_EN PWM1 ଆॶbč‫؀‬/ཿĎ + DPORT_TWAI_CLK_EN TWAI ଆॶbč‫؀‬/ཿĎ + DPORT_I2C_EXT1_CLK_EN I2C1 ଆॶbč‫؀‬/ཿĎ + DPORT_PWM0_CLK_EN PWM0 ଆॶbč‫؀‬/ཿĎ + DPORT_SPI3_CLK_EN SPI3 ଆॶbč‫؀‬/ཿĎ + DPORT_TIMERGROUP1_CLK_EN TIMG1 ଆॶbč‫؀‬/ཿĎ + DPORT_EFUSE_CLK_EN eFuse ଆॶbč‫؀‬/ཿĎ + DPORT_TIMERGROUP_CLK_EN TIMG0 ଆॶbč‫؀‬/ཿĎ + DPORT_UHCI1_CLK_EN UDMA1 ଆॶbč‫؀‬/ཿĎ + DPORT_LEDC_CLK_EN LEDC ଆॶbč‫؀‬/ཿĎ + DPORT_PCNT_CLK_EN PCNT ଆॶbč‫؀‬/ཿĎ + DPORT_RMT_CLK_EN RMT ଆॶbč‫؀‬/ཿĎ + DPORT_UHCI0_CLK_EN UDMA0 ଆॶbč‫؀‬/ཿĎ + DPORT_I2C_EXT0_CLK_EN I2C0 ଆॶbč‫؀‬/ཿĎ + DPORT_SPI2_CLK_EN SPI2 ଆॶbč‫؀‬/ཿĎ + ࢤ༯် + +ুᶈྐ༏॓࠯ 97 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.17. DPORT_PERIP_CLK_EN_REG (0x0C0) + + ࢤഈ် + DPORT_UART1_CLK_EN UART1 ଆॶbč‫؀‬/ཿĎ + DPORT_I2S0_CLK_EN I2S0 ଆॶbč‫؀‬/ཿĎ + DPORT_UART_CLK_EN UART0 ଆॶbč‫؀‬/ཿĎ + DPORT_SPI01_CLK_EN SPI0 ‫ ބ‬SPI1 ଆॶbč‫؀‬/ཿĎ + + Register 5.18. DPORT_PERIP_RST_EN_REG (0x0C4) + + (reserved) (reserv(reeds)ervDePdO) RDTP_OUARDRTP_TOU_MARDRTEP_TMOS2_P_RRDRIT_SPS_DTOIT2MRSADT1_P__ROPRSWRSTDTTMP_1OT_WRRDTASP_IT_OI2RRCSDT_TP_EOPXWRTD1TMP__R0OS_SPRRDTIT3SP__TOTRIRSMDTTEP_ROEGFRDURTPSO_OTEUI_RMPDRT1EPS__ROTURGHRSDRTCTPO_I1OLU_ERPRDDT_SPC_RTOP_SRCRTDSNTPT_TOR_RMRDSTTP_T_OURHRSDTCTP_I0OI2_RCRDT_SP_ETOSXPRTDI0T2P___ROURSARS(TrRTTe_TsI1e2_rSvDR0ePS_dORT) RSDTTP_OUAR(rRTe_TsS_eRPrvISe0Td1)_RST + +31 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +ᇂ໊ૄ۱ሳ‫໊گ؍‬ཌྷႋຓഡbౢਬ൤٢ཌྷႋຓഡbຓഡਙі౨Ұु࠷թఖ૭ඍ 5.17b + + Register 5.19. DPORT_WIFI_CLK_EN_REG (0x0CC) + + (reserved) DPORDTP_OWRIFTI__CWLIFKI__ECMLKA_CS_DEINO_(rHesOeSrvTe_dE)N DPORT_WIFI_(CreLsKe_rvSeDdI)OSLAVE_EN + +31 15 14 13 12 543 0 + +1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 Reset + + DPORT_WIFI_CLK_EMAC_EN ᇂ໊൐ି Ethernet MAC ଆॶ֥ൈᇒbౢਬܱо Ethernet MAC ଆॶ + ֥ൈᇒbč‫؀‬/ཿĎ + + DPORT_WIFI_CLK_SDIO_HOST_EN ᇂ໊൐ି SD/MMC ଆॶ֥ൈᇒbౢਬܱо SD/MMC ଆॶ֥ + ൈᇒbč‫؀‬/ཿĎ + + DPORT_WIFI_CLK_SDIOSLAVE_EN ᇂ໊൐ି SDIO ଆॶ֥ൈᇒbౢਬܱо SDIO ଆॶ֥ൈ + ᇒbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 98 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.20. DPORT_WIFI_RST_EN_REG (0x0D0) + + (reserved) DPORDTP_OEMRDTAP_COS_DRRITSO_T_SHDOIOS_TR_SR(reTSsTerved) + +31 87 6 54 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_EMAC_RST ᇂ໊‫ ໊گ‬Ethernet MAC ଆॶbౢਬ൤٢ Ethernet MAC ଆॶbč‫؀‬/ཿĎ + DPORT_SDIO_HOST_RST ᇂ໊‫ ໊گ‬SD/MMC ଆॶbౢਬ൤٢ SD/MMC ଆॶbč‫؀‬/ཿĎ + DPORT_SDIO_RST ᇂ໊‫ ໊گ‬SDIO ଆॶbౢਬ൤٢ SDIO ଆॶbč‫؀‬/ཿĎ + + Register 5.21. DPORT_CPU_INTR_FROM_CPU_n_REG (n: 0­3) (0xDC+4*n) + + (reserved) DPORT_CPU_INTR_FROM_CPU_n + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_CPU_INTR_FROM_CPU_n Վ࠷թఖᇂ 1 Ԩ‫ ؿ‬CPU ᇏ؎bč‫؀‬ĔཿĎ + + Register 5.22. DPORT_PRO_INTR_STATUS_REG_n_REG (n: 0­2) (0xEC+4*n) 0 + +31 Reset + + 0x000000000 + + DPORT_PRO_INTR_STATUS_REG_n_REG PRO_CPU ᇏ؎ሑ෿bčᆺ‫؀‬Ď + + Register 5.23. DPORT_APP_INTR_STATUS_REG_n_REG (n: 0­2) (0xF8+4*n) 0 + +31 Reset + + 0x000000000 + + DPORT_APP_INTR_STATUS_REG_n_REG APP_CPU ᇏ؎ሑ෿bčᆺ‫؀‬Ď + + Register 5.24. DPORT_PRO_MAC_INTR_MAP_REG (0x104) + +ুᶈྐ༏॓࠯ 99 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.25. DPORT_PRO_MAC_NMI_MAP_REG (0x108) + Register 5.26. DPORT_PRO_BB_INT_MAP_REG (0x10C) + + Register 5.27. DPORT_PRO_BT_MAC_INT_MAP_REG (0x110) + Register 5.28. DPORT_PRO_BT_BB_INT_MAP_REG (0x114) + Register 5.29. DPORT_PRO_BT_BB_NMI_MAP_REG (0x118) + Register 5.30. DPORT_PRO_RWBT_IRQ_MAP_REG (0x11C) + Register 5.31. DPORT_PRO_RWBLE_IRQ_MAP_REG (0x120) + Register 5.32. DPORT_PRO_RWBT_NMI_MAP_REG (0x124) + Register 5.33. DPORT_PRO_RWBLE_NMI_MAP_REG (0x128) + Register 5.34. DPORT_PRO_SLC0_INTR_MAP_REG (0x12C) + Register 5.35. DPORT_PRO_SLC1_INTR_MAP_REG (0x130) + Register 5.36. DPORT_PRO_UHCI0_INTR_MAP_REG (0x134) + Register 5.37. DPORT_PRO_UHCI1_INTR_MAP_REG (0x138) + Register 5.38. DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (0x13C) + Register 5.39. DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (0x140) + Register 5.40. DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (0x144) + Register 5.41. DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (0x148) + Register 5.42. DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (0x14C) + Register 5.43. DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (0x150) + Register 5.44. DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (0x154) + Register 5.45. DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (0x158) + Register 5.46. DPORT_PRO_GPIO_INTERRUPT_MAP_REG (0x15C) + Register 5.47. DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (0x160) + Register 5.48. DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (0x164) + Register 5.49. DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (0x168) + Register 5.50. DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (0x16C) + Register 5.51. DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (0x170) + Register 5.52. DPORT_PRO_SPI_INTR_0_MAP_REG (0x174) + Register 5.53. DPORT_PRO_SPI_INTR_1_MAP_REG (0x178) + Register 5.54. DPORT_PRO_SPI_INTR_2_MAP_REG (0x17C) + Register 5.55. DPORT_PRO_SPI_INTR_3_MAP_REG (0x180) + + Register 5.56. DPORT_PRO_I2S0_INT_MAP_REG (0x184) + Register 5.57. DPORT_PRO_I2S1_INT_MAP_REG (0x188) + Register 5.58. DPORT_PRO_UART_INTR_MAP_REG (0x18C) + Register 5.59. DPORT_PRO_UART1_INTR_MAP_REG (0x190) + +ুᶈྐ༏॓࠯ 100 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.60. DPORT_PRO_UART2_INTR_MAP_REG (0x194) + Register 5.61. DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (0x198) + + Register 5.62. DPORT_PRO_EMAC_INT_MAP_REG (0x19C) + Register 5.63. DPORT_PRO_PWM0_INTR_MAP_REG (0x1A0) + Register 5.64. DPORT_PRO_PWM1_INTR_MAP_REG (0x1A4) + + Register 5.65. DPORT_PRO_LEDC_INT_MAP_REG (0x1B0) + Register 5.66. DPORT_PRO_EFUSE_INT_MAP_REG (0x1B4) + Register 5.67. DPORT_PRO_TWAI_INT_MAP_REG (0x1B8) + Register 5.68. DPORT_PRO_RTC_CORE_INTR_MAP_REG (0x1BC) + Register 5.69. DPORT_PRO_RMT_INTR_MAP_REG (0x1C0) + Register 5.70. DPORT_PRO_PCNT_INTR_MAP_REG (0x1C4) + Register 5.71. DPORT_PRO_I2C_EXT0_INTR_MAP_REG (0x1C8) + Register 5.72. DPORT_PRO_I2C_EXT1_INTR_MAP_REG (0x1CC) + Register 5.73. DPORT_PRO_RSA_INTR_MAP_REG (0x1D0) + Register 5.74. DPORT_PRO_SPI1_DMA_INT_MAP_REG (0x1D4) + Register 5.75. DPORT_PRO_SPI2_DMA_INT_MAP_REG (0x1D8) + Register 5.76. DPORT_PRO_SPI3_DMA_INT_MAP_REG (0x1DC) + Register 5.77. DPORT_PRO_WDG_INT_MAP_REG (0x1E0) + Register 5.78. DPORT_PRO_TIMER_INT1_MAP_REG (0x1E4) + Register 5.79. DPORT_PRO_TIMER_INT2_MAP_REG (0x1E8) + Register 5.80. DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (0x1EC) + Register 5.81. DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (0x1F0) + Register 5.82. DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (0x1F4) + Register 5.83. DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (0x1F8) + Register 5.84. DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (0x1FC) + Register 5.85. DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (0x200) + Register 5.86. DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (0x204) + Register 5.87. DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (0x208) + Register 5.88. DPORT_PRO_MMU_IA_INT_MAP_REG (0x20C) + Register 5.89. DPORT_PRO_MPU_IA_INT_MAP_REG (0x210) + Register 5.90. DPORT_PRO_CACHE_IA_INT_MAP_REG (0x214) + + (reserved) DPORT_PRO_*_MAP + +31 54 0 + +000000000000000000000000000 10000 Reset + + DPORT_PRO_*_MAP ᇏ؎ؓႋܱ༢஥ᇂ࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 101 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.91. DPORT_APP_MAC_INTR_MAP_REG (0x218) + Register 5.92. DPORT_APP_MAC_NMI_MAP_REG (0x21C) + + Register 5.93. DPORT_APP_BB_INT_MAP_REG (0x220) + Register 5.94. DPORT_APP_BT_MAC_INT_MAP_REG (0x224) + Register 5.95. DPORT_APP_BT_BB_INT_MAP_REG (0x228) + Register 5.96. DPORT_APP_BT_BB_NMI_MAP_REG (0x22C) + Register 5.97. DPORT_APP_RWBT_IRQ_MAP_REG (0x230) + Register 5.98. DPORT_APP_RWBLE_IRQ_MAP_REG (0x234) + Register 5.99. DPORT_APP_RWBT_NMI_MAP_REG (0x238) + Register 5.100. DPORT_APP_RWBLE_NMI_MAP_REG (0x23C) + Register 5.101. DPORT_APP_SLC0_INTR_MAP_REG (0x240) + Register 5.102. DPORT_APP_SLC1_INTR_MAP_REG (0x244) + Register 5.103. DPORT_APP_UHCI0_INTR_MAP_REG (0x248) + Register 5.104. DPORT_APP_UHCI1_INTR_MAP_REG (0x24C) + Register 5.105. DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (0x250) + Register 5.106. DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (0x254) + Register 5.107. DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (0x258) + Register 5.108. DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (0x25C) + Register 5.109. DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (0x260) + Register 5.110. DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (0x264) + Register 5.111. DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (0x268) + Register 5.112. DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (0x26C) + Register 5.113. DPORT_APP_GPIO_INTERRUPT_MAP_REG (0x270) + Register 5.114. DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (0x274) + Register 5.115. DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (0x278) + Register 5.116. DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (0x27C) + Register 5.117. DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (0x280) + Register 5.118. DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (0x284) + Register 5.119. DPORT_APP_SPI_INTR_0_MAP_REG (0x288) + Register 5.120. DPORT_APP_SPI_INTR_1_MAP_REG (0x28C) + Register 5.121. DPORT_APP_SPI_INTR_2_MAP_REG (0x290) + Register 5.122. DPORT_APP_SPI_INTR_3_MAP_REG (0x294) + + Register 5.123. DPORT_APP_I2S0_INT_MAP_REG (0x298) + Register 5.124. DPORT_APP_I2S1_INT_MAP_REG (0x29C) + Register 5.125. DPORT_APP_UART_INTR_MAP_REG (0x2A0) + +ুᶈྐ༏॓࠯ 102 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.126. DPORT_APP_UART1_INTR_MAP_REG (0x2A4) + Register 5.127. DPORT_APP_UART2_INTR_MAP_REG (0x2A8) + Register 5.128. DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (0x2AC) + Register 5.129. DPORT_APP_EMAC_INT_MAP_REG (0x2B0) + Register 5.130. DPORT_APP_PWM0_INTR_MAP_REG (0x2B4) + Register 5.131. DPORT_APP_PWM1_INTR_MAP_REG (0x2B8) + + Register 5.132. DPORT_APP_LEDC_INT_MAP_REG (0x2C4) + Register 5.133. DPORT_APP_EFUSE_INT_MAP_REG (0x2C8) + Register 5.134. DPORT_APP_TWAI_INT_MAP_REG (0x2CC) + Register 5.135. DPORT_APP_RTC_CORE_INTR_MAP_REG (0x2D0) + Register 5.136. DPORT_APP_RMT_INTR_MAP_REG (0x2D4) + Register 5.137. DPORT_APP_PCNT_INTR_MAP_REG (0x2D8) + Register 5.138. DPORT_APP_I2C_EXT0_INTR_MAP_REG (0x2DC) + Register 5.139. DPORT_APP_I2C_EXT1_INTR_MAP_REG (0x2E0) + Register 5.140. DPORT_APP_RSA_INTR_MAP_REG (0x2E4) + Register 5.141. DPORT_APP_SPI1_DMA_INT_MAP_REG (0x2E8) + Register 5.142. DPORT_APP_SPI2_DMA_INT_MAP_REG (0x2EC) + Register 5.143. DPORT_APP_SPI3_DMA_INT_MAP_REG (0x2F0) + Register 5.144. DPORT_APP_WDG_INT_MAP_REG (0x2F4) + Register 5.145. DPORT_APP_TIMER_INT1_MAP_REG (0x2F8) + Register 5.146. DPORT_APP_TIMER_INT2_MAP_REG (0x2FC) + Register 5.147. DPORT_APP_TG_T0_EDGE_INT_MAP_REG (0x300) + Register 5.148. DPORT_APP_TG_T1_EDGE_INT_MAP_REG (0x304) + Register 5.149. DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (0x308) + Register 5.150. DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (0x30C) + Register 5.151. DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (0x310) + Register 5.152. DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (0x314) + Register 5.153. DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (0x318) + Register 5.154. DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (0x31C) + Register 5.155. DPORT_APP_MMU_IA_INT_MAP_REG (0x320) + Register 5.156. DPORT_APP_MPU_IA_INT_MAP_REG (0x324) + Register 5.157. DPORT_APP_CACHE_IA_INT_MAP_REG (0x328) + + (reserved) DPORT_APP_*_MAP + +31 54 0 + +000000000000000000000000000 10000 Reset + + DPORT_APP_*_MAP ᇏ؎ؓႋܱ༢஥ᇂ࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 103 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.158. DPORT_AHBLITE_MPU_TABLE_UART_REG (0x32C) + Register 5.159. DPORT_AHBLITE_MPU_TABLE_SPI1_REG (0x330) + Register 5.160. DPORT_AHBLITE_MPU_TABLE_SPI0_REG (0x334) + Register 5.161. DPORT_AHBLITE_MPU_TABLE_GPIO_REG (0x338) + Register 5.162. DPORT_AHBLITE_MPU_TABLE_RTC_REG (0x348) + Register 5.163. DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (0x34C) + Register 5.164. DPORT_AHBLITE_MPU_TABLE_HINF_REG (0x354) + Register 5.165. DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (0x358) + Register 5.166. DPORT_AHBLITE_MPU_TABLE_I2S0_REG (0x364) + Register 5.167. DPORT_AHBLITE_MPU_TABLE_UART1_REG (0x368) + Register 5.168. DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (0x374) + Register 5.169. DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (0x378) + Register 5.170. DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (0x37C) + Register 5.171. DPORT_AHBLITE_MPU_TABLE_RMT_REG (0x380) + Register 5.172. DPORT_AHBLITE_MPU_TABLE_PCNT_REG (0x384) + Register 5.173. DPORT_AHBLITE_MPU_TABLE_SLC_REG (0x388) + Register 5.174. DPORT_AHBLITE_MPU_TABLE_LEDC_REG (0x38C) + Register 5.175. DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (0x390) + Register 5.176. DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (0x394) + Register 5.177. DPORT_AHBLITE_MPU_TABLE_PWM0_REG (0x39C) + Register 5.178. DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (0x3A0) + Register 5.179. DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (0x3A4) + Register 5.180. DPORT_AHBLITE_MPU_TABLE_SPI2_REG (0x3A8) + Register 5.181. DPORT_AHBLITE_MPU_TABLE_SPI3_REG (0x3AC) + Register 5.182. DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG (0x3B0) + Register 5.183. DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (0x3B4) + Register 5.184. DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (0x3B8) + Register 5.185. DPORT_AHBLITE_MPU_TABLE_EMAC_REG (0x3BC) + Register 5.186. DPORT_AHBLITE_MPU_TABLE_PWM1_REG (0x3C4) + Register 5.187. DPORT_AHBLITE_MPU_TABLE_I2S1_REG (0x3C8) + Register 5.188. DPORT_AHBLITE_MPU_TABLE_UART2_REG (0x3CC) + +ুᶈྐ༏॓࠯ 104 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.189. DPORT_AHBLITE_MPU_TABLE_PWR_REG (0x3E4) + + (reserved) DPORT_AHBLITE_*_ACCESS_GRANT_CONFIG + +31 65 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_AHBLITE_*_ACCESS_GRANT_CONFIG ஥ᇂຓഡ MPUbč‫؀‬ĔཿĎ + + Register 5.190. DPORT_IMMU_TABLEn_REG (n: 0­15) (0x504+4*n) + + (reserved) DPORT_IMMU_TABLEn + +31 76 0 + +0000000000000000000000000 15 Reset + + DPORT_IMMU_TABLEn ஥ᇂ Internal SRAM ֥ MMUbn ູ 0 ~ 9 ൈđreset ᆴູ 0bn ູ 10 ~ 15 + ൈđreset ᆴ‫ٳ‬љູ 10, 11, 12, 13, 14, 15bč‫؀‬ĔཿĎ + + Register 5.191. DPORT_DMMU_TABLEn_REG (n: 0­15) (0x544+4*n) + + (reserved) DPORT_DMMU_TABLEn + +31 76 0 + +0000000000000000000000000 15 Reset + + DPORT_DMMU_TABLEn ஥ᇂ Internal SRAM ֥ MMUbn ູ 0 ~ 15 ൈđreset ᆴ‫ٳ‬љູ 0 ~ 15bč‫؀‬ + ĔཿĎ + +ুᶈྐ༏॓࠯ 105 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 5 DPort ࠷թఖ + + Register 5.192. DPORT_SPI_DMA_CHAN_SEL_REG (0x5A8) + + (reserved) DPORT_SPDI_PSOPRI3T__DSMPDAI_P_SCOPHRI2AT_N_DS_MPSAIE__LSCPHI1A_ND_MSAE_LCHAN_SEL + +31 65 43 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DPORT_SPI_SPI3_DMA_CHAN_SEL ࿊ᄴ SPI3 ֥ DMA ྐ֡bč‫؀‬ĔཿĎ + DPORT_SPI_SPI2_DMA_CHAN_SEL ࿊ᄴ SPI2 ֥ DMA ྐ֡bč‫؀‬ĔཿĎ + DPORT_SPI_SPI1_DMA_CHAN_SEL ࿊ᄴ SPI1 ֥ DMA ྐ֡bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 106 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 6 DMA ॥ᇅఖ (DMA) + +6 DMA ॥ᇅఖ (DMA) + +6.1 ‫ۀ‬ඍ + +ᆰࢤթԥ٠໙ (Direct Memory Access, DMA) ႨႿᄝຓഡაթԥఖᆭࡗၛࠣթԥఖაթԥఖᆭࡗิ‫ۚ܂‬෎ඔऌ +Ԯൻbॖၛᄝ໭ླ಩‫ ޅ‬CPU Ҡቔ֥౦ঃ༯๙‫ ݖ‬DMA ॹ෎၍‫׮‬ඔऌđՖ‫ۚิط‬ਔ CPU ི֥ੱb +ESP32 ᇏႵ 13 ۱ຓഡ‫׻‬ऎႵ DMA ‫ିۿ‬đᆃ 13 ۱ຓഡ൞ğUART0aUART1aUART2aSPI1aSPI2aSPI3a +I2S0aI2S1aSDIO slaveaSD/MMC hostaEMACaBT ‫ ބ‬Wi-Fib + +6.2 หྟ + +DMA ॥ᇅఖऎႵၛ༯ࠫ۱หׄğ + • AHB ሹཌࡏ‫ܒ‬ + • ᆦӻ϶ච‫ބ۽‬ಆච‫۽‬൬‫ؿ‬ඔऌ + • ඔऌԮൻၛሳࢫູֆ໊đԮൻඔऌਈॖೈࡱщӱ + • ᆦӻ 4-beat burst Ԯൻ + • 328 KB DMA ֹᆶॢࡗ + • ๙‫ ݖ‬DMA ൌགྷۚ෎ඔऌԮൻ + +6.3 ‫ିۿ‬૭ඍ + +ESP32 ᇏ෮Ⴕླေࣉྛۚ෎ඔऌԮൻ֥ଆॶ‫׻‬ऎႵ DMA ‫ିۿ‬bDMA ॥ᇅఖა CPU ֥ඔऌሹཌ൐Ⴈཌྷ๝ֹ֥ +ᆶॢࡗ٠໙ଽ҆ RAMb +۴ऌ۲ሱଆॶ֥ླ౰đ۲۱ଆॶ֥ DMA ॥ᇅఖ‫ିۿ‬Ⴕ෮ҵљđ֌൞ DMA ႄౣ (DMA_ENGINE) ֥ࢲ‫ܒ‬ཌྷ +๝b + +6.3.1 DMA ႄౣ֥ࡏ‫ܒ‬ + + ๭ 6­1. DMA ႄౣ֥ࡏ‫ܒ‬ + +DMA ႄౣ๙‫ ݖ‬AHB_BUS ࡼඔऌթೆଽ҆ RAM ࠇᆀࡼඔऌՖ RAM ౼ԛb๭ 6-1 ູ DMA ႄౣࠎЧࡏ‫ܒ‬๭bః +ᇏ RAM ູ ESP32 ֥ଽ҆ SRAMđSRAM ֥ऎุ൐Ⴈٓຶབྷ࡮ᅣࢫ༢๤‫ބ‬թԥఖbೈࡱॖၛ๙‫ܫݖ‬ᄛ৽і֥ٚ + +ুᶈྐ༏॓࠯ 107 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 6 DMA ॥ᇅఖ (DMA) + +ൔট൐Ⴈ DMA ႄౣbDMA_ENGING ۴ऌ out_link ᇏ֥ଽಸࡼཌྷႋ RAM ᇏ֥ඔऌ‫ؿ‬ෂԛಀđ္ॖ۴ऌ in_link +ᇏ֥ଽಸࡼࢤ൬֥ඔऌթೆᆷ‫ ק‬RAM ֹᆶॢࡗb + +6.3.2 ৽і + + ๭ 6­2. ৽іࢲ‫ܒ‬๭ + +out_link ა in_link ࢲ‫ܒ‬ཌྷ๝đ๭ 6-2 ෮ൕູ৽і֥ࢲ‫ܒ‬๭đ၂۱৽іႮ 3 ۱ሳቆӮbૄ၂ሳ‫֥؍‬ၩၬೂ +༯ğ + + • owner (DW0) [31]ğіൕ֒భ৽іؓႋ֥ buffer ᄍྸ֥Ҡቔᆀb + 1’b0ğᄍྸ֥Ҡቔᆀູ CPUĠ + 1’b1ğᄍྸ֥Ҡቔᆀູ DMA ॥ᇅఖb + + • eof (DW0) [30]ğіൕࢲඏѓᆽb + 1’b0ğ֒భ৽і҂൞ቋު၂۱৽іĠ + 1’b1ğ֒భ৽іູඔऌЇ֥ቋު၂۱৽іb + + • reserved (DW0) [29:24]ğreservedb + ೈࡱ҂ିཿ 1b + + • length (DW0) [23:12]ğіൕ֒భ৽іؓႋ֥ buffer ᇏ֥ႵིሳࢫඔbՖ buffer ᇏ‫؀‬౼ඔऌൈіൕି‫؀ܔ‬౼ + ֥ሳࢫඔĠཟ buffer ᇏթԥඔऌൈіൕၘթඔऌ֥ሳࢫඔb + + • size (DW0) [11:0]ğіൕ֒భ৽іؓႋ֥ buffer ֥նཬb + ᇿၩğնཬсྶሳؓఊb + + • buffer address pointer (DW1)ğbuffer ֹᆶᆷᆌb + ᇿၩğֹᆶсྶሳؓఊb + + • next descriptor address (DW2)ğ༯၂۱৽іֹ֥ᆶᆷᆌb֒భ৽іູቋު၂۱৽іൈ (eof=1)đ‫ھ‬ᆴູ 0b +Ⴈ DMA ࢤ൬ඔऌൈ, ೂ‫ݔ‬၂ᆠඔऌӉ؇ཬႿ۳‫ ֥ק‬buffer Ӊ؇đପહ DMA ҂߶ࢤሢ൐Ⴈᆃ۱ buffer ഺჅॢࡗb +ᆃ൐֤ DMA_ENGING ॖၛႨႿԮൻ಩ၩሳࢫඔ֥ඔऌb + +6.4 UART DMA (UDMA) ॥ᇅఖ + +ESP32 ᇏႵ 3 ۱ UART ࢤ१đ෱ૌ‫܋‬Ⴈ 2 ۱ UDMA ॥ᇅఖbUHCI_UARTx_CEčx ູ 0a1a2Ď࠷թఖႨႿ࿊ +ᄴଧ၂۱ UART ൐Ⴈ֒భ֥ UDMAb + +ুᶈྐ༏॓࠯ 108 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 6 DMA ॥ᇅఖ (DMA) + + ๭ 6­3. UDMA ଆൔඔऌԮൻ + +๭ 6-3 ູ UDMA ٚൔඔऌԮൻ๭bᄝࢤ൬ඔऌభđೈࡱࡼࢤ൬৽іሙС‫ݺ‬bUHCI_INLINK_ADDR ႨႿᆷཟֻ +၂۱ in_link ৽іb࠷թఖсྶ஥ᇂࢤ൬৽і֥֮ 20 ֹ໊ᆶbᇂ໊ UHCI_INLINK_START ᆭުđ๙Ⴈᇶࠏ॥ᇅ +ఖࢤ१ (UHCI) ߶ࡼ UART ࢤ൬֥֞ඔऌԮෂ۳ Decoderbࣜ‫ ݖ‬Decoder ࢳ༅ᆭު֥ඔऌᄝ DMA ႄౣ֥॥ᇅ༯ +թೆࢤ൬৽іᆷ‫ ֥ק‬RAM ॢࡗb +ᄝ‫ؿ‬ෂඔऌభđೈࡱླေࡼ‫ؿ‬ෂ৽і‫ؿބ‬ෂඔऌሙС‫ݺ‬đUHCI_OUTLINK_ADDR ႨႿᆷཟֻ၂۱ out_link ৽іb +࠷թఖсྶ஥ᇂ‫ؿ‬ෂ৽і֥֮ 20 ֹ໊ᆶbᇂ໊ UHCI_OUTLINK_START ᆭުđDMA ႄౣࠧՖ৽іᇏᆷ‫֥ק‬ +RAM ֹᆶ‫؀‬౼ඔऌđѩ๙‫ ݖ‬Encoder ࣉྛඔऌЇ‫ٿ‬ልđಖުࣜ UART ֥‫ؿ‬ෂଆॶԱྛ‫ؿ‬ෂԛಀb +UART DMA ֥ඔऌЇ۬ൔູč‫ ژۯٳ‬+ ඔऌ + ‫ژۯٳ‬ĎbEncoder ႨႿᄝඔऌభުࡆഈ‫ژۯٳ‬đѩࡼඔऌᇏ‫ބ‬ +‫ژۯٳ‬၂ဢ֥ඔऌႨห൹ሳ‫ߐูژ‬bDecoder ႨႿಀԢඔऌЇభު‫ژۯٳ‬đѩࡼඔऌᇏ֥ห൹ሳ‫ູߐูྛࣉژ‬ +‫ژۯٳ‬bඔऌభު֥‫ژۯٳ‬ॖၛႵ৵࿃‫؟‬۱b‫ژۯٳ‬ॖႮ UHCI_SEPER_CHAR ࣉྛ஥ᇂđଏಪᆴູ 0xC0bඔ +ऌᇏა‫ژۯٳ‬၂ဢ֥ඔऌॖၛႨ UHCI_ESC_SEQ0_CHAR0čଏಪູ 0xDBĎ‫ ބ‬UHCI_ESC_SEQ0_CHAR1čଏ +ಪູ 0xDDĎࣉྛูߐb֒ඔऌಆ҆‫ؿ‬ෂປӮުđ߶Ӂള UHCI_OUT_TOTAL_EOF_INT ᇏ؎b֒ඔऌࢤ൬ປӮ +ުđ߶Ӂള UHCI_IN_SUC_EOF_INT ᇏ؎b + + ඪૼğ + ླေᇿၩ֥൞đࢤ൬৽і૭ඍ‫֥ژ‬ҕඔ buffer address pointer ླေοሳؓఊđѩ౏ቋު၂۱૭ඍ‫֥ژ‬ҕඔ size ླေᇀ + ഒбࢤ൬֥ඔऌӉ؇ն 4 ሳࢫb + +ুᶈྐ༏॓࠯ 109 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 6 DMA ॥ᇅఖ (DMA) + +6.5 SPI DMA ॥ᇅఖ + + ๭ 6­4. SPI DMA + +ESP32 SPI Ԣਔ൐Ⴈ CPU ൌགྷაຓഡ֥ඔऌࢌߐຓđߎॖၛ൐Ⴈ DMA bೂ๭ 6-4 ෮ൕđ‫܋‬Ⴕਆ۱ DMA ๙֡ +ॖ‫ ܂‬SPI1aSPI2 ‫ ބ‬SPI3 ॥ᇅఖ࿊ᄴđૄ۱ DMA ๙֡ॖ‫܂‬၂۱ SPI ॥ᇅఖ൐ႨđࠧૄՑॖၛႵਆ۱ SPI ॥ᇅ +ఖ๝ൈ൐Ⴈ DMAb + +ESP32 SPI DMA ൐Ⴈ৽іࢤ൬/‫ؿ‬ෂඔऌđ‫ؿ‬ෂඔऌᆦӻ burst Ҡቔđ၂Ցࢤ൬/‫ؿ‬ෂ֥ඔऌӉ؇ᇀഒູ 1 ۱ሳ +ࢫbSPI DMA ᆦӻ৵࿃൬‫ؿ‬ඔऌb + +஥ᇂ DPORT_SPI_DMA_CHAN_SEL_REG ࠷թఖ֥ SPI1_DMA_CHAN_SEL[1:0]aSPI2_DMA_CHAN_SEL[1:0] +‫ ބ‬SPI3_DMA_CHAN_SEL[1:0] ೘۱თၛ൐ି SPI DMA ࢤ१bૄ۱ SPI ॥ᇅఖؓႋ၂۱თđૄ۱თႵ 2 бหđ +ؓႋ౼ᆴູ 0a1 ‫ ބ‬2đ‫ط‬҂ॖၛ౼ 3 b + +ၛ SPI1 ູ২đ +೏ SPI1_DMA_CHAN_SEL[1:0] = 0đପહ SPI1 ҂൐Ⴈ DMA ๙֡Ġ +೏ SPI1_DMA_CHAN_SEL[1:0] = 1đପહ SPI1 ൐ି DMA ๙֡ 1Ġ +೏ SPI1_DMA_CHAN_SEL[1:0] = 2đପહ SPI1 ൐ି DMA ๙֡ 2b + +࠷թఖ SPI_DMA_OUT_LINK_REG ֥ SPI_OUTLINK_START бห‫࠷ބ‬թఖ SPI_DMA_IN_LINK_REG ֥ +SPI_INLINK_START бหႨႿ൐ି DMA ႄౣđᆃਆ۱бหႮ႗ࡱౢਬb֒ SPI_OUTLINK_START бหФᇂູ 1 +ൈđDMA ႄౣष൓ԩ৘‫ؿ‬ෂ৽іđѩሙС‫ؿ‬ෂඔऌĠ֒ SPI_INLINK_START бหФᇂູ 1 ൈđDMA ႄౣष൓ +ԩ৘ࢤ൬৽іđѩሙСࢤ൬ඔऌb + +SPI_DMA ࢤ१֥ೈࡱ஥ᇂੀӱೂ༯ğ + + 1. ൮༵‫ ໊گ‬DMA ሑ෿ࠏ‫ ބ‬FIFO ᆷᆌĠ + + 2. ஥ᇂ DMA ཌྷܱ࠷թఖĠ + + 3. ஥ᇂ SPI ࢤ१ཌྷܱ࠷թఖĠ + + 4. ൐ି၂Ց DMA Ҡቔb + +ুᶈྐ༏॓࠯ 110 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 6 DMA ॥ᇅఖ (DMA) + +6.6 I2S DMA ॥ᇅఖ + +ESP32 Ⴕਆ۱ I2S ࢤ१đࠧ I2S0 ‫ ބ‬I2S1bI2S0 ‫ ބ‬I2S1 ۲Ⴕ၂۱ DMA ๙֡b࠷թఖ I2S_FIFO_CONF_REG ֥ +REG_I2S_DSCR_EN бหႨႿ൐ି I2S ֥ DMA ҠቔbESP32 I2S DMA ൐Ⴈ৽іࢤ൬/‫ؿ‬ෂඔऌđ‫ؿ‬ෂඔऌᆦӻ +burst Ҡቔđ၂Ցࢤ൬/‫ؿ‬ෂ֥ඔऌӉ؇ູ 1 ۱ሳč4 ۱ሳࢫĎb࠷թఖ I2S_RXEOF_NUM_REG ֥ +REG_I2S_RX_EOF_NUM[31:0] бหႨႿ஥ᇂ DMA ၂Ցࢤ൬ඔऌӉ؇đֆູ໊ሳb + +࠷թఖ I2S_OUT_LINK_REG ֥ I2S_OUTLINK_START бห‫࠷ބ‬թఖ I2S_IN_LINK_REG ֥ I2S_INLINK_START +бหႨႿ൐ି DMA ႄౣ, ᆃਆ۱бหႮ႗ࡱౢਬb֒ I2S_OUTLINK_START бหФᇂູ 1 ൈđDMA ႄౣष൓ +ԩ৘‫ؿ‬ෂ৽іđѩሙС‫ؿ‬ෂඔऌđ֒ I2S_INLINK_START бหФᇂູ 1 ൈđDMA ႄౣष൓ԩ৘ࢤ൬৽іđѩሙ +Сࢤ൬ඔऌb + +I2S DMA ࢤ१֥ೈࡱ஥ᇂੀӱೂ༯ğ + + 1. ൮༵஥ᇂ I2S ࢤ१ཌྷܱ࠷թఖĠ + + 2. ‫ ໊گ‬DMA ሑ෿ࠏ‫ ބ‬FIFO ᆷᆌĠ + + 3. ஥ᇂ DMA ཌྷܱ࠷թఖĠ + + 4. ᄝ I2S ᇶࠏଆൔ༯đഡᇂ I2S_TX_START бหࠇᆀ I2S_RX_START бหđ‫ؿ‬ఏ၂Ց I2S ҠቔĠ + ᄝ I2S Ֆࠏଆൔ༯đഡᇂ I2S_TX_START бหࠇᆀ I2S_RX_START бหު֩րᇶࠏ‫ؿ‬ఏඔऌԮൻ֥౨౰b + +I2S DMA ᇏ؎ඪૼབྷ࡮ᅣࢫ I2SđDMA ᇏ؎ b + +ুᶈྐ༏॓࠯ 111 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + +7 SPI ॥ᇅఖ (SPI) + +7.1 ‫ۀ‬ඍ + + ๭ 7­1. SPI ༢๤ॿ๭ + + ೂ๭ 7-1 ෮ൕđESP32 ‫܋‬Ⴕ 4 ۱ SPI ॥ᇅఖ SPI0aSPI1aSPI2aSPI3đႨႿ৵ࢤᆦӻ SPI ླྀၰ֥ഡСbSPI0 + ॥ᇅఖቔູ cache ٠໙ຓ҆թԥֆჭࢤ१൐ႨđSPI1 ቔູᇶࠏ൐ႨđSPI2 ‫ ބ‬SPI3 ॥ᇅఖ࠻ॖቔູᇶࠏ൐ႨႻ + ॖቔູՖࠏ൐Ⴈbቔᇶࠏ൐Ⴈൈđૄ۱ SPI ॥ᇅఖॖၛ൐Ⴈ‫؟‬۱ோ࿊ྐ‫( ݼ‬CS0 ~ CS2) ট৵ࢤ‫؟‬۱ SPI Ֆࠏഡ + СbSPI1 ~ SPI3 ॥ᇅఖ‫܋‬ཚਆ۱ DMA ๙֡b + + SPI0 ‫ ބ‬SPI1 ॥ᇅఖ๙‫ݖ‬၂۱ᇘҊఖ‫܋‬Ⴈ၂ቆྐ‫ݼ‬ሹཌđᆃቆջభሗ SPI ֥ྐ‫ݼ‬ሹཌႮ DaQaCS0 ~ CS2a + CLKaWP ‫ ބ‬HD ྐ‫ݼ‬ቆӮđೂі 7-1 ෮ൕbཌྷႋֹđ॥ᇅఖ SPI2 ‫ ބ‬SPI3 ‫ٳ‬љ൐Ⴈջభሗ HSPI ‫ ބ‬VSPI ֥ྐ + ‫ݼ‬ሹཌbᆃུྐ‫ݼ‬ሹཌЇ‫֥ݣ‬ൻೆൻԛྐ‫ݼ‬ཌॖၛࣜ‫ ݖ‬GPIO ࢌߐइᆔ‫ ބ‬IO_MUX ଆॶൌགྷაྉோܵ࢖֥႘ഝ +čབྷ࡮ᅣࢫ IO_MUXĎb + + SPI ॥ᇅఖᄝ GP-SPI ଆൔ༯đᆦӻѓሙ֥ඹཌಆච‫۽‬/϶ච‫۽‬๙ྐčMOSIaMISOaCSaCLKĎ‫ބ‬೘ཌ϶ච‫۽‬ + ๙ྐčDATAaCSaCLKĎbSPI ॥ᇅఖᄝ QSPI ଆൔ༯൐Ⴈྐ‫ݼ‬ሹཌ DaQaCS0 ~ CS2aCLKaWP ‫ ބ‬HD ቔູ + 4-bit ѩྛ SPI ሹཌট٠໙ຓ҆ flash ࠇ SRAMb҂๝ଆൔ༯ܵ࢖‫ݼྐିۿ‬აሹཌྐ‫֥ؓݼ‬ႋܱ༢ೂі 7-1 ෮ + ൕb + + і 7­1. ܵ࢖‫ݼྐିۿ‬აሹཌྐ‫ݼ‬႘ഝܱ༢ + +GP-SPI ඹཌ GP-SPI ೘ཌ QSPI ႄ࢖‫ݼྐିۿ‬ + ྐ‫ݼ‬ሹཌ HSPI ྐ‫ݼ‬ሹཌ +ಆච‫۽‬/϶ච‫ݼྐ۽‬ሹཌ ϶ච‫ݼྐ۽‬ሹཌ D SPI ྐ‫ݼ‬ሹཌ HSPID VSPI ྐ‫ݼ‬ሹཌ + Q SPID HSPIQ VSPID +MOSI DATA CS SPIQ HSPICS0 VSPIQ + CLK SPICS0 HSPICLK VSPICS0 +MISO - WP SPICLK HSPIWP VSPICLK + HD SPIWP HSPIHD VSPIWP +CS CS SPIHD VSPIHD + +CLK CLK + +- - + +- - + +7.2 SPI หᆘ + +GP­SPIč๙Ⴈ SPIĎࢤ१ + + • ඔऌԮൻӉ؇ၛ byte ູֆ໊ॖ஥ᇂ + + • ᆦӻඹཌಆච‫۽‬/϶ච‫۽‬๙ྐ‫ބ‬೘ཌ϶ච‫۽‬๙ྐ + +ুᶈྐ༏॓࠯ 112 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + • ᇶࠏଆൔ‫ބ‬Ֆࠏଆൔ + • ൈᇒࠞྟ (CPOL) ‫ބ‬ൈᇒཌྷ໊ (CPHA) ॖ஥ᇂ + • ൈᇒॖ஥ᇂ +ѩྛ QSPI ࢤ१ + • ᆦӻᇭೂ flash ֩ห൹ՖࠏഡС֥๙ྐ۬ൔ + • ॖ஥ᇂ֥๙ྐ۬ൔ + • ᆦӻ 6 ᇕ‫ ؀‬flash Ҡቔ + • ᆦӻ٠໙ flash ‫ ބ‬SRAM ሱ‫ߐ్׮‬ + • ᆦӻሱ‫֩׮‬ր flash ॢ༽ +SPI DMA ࢤ१ + • ᆦӻ൐Ⴈ৽і൬/‫ؿ‬ඔऌ +SPI ᇏ؎ࢤ१ + • SPI ᇏ؎ + • SPI DMA ᇏ؎ + +7.3 GP­SPI ࢤ१ + +ESP32 SPI ᆦӻඹཌಆච‫۽‬/϶ච‫۽‬๙ྐ‫ބ‬೘ཌ϶ච‫۽‬๙ྐbඹཌಆච‫۽‬/϶ච‫۽‬๙ྐ‫׈‬గ৵ࢤೂ๭ 7-2 ෮ +ൕb + + ๭ 7­2. SPI ඹཌಆච‫۽‬/϶ච‫۽‬๙ྐ + +ESP32 SPI1 ~ SPI3 ॖၛቔູ SPI ᇶࠏაః෰Ֆࠏ๙ྐđSPI2 ‫ ބ‬SPI3 ္ॖၛቔູՖࠏbૄ۱ ESP32 SPI ᇶࠏ +ଏಪቋ‫؟‬ॖၛࢤ 3 ۱Ֆࠏbᄝ٤ DMA ଆൔ༯đ၂Ցቋ‫؟‬ॖၛࢤ൬/‫ؿ‬ෂ 64 byte ֥ඔऌđ൬‫ؿ‬ඔऌӉ؇ၛሳࢫ +ູֆ໊b + +7.3.1 GP­SPI ඹཌಆච‫۽‬ଆൔ + +֒஥ᇂӮඹཌಆච‫۽‬ଆൔൈđESP32 SPI ࠻ॖၛቔູᇶࠏ္ॖၛቔູՖࠏ൐Ⴈb൐Ⴈൈđೈࡱླေ஥ᇂࢤ൬‫ބ‬ +‫ؿ‬ෂඔऌ֥Ӊ؇ğᄝᇶࠏଆൔ༯đ๙‫࠷ݖ‬թఖ SPI_MISO_DLEN_REG ‫ ބ‬SPI_MOSI_DLEN_REG ஥ᇂĠᄝՖࠏ +ଆൔ༯đ๙‫࠷ݖ‬թఖ SPI_SLV_RDBUF_DLEN_REG ‫ ބ‬SPI_SLV_WRBUF_DLEN_REG ஥ᇂbߎླေ஥ᇂ࠷թఖ +SPI_USER_REG ֥ SPI_DOUTDIN ໊‫ ބ‬SPI_USR_MOSI ໊ট൐ିඹཌಆච‫۽‬ଆൔbቋުླေ஥ᇂ࠷թఖ +SPI_CMD_REG ֥ SPI_USR ໊টఓ‫׮‬၂ՑඔऌԮൻb + +ুᶈྐ༏॓࠯ 113 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + +7.3.2 GP­SPI ඹཌ϶ච‫۽‬ଆൔ + +֒஥ᇂӮඹཌ϶ච‫۽‬ଆൔൈđESP32 SPI ࠻ॖၛቔູᇶࠏ္ॖၛቔູՖࠏ൐ႨbՎൈ ESP32 SPI ऎႵਲࠃ֥๙ +ྐ۬ൔğଁ਷ + ֹᆶ + ֩ր + ࢤ൬‫ބ‬/ࠇ‫ؿ‬ෂඔऌbऎุູğ + + 1. ଁ਷ğӉ؇ 0 ~ 16 bitĠᇶࠏൻԛՖࠏൻೆb + + 2. ֹᆶğӉ؇ 0 ~ 32 bit/64 bitĠᇶࠏൻԛՖࠏൻೆb + + 3. ֩րğӉ؇ 0 ~ 256 ۱ SPI ൈᇒb + + 4. ࢤ൬‫ބ‬/ࠇ‫ؿ‬ෂඔऌğӉ؇ 0 ~ 512 bit (64 byte)ĠᇶࠏൻԛՖࠏൻೆࠇᇶࠏൻೆՖࠏൻԛb + +ఃᇏ GP-SPI ᇶࠏଆൔֹ֥ᆶሑ෿ቋնӉ؇ູ 32 bitđQSPI ᇶࠏଆൔֹ֥ᆶሑ෿ቋնӉ؇ູ 64 bitbଁ਷ሑ෿a +ֹᆶሑ෿a֩րሑ෿‫ބ‬൬/‫ؿ‬ඔऌሑ෿‫ٳ‬љؓႋ SPI_USER_REG ࠷թఖ֥ SPI_USR_COMMANDa +SPI_USR_ADDRaSPI_USR_DUMMY ‫ ބ‬SPI_USR_MISO/SPI_USR_MOSI ֩თbࣇ֒ᆃུбห໊Фᇂ 1 ൈđ၂ +Ց SPI ҠቔҌ߶ࣜ৥‫ھ‬ሑ෿đབྷ࡮ᅣࢫ࠷թఖඪૼbቔູᇶࠏ൐Ⴈൈđೈࡱॖၛ۴ऌླေ๙‫ݖ‬஥ᇂ࠷թఖট࿊ +ᄴ൞‫ڎ‬Ї‫ଁݣ‬਷aֹᆶa֩ր‫ࢤބ‬൬ࠇ‫ؿ‬ෂඔऌ֩ሑ෿b + +ቔູՖࠏ൐ႨൈđԮൻൈсྶЇ‫ଁݣ‬਷aֹᆶ‫ࢤބ‬൬ࠇ‫ؿ‬ෂඔऌሑ෿đѩ౏Ֆࠏଁ਷‫ູקܥ‬і 7-2bᄝ၂Ց +൬/‫ݖؿ‬ӱᇏđோ࿊ྐ‫ ݼ‬CS сྶЌӻ֮‫׈‬௜bೂ‫ݔ‬ᄝ‫ؿ‬ෂ‫ݖ‬ӱᇏ CS ФঘۚđՖࠏଽ҆ሑ෿ࡼ߶‫໊گ‬b + + і 7­2. Ֆࠏଁ਷૭ඍ + +ଁ਷ ૭ඍ +0x1 Ֆࠏࢤ൬đࡼᇶࠏ‫ؿ‬ෂඔऌ๙‫ ݖ‬MOSI ཿೆՖࠏሑ෿࠷թఖ +0x2 Ֆࠏࢤ൬đࡼᇶࠏ‫ؿ‬ෂඔऌ๙‫ ݖ‬MOSI ཿೆՖࠏඔऌߏթ +0x3 Ֆࠏ‫ؿ‬ෂđࡼՖࠏߏթᇏ֥ඔऌ๙‫ ݖ‬MISO ‫ؿ‬ෂ֞ᇶࠏ +0x4 Ֆࠏ‫ؿ‬ෂđࡼՖࠏሑ෿࠷թఖᇏ֥ඔऌ๙‫ ݖ‬MISO ‫ؿ‬ෂ֞ᇶࠏ +0x6 ༵ࡼ MOSI ഈ֥ᇶࠏඔऌཿೆඔऌߏթđಖުᄜࡼՖࠏඔऌߏթᇏ֥ඔऌ‫ؿ‬ෂᇀ MISO + +ᇶࠏॖၛཿ SPI Ֆࠏ֥ሑ෿࠷թఖ SPI_SLV_WR_STATUS_REGđѩॖၛ๙‫ ݖ‬SPI_SLAVE1_REG ࠷թఖᇏ֥ +SPI_SLV_STATUS_READBACK ໊đथ‫ ؀ק‬SPI_SLV_WR_STATUS_REG ࠷թఖߎ൞ SPI_RD_STATUS_REG ࠷ +թఖ֥ඔऌbSPI ᇶࠏॖၛ๙‫؀ݖ‬ཿՖࠏሑ෿࠷թఖđղ֞აՖࠏЌӻ܎๙֥ଢ֥đၛՎൌགྷࢠ‫گ‬ᄖ֥๙ +ྐb + +ೈࡱ๙‫ݖ‬ᇶࠏଆൔ֥ SPI_MISO_DLEN_REG ‫ ބ‬SPI_MOSI_DLEN_REG ࠷թఖaՖࠏଆൔ֥ +SPI_SLV_RDBUF_DLEN_REGaSPI_SLV_WRBUF_DLEN_REG ট஥ᇂ SPI ࢤ൬ࠇ‫ؿ‬ෂඔऌ֥Ӊ؇b๙‫ݖ‬஥ᇂ࠷ +թఖ SPI_USER_REG ֥ SPI_USR_MOSI ໊ࠇ SPI_USR_MISO ໊ট॥ᇅ SPI ࢤ൬ࠇ‫ؿ‬ෂඔऌbቋު஥ᇂ࠷թఖ +SPI_CMD_REG ֥ SPI_USR ໊টఓ‫׮‬၂ՑඔऌԮൻb + +7.3.3 GP­SPI ೘ཌ϶ච‫۽‬ଆൔ + +ESP32 SPI ֥೘ཌ϶ච‫ބ۽‬ඹཌ϶ච‫֥۽‬౵љᄝႿࢤ൬‫ؿބ‬ෂඔऌ൐Ⴈ๝၂۴ྐ‫ݼ‬ཌđ౏сྶЇ‫ଁݣ‬਷aֹᆶ +‫ࢤބ‬൬ࠇ‫ؿ‬ෂඔऌሑ෿bೈࡱླေ๙‫ݖ‬஥ᇂ SPI_USER_REG ࠷թఖ֥ SPI_SIO ໊ট൐ି೘ཌ϶ච‫۽‬ଆ +ൔb + + ඪૼğ + + • ᄝ϶ච‫۽‬ଆൔ༯đଁ਷aֹᆶ‫ࢤބ‬൬ࠇ‫ؿ‬ෂඔऌ֥ඨ྽҂ॖэĠ + • ᄝ϶ච‫۽‬ଆൔ༯đoଁ਷ + ֹᆶ + ൬൬ऌ + ‫ؿ‬ඔऌp‫ބ‬o൬ඔऌ + ‫ؿ‬ඔऌpᆃਆᇕ๙ྐ۬ൔ҂ᆦӻ DMAĠ + +ুᶈྐ༏॓࠯ 114 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + • ESP32 SPI ቔູՖࠏൈđᇶࠏ CS ླေิభᇀഒ၂۱ SPI ൈᇒӉ؇ႵིĠ‫؀‬/ཿࢲඏުđCS ླေᇀഒ࿼Ӿ၂۱ + SPI ൈᇒӉ؇ാིb + +7.3.4 GP­SPI ඔऌߏթ + + ๭ 7­3. SPI ඔऌߏթ + +ESP32 SPI ‫܋‬Ⴕնཬູ 16 × 32 bit ֥ඔऌߏթđႨႿթԥ‫ؿ‬ෂ/ࢤ൬֥ඔऌbೂ๭ 7-3 ෮ൕbࢤ൬ඔऌൈđඔऌ +ଏಪՖ SPI_W0_REG ֥֮ሳࢫ҆‫ٳ‬ष൓แԉđ၂ᆰ֞ SPI_W15_REG ࢲඏbೂ‫ݔ‬ඔऌӉ؇նႿ 64 byteđ‫؟‬ԛ +҆‫ٳ‬Ֆ SPI_W0_REG ष൓࠿࿃แԉb + +ඔऌߏթ֥ SPI_W0_REG ~ SPI_W7_REG ‫ ބ‬SPI_W8_REG ~ SPI_W15_REG ‫ٳ‬љؓႋ֮‫ۚބ‬ਆ۱҆‫ٳ‬đ෰ +ૌॖၛ‫ٳ‬ष൐ႨbႮ࠷թఖ SPI_USER_REG ֥ SPI_USR_MOSI_HIGHPART ‫ ބ‬SPI_USR_MISO_HIGHPART ਆ +۱бห॥ᇅb২ೂđ֒ SPI ቔູᇶࠏđ֒ SPI_USR_MOSI_HIGHPART = 1 ൈđSPI_W8_REG ~ SPI_W15_REG +ቔູ‫ؿ‬ෂඔऌߏթ൐Ⴈđ֒ SPI_USR_MISO_HIGHPART = 1 ൈđSPI_W8_REG-SPI_W15_REG ቔູࢤ൬ඔऌߏ +թ൐Ⴈb‫ ֒ط‬SPI ቔູՖࠏൈđ೏ SPI_USR_MOSI_HIGHPART = 1đᄵ SPI_W8_REG ~ SPI_W15_REG ቔູ +ࢤ൬ඔऌߏթ൐Ⴈđ೏ SPI_USR_MISO_HIGHPART = 1đᄵ SPI_W8_REG-SPI_W15_REG ቔູ‫ؿ‬ෂඔऌߏթ൐ +Ⴈb + +7.4 GP­SPI ൈᇒ॥ᇅ + +ESP32 GP-SPI ᇶࠏൻԛൈᇒ௔ੱቋູۚ fapb/2đՖࠏൻೆൈᇒቋູۚ fapb/8bᇶࠏॖၛ๙‫ٳݖ‬௔֤֞ః෰ൈ +ᇒ௔ੱb + + fspi = fapb + (SPI_CLKCNT_N+1)(SPI_CLKDIV_PRE+1) + +ఃᇏ SPI_CLKCNT_N ‫ ބ‬SPI_CLKDIV_PRE ູ࠷թఖ SPI_CLOCK_REG ֥ਆ۱໊čབྷ࡮ 7.7 ࠷թఖ૭ඍĎđ + +SPI_CLKCNT_H = ⌊ SPI_CLKCNT_N+1 –1⌋đSPI_CLKCNT_N=SPI_CLKCNT_Lb֒࠷թఖ SPI_CLOCK_REG + 2 + +֥ + +SPI_CLK_EQU_SYSCLK ໊ᇂ 1đః෰໊ᇂູ 0 ൈđSPI ൻԛൈᇒູ fapbĠԢՎᆭຓđSPI_CLK_EQU_SYSCLK +໊नླᇂູ 0bᄝՖࠏଆൔ༯đSPI_CLKCNT_NaSPI_CLKCNT_LaSPI_CLKCNT_H ‫ ބ‬SPI_CLKDIV_PRE नླ + +ေᇂູ 0b + +7.4.1 GP­SPI ൈᇒࠞྟ‫ބ‬ൈᇒཌྷ໊ + +ESP32 SPI ֥ൈᇒࠞྟ‫ބ‬ཌྷ໊đႮ࠷թఖ SPI_PIN_REG ֥ SPI_CK_IDLE_EDGE ໊a࠷թఖ SPI_USER_REG +֥ SPI_CK_OUT_EDGE ໊ა SPI_CK_I_EDGE ໊đၛࠣ SPI_CTRL2_REG ࠷թఖ֥ +SPI_MISO_DELAY_MODE[1:0] ໊aSPI_MISO_DELAY_NUM[2:0] ໊aSPI_MOSI_DELAY_MODE[1:0] ໊ა +SPI_MOSI_DELAY_MUM[2:0] ໊॥ᇅbі 7-3 ‫ބ‬і 7-4 ‫ٳ‬љؓႋູ ESP32 SPI ᇶࠏ‫ބ‬Ֆࠏൈᇒࠞྟ‫ބ‬ཌྷ໊॥ᇅ + +ুᶈྐ༏॓࠯ 115 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + +ࠣఃؓႋ࠷թఖᆴbі 7-4 ᇏ mode0 ‫ ބ‬mode2 ‫ ູٳ‬DMA ଆൔ‫ބ‬٤ DMA ଆൔ༯֥࠷թఖ஥ᇂbླေᇿၩ֥൞ +DMA ଆൔ༯ mode0 ‫ ބ‬mode2 Ֆࠏ֥ඔऌ߶ิభൻԛb + + і 7­3. ᇶࠏଆൔൈᇒࠞྟ‫ބ‬ཌྷ໊॥ᇅ࠷թఖᆴ + +࠷թఖ mode0 mode1 mode2 mode3 +SPI_CK_IDLE_EDGE 0 0 1 1 +SPI_CK_OUT_EDGE 0 1 1 0 +SPI_MISO_DELAY_MODE 2(0) 1(0) 1(0) 2(0) +SPI_MISO_DELAY_NUM 0 0 0 0 +SPI_MOSI_DELAY_MODE 0 0 0 0 +SPI_MOSI_DELAY_NUM 0 0 0 0 + + і 7­4. Ֆࠏଆൔൈᇒࠞྟ‫ބ‬ཌྷ໊॥ᇅ࠷թఖᆴ + +࠷թఖ mode0 mode1 mode2 mode3 + +SPI_CK_IDLE_EDGE ٤ DMA DMA 1 ٤ DMA DMA 0 +SPI_CK_I_EDGE 1 0 +SPI_MISO_DELAY_MODE 1 0 2 0 1 1 +SPI_MISO_DELAY_NUM 0 0 +SPI_MOSI_DELAY_MODE 0 1 0 1 0 0 +SPI_MOSI_DELAY_NUM 0 0 + 0 0 0 0 + + 0 2 0 2 + + 2 0 1 0 + + 2 3 2 3 + + 1. mode0 іൕ CPOL=0, CPHA=0đSPI ॢ༽ൈđൈᇒ֥ൻԛູ֮‫׈‬௜đඔऌᄝ SPI ༯ࢆခэ߄đᄝഈശခ + ҐဢĠ + + 2. mode1 іൕ CPOL=0, CPHA=1đSPI ॢ༽ൈđൈᇒ֥ൻԛູ֮‫׈‬௜đඔऌᄝ SPI ഈശခэ߄đᄝ༯ࢆခ + ҐဢĠ + + 3. mode2 іൕ CPOL=1, CPHA=0đSPI ॢ༽ൈđൈᇒ֥ൻԛູۚ‫׈‬௜đඔऌᄝ SPI ഈശခэ߄đᄝ༯ࢆခ + ҐဢĠ + + 4. mode3 іൕ CPOL=1, CPHA=1đSPI ॢ༽ൈđൈᇒ֥ൻԛູۚ‫׈‬௜đඔऌᄝ SPI ༯ࢆခэ߄đᄝഈശခ + Ґဢb + +7.4.2 GP­SPI ൈ྽ + +ESP32 GP-SPI ࢤ१֥ඔऌྐ‫࠻ݼ‬ॖၛ๙‫ ݖ‬IO_MUX ႘ഝ֞ܵ࢖đႻॖၛ๙‫ ݖ‬IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ႘ഝ +֞ܵ࢖b֒ྐ‫ݼ‬๙‫ߐࢌݖ‬इᆔൈđൻೆྐ‫߶ݼ‬Ф࿼Ӿਆ۱ clkapb ൈᇒᇛ௹đൻԛྐ‫ݼ‬҂߶Ф࿼Ӿb + +GP-SPI ቔູᇶࠏđѩ౏ྐ‫ݼ‬҂ࣜ‫ ݖ‬GPIO ࢌߐइᆔࣉೆ֞ SPI ॥ᇅఖൈđ೏ GP-SPI ൻԛൈᇒ௔ੱູ clkapb/2đ +ᄵᄝ஥ᇂൈᇒࠞྟൈđ࠷թఖ SPI_MISO_DELAY_MODE ླေᇂູ 0b೏ GP-SPI ൻԛൈᇒ௔ੱ҂նႿ clkapb/4đ +ᄵᄝ஥ᇂൈᇒࠞྟൈđSPI_MISO_DELAY_MODE ॖၛᇂູі 7-3 ᇏ֥ؓႋඔᆴb + +GP-SPI ቔູᇶࠏൈđѩ౏ྐ‫ ݖࣜݼ‬GPIO ࢌߐइᆔࣉೆ֞ SPI ॥ᇅఖğ + + 1. ೂ‫ ݔ‬GP-SPI ൻԛൈᇒ௔ੱູ clkapb/2đᄵᄝ஥ᇂൈᇒࠞྟൈđ࠷թఖ SPI_MISO_DELAY_MODE ླေᇂ + ູ 0đ๝ൈླေ൐ି֩րሑ෿ (SPI_USR_DUMMY = 1)đ֩րӉ؇ູ 1 ۱ clkspi ൈᇒᇛ௹ + (SPI_USR_DUMMY_CYCLELEN = 0)Ġ + +ুᶈྐ༏॓࠯ 116 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + 2. ೂ‫ ݔ‬GP-SPI ൻԛൈᇒ௔ੱູ clkapb/4đᄝ஥ᇂൈᇒࠞྟൈ࠷թఖ SPI_MISO_DELAY_MODE ླေᇂູ 0Ġ + 3. ೂ‫ ݔ‬GP-SPI ൻԛൈᇒ௔ੱ҂նႿ clkapb/8đᄵᄝ஥ᇂൈᇒࠞྟൈđSPI_MISO_DELAY_MODE ॖၛᇂູі + + 7-3 ᇏ֥ؓႋඔᆴb +GP-SPI ቔູՖࠏൈđေ౰ൈᇒྐ‫ބݼ‬ඔऌྐ‫ݼ‬࿊ᄴཌྷ๝֥ٚൔࣉೆ SPI ॥ᇅఖđࠧൈᇒྐ‫ބݼ‬ඔऌྐ‫׻ݼ‬҂ࣜ +‫ ݖࣜ׻ࠇݖ‬GPIO ࢌߐइᆔࣉೆ SPI ॥ᇅఖbᆃဢҌିٝᆸᄝྐ‫֞ݼ‬ղ SPI ႗ࡱᆭభđ࿼Ӿ֥ൈࡗ҂๝b +ၛ mode0 ູ২, ๭ 7-4 ᇏ tspiatpre ‫ ބ‬tv ‫ٳ‬љູ SPI ൈᇒᇛ௹aඔऌൻԛิభൈࡗ‫ބ‬ඔऌൻԛ࿼ުൈࡗđ๝ൈࡌ +ഡ SPI Ֆࠏᇶൈᇒᇛ௹ູ tapbbᄝ٤ DMA ଆൔ༯đՖࠏඔऌ߶࿼ުൻԛđ࿼ުൈࡗ tvğ + + • ೂ‫ ݔ‬CLK ҂ࣜ‫ߐࢌݖ‬इᆔൻೆđପહ tv < 3.5 ∗ tapb; + • ೂ‫ ݔ‬CLK ࣜ‫ߐࢌݖ‬इᆔൻೆđପહ tv < 5.5 ∗ tapb; +ᄝ DMA ଆൔ༯, mode1 ‫ ބ‬mode3, Ֆࠏඔऌ߶࿼ުൻԛ, ࿼ުൈࡗ tv ‫ބ‬٤ DMA ଆൔཌྷ๝b‫ط‬ᄝ mode0 ‫ބ‬ +mode2, Ֆࠏඔऌ߶ิభൻԛ, ิభൈࡗ tpre: + • ೂ‫ ݔ‬clk ҂ࣜ‫ߐࢌݖ‬इᆔൻೆđପહ tpre < (tspi/2 − 5.5 ∗ tapb); + • ೂ‫ ݔ‬clk ࣜ‫ߐࢌݖ‬इᆔൻೆđପહ tpre < (tspi/2 − 7.5 ∗ tapb); + + ๭ 7­4. GP­SPI Ֆࠏඔऌൻԛ + +ၹՎđೂ‫ݼྐݔ‬҂ࣜ‫ߐࢌݖ‬इᆔൻೆՖࠏđପહՖࠏൈᇒቋູۚ fapb/8đೂ‫ߐࢌݖࣜݼྐݔ‬इᆔൻೆՖࠏđପ +હՖࠏൈᇒቋູۚ fapb/12 b๝ൈླေᇿၩ֥൞đ֒ mode0 ‫ ބ‬mode2 ൈđ(tspi/2 − tpre) ္൞Ֆࠏൻԛඔऌ֥Ќ +ӻൈࡗb + +7.5 ѩྛ QSPI ࢤ१ + +ESP32 SPI ॥ᇅఖؓ SPI ࢤ१թԥఖčೂ flashđSRAMĎቓਔห൹֥ᆦӻbSPI ܵ࢖აթԥఖ֥႗ࡱ৵ࢤೂ๭ +7-5 ෮ൕb + +SPI1aSPI2 ‫ ބ‬SPI3 ॥ᇅఖ္ॖၛቔູ QSPI ࢤ१֥ᇶࠏ‫ބ‬ຓ҆թԥఖ৵ࢤbSPI թԥఖࢤ१֥ቋۚൻԛൈᇒ௔ +ੱູ fapbđൈᇒ஥ᇂ‫ ބ‬GP-SPI ࢤ१ᇶࠏൈᇒ஥ᇂཌྷ๝b + +7.5.1 ѩྛ QSPI ࢤ१๙ྐ۬ൔ + +ESP32 QSPI ູਔᆦӻაห൹Ֆࠏଆൔᆭࡗ֥๙ྐđֆ‫׿‬ഡ࠹აᆭཌྷؓႋ֥๙ྐླྀၰbESP32 QSPI ᇶࠏ๙ྐ۬ +ൔა GP-SPI ඹཌ϶ච‫۽‬ଆൔཌྷ๝b҂๝֥൞ᄝֹᆶሑ෿‫ބ‬ඔऌሑ෿đೈࡱॖၛ๙‫ݖ‬஥ᇂ࠷թఖ൐ି 2 ཌࠇᆀ +4 ཌଆൔԮൻඔऌđೂ๭ 7-6 ෮ൕđֹູᆶ‫ބ‬ඔऌनູ 4 ཌԮൻ֥๙ྐଆൔb + +ESP32 QSPI ࢤ१ᆦӻ၂ཌଆൔaਆཌଆൔ‫ބ‬ඹཌଆൔ֥ flash ‫؀‬Ҡቔbა GP-SPI ཌྷ๝đቔູᇶࠏൈđQSPI ଆ +ൔॖၛ۴ऌླေؓଁ਷aֹᆶa֩ր‫ࢤބ‬൬ࠇ‫ؿ‬ෂඔऌ֩ሑ෿ࣉྛᄹࡨb + +ᇿၩğᄝ GPI-SPI ಆච‫۽‬ଆൔ༯֩րሑ෿҂ॖႨb + +ুᶈྐ༏॓࠯ 117 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + ๭ 7­5. ѩྛ QSPI ࢤ१ + + ๭ 7­6. ѩྛ QSPI ࢤ१֥๙ྐଆൔ + +7.6 GP­SPI ᇏ؎႗ࡱ + +ESP32 SPI ᇏ؎‫ູٳ‬ਆোđ၂োູ SPI ࢤ१ᇏ؎đਸ਼၂োູ SPI DMA ࢤ१ᇏ؎b +ESP32 SPI ࡼ‫ؿ‬ෂ‫ބ‬/ࠇࢤ൬ਆᇕҠቔࢲඏൈ֥ᇏ؎๤၂Ӯ၂۱đࠧಪູ๝൞॥ᇅఖ၂ՑҠቔ֥ࢲඏđ‫ط‬҂ࡆၛ +౵‫ٳ‬bESP32 SPI ቔູՖࠏൈđ۴ऌҠቔ֥҂๝đՖࠏ߶Ӂള‫؀‬/ཿሑ෿࠷թఖ‫؀ބ‬/ཿߏթඔऌᇏ؎b + +7.6.1 SPI ᇏ؎ + +๙‫࠷ࡼݖ‬թఖ SPI_SLAVE_REG ֥ SPI_*_INTEN ໊ᇂ 1đॖၛ൐ି SPI ࢤ१ᇏ؎b֒ᇏ؎‫ؿ‬ളൈđؓႋ֥ +SPI_*_DONE ࠷թఖ֥ᇏ؎ѓᆽ္߶Фᇂ 1bᇏ؎ѓᆽ࠷թఖॖཿđ೏ေౢԢᇏ؎đᆺླࡼؓႋ bit ᇂ 0b + + • SPI_TRANS_DONE_INTğSPI ҠቔࢲඏФԨ‫ؿ‬b + • SPI_SLV_WR_STA_INTğSPI Ֆࠏཿሑ෿ࢲඏൈФԨ‫ؿ‬b + • SPI_SLV_RD_STA_INTğSPI Ֆࠏ‫؀‬ሑ෿ࢲඏൈФԨ‫ؿ‬b + • SPI_SLV_WR_BUF_INTğSPI ՖࠏཿߏթࢲඏൈФԨ‫ؿ‬b + • SPI_SLV_RD_BUD_INTğSPI Ֆࠏ‫ߏ؀‬թࢲඏൈФԨ‫ؿ‬b + +7.6.2 DMA ᇏ؎ + + • SPI_OUT_TOTAL_EOF_INTğ෮Ⴕ৽і‫ؿ‬ෂປൈФԨ‫ؿ‬b + • SPI_OUT_EOF_INTğ၂۱৽і‫ؿ‬ෂປൈФԨ‫ؿ‬b + +ুᶈྐ༏॓࠯ 118 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + +• SPI_OUT_DONE_INTğቋު၂۱৽іӉ؇ູ 0 ൈФԨ‫ؿ‬b +• SPI_IN_SUC_EOF_INTğ෮Ⴕ৽іФࢤ൳ൈФԨ‫ؿ‬b +• SPI_IN_ERR_EOF_INTğࢤ൬৽іԛགྷհ༂ൈФԨ‫ؿ‬b +• SPI_IN_DONE_INTğࢤ൬֥ቋު၂۱৽іӉ؇ູ 0 ൈФԨ‫ؿ‬b +• SPI_INLINK_DSCR_ERROR_INTğࢤ൬৽іౢֆհ༂ൈФԨ‫ؿ‬b +• SPI_OUTLINK_DSCR_ERROR_INTğေ‫ؿ‬ෂ֥৽і໭ིൈФԨ‫ؿ‬b +• SPI_INLINK_DSCR_EMPTY_INTğ໭Ⴕི৽іൈФԨ‫ؿ‬b + +7.7 ࠷թఖਙі ૭ඍ SPI0 SPI1 SPI2 SPI3 ٠໙ + + ଀ӫ Bit ඨ྽‫ ބ‬QIO/DIO/ 3FF43008 3FF42008 3FF64008 3FF65008 ‫؀‬/ཿ + ॥ᇅ‫ބ‬஥ᇂ࠷թఖ QOUT/DOUT ଆൔഡ + ᇂ 3FF43014 3FF42014 3FF64014 3FF65014 ‫؀‬/ཿ + SPI_CTRL_REG ൈ྽஥ᇂ 3FF43018 3FF42018 3FF64018 3FF65018 ‫؀‬/ཿ + ൈᇒ஥ᇂ 3FF43034 3FF42034 3FF64034 3FF65034 ‫؀‬/ཿ + SPI_CTRL2_REG ࠞྟ‫ ބ‬CS ஥ᇂ + SPI_CLOCK_REG + SPI_PIN_REG Ֆࠏଆൔ஥ᇂაᇏ؎ 3FF43038 3FF42038 3FF64038 3FF65038 ‫؀‬/ཿ + Ֆࠏଆൔ஥ᇂ࠷թఖ ሑ෿ + Ֆࠏඔऌ bit Ӊ؇ 3FF4303C 3FF4203C 3FF6403C 3FF6503C ‫؀‬/ཿ + SPI_SLAVE_REG ֩րᇛ௹Ӊ؇஥ᇂ 3FF43040 3FF42040 3FF64040 3FF65040 ‫؀‬/ཿ + Ֆ ࠏ ሑ ෿/ᇶ ࠏ ֮ ໊ + SPI_SLAVE1_REG ֹᆶ 3FF43030 3FF42030 3FF64030 3FF65030 ‫؀‬/ཿ + SPI_SLAVE2_REG ཿߏթҠቔӉ؇ + ‫ߏ؀‬թҠቔӉ؇ 3FF43048 3FF42048 3FF64048 3FF65048 ‫؀‬/ཿ + SPI_SLV_WR_STATUS_REG ‫؀‬ඔऌҠቔӉ؇ 3FF4304C 3FF4204C 3FF6404C 3FF6504C ‫؀‬/ཿ + 3FF43064 3FF42064 3FF64064 3FF65064 ‫؀‬/ཿ + SPI_SLV_WRBUF_DLEN_REG + SPI_SLV_RDBUF_DLEN_REG ष൓Ⴈ޼ሱ‫ק‬ၬଁ਷ 3FF43000 3FF42000 3FF64000 3FF65000 ‫؀‬/ཿ + SPI_SLV_RD_BIT_REG ֹᆶඔऌ 3FF43004 3FF42004 3FF64004 3FF65004 ‫؀‬/ཿ + Ⴈ޼ሱ‫ק‬ၬଁ਷ଆൔ࠷թఖ Ⴈ޼ሱ‫ק‬ၬଁ਷஥ᇂ 3FF4301C 3FF4201C 3FF6401C 3FF6501C ‫؀‬/ཿ + SPI_CMD_REG ֹᆶ‫֩ބ‬րᇛ௹஥ᇂ 3FF43020 3FF42020 3FF64020 3FF65020 ‫؀‬/ཿ + SPI_ADDR_REG ଁ਷Ӊ؇‫ބ‬ᆴ஥ᇂ 3FF43024 3FF42024 3FF64024 3FF65024 ‫؀‬/ཿ + SPI_USER_REG MOSI Ӊ؇ 3FF43028 3FF42028 3FF64028 3FF65028 ‫؀‬/ཿ + SPI_USER1_REG SPI ඔऌ࠷թఖ 0 3FF43080 3FF42080 3FF64080 3FF65080 ‫؀‬/ཿ + SPI_USER2_REG SPI ඔऌ࠷թఖ 1 3FF43084 3FF42084 3FF64084 3FF65084 ‫؀‬/ཿ + SPI_MOSI_DLEN_REG SPI ඔऌ࠷թఖ 2 3FF43088 3FF42088 3FF64088 3FF65088 ‫؀‬/ཿ + SPI_W0_REG SPI ඔऌ࠷թఖ 3 3FF4308C 3FF4208C 3FF6408C 3FF6508C ‫؀‬/ཿ + SPI_W1_REG SPI ඔऌ࠷թఖ 4 3FF43090 3FF42090 3FF64090 3FF65090 ‫؀‬/ཿ + SPI_W2_REG SPI ඔऌ࠷թఖ 5 3FF43094 3FF42094 3FF64094 3FF65094 ‫؀‬/ཿ + SPI_W3_REG SPI ඔऌ࠷թఖ 6 3FF43098 3FF42098 3FF64098 3FF65098 ‫؀‬/ཿ + SPI_W4_REG + SPI_W5_REG + SPI_W6_REG + +ুᶈྐ༏॓࠯ 119 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + +଀ӫ ૭ඍ SPI0 SPI1 SPI2 SPI3 ٠໙ + +SPI_W7_REG SPI ඔऌ࠷թఖ 7 3FF4309C 3FF4209C 3FF6409C 3FF6509C ‫؀‬/ཿ + +SPI_W8_REG SPI ඔऌ࠷թఖ 8 3FF430A0 3FF420A0 3FF640A0 3FF650A0 ‫؀‬/ཿ + +SPI_W9_REG SPI ඔऌ࠷թఖ 9 3FF430A4 3FF420A4 3FF640A4 3FF650A4 ‫؀‬/ཿ + +SPI_W10_REG SPI ඔऌ࠷թఖ 10 3FF430A8 3FF420A8 3FF640A8 3FF650A8 ‫؀‬/ཿ + +SPI_W11_REG SPI ඔऌ࠷թఖ 11 3FF430AC 3FF420AC 3FF640AC 3FF650AC ‫؀‬/ཿ + +SPI_W12_REG SPI ඔऌ࠷թఖ 12 3FF430B0 3FF420B0 3FF640B0 3FF650B0 ‫؀‬/ཿ + +SPI_W13_REG SPI ඔऌ࠷թఖ 13 3FF430B4 3FF420B4 3FF640B4 3FF650B4 ‫؀‬/ཿ + +SPI_W14_REG SPI ඔऌ࠷թఖ 14 3FF430B8 3FF420B8 3FF640B8 3FF650B8 ‫؀‬/ཿ + +SPI_W15_REG SPI ඔऌ࠷թఖ 15 3FF430BC 3FF420BC 3FF640BC 3FF650BC ‫؀‬/ཿ + +DMA ஥ᇂ࠷թఖ + +SPI_DMA_CONF_REG DMA ஥ᇂ࠷թఖ 3FF43100 3FF42100 3FF64100 3FF65100 ‫؀‬/ཿ + 3FF43104 3FF42104 3FF64104 3FF65104 ‫؀‬/ཿ +SPI_DMA_OUT_LINK_REG DMA ‫ؿ‬ෂ৽іֹᆶ + ა஥ᇂ + +SPI_DMA_IN_LINK_REG DMA ࢤ൬৽іֹᆶ 3FF43108 3FF42108 3FF64108 3FF65108 ‫؀‬/ཿ + ა஥ᇂ 3FF4310C 3FF4210C 3FF6410C 3FF6510C ᆺ‫؀‬ + 3FF43120 3FF42120 3FF64120 3FF65120 ᆺ‫؀‬ +SPI_DMA_STATUS_REG DMA ሑ෿ + +SPI_IN_ERR_EOF_DES_ADDR_REG ԛགྷհ༂֥૭ඍ‫ֹژ‬ + ᆶ + + ࢤ൬૭ඍ‫֥֒ژ‬భֹ 3FF43124 3FF42124 3FF64124 3FF65124 ᆺ‫؀‬ +SPI_IN_SUC_EOF_DES_ADDR_REG 3FF43128 3FF42128 3FF64128 3FF65128 ᆺ‫؀‬ + 3FF4312C 3FF4212C 3FF6412C 3FF6512C ᆺ‫؀‬ + ᆶ 3FF43130 3FF42130 3FF64130 3FF65130 ᆺ‫؀‬ + 3FF43134 3FF42134 3FF64134 3FF65134 ᆺ‫؀‬ +SPI_INLINK_DSCR_REG ֒భ૭ඍ‫ژ‬ᆷᆌ + +SPI_INLINK_DSCR_BF0_REG ༯၂۱૭ඍ‫ژ‬ඔऌᆷ + ᆌ + +SPI_INLINK_DSCR_BF1_REG ֒భ૭ඍ‫ژ‬ඔऌᆷᆌ + + ջႵ EOF ֥ؓႋߏ +SPI_OUT_EOF_BFR_DES_ADDR_REG + + թֹᆶ + +SPI_OUT_EOF_DES_ADDR_REG ջႵ EOF ֥૭ඍ‫ژ‬ 3FF43138 3FF42138 3FF64138 3FF65138 ᆺ‫؀‬ + ֹᆶ + 3FF4313C 3FF4213C 3FF6413C 3FF6513C ᆺ‫؀‬ +SPI_OUTLINK_DSCR_REG ֒భ૭ඍ‫ژ‬ᆷᆌ + 3FF43140 3FF42140 3FF64140 3FF65140 ᆺ‫؀‬ +SPI_OUTLINK_DSCR_BF0_REG ༯၂۱૭ඍ‫ژ‬ඔऌᆷ + ᆌ 3FF43144 3FF42144 3FF64144 3FF65144 ᆺ‫؀‬ + 3FF43148 3FF42148 3FF64148 3FF65148 ᆺ‫؀‬ +SPI_OUTLINK_DSCR_BF1_REG ֒భ૭ඍ‫ژ‬ඔऌᆷᆌ 3FF4314C 3FF4214C 3FF6414C 3FF6514C ᆺ‫؀‬ + +SPI_DMA_RSTATUS_REG DMA ଽթ‫؀‬౼ሑ෿ + +SPI_DMA_TSTATUS_REG DMA ଽթཿሑ෿ + +DMA ᇏ؎࠷թఖ + +SPI_DMA_INT_RAW_REG ჰ൓ᇏ؎ሑ෿ 3FF43114 3FF42114 3FF64114 3FF65114 ᆺ‫؀‬ + 3FF43118 3FF42118 3FF64118 3FF65118 ᆺ‫؀‬ +SPI_DMA_INT_ST_REG ௠зᇏ؎ሑ෿ 3FF43110 3FF42110 3FF64110 3FF65110 ‫؀‬/ཿ + 3FF4311C 3FF4211C 3FF6411C 3FF6511C ‫؀‬/ཿ +SPI_DMA_INT_ENA_REG ᇏ؎൐ି໊ + +SPI_DMA_INT_CLR_REG ᇏ؎ౢԢ໊ + +ুᶈྐ༏॓࠯ 120 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + +7.8 ࠷թఖ + +Чཬࢫও‫ݼ‬ᇏֹ֥ᆶनູཌྷؓႿ SPI0/SPI1/SPI2/SPI3 ࠎֹᆶֹ֥ᆶொ၍ਈčཌྷֹؓᆶĎđऎุࠎֹᆶ࡮ᅣࢫ 1 +༢๤‫ބ‬թԥఖ ᇏ֥і 1-6 ຓഡֹᆶ႘ഝb࠷թఖधֹؓᆶ࡮ᅣࢫ 7.7 ࠷թఖਙіb + + Register 7.1. SPI_CMD_REG (0x0) + + (reserved) SPI_USR (reserved) + +31 19 18 17 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_USR Վ໊ᇂ 1 ൈ, Ԩ‫ؿ‬၂Ց SPI ҠቔđҠቔࢲඏުՎ໊Фሱ‫׮‬ౢਬbč‫؀‬/ཿĎ + + Register 7.2. SPI_ADDR_REG (0x4) + +31 0 + + 0x000000000 Reset + + SPI_ADDR_REG ႨႿթԥᇶࠏᄝ϶ච‫۽‬ଆൔࠇ QSPI ଆൔ֥‫ؿ‬ෂֹᆶbೂ‫ֹݔ‬ᆶӉ؇նႿ 32 + bitđᄵՎ࠷թఖЇ‫ֹۚݣ‬ᆶ໊đSPI_SLV_WR_STATUS_REG Ї‫ ֮ݣ‬32 bitbՎ࠷թఖࣇ֒ + SPI_USR_ADDR Фᇂ 1 ൈႵིbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 121 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.3. SPI_CTRL_REG (0x8) + + (reserved) SPI_WSRP_I_BRISTDP__OIB_RFITSRD_PEEOIAR_RDFD(R_reEQEsRAIeODrvS_ePDdII_)OWSPPI_FREAD_QUA(rDeserved) SPI_FSRPEIA_DFA_SDTURADL_MODE (reserved) + +31 27 26 25 24 23 22 21 20 19 15 14 13 12 0 + +0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_WR_BIT_ORDER ႨႿ஥ᇂ‫ؿ‬ෂྐ‫֥ݼ‬бหඨ྽đᆺؓ‫ؿ‬ෂ֥ଁ਷aֹᆶ‫ބ‬ඔऌႵིb1ğ༵‫ؿ‬ + ෂ֮Ⴕ໊ིĠ0ğ༵‫ؿ‬ෂۚႵ໊ིbč‫؀‬/ཿĎ + + SPI_RD_BIT_ORDER ႨႿ஥ᇂࢤ൬ྐ‫֥ݼ‬бหඨ྽đᆺؓࢤ൬֥ඔऌႵིb1ğ༵ࢤ൬֮Ⴕ໊ིĠ + 0ğ༵ࢤ൬ۚႵ໊ིbč‫؀‬/ཿĎ + + SPI_FREAD_QIO ႨႿ൐ି 4 ཌଆൔ‫ؿ‬ෂֹᆶ‫؀ބ‬౼ඔऌbࣇᄝ QSPI ଆൔ൐Ⴈbč‫؀‬/ཿĎ + SPI_FREAD_DIO ႨႿ൐ି 2 ཌଆൔ‫ؿ‬ෂֹᆶ‫؀ބ‬౼ඔऌbࣇᄝ QSPI ଆൔ൐Ⴈbč‫؀‬/ཿĎ + SPI_WP ႨႿ஥ᇂॢ༽ൈ֥ WP ྐ‫ݼ‬ൻԛ‫׈‬௜b1ğൻԛۚ‫׈‬௜Ġ2ğൻԛ֮‫׈‬௜bࣇᄝ QSPI ଆൔ + + ൐Ⴈbč‫؀‬/ཿĎ + SPI_FREAD_QUAD ႨႿ൐ି 4 ཌଆൔ‫؀‬౼ඔऌbࣇᄝ QSPI ଆൔ൐Ⴈbč‫؀‬/ཿĎ + SPI_FREAD_DUAL ႨႿ൐ି 2 ཌଆൔ‫؀‬౼ඔऌbࣇᄝ QSPI ଆൔ൐Ⴈbč‫؀‬/ཿĎ + SPI_FASTRD_MODE Ќ਽b + + Register 7.4. SPI_CTRL1_REG (0xC) + + SPI_CS_HOLD_DELAY (reserved) + +31 28 27 0 + + 0x05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_CS_HOLD_DELAY Ќ਽b + +ুᶈྐ༏॓࠯ 122 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.5. SPI_RD_STATUS_REG (0x10) + + SPI_STATUS_EXT SPI_STATUS + +31 24 23 16 15 0 + + 0x000 0x000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_STATUS_EXT Ќ਽b + SPI_STATUS Ќ਽b + +ুᶈྐ༏॓࠯ 123 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.6. SPI_CTRL2_REG (0x14) + + SPI_CS_DELAY_SNPUIM_CS_DELASYP_MI_MODOESI_DESLPAYI__MNOUSMI_DESLPAYI__MMISOOD_EDESLPAYI__MNIUSOM_DELAYS_PMI_OCDK_EOUT_HIGH_MreOsDeErved SPI_HOLD_TIME SPI_SETUP_TIME + +31 28 27 26 25 23 22 21 20 18 17 16 15 12 11 87 43 0 + + 0x00 0x0 0x0 0x0 0x0 0x0 0x00 0x00 0x01 0x01 Reset + + SPI_CS_DELAY_NUM Ќ਽b + + SPI_CS_DELAY_MODE Ќ਽b + + SPI_MOSI_DELAY_NUM ႨႿ஥ᇂ MOSI ྐ‫ࠎݼ‬Ⴟ༢๤ൈᇒ֥࿼Ӿඔbč‫؀‬/ཿĎ + + SPI_MOSI_DELAY_MODE ႨႿ஥ᇂ MOSI ྐ‫ࠎݼ‬Ⴟ SPI ൈᇒ֥࿼Ӿ֥ٚൔbč‫؀‬/ཿĎ + MOSI ྐ‫ݼ‬ᄝ࿼Ӿ SPI_MOSI_DELAY_NUM ۱༢๤ൈᇒުđᄜࣉྛೂ༯࿼Ӿğ + 0ğ໭࿼Ӿb + 1ğ೏ SPI_CK_OUT_EDGE ࠇ SPI_CK_I_EDGE Фᇂ 1đMOSI Ф࿼Ӿ϶۱ᇛ௹đ‫ڎ‬ᄵФ࿼Ӿ၂ + ۱ᇛ௹b + 2ğ೏ SPI_CK_OUT_EDGE ࠇ SPI_CK_I_EDGE Фᇂ 1đMOSI Ф࿼Ӿ၂۱ᇛ௹đ‫ڎ‬ᄵФ࿼Ӿ϶ + ۱ᇛ௹b + 3ğ࿼Ӿ၂۱ᇛ௹b + + SPI_MISO_DELAY_NUM ႨႿ஥ᇂ MISO ྐ‫ࠎݼ‬Ⴟ༢๤ൈᇒ֥࿼Ӿඔbč‫؀‬/ཿĎ + + SPI_MISO_DELAY_MODE ႨႿ஥ᇂ MISO ྐ‫ࠎݼ‬Ⴟ SPI ൈᇒ֥࿼Ӿ֥ٚൔbč‫؀‬/ཿĎ + MISO ྐ‫ݼ‬ᄝ࿼Ӿ SPI_MISO_DELAY_NUM ۱༢๤ൈᇒުđᄜࣉྛೂ༯࿼Ӿğ + 0ğ໭࿼Ӿb + 1ğ೏ SPI_CK_OUT_EDGE ࠇ SPI_CK_I_EDGE Фᇂ 1đMISO Ф࿼Ӿ϶۱ᇛ௹đ‫ڎ‬ᄵФ࿼Ӿ၂ + ۱ᇛ௹b + 2ğ೏ SPI_CK_OUT_EDGE ࠇ SPI_CK_I_EDGE Фᇂ 1đMISO Ф࿼Ӿ၂۱ᇛ௹đ‫ڎ‬ᄵФ࿼Ӿ϶ + ۱ᇛ௹b + 3ğ࿼Ӿ၂۱ᇛ௹b + + SPI_HOLD_TIME CS ྐ‫ݼ‬Ф࿼Ӿ֥ SPI ൈᇒᇛ௹ඔbࣇ֒ SPI_CS_HOLD ᇂ 1 ൈႵིbč‫؀‬/ཿĎ + + SPI_SETUP_TIME ႨႿ‫ט‬ᆜ CS ྐ‫ݼ‬Ⴕིခֻ֞၂۱ SPI ൈᇒခ֥ൈࡗbࣇᄝ SPI_CS_SETUP ᇂ + 1 ൈႵིbᆺᄝ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔ༯Ⴕིbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 124 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.7. SPI_CLOCK_REG (0x18) + + SPI_CLK_EQU_SYSCLK SPI_CLKDIV_PRE SPI_CLKCNT_N SPI_CLKCNT_H SPI_CLKCNT_L + +31 30 18 17 12 11 65 0 + +10 0 0 0 0 0 0 0 0 0 0 0 0 0x03 0x01 0x03 Reset + +SPI_CLK_EQU_SYSCLK ᇶࠏଆൔ༯đ1ğSPI ൻԛൈᇒ֩Ⴟ༢๤ൈᇒĠ0ğSPI ൻԛൈᇒႮ༢๤ൈ + ᇒ‫ٳ‬௔‫ط‬টbՖࠏଆൔ༯đՎ࠷թఖᆴླေᇂູ 0bč‫؀‬/ཿĎ + +SPI_CLKDIV_PRE ᇶࠏଆൔ༯đႨႿ஥ᇂ SPI ൻԛൈᇒ֥ყ‫ٳ‬௔ඔbࣇᄝ SPI_CLK_EQU_SYSCLK + ູ 0 ൈႵིbՖࠏଆൔ༯đՎ࠷թఖᆴླေᇂູ 0bč‫؀‬/ཿĎ + +SPI_CLKCNT_N ᇶࠏଆൔ༯đႨႿ஥ᇂ SPI ൻԛൈᇒ֥‫ٳ‬௔ඔbࣇᄝ SPI_CLK_EQU_SYSCLK ູ + 0 ൈႵིbՖࠏଆൔ༯đՎ࠷թఖᆴླေᇂູ 0bč‫؀‬/ཿĎ + +SPI_CLKCNT_H ᇶࠏଆൔ༯đSPI_CLKCNT_H = ⌊ SPI_CLKCNT_N+1 –1⌋bࣇᄝ SPI_CLK_EQU_SYSCLK + 2 + +ູ 0 ൈႵིbՖࠏଆൔ༯đՎ࠷թఖᆴླေᇂູ 0bč‫؀‬/ཿĎ + +SPI_CLKCNT_L ᇶࠏଆൔ༯đՎ࠷թఖ֥ᆴ֩Ⴟ SPI_CLKCNT_Nbࣇᄝ SPI_CLK_EQU_SYSCLK + ູ 0 ൈႵིbՖࠏଆൔ༯đՎ࠷թఖᆴູ 0bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 125 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.8. SPI_USER_REG (0x1C) + + SPI_USSPRI__UCSSOPRMI__MUASDSAPRNDI__RDUDSSUPRMI__MUMSYSIPSRIO__UMSSOPRSI__IUDSSUPRMI__MUMYSO_RSI_DI_MLHEISIGOH_PHAIGRHT(PreAsReTrved) SPI_SSIOPI_FSWPRI_ITFSEW_PRQI_IITFOSEW_PRDI_IITFOSEW_PRQI_IUTWSEAR_PDD_I_BURYADTL_E(Br_eYOsTeRErDv_eEOdRSR)PDI_ECRSKP_IO_CUSKTP__IIE__CDESSDGP_GEIS_ECETSU_HPO(rLeDserved) SPI_DOUTDIN + +31 30 29 28 27 26 25 24 23 17 16 15 14 13 12 11 10 9 87 6 5 43 10 + +1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Reset + +SPI_USR_COMMAND ᄝ SPI ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔđႨႿ൐ି SPI Ҡቔ֥ଁ਷ሑ෿bč‫؀‬/ཿĎ +SPI_USR_ADDR ᄝ SPI ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔđႨႿ൐ି SPI Ҡቔֹ֥ᆶሑ෿bč‫؀‬/ཿĎ +SPI_USR_DUMMY ᄝ SPI ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔđႨႿ൐ି SPI Ҡቔ֥֩րሑ෿bč‫؀‬/ཿĎ +SPI_USR_MISO ᄝ SPI ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔđႨႿ൐ି SPI Ҡቔ֥ඔऌ‫؀‬౼ሑ෿bč‫؀‬/ཿĎ +SPI_USR_MOSI ᄝ SPI ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔđႨႿ൐ି SPI Ҡቔ֥ཿඔऌሑ෿bč‫؀‬/ཿĎ +SPI_USR_DUMMY_IDLE ᄝ SPI ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔđᄝ֩րሑ෿໭ൈᇒൻԛbč‫؀‬/ཿĎ +SPI_USR_MOSI_HIGHPART ᇶࠏൻԛ/ՖࠏൻೆඔऌթԥႿ SPI_W8_REG ~ SPI_W15_REGčb‫؀‬/ཿĎ +SPI_USR_MISO_HIGHPART ᇶࠏൻೆ/ՖࠏൻԛඔऌթԥႿ SPI_W8_REG ~ SPI_W15_REGčb‫؀‬/ཿĎ +SPI_SIO ൐ି೘ཌ϶ච‫۽‬๙ྐbč‫؀‬/ཿĎ +SPI_FWRITE_QIO Ќ਽b +SPI_FWRITE_DIO Ќ਽b +SPI_FWRITE_QUAD Ќ਽b +SPI_FWRITE_DUAL Ќ਽b +SPI_WR_BYTE_ORDER ႨႿ஥ᇂ‫ؿ‬ෂྐ‫֥ݼ‬ሳࢫඨ྽đᆺؓ‫ؿ‬ෂ֥ଁ਷đֹᆶ‫ބ‬ඔऌႵིb1ğն + + ؊ሳࢫ྽Ġ0ğཬ؊ሳࢫ྽bč‫؀‬/ཿĎ +SPI_RD_BYTE_ORDER ႨႿ஥ᇂࢤ൬ྐ‫֥ݼ‬ሳࢫඨ྽đᆺؓࢤ൬֥ඔऌႵིb1ğն؊ሳࢫ྽Ġ0ğ + + ཬ؊ሳࢫ྽bč‫؀‬/ཿĎ +SPI_CK_OUT_EDGE Վ໊ა SPI_MOSI_DELAY_MODE ‫܋‬๝ഡᇂ MOSI ྐ‫֥ݼ‬࿼Ӿଆൔbᆺؓᇶࠏ + + ଆൔႵིbč‫؀‬/ཿĎ +SPI_CK_I_EDGE Վ໊აᇶࠏଆൔ༯֥ SPI_CK_OUT_EDGE ཌྷ๝bა SPI_MISO_DELAY_MODE ‫܋‬ + + ๝൐ႨbᆺؓՖࠏଆൔႵིbč‫؀‬/ཿĎ +SPI_CS_SETUP ᄝ CS Ⴕིခ‫ֻބ‬၂۱ൈᇒခᆭࡗࡆೆ࿼Ӿ, ၛ SPI ൈᇒᇛ௹ູֆ໊bՎ໊ᇂ 1 ൈđ + + ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔ༯đ࿼Ӿൈࡗູ (SPI_SETUP_TIME + 1.5)Ġᄝಆච‫۽‬ଆൔ༯đmode0 ‫ބ‬ + mode2 ֥࿼Ӿൈࡗູ 1.5đmode1 ‫ ބ‬mode3 ֥࿼Ӿൈࡗູ 1bč‫؀‬/ཿĎ +SPI_CS_HOLD ᄝ ඔ ऌ Ԯ ൻ ࢲ ඏ ‫ ބ‬CS ໭ ི ခ ᆭ ࡗ ࡆ ೆ ၂ ‫ ؍‬࿼ Ӿđ ࿼ Ӿ ൈ ࡗ ູ + SPI_HOLD_TIMEbč‫؀‬/ཿĎ +SPI_DOUTDIN ൐ିಆච‫۽‬ଆൔbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 126 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.9. SPI_USER1_REG (0x20) + + SPI_USR_ADDR_BITLEN (reserved) SPI_USR_DUMMY_CYCLELEN + +31 26 25 87 0 + + 23 000000000000000000 7 Reset + + SPI_USR_ADDR_BITLEN ᄝ SPI ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔđіൕ SPI ‫ؿ‬ෂֹ֥ᆶ໊ॺࡨ 1đֆູ໊ + bitbࣇ֒ SPI_USR_ADDR Фᇂ 1 ൈႵིbčᆺ‫؀‬Ď + + SPI_USR_DUMMY_CYCLELEN ᄝ SPI ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔđіൕ SPI ֩րሑ෿ӻ࿃֥ spi_clk + ൈᇒᇛ௹ඔࡨ 1 bࣇ֒ SPI_USR_DUMMY Фᇂ 1 ൈႵིbč‫؀‬/ཿĎ + + Register 7.10. SPI_USER2_REG (0x24) + + SPI_USR_COMMAND_BITLEN (reserved) SPI_USR_COMMAND_VALUE + +31 28 27 16 15 0 + + 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_USR_COMMAND_BITLEN ᄝ SPI ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔđіൕ SPI ‫ؿ‬ෂ֥ଁ਷Ӊ؇ࡨ 1đ + ֆູ໊ bitbࣇ֒ SPI_USR_COMMAND Фᇂ 1 ൈႵིbč‫؀‬/ཿĎ + + SPI_USR_COMMAND_VALUE ᄝ SPI ϶ච‫۽‬ଆൔ‫ ބ‬QSPI ଆൔđіൕ SPI ေ‫ؿ‬ෂ֥ଁ਷ᆴbࣇ֒ + SPI_USR_COMMAND Фᇂ 1 ൈႵིbč‫؀‬/ཿĎ + + Register 7.11. SPI_MOSI_DLEN_REG (0x28) + + (reserved) SPI_USR_MOSI_DBITLEN + 0x0000000 +31 24 23 0 + +00000000 Reset + + SPI_USR_MOSI_DBITLEN ႨႿ஥ᇂԮൻඔऌӉ؇đᇶࠏൻԛ/Ֆࠏൻೆ֥ඔऌӉ؇ࡨ 1đֆູ໊ + bitbࣇ֒ SPI_USR_MOSI Фᇂ 1 ൈႵིbᇶࠏଆൔႵིbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 127 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.12. SPI_MISO_DLEN_REG (0x2C) + + (reserved) SPI_USR_MISO_DBITLEN + 0x0000000 +31 24 23 0 + +00000000 Reset + + SPI_USR_MISO_DBITLEN ႨႿ஥ᇂԮൻඔऌӉ؇đᇶࠏൻೆ/Ֆࠏൻԛ‫؀‬౼֥ඔऌӉ؇ࡨ 1đֆ໊ + ູ bitbࣇ֒ SPI_USR_MISO Фᇂ 1 ൈႵིbᇶࠏଆൔႵིbč‫؀‬/ཿĎ + + Register 7.13. SPI_SLV_WR_STATUS_REG (0x30) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_SLV_WR_STATUS_REG Ֆࠏଆൔ༯đіൕᇶࠏཿೆՖࠏ֥ሑ෿࠷թఖbᇶࠏଆൔ༯đೂ‫ֹݔ‬ + ᆶӉ؇նႿ 32 bitđՎ࠷թఖູ֮ 32 bitbč‫؀‬/ཿĎ + + Register 7.14. SPI_PIN_REG (0x34) + + (reservSePdI_) CSSP_IK_CEEKP_I_DALCET_IEVDEGE (reserved) SPI_MASTER_(rCeKse_rSvEedL) SPI_MASTESRP_I_CCSK__P(DrOeIsLServedS) PI_CSSP2I__DCSISSP1I__DCISS0_DIS + +31 30 29 28 14 13 11 10 98 654 32 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Reset + + SPI_CS_KEEP_ACTIVE Վ໊ᇂ 1 ൈđCS ྐ‫ࡼݼ‬ЌӻႵིሑ෿bᆺႨႿᇶࠏଆൔbč‫؀‬/ཿĎ + SPI_CK_IDLE_EDGE ႨႿ஥ᇂ SPI ൻԛൈᇒᄝॢ༽ሑ෿֥‫׈‬௜bᆺႨႿᇶࠏଆൔbč‫؀‬/ཿĎ + + 1ğॢ༽ሑ෿ൈ, spi_clk ྐ‫ݼ‬ཌЌӻۚ‫׈‬௜Ġ + 0ğॢ༽ሑ෿ൈ, spi_clk ྐ‫ݼ‬ཌЌӻ֮‫׈‬௜b + SPI_MASTER_CK_SEL Ќ਽b + SPI_MASTER_CS_POL Ќ਽b + SPI_CK_DIS Ќ਽b + SPI_CS2_DIS ൐ି SPI CS2 ྐ‫ݼ‬b1ğܱо CS2Ġ0ğषఓ CS2bč‫؀‬/ཿĎ + SPI_CS1_DIS ൐ି SPI CS1 ྐ‫ݼ‬b1ğܱо CS1Ġ0ğषఓ CS1bč‫؀‬/ཿĎ + SPI_CS0_DIS ൐ି SPI CS0 ྐ‫ݼ‬b1ğܱо CS0Ġ0ğषఓ CS0bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 128 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.15. SPI_SLAVE_REG (0x38) + +SPI_SSYPNI_CS_SLRPAEIV_SESES_LTMVP_IO_WSDSLREVP__IR_WSDLR_VB__RUCDFM__ESDSNT_PADI__EETFNRINAENS_CNT SPI_SLV_LAST_SSTPAIT_ESLV_LAST_COMM(rAeNseDrved) SPI_CS_SI_PMI_OTSDRPEAIN_SSSL_VPIN_I_WTSESLRNVP__IS_RSTDSALVP__SI_IN_WTSTASLRE_VPN_IN_IB_RTTUDSERFNP_A_BIIN_NUSSTSFL_E_VPDNI_IN_OWSTNSELREVPN__IS_RSTDSALVP__SD_I_WTOSALNR_V_ED_BORUDNF_E_BDUOFN_EDONE + +31 30 29 28 27 26 23 22 20 19 17 16 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +SPI_SYNC_RESET ‫໊ھ‬ႨႿ‫ ໊گ‬SPI ൈᇒཌđCS ཌ‫ބ‬ඔऌཌ֥෭թᆴbč‫؀‬/ཿĎ +SPI_SLAVE_MODE ‫໊ھ‬ႨႿഡᇂ SPI ഡС֥ଆൔbč‫؀‬/ཿĎ + + 1ğՖࠏଆൔĠ + 0ğᇶࠏଆൔb +SPI_SLV_WR_RD_BUF_EN ࡼՎ໊ᇂ 1đ൐ିՖࠏଆൔ༯֥‫؀‬ཿඔऌҠቔଁ਷bᆺႨႿՖࠏ϶ච‫۽‬ + ଆൔbč‫؀‬/ཿĎ +SPI_SLV_WR_RD_STA_EN ࡼՎ໊ᇂ 1đ൐ିՖࠏଆൔ༯֥‫؀‬ཿሑ෿Ҡቔଁ਷bᆺႨႿՖࠏ϶ච‫۽‬ + ଆൔbč‫؀‬/ཿĎ +SPI_SLV_CMD_DEFINE Ќ਽b +SPI_TRANS_CNT ᇶࠏ‫ބ‬Ֆࠏଆൔ༯֥Ҡቔ࠹ඔఖbčᆺ‫؀‬Ď +SPI_SLV_LAST_STATE Ֆࠏଆൔ༯đՎ໊Ї‫ݣ‬ਔ SPI ሑ෿ࠏ֥ሑ෿bčᆺ‫؀‬Ď +SPI_SLV_LAST_COMMAND Ќ਽b +SPI_CS_I_MODE Ќ਽b +SPI_TRANS_INTEN SPI_TRANS_DONE_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ +SPI_SLV_WR_STA_INTEN SPI_SLV_WR_STA_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ +SPI_SLV_RD_STA_INTEN SPI_SLV_RD_STA_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ +SPI_SLV_WR_BUF_INTEN SPI_SLV_WR_BUF_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ +SPI_SLV_RD_BUF_INTEN SPI_SLV_RD_BUF_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ +SPI_TRANS_DONE SPI_TRANS_DONE_INT ֥ᇏ؎ሑ෿໊bՎ໊Ⴎ႗ࡱᇂ 1đླေೈࡱౢਬčb‫؀‬/ཿĎ +SPI_SLV_WR_STA_DONE SPI_SLV_WR_STA_INT ֥ᇏ؎ሑ෿໊bՎѓᆽႮ႗ࡱᇂ 1đླေೈࡱౢ + ਬbᆺႨႿՖࠏ϶ච‫۽‬ଆൔbč‫؀‬/ཿĎ +SPI_SLV_RD_STA_DONE SPI_SLV_RD_STA_INT ֥ᇏ؎ሑ෿໊bՎѓᆽႮ႗ࡱᇂ 1đླေೈࡱౢ + ਬbᆺႨႿՖࠏ϶ච‫۽‬ଆൔbč‫؀‬/ཿĎ +SPI_SLV_WR_BUF_DONE SPI_SLV_WR_BUF_INT ֥ᇏ؎ሑ෿໊bՎѓᆽႮ႗ࡱᇂ 1đླေೈࡱౢ + ਬbᆺႨႿՖࠏ϶ච‫۽‬ଆൔbč‫؀‬/ཿĎ +SPI_SLV_RD_BUF_DONE SPI_SLV_RD_BUF_INT ֥ᇏ؎ሑ෿໊bՎѓᆽႮ႗ࡱᇂ 1đླေೈࡱౢ + ਬbᆺႨႿՖࠏ϶ච‫۽‬ଆൔbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 129 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.16. SPI_SLAVE1_REG (0x3C) + +31 SPI_SLV_STATUSS_PBI_ITSLSLEVPN_I_SSTLAVT_USSTA_FTAUSST__REENADBAC(reKserved) 16 15 SPI_SLV_RD_ADDR_BITLEN SPI_SLV_WR_ADDRS_PBI_ITSLSLEVPN_I_WSSLRVPS_I_TRSADSL_VPSD_ITU_WASM_LRMDVBU_YURM_FDEM_NBDYUU_FEM_NMDUYM_EMNY_EN + +00 27 26 25 24 00 10 9 43 2 1 0 + + 0 0 00 10 0 0 0 0 0 0 0x00 0x00 0 0 0 0 Reset + +SPI_SLV_STATUS_BITLEN Վ໊ႨႿ஥ᇂᇶࠏཿሑ෿࠷թఖ֥Ӊ؇bࣇᄝՖࠏ϶ච‫۽‬ଆൔ༯Ⴕ + ིbč‫؀‬/ཿĎ + +SPI_SLV_STATUS_FAST_EN Ќ਽b + +SPI_SLV_STATUS_READBACK Ќ਽b + +SPI_SLV_RD_ADDR_BITLEN іൕ‫؀‬౼Ֆࠏඔऌֹ֥ᆶӉ؇ࡨ 1đֆູ໊ bitbࣇᄝՖࠏ϶ච‫۽‬ଆൔ + ༯Ⴕིbč‫؀‬/ཿĎ + +SPI_SLV_WR_ADDR_BITLEN іൕཿՖࠏඔऌֹ֥ᆶӉ؇ࡨ 1đֆູ໊ bitbࣇᄝՖࠏ϶ච‫۽‬ଆൔ + ༯Ⴕིbč‫؀‬/ཿĎ + +SPI_SLV_WRSTA_DUMMY_EN ൐ ି ཿ ሑ ෿ ࠷ թ ఖ ֥ ֩ ր ሑ ෿b ࣇ ᄝ Ֆ ࠏ ϶ ච ‫ ۽‬ଆ ൔ ༯ Ⴕ + ིbč‫؀‬/ཿĎ + +SPI_SLV_RDSTA_DUMMY_EN ൐ ି ‫ ؀‬ሑ ෿ ࠷ թ ఖ ֥ ֩ ր ሑ ෿b ࣇ ᄝ Ֆ ࠏ ϶ ච ‫ ۽‬ଆ ൔ ༯ Ⴕ + ིbč‫؀‬/ཿĎ + +SPI_SLV_WRBUF_DUMMY_EN ൐ିཿඔऌҠቔ֥֩րሑ෿bࣇᄝՖࠏ϶ච‫۽‬ଆൔ༯Ⴕིbč‫؀‬/ཿĎ + +SPI_SLV_RDBUF_DUMMY_EN ൐ି‫؀‬ඔऌҠቔ֥֩րሑ෿bࣇᄝՖࠏ϶ච‫۽‬ଆൔ༯Ⴕིbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 130 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.17. SPI_SLAVE2_REG (0x40) + + SPI_SLV_WRBUF_DUMMY_CYCLELEN SPI_SLV_RDBUF_DUMMY_CYCLELEN SPI_SLV_WRSTA_DUMMY_CYCLELEN SPI_SLV_RDSTA_DUMMY_CYCLELEN + +31 24 23 16 15 87 0 + +00000000 0x000 0x000 0x000 Reset + + SPI_SLV_WRBUF_DUMMY_CYCLELEN ཿඔऌҠቔ֥֩րሑ෿෮ӻ࿃֥ SPI ൈᇒᇛ௹ඔࡨ 1bՎ + ໊ࣇ֒ SPI_SLV_WRBUF_DUMMY_EN Фᇂ 1 ൈႵིbࣇᄝՖࠏ϶ච‫۽‬ଆൔ༯Ⴕིbč‫؀‬/ཿĎ + + SPI_SLV_RDBUF_DUMMY_CYCLELEN ‫؀‬ඔऌҠቔ֥֩րሑ෿෮ӻ࿃֥ SPI ൈᇒᇛ௹ඔࡨ 1bՎ + ໊ࣇ֒ SPI_SLV_RDBUF_DUMMY_EN Фᇂ 1 ൈႵིbࣇᄝՖࠏ϶ච‫۽‬ଆൔ༯Ⴕིbč‫؀‬/ཿĎ + + SPI_SLV_WRSTA_DUMMY_CYCLELEN ཿሑ෿࠷թఖҠቔ֥֩րሑ෿෮ӻ࿃֥ SPI ൈᇒᇛ௹ඔࡨ + 1bՎ໊ࣇ֒ SPI_SLV_WRSTA_DUMMY_EN Фᇂ 1 ൈႵིbࣇᄝՖࠏ϶ච‫۽‬ଆൔ༯Ⴕིbč‫؀‬/ཿĎ + + SPI_SLV_RDSTA_DUMMY_CYCLELEN ‫؀‬ሑ෿࠷թఖҠቔ֥֩րሑ෿෮ӻ࿃֥ SPI ൈᇒᇛ௹ඔࡨ + 1bՎ໊ࣇ֒ SPI_SLV_RDSTA_DUMMY_EN Фᇂ 1 ൈႵིbࣇᄝՖࠏ϶ච‫۽‬ଆൔ༯Ⴕིbč‫؀‬/ཿĎ + + Register 7.18. SPI_SLAVE3_REG (0x44) + + SPI_SLV_WRSTA_CMD_VALUE SPI_SLV_RDSTA_CMD_VALUE SPI_SLV_WRBUF_CMD_VALUE SPI_SLV_RDBUF_CMD_VALUE + +31 24 23 16 15 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_SLV_WRSTA_CMD_VALUE Ќ਽b + SPI_SLV_RDSTA_CMD_VALUE Ќ਽b + SPI_SLV_WRBUF_CMD_VALUE Ќ਽b + SPI_SLV_RDBUF_CMD_VALUE Ќ਽b + +ুᶈྐ༏॓࠯ 131 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.19. SPI_SLV_WRBUF_DLEN_REG (0x48) + + (reserved) SPI_SLV_WRBUF_DBITLEN + 0x0000000 +31 24 23 0 + +00000000 Reset + + SPI_SLV_WRBUF_DBITLEN іൕཿೆඔऌӉ؇ࡨ 1đֆູ໊ bitbࣇᄝՖࠏ϶ච‫۽‬ଆൔ༯Ⴕིb + + Register 7.20. SPI_SLV_RDBUF_DLEN_REG (0x4C) + + (reserved) SPI_SLV_RDBUF_DBITLEN + 0x0000000 +31 24 23 0 + +00000000 Reset + + SPI_SLV_RDBUF_DBITLEN іൕ‫؀‬౼ඔऌӉ؇ࡨ 1đֆູ໊ bitbࣇᄝՖࠏ϶ච‫۽‬ଆൔ༯Ⴕ + ིbč‫؀‬/ཿĎ + + Register 7.21. SPI_SLV_RD_BIT_REG (0x64) + + (reserved) SPI_SLV_RDATA_BIT + +31 24 23 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_SLV_RDATA_BIT ᇶࠏ‫؀‬౼ՖࠏඔऌӉ؇ࡨ 1bࣇᄝՖࠏ϶ච‫۽‬ଆൔ༯Ⴕིbč‫؀‬/ཿĎ + + Register 7.22. SPI_Wn_REG (nğ0­15) (0x80+4*n) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_Wn_REG ඔऌߏթbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 132 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.23. SPI_TX_CRC_REG (0xC0) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_TX_CRC_REG Ќ਽b + + Register 7.24. SPI_EXT2_REG (0xF8) + + (reserved) SPI_ST + +31 32 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 Reset + + SPI_ST SPI ሑ෿ࠏ֥֒భሑ෿bčᆺ‫؀‬Ď + 0ğॢ༽ሑ෿Ġ + 1ğሙСሑ෿Ġ + 2ğ‫ؿ‬ෂଁ਷ሑ෿Ġ + 3ğ‫ؿ‬ෂඔऌሑ෿Ġ + 4ğ‫؀‬౼ඔऌሑ෿Ġ + 5ğཿඔऌሑ෿Ġ + 6ğ֩րሑ෿Ġ + 7ğປӮሑ෿b + +ুᶈྐ༏॓࠯ 133 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.25. SPI_DMA_CONF_REG (0x100) + + (reserved) SPI_DSMPAI__DCSMOPANI__TDT(IMrNXe_UsASeE_TrRvSOeXPPd_I_)SOTSOUPTPI__IDNSADPTSIA_C_OSBRUPU_TBIR_DUOSSRTUC_STRET__N_EB(EOrUeNFsR_eSMrvTOe_dDE)NESPI_ASHPBI_MA_SHRPBSI_MTO_SUFPTIFI__OIRN_S_RTR(SrSeTsTerved) + +31 17 16 15 14 13 12 11 10 9 8 65 4 3 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reset + + SPI_DMA_CONTINUE ൐ି SPI DMA ඔऌ৵࿃ TX/RX ଆൔbč‫؀‬/ཿĎ + SPI_DMA_TX_STOP ᄝ৵࿃ TX/RX ଆൔ༯đࡼՎ໊ᇂ 1 ๔ᆸ‫ؿ‬ෂඔऌbč‫؀‬/ཿĎ + SPI_DMA_RX_STOP ᄝ৵࿃ TX/RX ଆൔ༯đࡼՎ໊ᇂ 1 ๔ᆸࢤ൬ඔऌbč‫؀‬/ཿĎ + SPI_OUT_DATA_BURST_EN DMA ൐Ⴈ burst ଆൔՖଽթ‫؀‬౼ඔऌbč‫؀‬/ཿĎ + SPI_INDSCR_BURST_EN DMA ൐Ⴈ burst ଆൔ‫ࢤ؀‬൬৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + SPI_OUTDSCR_BURST_EN DMA ൐Ⴈ burst ଆൔ‫ؿ؀‬ෂ৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + SPI_OUT_EOF_MODE DMA ॥ᇅఖളӮ‫ؿ‬ෂ EOF ѓᆽ֥ଆൔbč‫؀‬/ཿĎ + + 1ğ֒ DMA ၘՖ FIFO ᇏ‫؀‬ԛ෮ႵඔऌൈđӁള EOF ѓᆽĠ + 0ğ֒ DMA ࡼ෮Ⴕඔऌཿೆ FIFO ൈđӁള EOF ѓᆽb + SPI_AHBM_RST ႨႿ‫ ໊گ‬SPI DMA AHB ᇶࠏbč‫؀‬/ཿĎ + SPI_AHBM_FIFO_RST ႨႿ‫ ໊گ‬SPI DMA AHB ᇶࠏ FIFO ᆷᆌbč‫؀‬/ཿĎ + SPI_OUT_RST ႨႿ‫ ໊گ‬DMA ‫ؿ‬ෂሑ෿ࠏ‫ؿބ‬ෂඔऌ FIFO ᆷᆌbč‫؀‬/ཿĎ + SPI_IN_RST ႨႿ‫ ໊گ‬DMA ࢤ൬ሑ෿ࠏ‫ࢤބ‬൬ඔऌ FIFO ᆷᆌbč‫؀‬/ཿĎ + + Register 7.26. SPI_DMA_OUT_LINK_REG (0x104) + + (reservSePdI_) OSUPTI_LOINSUKPT_I_LROINEUSKTT_LASINRTATKR_TSTOP (reserved) SPI_OUTLINK_ADDR + 0x000000 +31 30 29 28 27 20 19 0 + +0 0 0 00 0 0 0 0 0 0 0 Reset + + SPI_OUTLINK_RESTART ࡼՎ໊ᇂ 1 ൐Ⴈྍ֥‫ؿ‬ෂ৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + SPI_OUTLINK_START ࡼՎ໊ᇂ 1 ष൓൐Ⴈ‫ؿ‬ෂ৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + SPI_OUTLINK_STOP ࡼՎ໊ᇂ 1 ๔ᆸ൐Ⴈ‫ؿ‬ෂ৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + SPI_OUTLINK_ADDR ֻ၂۱‫ؿ‬ෂ৽і૭ඍ‫ֹژ‬ᆶbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 134 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.27. SPI_DMA_IN_LINK_REG (0x108) + + (reservSePdI_) INSLPINI_KINS_LPRINIE_SKINT_LASINRTATKR_TSTOP (reserved) SPI_INLINK_AUTO_RET SPI_INLINK_ADDR + 0x000000 +31 30 29 28 27 21 20 19 0 + +0 0 0 00 0 0 0 0 0 00 Reset + + SPI_INLINK_RESTART ࡼՎ໊ᇂ 1 ൐Ⴈྍ֥ࢤ൬৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + SPI_INLINK_START ࡼՎ໊ᇂ 1 ष൓൐Ⴈࢤ൬৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + SPI_INLINK_STOP ࡼՎ໊ᇂ 1 ๔ᆸ൐Ⴈࢤ൬৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + SPI_INLINK_AUTO_RET Վ໊ᇂ 1 ൈđ֒ඔऌЇ໭ིđࢤ൬৽і૭ඍ‫๋֞ژ‬༯၂۱૭ඍ‫ژ‬bč‫؀‬/ཿĎ + SPI_INLINK_ADDR ֻ၂۱ࢤ൬৽і૭ඍ‫ֹژ‬ᆶbč‫؀‬/ཿĎ + + Register 7.28. SPI_DMA_STATUS_REG (0x10C) + + (reserved) SPI_DSMPAI__DTMX_AE_NRX_EN + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_DMA_TX_EN SPI DMA ‫ؿ‬ෂඔऌሑ෿໊bčᆺ‫؀‬Ď + SPI_DMA_RX_EN SPI DMA ࢤ൬ඔऌሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 135 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.29. SPI_DMA_INT_ENA_REG (0x110) + + (reserved) SPI_OSUPTI__OTSOUPTTIA__OLES_OUEPFTOI___FIIDNNS_OT_IPNS_NI_TEUEI_NNC_SEAI__NPNEEITA_RO_INREFS___NPEDINAI_OOTINFNS__LEPEIINNNI__ITAKON_S_TUEPD_TNIES_LANCIINNARLK_I_NEDKRS_RCDORSR_C_ERINR_RTE_OMERPN_TAIYN_TI_NETN_EANA + +31 98 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_OUT_TOTAL_EOF_INT_ENA SPI_OUT_TOTAL_EOF_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SPI_OUT_EOF_INT_ENA SPI_OUT_EOF_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SPI_OUT_DONE_INT_ENA SPI_OUT_DONE_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SPI_IN_SUC_EOF_INT_ENA SPI_IN_SUC_EOF_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SPI_IN_ERR_EOF_INT_ENA SPI_IN_ERR_EOF_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SPI_IN_DONE_INT_ENA SPI_IN_DONE_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SPI_INLINK_DSCR_ERROR_INT_ENA SPI_INLINK_DSCR_ERROR_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SPI_OUTLINK_DSCR_ERROR_INT_ENA SPI_OUTLINK_DSCR_ERROR_INT ֥ᇏ؎൐ି + ໊bč‫؀‬/ཿĎ + + SPI_INLINK_DSCR_EMPTY_INT_ENA SPI_INLINK_DSCR_EMPTY_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 136 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.30. SPI_DMA_INT_RAW_REG (0x114) + + (reserved) SPI_OSUPTI__OTSOUPTTIA__OLES_OUEPFTOI___FIIDNNS_OT_IPNS_NI_TRUEI_ANC_SRWI__NPAEEITW_RO_INRRFS___APEDINWI_OOTINFNS__LRPEIINANI__ITWKON_S_TURPD_TAIRS_LWCIAINNWRLK_I_NEDKRS_RCDORSR_C_ERINR_RTE_OMRRPA_TWIYN_TI_NRTA_RWAW + +31 98 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_OUT_TOTAL_EOF_INT_RAW SPI_OUT_TOTAL_EOF_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_OUT_EOF_INT_RAW SPI_OUT_EOF_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_OUT_DONE_INT_RAW SPI_OUT_DONE_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_IN_SUC_EOF_INT_RAW SPI_IN_SUC_EOF_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_IN_ERR_EOF_INT_RAW SPI_IN_ERR_EOF_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_IN_DONE_INT_RAW SPI_IN_DONE_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_INLINK_DSCR_ERROR_INT_RAW SPI_INLINK_DSCR_ERROR_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ + + ‫؀‬Ď + SPI_OUTLINK_DSCR_ERROR_INT_RAW SPI_OUTLINK_DSCR_ERROR_INT ֥ ჰ ൓ ᇏ ؎ ሑ ෿ + + ໊bčᆺ‫؀‬Ď + SPI_INLINK_DSCR_EMPTY_INT_RAW SPI_INLINK_DSCR_EMPTY_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ + + ‫؀‬Ď + +ুᶈྐ༏॓࠯ 137 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.31. SPI_DMA_INT_ST_REG (0x118) + + (reserved) SPI_OSUPTI__OTSOUPTTIA__OLES_OUEPFTOI___FIIDNNS_OT_IPNS_NI_TSUEI_TNC_SSI__NPTEEIT_RO_INRSFS___TPEDINI_OOTINFNS__LSPEIINTNI__ITKON_S_TUSPD_TTISS_LTCIINNRLK_I_NEDKRS_RCDORSR_C_ERINR_RTE_OMSRPT_TIYN_TI_NSTT_ST + +31 98 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_OUT_TOTAL_EOF_INT_ST SPI_OUT_TOTAL_EOF_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_OUT_EOF_INT_ST SPI_OUT_EOF_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_OUT_DONE_INT_ST SPI_OUT_DONE_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_IN_SUC_EOF_INT_ST SPI_IN_SUC_EOF_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_IN_ERR_EOF_INT_ST SPI_IN_ERR_EOF_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_IN_DONE_INT_ST SPI_IN_DONE_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_INLINK_DSCR_ERROR_INT_ST SPI_INLINK_DSCR_ERROR_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SPI_OUTLINK_DSCR_ERROR_INT_ST SPI_OUTLINK_DSCR_ERROR_INT ֥௠зᇏ؎ሑ෿໊čbᆺ + + ‫؀‬Ď + SPI_INLINK_DSCR_EMPTY_INT_ST SPI_INLINK_DSCR_EMPTY_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 138 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.32. SPI_DMA_INT_CLR_REG (0x11C) + + (reserved) SPI_OSUPTI__OTSOUPTTIA__OLES_OUEPFTOI___FIIDNNS_OT_IPNS_NI_TCUEI_NLC_SCRI__NPLEEITR_RO_INRCFS___PLEDIRNI_OOTINFNS__LCPEIINNIL__IRTKON_S_TUCPD_TLICS_LRCILINNRRLK_I_NEDKRS_RCDORSR_C_ERINR_RTE_OMCRPL_TRIYN_TI_NCTL_RCLR + +31 98 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_OUT_TOTAL_EOF_INT_CLR ࡼՎ໊ᇂ 1 ౢԢ SPI_OUT_TOTAL_EOF_INT ᇏ؎bč‫؀‬/ཿĎ + SPI_OUT_EOF_INT_CLR ࡼՎ໊ᇂ 1 ౢԢ SPI_OUT_EOF_INT ᇏ؎bč‫؀‬/ཿĎ + SPI_OUT_DONE_INT_CLR ࡼՎ໊ᇂ 1 ౢԢ SPI_OUT_DONE_INT ᇏ؎bč‫؀‬/ཿĎ + SPI_IN_SUC_EOF_INT_CLR ࡼՎ໊ᇂ 1 ౢԢ SPI_IN_SUC_EOF_INT ᇏ؎bč‫؀‬/ཿĎ + SPI_IN_ERR_EOF_INT_CLR ࡼՎ໊ᇂ 1 ౢԢ SPI_IN_ERR_EOF_INT ᇏ؎bč‫؀‬/ཿĎ + SPI_IN_DONE_INT_CLR ࡼՎ໊ᇂ 1 ౢԢ SPI_IN_DONE_INT ᇏ؎bč‫؀‬/ཿĎ + SPI_INLINK_DSCR_ERROR_INT_CLR ࡼ Վ ໊ ᇂ 1 ౢ Ԣ SPI_INLINK_DSCR_ERROR_INT ᇏ + + ؎bč‫؀‬/ཿĎ + SPI_OUTLINK_DSCR_ERROR_INT_CLR ࡼՎ໊ᇂ 1 ౢԢ SPI_OUTLINK_DSCR_ERROR_INT ᇏ + + ؎bč‫؀‬/ཿĎ + SPI_INLINK_DSCR_EMPTY_INT_CLR ࡼ Վ ໊ ᇂ 1 ౢ Ԣ SPI_INLINK_DSCR_EMPTY_INT ᇏ + + ؎bč‫؀‬/ཿĎ + + Register 7.33. SPI_IN_ERR_EOF_DES_ADDR_REG (0x120) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_IN_ERR_EOF_DES_ADDR_REG ֒ SPI DMA ԛགྷࢤ൬հ༂ൈ֥ࢤ൬৽і૭ඍ‫ֹژ‬ᆶbčᆺ‫؀‬Ď + + Register 7.34. SPI_IN_SUC_EOF_DES_ADDR_REG (0x124) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_IN_SUC_EOF_DES_ADDR_REG ֒ SPI DMA ‫ؿ‬ෂӮ‫ۿ‬ൈ֥ቋު၂۱ࢤ൬৽і૭ඍ‫ֹژ‬ᆶčbᆺ + ‫؀‬Ď + +ুᶈྐ༏॓࠯ 139 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.35. SPI_INLINK_DSCR_REG (0x128) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_INLINK_DSCR_REG ֒భࢤ൬৽і૭ඍ‫ֹژ‬ᆶbčᆺ‫؀‬Ď + + Register 7.36. SPI_INLINK_DSCR_BF0_REG (0x12C) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_INLINK_DSCR_BF0_REG ༯၂۱ࢤ൬৽і૭ඍ‫ֹژ‬ᆶbčᆺ‫؀‬Ď + + Register 7.37. SPI_INLINK_DSCR_BF1_REG (0x130) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_INLINK_DSCR_BF1_REG ༯၂۱ࢤ൬৽і૭ඍ‫ژ‬ඔऌߏթֹᆶbčᆺ‫؀‬Ď + + Register 7.38. SPI_OUT_EOF_BFR_DES_ADDR_REG (0x134) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_OUT_EOF_BFR_DES_ADDR_REG ളӮ EOF ֥‫ؿ‬ෂ৽і૭ඍ‫ؓژ‬ႋ֥ߏթֹᆶbčᆺ‫؀‬Ď + + Register 7.39. SPI_OUT_EOF_DES_ADDR_REG (0x138) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_OUT_EOF_DES_ADDR_REG ֒ SPI DMA ‫ؿ‬ෂӮ‫ۿ‬ൈ֥ቋު၂۱‫ؿ‬ෂ৽і૭ඍ‫ֹژ‬ᆶbčᆺ + ‫؀‬Ď + + Register 7.40. SPI_OUTLINK_DSCR_REG (0x13C) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_OUTLINK_DSCR_REG ֒భ‫ؿ‬ෂ৽і૭ඍ‫ֹژ‬ᆶbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 140 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 7 SPI ॥ᇅఖ (SPI) + + Register 7.41. SPI_OUTLINK_DSCR_BF0_REG (0x140) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_OUTLINK_DSCR_BF0_REG ༯၂۱‫ؿ‬ෂ৽і૭ඍ‫ֹژ‬ᆶbčᆺ‫؀‬Ď + + Register 7.42. SPI_OUTLINK_DSCR_BF1_REG (0x144) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SPI_OUTLINK_DSCR_BF1_REG ༯၂۱‫ؿ‬ෂ৽і૭ඍ‫ژ‬ඔऌߏթֹᆶbčᆺ‫؀‬Ď + + Register 7.43. SPI_DMA_RSTATUS_REG (0x148) + + TX_FIFTOX__FEIMFOP_TFYULL (reserved) TX_DES_ADDRESS + +31 30 29 20 19 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + TX_FIFO_EMPTY SPI DMA ‫ؿ‬ෂ FIFO ູॢbčᆺ‫؀‬Ď + TX_FIFO_FULL SPI DMA ‫ؿ‬ෂ FIFO ູડbčᆺ‫؀‬Ď + TX_DES_ADDRESS SPI DMA ‫ؿ‬ෂ૭ඍ‫ژ‬ᆷᆌ֥֮Ⴕ໊ིbčᆺ‫؀‬Ď + + Register 7.44. SPI_DMA_TSTATUS_REG (0x14C) + + RX_FIRFOX__FEIMFOP_TFYULL (reserved) RX_DES_ADDRESS + +31 30 29 20 19 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RX_FIFO_EMPTY SPI DMA ࢤ൬ FIFO ູॢbčᆺ‫؀‬Ď + RX_FIFO_FULL SPI DMA ࢤ൬ FIFO ູડbčᆺ‫؀‬Ď + RX_DES_ADDRESS SPI DMA ࢤ൬૭ඍ‫ژ‬ᆷᆌ֥֮Ⴕ໊ིbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 141 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + +8 SDIO Ֆࠏ॥ᇅఖ + +8.1 ‫ۀ‬ඍ + +ESP32 ᆦӻඔሳൻೆൻԛ (SDIO) ഡСࢤ१đ‫ ކژ‬SDIO ಆ෎व V2.0 ܿٓbᇶ॥ఖॖၛ๙‫ ݖ‬SDIO ሹཌླྀၰ٠ +໙ ESP32b +ᇶࠏ (Host) ॖၛᆰࢤ٠໙ SDIO ࢤ१࠷թఖđࠇ๙‫ݖ‬൐Ⴈ DMA ႄౣ٠໙ഡСഈ֥‫܋‬ཚթԥఖđᄝЌᆣྟି֥๝ +ൈࡨഒਔԩ৘ྟି֥শ‫ٮ‬b + +8.2 ᇶေหྟ + + • ‫ ކژ‬SDIO ಆ෎व V2.0 ܿٓ + • ᆦӻ SDIO SPIđ1-bit ‫ ބ‬4-bit Ԯൻଆൔ + • 0 ~ 50 MHz ൈᇒٓຶ + • ॖ஥ᇂ֥Ґဢൈᇒခࠇ౺‫׮‬ൈᇒခ + • ູྐ༏ࢌ޺ഡ‫֥ק‬ห‫࠷ק‬թఖ + • ᆦӻሱ‫׮‬แԉ SDIO ሹཌഈ֥‫ؿ‬ෂඔऌđ๝ဢᆦӻሱ‫ש׮‬ఙ SDIO ሹཌഈ֥แԉඔऌ + • ۚղ 512 ሳࢫ֥ॶնཬ + • Host ა Slave ࡗႵᇏ؎ཟਈॖၛཌྷ޺ᇏ؎ؓٚ + • ႨႿඔऌԮൻ֥ DMA + +8.3 ‫ିۿ‬૭ඍ + +8.3.1 SDIO Slave ‫ॶିۿ‬๭ + +SDIO Slave ֥‫ॶିۿ‬๭ೂ๭ 8-1 ෮ൕb + + ๭ 8­1. SDIO Slave ‫ॶିۿ‬๭ + +ᇶࠏ༢๤ (Host System) սі಩၂‫ ކژ‬SDIO V2.0 ֥ܿٓ Host ഡСbHost ๙‫ݖ‬ѓሙ SDIO ሹཌაቔູ SDIO +Slave ֥ ESP32 ޺‫׮‬bSDIO ഡСࢤ१ଆॶ๙‫ݖ‬ᆰࢤิ‫ ܂‬SDIO ࢤ१࠷թఖѩ൐ି DMA Ҡቔটა Host ๙ྐđ +ൌགྷۚࠩྟିሹཌ (AHB) ഈ֥ۚ෎ඔऌԮൻđѩ౏҂ླေ CPU ֥ҕაb + +8.3.2 SDIO ሹཌഈ֥ඔऌ‫ؿ‬ෂ‫ࢤބ‬൬ + +Host ა Slave ࡗ๙‫ ݖ‬SDIO bus I/O Function1 ࣉྛඔऌԮൻb֒ Host οᅶ SDIO ླྀၰ൐ି Slave ֥ I/O +Function1 ުđࠧॖၛࣉྛඔऌ֥Ԯൻb + +ুᶈྐ༏॓࠯ 142 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + +ඔऌ֥ԮൻၛЇູֆ໊đૄՑ֥Ԯൻ‫׻‬൞ᆷ֥၂۱ඔऌЇbູิۚԮൻིੱđ๷ࡩ൐ႨֆՑॶԮൻčऎุ࡮ +SDIO ླྀၰĎࣉྛЇ֥ԮൻbູਔൌགྷֆՑॶԮൻđHost ‫ ބ‬Slave ‫ླ׻‬ေࡼ SDIO ሹཌഈ‫ؿ‬ෂ֥ඔऌแԉູᆜ۱ +ॶbSlave ᄝ‫ؿ‬Їൈ߶ሱ‫׮‬แԉඔऌđᄝ൬Їൈሱ‫ש׮‬ఙแԉඔऌb +Slave ሱ‫׮‬แԉ‫שބ‬ఙඔऌ൞๙‫ ݖ‬SDIO ሹཌഈ֥ඔऌֹᆶট஑؎đ֒ඔऌֹᆶնႿ֩Ⴟ 0x1F800 ުࣉྛඔऌ +แԉࠇ‫ש‬đ෮ၛԮൻ֥ఏ൓ඔऌֹᆶູ 0x1F800 ⚶Packet_lengthčPacket_length ֥ֆ໊൞ሳࢫĎbᄝ SDIO ሹཌ +ഈ֥ඔऌੀೂ๭ 8-2 ෮ൕğ + + ๭ 8­2. SDIO ሹཌഈඔऌԮൻ + +Ԯൻ൐Ⴈ֥൞ IO_RW_EXTENDED (CMD53) ଁ਷đఃቆӮೂ๭ 8-3đ۲҆‫ٳ‬ऎุ‫ݣ‬ၬ౨Ұु SDIO ླྀၰb + + ๭ 8­3. CMD53 ଽಸ + +8.3.3 ࠷թఖ٠໙ + +ູਔٚь Host ა Slave ᆭࡗ֥ྐ༏ࢌ޺đHost ॖၛ๙‫ ݖ‬SDIO bus I/O Function1 ٠໙ Slave ᇏ֥ห‫࠷ק‬թఖb +ᆃུ࠷թఖᄝ SLC0HOST_TOKEN_RDATA ֞ SLCHOST_INF_ST ֥৵࿃ֹᆶ‫؍‬ଽbHost ٠໙ൈᆺླࡼ CMD52 +ࠇ CMD53 ᇏ֥࠷թఖֹᆶഡᇂູؓႋ࠷թఖֹᆶ֥֮ 10 ໊bHost ॖၛ൐Ⴈ CMD53 ๝ൈ٠໙‫؟‬۱࠷թఖđ +ิۚਔඔऌԮൻ֥෎ੱb +SLCHOST_CONF_W0_REG ֞ SLCHOST_CONF_W15_REG ‫܋‬Ⴕ 54 ۱ሳࢫ֥౵თđHost ‫ ބ‬Slave ॖၛ಩ၩ٠ +໙‫ڿྩބ‬đٚьਔ Host ა Slave ᆭࡗ֥ྐ༏ࢌ޺b + +8.3.4 DMA + +SDIO Slave Ⴕ၂۱ህ૊֥ DMA ႨႿՖ RAM ࠆ౼ࠇթԥԮൻඔऌbೂ๭ 8-1 ෮ൕđDMA ๙‫ ݖ‬AHB ٠໙ RAMb +DMA ൐Ⴈ৽іࢲ‫ܒ‬ট٠໙ RAMbૄ۱৽іႮ 3 ۱ሳ (word) ቆӮđऎุࢲ‫ܒ‬ೂ๭ 8-4 ෮ൕb + + ๭ 8­4. SDIO Slave DMA ৽іࢲ‫ܒ‬ + +• Ownerğ֒భ৽іؓႋ buffer ᄍྸ֥Ҡቔᆀb + 0ğᄍྸ֥Ҡቔᆀູ CPU + +ুᶈྐ༏॓࠯ 143 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + 1ğᄍྸ֥Ҡቔᆀູ DMA + • Eofğࢲඏѓᆽđіૼ֒భ৽і൞ඔऌЇ֥ቋު၂۱৽іb + • LengthğBuffer ᇏ֥ႵིሳࢫඔđࠧՖ buffer ᇏି‫ܔ‬Ф‫؀‬౼֥ሳࢫඔb + • SizeğBuffer ᄍྸ൐Ⴈ֥ቋնሳࢫඔb + • Buffer Address PointerğBuffer ֹᆶᆷᆌb + • Next Descriptor Addressğ༯၂۱৽іֹ֥ᆶᆷᆌb֒֒భ৽іၘࣜ൞ቋު၂۱৽іൈđEof ໊֥ᆴႋູ + + 1đ‫ھ‬ᆴႋູ 0b +Slave ৽іԱೂ๭ 8-5 ෮ൕğ + + ๭ 8­5. ৽іԱ + +8.3.5 Ї֥‫ؿ‬ෂ‫ࢤބ‬൬ੀӱ + +Host ა Slave ࡗ֥ЇԮൻླေਆᆀοᅶห‫֥ק‬ੀӱ஥‫ކ‬ປӮb + +8.3.5.1 Slave ཟ Host ‫ؿ‬ෂЇ + +Ї֥‫ؿ‬ෂ൞Ⴎ Slave ‫ؿ‬ఏđ๙‫ݖ‬ᇏ؎ট๙ᆩ Hostčᇏ؎ൌགྷٚൔҕु SDIO ླྀၰĎbHost Ֆ Slave ‫؀‬౼ཌྷܱྐ༏ +ު‫ؿ‬ఏ SDIO ሹཌԮൻbᆜ۱ੀӱೂ๭ 8-6 ෮ൕğ + +ুᶈྐ༏॓࠯ 144 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + ๭ 8­6. Slave ཟ Host ‫ؿ‬ෂЇ֥ੀӱ + +ুᶈྐ༏॓࠯ 145 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + +Host Ֆ Slave ‫؀‬౼ཌྷܱྐ༏൞๙‫ݖ‬٠໙ SLC0HOST_INT ‫ ބ‬SLCHOST_PKT_LEN ᆃਆ۱࠷թఖൌགྷ֥b + • SLC0HOST_INTğᇏ؎ሑ෿࠷թఖđఃᇏ bit SLC0_RX_NEW_PACKET_INT_ST ູ 1 іૼᇏ؎֥ჰၹ൞ + Slave ‫ؿ‬Їb + • SLCHOST_PKT_LENğSlave ‫ؿ‬ෂЇӉ؇৆ࡆ࠷թఖđHost ႨЧՑ‫؀‬౼ᆴࡨಀഈՑ‫؀‬౼ᆴࣼॖၛ֤֞Ч + Ց‫ؿ‬ෂЇ֥Ӊ؇b + +CPU ఓ‫ ׮‬DMA ླေ༵ࡼ৽іԱֻ၂۱৽іֹ֥ᆶ֮ 20 ໊ཿ֞࠷թఖ SLC0RX_LINK ֥ SLC0_RXLINK_ADDR +ᇏđᄜ஥ᇂ SLC0RX_LINK ֥ SLC0_RXLINK_START টఓ‫ ׮‬DMAbᆭު DMA ߶ሱ‫׮‬ປӮඔऌ֥Ԯൻb +‫ؿ‬ෂປӮު DMA ߶ཟ CPU ‫ؿ‬ෂᇏ؎đᆃൈ CPU ॖၛ߭൬ bufferb + +8.3.5.2 Slave Ֆ Host ࢤ൬Ї + +Ї֥ࢤ൬൞Ⴎ Host ‫ؿ‬ఏđSlave ๙‫ ݖ‬DMA ࢤ൬ඔऌѩթԥ֞ RAM ᇏđԮൻປӮު๙‫ݖ‬ᇏ؎๙ᆩ CPU ࣉྛඔ +ऌԩ৘bᆜ۱ੀӱೂ๭ 8-7 ෮ൕğ + + ๭ 8­7. Slave Ֆ Host ࢤ൬Ї֥ੀӱ + +ুᶈྐ༏॓࠯ 146 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + +Host ๙‫ݖ‬٠໙࠷թఖ SLC0HOST_TOKEN_RDATA ࠆ౼ Slave ҧॖႨႿࢤ൬Ї֥ buffer ඔbSlave ҧ֥ CPU ေ +ᄝሙС‫ݺ‬ႨႿࢤ൬Ї֥ DMA ৽іު۷ྍᆃ۱ᆴb +SLC0HOST_TOKEN_RDATA ᇏ HOSTREG_SLC0_TOKEN1 թ٢ॖႨ buffer ֥৆࠹ᆴb +Host ๙‫ ݖ‬HOSTREG_SLC0_TOKEN1 ࡨಀሱ࠭ၘႨ‫ ֥ו‬buffer ඔ֤ࣼ֞ਔ֒భॖႨ֥ buffer ඔb +֒ buffer ҂‫ܔ‬ႨൈđHost ླေ๙‫ݖ‬҂๔ֹ٠໙ᆃ۱࠷թఖᆰ֞ buffer ‫ܔ‬Ⴈູᆸb +ູਔЌᆣႵԉቀ֥ buffer টࢤ൬ЇđSlave ֥ CPU сྶ҂๔ֹᄝࢤ൬৽іഈ‫ܫ‬ᄛ bufferb‫ܫ‬ᄛ֥ੀӱೂ๭ 8-8 +෮ൕb + + ๭ 8­8. Slave CPU ‫ܫ‬ᄛ buffer ֥ੀӱ + +CPU ൮༵ླေࡼྍ֥ buffer ቆӮ৽іԱѩ౏‫ܫ‬ᄛᄝ DMA ᆞᄝ൐Ⴈ֥৽іԱࢲແb +ಖު CPU ླေ๙ᆩ DMA ৽іԱၘ۷ྍđॖၛ๙‫ݖ‬ᇂ໊ SLC0TX_LINK ࠷թఖ֥ SLC0_TXLINK_RESTART ູ 1 +টൌགྷbᇿၩđCPU ᄝ൮Ցఓ‫ ׮‬DMA ႨႿ൬Їൈླᇂ໊ᇂ SLC0TX_LINK ࠷թఖ֥ +SLC0_TXLINK_STARTb +ቋުđCPU ๙‫ݖ‬஥ᇂ SLC0TOKEN1 ࠷թఖ۷ྍॖႨ֥ bufferb + +8.3.6 SDIO ሹཌൈ྽ + +Host ა Slave ࡗ൞๙‫ ݖ‬PCB ሼཌ৵ࢤđ෮ၛ࿼ӾնbູਔЌᆣሹཌഈൈ྽ᆞಒđSlave ᆦӻ‫ט‬ᆜ SDIO ሹཌൻ +ೆ֥Ґဢൈᇒခ‫ބ‬ൻԛ֥౺‫׮‬ൈᇒခb +֒Ֆ Host ট֥ඔऌэ߄֥ൈख़ौ࣍ൈᇒ֥ഈശခൈđSlave ߶࿊ᄴൈᇒ֥༯ࢆခࣉྛҐဢbҐဢൈ྽๭ೂ๭ +8-9 ෮ൕğ + + ๭ 8­9. Ґဢൈ྽๭ + +Slave ܵ࢖ҐဢခଏಪႮ MTDO strapping ᆴथ‫ק‬đ֌๙‫ݖ‬஥ᇂ SLCHOST_CONF_REG ࠷թఖॖၛ఼ᇅथ‫ק‬ଆ + +ুᶈྐ༏॓࠯ 147 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + +ൔčႪ༵ࠩՖ֮ۚ֞Ďğ(1) ᇂ໊ SLCHOST_FRC_POS_SAMPđؓႋܵ࢖఼ᇅഈശခҐဢĠ(2) ᇂ໊ +SLCHOST_FRC_NEG_SAMPđؓႋܵ࢖఼ᇅ༯ࢆခҐဢb +SLCHOST_FRC_POS_SAMP ‫ ބ‬SLCHOST_FRC_NEG_SAMP ໊֥ॺनູ 5 bitđ5 ۱ bit ‫ٳ‬љؓႋ CMD ཌ‫ ބ‬4 +۱ DATA ཌ (0-3)bᇂ໊ᆃਆ۱თ൐֤ Slave ؓཌྷႋ֥ཌᄝൈᇒഈശခࠇ༯ࢆခഈࣉྛҐဢb +Slave ߎॖၛ࿊ᄴൈᇒ֥ഈശခߎ൞༯ࢆခؓඔऌൻԛཌࣉྛ౺‫׮‬đၛൡႋ҂๝֥࿼Ӿbൈ྽๭ೂ๭ 8-10 ෮ +ൕğ + + ๭ 8­10. ൻԛൈ྽๭ + +Slave ܵ࢖ൻԛခଏಪႮ GPIO5 strapping ᆴथ‫ק‬đ֌๙‫ݖ‬஥ᇂၛ༯࠷թఖॖၛ఼ᇅथ‫ק‬ଆൔčႪ༵ࠩՖۚ֞ +֮Ďğ(1) ᇂ໊ SLCHOST_CONF_REG ᇏ֥ SLCHOST_FRC_SDIO11đؓႋܵ࢖఼ᇅ༯ࢆခൻԛĠ(2) ᇂ໊ +SLCHOST_CONF_REG ᇏ֥ SLCHOST_FRC_SDIO22đؓႋܵ࢖఼ᇅഈശခൻԛĠ(3) ᇂ໊ +HINF_CFG_DATA1_REG ᇏ֥ HINF_HIGHSPEED_ENABLE ‫ ބ‬SLCHOST_CONF_REG ᇏ֥ +SLCHOST_HSPEED_CON_EN ުđᇶࠏ๙‫ݖ‬஥ᇂ CCCR ᇏ֥ EHS (Enable High-Speed) ູ 1 ఼ᇅഈശခൻ +ԛb + +SLCHOST_FRC_SDIO11 ‫ ބ‬SLCHOST_FRC_SDIO22 ໊֥ॺनູ 5 bitđ5 ۱ bit ‫ٳ‬љؓႋ CMD ཌ‫ ބ‬4 ۱ DATA +ཌ (0-3)bᇂ໊ᆃਆ۱თ൐֤ Slave ᄝൈᇒ༯ࢆခࠇഈശခഈؓཌྷႋ֥ཌࣉྛ౺‫׮‬b + +ܱႿႪ༵֥ࠩඪૼğ໭ંൻೆߎ൞ൻԛđstrapping ܵ࢖֥஥ᇂ္ФЇ‫ݣ‬ᄝႪ༵ࠩٓຶଽčႪ༵ࠩቋ֮Ďbૄ၂ +ࠩႵི֥భิ൞б෱֥ۚႪ༵ࠩ‫׻‬҂ളིb২ೂ MTDO strapping ֥஥ᇂथ‫ؓק‬ႋܵ࢖֥Ґဢခđളི֥భิ +൞ SCLHOST_FRC_POS_SAMP ીႵᇂ 1đSCLHOST_FRC_NEG_SAMP ္ીႵᇂ 1b + +8.3.7 ᇏ؎ + +Host ‫ ބ‬Slave ࡗॖၛ๙‫ݖ‬஥ᇂᇏ؎ཟਈਲࠃֹᇏ؎ؓٚbHost ‫ ބ‬Slave ۲Ⴕ 8 ۱ᇏ؎ཟਈॖႨႿᇏ؎ؓٚbᄝ +஥ᇂᇏ؎ཟਈ࠷թఖުࣼ߶ཟؓٚ‫ؿ‬ෂᇏ؎č஥ᇂཌྷႋ֥ᇏ؎൐ି࠷թఖĎbᇏ؎ཟਈ࠷թఖऎႵሱౢ‫ିۿ‬đ෮ +ၛ஥ᇂ၂Ց߶Ӂള၂Ցᇏ؎đ҂ླေః෰Ҡቔb + +8.3.7.1 Host ҧᇏ؎ + + • SLC0HOST_SLC0_RX_NEW_PACKET_INT Slave ‫ؿ‬Їᇏ؎ + • SLC0HOST_SLC0_TX_OVF_INT Slave ࢤ൬ buffer ၮԛᇏ؎ + • SLC0HOST_SLC0_RX_UDF_INT Slave ‫ؿ‬ෂ buffer ༯ၮᇏ؎ + • SLC0HOST_SLC0_TOHOST_BITn_INT (n: 0 ~ 7) Slave ᇏ؎ Host + +8.3.7.2 Slave ҧᇏ؎ + + • SLC0INT_SLC0_RX_DSCR_ERR_INT Slave ‫ؿ‬ෂ૭ඍ‫ژ‬հ༂ᇏ؎ + +ুᶈྐ༏॓࠯ 148 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + +• SLC0INT_SLC0_TX_DSCR_ERR_INT Slave ࢤ൬૭ඍ‫ژ‬հ༂ᇏ؎ +• SLC0INT_SLC0_RX_EOF_INT Slave ‫ؿ‬ෂҠቔປӮᇏ؎ +• SLC0INT_SLC0_RX_DONE_INT ֆ۱ buffer Ⴎ Slave ‫ؿ‬ෂປӮ֥ᇏ؎ +• SLC0INT_SLC0_TX_SUC_EOF_INT Slave ࢤ൬ҠቔປӮᇏ؎ +• SLC0INT_SLC0_TX_DONE_INT A ֆ۱ buffer ᄝ Slave ࢤ൬Ҡቔൈแડਔ֥ᇏ؎ +• SLC0INT_SLC0_TX_OVF_INT Slave ࢤ൬ buffer ၮԛᇏ؎ +• SLC0INT_SLC0_RX_UDF_INT Slave ‫ؿ‬ෂ buffer ༯ၮᇏ؎ +• SLC0INT_SLC0_TX_START_INT Slave ࢤ൬Ҡቔष൓ᇏ؎ +• SLC0INT_SLC0_RX_START_INT Slave ‫ؿ‬ෂҠቔष൓ᇏ؎ +• SLC0INT_SLC_FRHOST_BITn_INT (n: 0 ~ 7) Host ᇏ؎ Slave + +8.4 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + + ଀ӫ SLCCONF0_SLC ஥ᇂ 0x3FF58000 ‫؀‬/ཿ + SDIO DMA (SLC) ஥ᇂ࠷թఖ ‫ؿ‬ෂ৽і஥ᇂ 0x3FF5803C ‫؀‬/ཿ + SLCCONF0_REG ࢤ൬৽і஥ᇂ 0x3FF58040 ‫؀‬/ཿ + SLC0RX_LINK_REG Slave ᇏ؎ Host ֥ᇏ؎ཟਈ 0x3FF5804C ᆺཿ + SLC0TX_LINK_REG ࢤ൬ buffer ඔ 0x3FF58054 ᆺཿ + SLCINTVEC_TOHOST_REG ॥ᇅ࠷թఖ 0x3FF58060 ‫؀‬/ཿ + SLC0TOKEN1_REG DMA Ԯൻ஥ᇂ 0x3FF58098 ‫؀‬/ཿ + SLCCONF1_REG ԮൻඔऌЇ֥Ӊ؇॥ᇅ 0x3FF580E4 ‫؀‬/ཿ + SLC_RX_DSCR_CONF_REG ԮൻඔऌЇ֥Ӊ؇ 0x3FF580E8 ‫؀‬/ཿ + SLC0_LEN_CONF_REG + SLC0_LENGTH_REG ჰ൓ᇏ؎ሑ෿ 0x3FF58004 ᆺ‫؀‬ + ᇏ؎࠷թఖ ᇏ؎ሑ෿ 0x3FF58008 ᆺ‫؀‬ + SLC0INT_RAW_REG ᇏ؎൐ି 0x3FF5800C ‫؀‬/ཿ + SLC0INT_ST_REG ᇏ؎ౢԢ 0x3FF58010 ᆺཿ + SLC0INT_ENA_REG + SLC0INT_CLR_REG + + ଀ӫ ૭ඍ ֹᆶ ٠໙ + SDIO SLC Host ࠷թఖ + SLC0HOST_TOKEN_RDATA Slave ࢤ൬ buffer ֥৆࠹ᆴ 0x3FF55044 ᆺ‫؀‬ + SLCHOST_PKT_LEN_REG ԮൻඔऌЇ֥Ӊ؇ 0x3FF55060 ᆺ‫؀‬ + SLCHOST_CONF_W0_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 0 0x3FF5506C ‫؀‬/ཿ + SLCHOST_CONF_W1_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 1 0x3FF55070 ‫؀‬/ཿ + SLCHOST_CONF_W2_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 2 0x3FF55074 ‫؀‬/ཿ + SLCHOST_CONF_W3_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 3 0x3FF55078 ‫؀‬/ཿ + SLCHOST_CONF_W4_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 4 0x3FF5507C ‫؀‬/ཿ + SLCHOST_CONF_W6_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 6 0x3FF55088 ‫؀‬/ཿ + SLCHOST_CONF_W7_REG Host ᇏ؎ Slave ֥ᇏ؎ཟਈ 0x3FF5508C ᆺཿ + +ুᶈྐ༏॓࠯ 149 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + +SLCHOST_CONF_W8_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 8 0x3FF5509C ‫؀‬/ཿ +SLCHOST_CONF_W9_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 9 0x3FF550A0 ‫؀‬/ཿ +SLCHOST_CONF_W10_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 10 0x3FF550A4 ‫؀‬/ཿ +SLCHOST_CONF_W11_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 11 0x3FF550A8 ‫؀‬/ཿ +SLCHOST_CONF_W12_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 12 0x3FF550AC ‫؀‬/ཿ +SLCHOST_CONF_W13_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 13 0x3FF550B0 ‫؀‬/ཿ +SLCHOST_CONF_W14_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 14 0x3FF550B4 ‫؀‬/ཿ +SLCHOST_CONF_W15_REG Host ‫ ބ‬Slave ๙ྐ࠷թఖ 15 0x3FF550B8 ‫؀‬/ཿ +SLCHOST_CONF_REG ခ஥ᇂ 0x3FF551F0 ‫؀‬/ཿ +ᇏ؎࠷թఖ +SLC0HOST_INT_RAW_REG ჰ൓ᇏ؎ 0x3FF55000 ᆺ‫؀‬ +SLC0HOST_INT_ST_REG ௠зᇏ؎ሑ෿ 0x3FF55058 ᆺ‫؀‬ +SLC0HOST_INT_CLR_REG ᇏ؎ౢԢ 0x3FF550D4 ᆺཿ +SLC0HOST_FUNC1_INT_ENA_REG ᇏ؎൐ି 0x3FF550DC ‫؀‬/ཿ + +଀ӫ ૭ඍ ֹᆶ ٠໙ +SDIO HINF ࠷թఖ SDIO ܿٓ஥ᇂ +HINF_CFG_DATA1_REG 0x3FF4B004 ‫؀‬/ཿ + +8.5 SLC ࠷թఖ + +SDIO ॥ᇅ࠷թఖֻ֥၂۱ॶ֥ఏ൓ֹᆶູ 0x3FF5_8000b + +ুᶈྐ༏॓࠯ 150 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.1. SLCCONF0_REG (0x0) + + (reserved) SLCCONF0_SLC0_TO(KreEsNer_vAeUdT) O_CLR SLCCSOLNCFC0SO_LSNCLFCC0O0__SN(RLrFeXC0s_0_eA_SrvURLeTXCdSO_0)LL__OCWTXOCR_SOPBLL_NOACTFCOEC0KSPO_T_SNTLFEC0S0_T_SRLXC_0R_STXT_RST + +31 15 14 13 76 5 43 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Reset + + SLCCONF0_SLC0_TOKEN_AUTO_CLR Ԛ൓߄ູ 0b౨໿ྩ‫ڿ‬bč‫؀‬/ཿĎ + + SLCCONF0_SLC0_RX_AUTO_WRBACK ᆦӻᄝ‫ؿ‬ෂඔऌൈᄝ‫ؿ‬ෂ buffer ৽іഈ‫ڿ‬ཿ owner + bitbč‫؀‬/ཿĎ + + SLCCONF0_SLC0_RX_LOOP_TEST Slave buffer ‫ؿ‬ෂЇࢲඏު࿖ߌbᇂ໊ުđ႗ࡱ҂߶ᇶ‫׮‬۷‫ڿ‬ + ৽іᇏ owner bitbč‫؀‬/ཿĎ + + SLCCONF0_SLC0_TX_LOOP_TEST Slave buffer ࢤ൬Їࢲඏު࿖ߌbᇂ໊ުđ႗ࡱ҂߶ᇶ‫׮‬۷‫ڿ‬ + ৽іᇏ owner bitbč‫؀‬/ཿĎ + + SLCCONF0_SLC0_RX_RST ᇂູ 1 ‫ؿ໊گ‬ෂ FSMbč‫؀‬/ཿĎ + + SLCCONF0_SLC0_TX_RST ᇂູ 1 ‫ࢤ໊گ‬൬ FSMbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 151 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.2. SLC0INT_RAW_REG (0x4) + + (reserved) + (reserved) + ((rrSSSSSSSSSSSSSSSSSSeeLLLLLLLLLLLLLLLLLLssCCCCCCCCCCCCCCCCCCee000000000000000000rrIIIIIIIIIIIIIIIIIIvvNNNNNNNNNNNNNNNNNNeeTTTTTTTTTTTTTTTTTTdd))__________________SSSSSSSSSSSSSSSSSSLLLLLLLLLLLLLLLLLLCCCCCCCCCCCCCCCCCC________0000000000FFFFFFFF__________TTTTTRRRRRRRRRRRRRXXXXXXXXXXHHHHHHHH__________OOOOOOOOSSDDESODDUSSSSSSSSTTSUVOSODOTTTTTTTTAAFFFCCNC________N_R___RIRIEIRBBBBBBBBETIIIIIIIITE___N_NNI_I_TTTTTTTTIEIOTETTN41235607N_FNR__NR________TTIIIIIIII_TRTIRRR_R___NNNNNNNN_A_AANIRIRRTTTTTTTTRTANWA________NWWAA_TTRRRRRRRRWWR_W_WAAAAAAAAARRWWWWWWWWAAWWW + +31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SLC0INT_SLC0_RX_DSCR_ERR_INT_RAW Slave ‫ؿ‬ෂ૭ඍ‫ژ‬հ༂֥ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_TX_DSCR_ERR_INT_RAW Slave ࢤ൬૭ඍ‫ژ‬հ༂֥ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_RX_EOF_INT_RAW Slave ‫ؿ‬ෂҠቔࢲඏ֥ᇏ؎ѓᆽ໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_RX_DONE_INT_RAW ֆ۱ buffer Ⴎ Slave ‫ؿ‬ෂປӮ֥ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_TX_SUC_EOF_INT_RAW Slave ࢤ൬ҠቔປӮ֥ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_TX_DONE_INT_RAW ֆ۱ buffer ᄝ Slave ࢤ൬Ҡቔൈแડਔ֥ჰ൓ᇏ؎໊bčᆺ + + ‫؀‬Ď + SLC0INT_SLC0_TX_OVF_INT_RAW Slave ࢤ൬ buffer ၮԛ֥ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_RX_UDF_INT_RAW Slave ‫ؿ‬ෂ buffer ༯ၮ֥ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_TX_START_INT_RAW Slave ࢤ൬ष൓ᇏ؎֥֥ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_RX_START_INT_RAW Slave ‫ؿ‬ෂष൓ᇏ؎֥֥ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT7_INT_RAW Host ᇏ؎ Slave ֥ᇏ؎ѓᆽ໊ 7bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT6_INT_RAW Host ᇏ؎ Slave ֥ᇏ؎ѓᆽ໊ 6bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT5_INT_RAW Host ᇏ؎ Slave ֥ᇏ؎ѓᆽ໊ 5bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT4_INT_RAW Host ᇏ؎ Slave ֥ᇏ؎ѓᆽ໊ 4bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT3_INT_RAW Host ᇏ؎ Slave ֥ᇏ؎ѓᆽ໊ 3bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT2_INT_RAW Host ᇏ؎ Slave ֥ᇏ؎ѓᆽ໊ 2bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT1_INT_RAW Host ᇏ؎ Slave ֥ᇏ؎ѓᆽ໊ 1bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT0_INT_RAW Host ᇏ؎ Slave ֥ᇏ؎ѓᆽ໊ 0bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 152 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.3. SLC0INT_ST_REG (0x8) + + (reserved) (reserved) SLC0ISNLTC_0SI(LNreCTs0_e_SrvSRLeLXCdC_0)D0_ISSTNXLCTC_R_D0S_SISELNCLRCTCRR0_0__S_ISERILNNRLXCTTCR_0__E0__SSOIIRLNNTFXCTT(__0r__IeDN_SSsOTLTTeXC_Nrv_S0EeST__dUSTI)NCXLTC___DE0SOOISNTLFNTC_E_I0N_SISILTNNLC_TTCS0__0T_SSISTLNTXLCTC_0_O0_SVISRLNFLXCT_C_0_IUN0_SISDTTLNXL_CFTCS__0_SIT0_SNTISRLNTALXC_TRC_S__TS0FTS_TISRLNIANLHCTRCTO___T0FSSS_ISRLNTITLNHC_TCTBO__0_FSISTSISRLNT7TLHC_T_CBO_I_N0FSISTTISRLNT6_LHC_T_SCBO_I_TN0FSISTTISRLNT5_LHC_T_SCBO_I_TN0FSISTTIRLNT4_HC_T_SBO_I_TNFSISTTRLT3_HC__SBO_ITNFISTTRT2_H__SBOITNISTTT1___SBITNITT0__SITNT_ST + +31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SLC0INT_SLC0_RX_DSCR_ERR_INT_ST Slave ‫ؿ‬ෂ૭ඍ‫ژ‬հ༂֥ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_TX_DSCR_ERR_INT_ST Slave ࢤ൬૭ඍ‫ژ‬հ༂֥ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_RX_EOF_INT_ST Slave ‫ؿ‬ෂҠቔࢲඏ֥ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_RX_DONE_INT_ST ֆ۱ buffer Ⴎ Slave ‫ؿ‬ෂປӮ֥ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_TX_SUC_EOF_INT_ST Slave ࢤ൬ҠቔປӮ֥ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_TX_DONE_INT_ST ֆ۱ buffer ᄝ Slave ࢤ൬Ҡቔൈแડਔ֥ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_TX_OVF_INT_ST Slave ࢤ൬ၮԛᇏ؎֥ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_RX_UDF_INT_ST Slave ‫ؿ‬ෂ buffer ༯ၮ֥ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_TX_START_INT_ST Slave ࢤ൬ᇏ؎ष൓֥ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_RX_START_INT_ST Slave ‫ؿ‬ෂᇏ؎ष൓֥ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT7_INT_ST Host ᇏ؎ Slave ֥ᇏ؎ሑ෿໊ 7bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT6_INT_ST Host ᇏ؎ Slave ֥ᇏ؎ሑ෿໊ 6bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT5_INT_ST Host ᇏ؎ Slave ֥ᇏ؎ሑ෿໊ 5bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT4_INT_ST Host ᇏ؎ Slave ֥ᇏ؎ሑ෿໊ 4bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT3_INT_ST Host ᇏ؎ Slave ֥ᇏ؎ሑ෿໊ 3bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT2_INT_ST Host ᇏ؎ Slave ֥ᇏ؎ሑ෿໊ 2bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT1_INT_ST Host ᇏ؎ Slave ֥ᇏ؎ሑ෿໊ 1bčᆺ‫؀‬Ď + SLC0INT_SLC_FRHOST_BIT0_INT_ST Host ᇏ؎ Slave ֥ᇏ؎ሑ෿໊ 0bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 153 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.4. SLC0INT_ENA_REG (0xC) + + (reserved) + (reserved) + ((rrSSSSSSSSSSSSSSSSSSeeLLLLLLLLLLLLLLLLLLssCCCCCCCCCCCCCCCCCCee000000000000000000rrIIIIIIIIIIIIIIIIIIvvNNNNNNNNNNNNNNNNNNeeTTTTTTTTTTTTTTTTTTdd))__________________SSSSSSSSSSSSSSSSSSLLLLLLLLLLLLLLLLLLCCCCCCCCCCCCCCCCCC________0000000000FFFFFFFF__________TTTTTRRRRRRRRRRRRRXXXXXXXXXXHHHHHHHH__________OOOOOOOOSSDDEOSUDDSSSSSSSSTTSUVSOODOTTTTTTTTAAFFFCCCN________N_R___RIRIEIRBBBBBBBBETIIIIIIIITE__N__NNI_I_TTTTTTTTIEITOETTN12354670N_FNR__NR________TTIIIIIIII_ETETEIR_R___NNNNNNNN_N_NNENIEIETTTTTTTTEATAANNN________NNN_TATEEEEEEEEAAEA__NNNNNNNNNEEAAAAAAAAANNAA + +31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SLC0INT_SLC0_RX_DSCR_ERR_INT_ENA Slave ‫ؿ‬ෂ৽і૭ඍ‫ژ‬հ༂֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + SLC0INT_SLC0_TX_DSCR_ERR_INT_ENA Slave ࢤ൬৽і૭ඍ‫ژ‬հ༂֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + SLC0INT_SLC0_RX_EOF_INT_ENA Slave ‫ؿ‬ෂҠቔࢲඏ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + SLC0INT_SLC0_RX_DONE_INT_ENA Slave ‫ ؿ‬ෂ ଆ ൔ ༯ ֆ ۱ buffer ‫ ؿ‬ෂ ປ Ӯ ֥ ᇏ ؎ ൐ ି + + ໊bč‫؀‬/ཿĎ + SLC0INT_SLC0_TX_SUC_EOF_INT_ENA Slave ࢤ൬ҠቔປӮ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + SLC0INT_SLC0_TX_DONE_INT_ENA Slave ࢤ൬ଆൔ༯ֆ۱ buffer แડਔ֥ᇏ؎൐ି໊bčᆺ‫؀‬Ď + SLC0INT_SLC0_TX_OVF_INT_ENA Slave ࢤ൬ buffer ၮԛ֥ᇏ؎ሑ෿໊bč‫؀‬/ཿĎ + SLC0INT_SLC0_RX_UDF_INT_ENA Slave ‫ؿ‬ෂ buffer ༯ၮ֥ᇏ؎ሑ෿໊bč‫؀‬/ཿĎ + SLC0INT_SLC0_TX_START_INT_ENA Slave ࢤ൬Ҡቔष൓֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + SLC0INT_SLC0_RX_START_INT_ENA Slave ‫ؿ‬ෂҠቔष൓֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + SLC0INT_SLC_FRHOST_BIT7_INT_ENA Host ᇏ؎ Slave ֥ᇏ؎൐ି໊ 7bč‫؀‬/ཿĎ + SLC0INT_SLC_FRHOST_BIT6_INT_ENA Host ᇏ؎ Slave ֥ᇏ؎൐ି໊ 6bč‫؀‬/ཿĎ + SLC0INT_SLC_FRHOST_BIT5_INT_ENA Host ᇏ؎ Slave ֥ᇏ؎൐ି໊ 5bč‫؀‬/ཿĎ + SLC0INT_SLC_FRHOST_BIT4_INT_ENA Host ᇏ؎ Slave ֥ᇏ؎൐ି໊ 4bč‫؀‬/ཿĎ + SLC0INT_SLC_FRHOST_BIT3_INT_ENA Host ᇏ؎ Slave ֥ᇏ؎൐ି໊ 3bč‫؀‬/ཿĎ + SLC0INT_SLC_FRHOST_BIT2_INT_ENA Host ᇏ؎ Slave ֥ᇏ؎൐ି໊ 2bč‫؀‬/ཿĎ + SLC0INT_SLC_FRHOST_BIT1_INT_ENA Host ᇏ؎ Slave ֥ᇏ؎൐ି໊ 1bč‫؀‬/ཿĎ + SLC0INT_SLC_FRHOST_BIT0_INT_ENA Host ᇏ؎ Slave ֥ᇏ؎൐ି໊ 0bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 154 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.5. SLC0INT_CLR_REG (0x10) + + (reserved) + (reserved) + ((rrSSSSSSSSSSSSSSSSSSeeLLLLLLLLLLLLLLLLLLssCCCCCCCCCCCCCCCCCCee000000000000000000rrIIIIIIIIIIIIIIIIIIvvNNNNNNNNNNNNNNNNNNeeTTTTTTTTTTTTTTTTTTdd))__________________SSSSSSSSSSSSSSSSSSLLLLLLLLLLLLLLLLLLCCCCCCCCCCCCCCCCCC________0000000000FFFFFFFF__________TTTTTRRRRRRRRRRRRRXXXXXXXXXXHHHHHHHH__________OOOOOOOOSSDDEOSUDDSSSSSSSSTTSUVSOODOTTTTTTTTAAFFFCCCN________N_R___RIRIEIRBBBBBBBBETIIIIIIIITE__N__NNI_I_TTTTTTTTIEITOETTN23546710N_FNR__NR________TTIIIIIIII_TCTIRCC_R___NNNNNNNNL_L_LNICICTTTTTTTTCRCTRRLNL________NLL_TRTRCCCCCCCCRRC__LLLLLLLLLCCRRRRRRRRRLLRR + +31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SLC0INT_SLC0_RX_DSCR_ERR_INT_CLR ࡼՎ໊ᇂູ 1đౢԢ‫ؿ‬ෂ৽і૭ඍ‫ژ‬հ༂֥ᇏ؎bčᆺ + ཿĎ + + SLC0INT_SLC0_TX_DSCR_ERR_INT_CLR ࡼՎ໊ᇂູ 1đౢԢࢤ൬৽і૭ඍ‫ژ‬հ༂֥ᇏ؎bčᆺ + ཿĎ + + SLC0INT_SLC0_RX_EOF_INT_CLR ࡼՎ໊ᇂູ 1đౢԢ Slave ‫ؿ‬ෂҠቔࢲඏ֥ᇏ؎bčᆺཿĎ + + SLC0INT_SLC0_RX_DONE_INT_CLR ࡼՎ໊ᇂູ 1đౢԢ Slave ‫ؿ‬ෂଆൔ༯ֆ۱ buffer ‫ؿ‬ෂປӮ + ֥ᇏ؎bčᆺཿĎ + + SLC0INT_SLC0_TX_SUC_EOF_INT_CLR ࡼՎ໊ᇂູ 1đౢԢ Slave ࢤ൬ҠቔປӮ֥ᇏ؎bčᆺཿĎ + + SLC0INT_SLC0_TX_DONE_INT_CLR ࡼՎ໊ᇂູ 1đౢԢ Slave ࢤ൬ଆൔ༯ֆ۱ buffer แડਔ֥ + ᇏ؎bčᆺཿĎ + + SLC0INT_SLC0_TX_OVF_INT_CLR ࡼՎ໊ᇂູ 1đౢԢ Slave ࢤ൬ၮԛᇏ؎bčᆺཿĎ + + SLC0INT_SLC0_RX_UDF_INT_CLR ࡼՎ໊ᇂູ 1đౢԢ Slave ‫ؿ‬ෂၮԛᇏ؎bčᆺཿĎ + + SLC0INT_SLC0_TX_START_INT_CLR ࡼՎ໊ᇂູ 1đౢԢ Slave ࢤ൬ҠቔԚ൓߄ᇏ؎bčᆺཿĎ + + SLC0INT_SLC0_RX_START_INT_CLR ࡼՎ໊ᇂູ 1đౢԢ Slave ‫ؿ‬ෂҠቔԚ൓߄ᇏ؎bčᆺཿĎ + + SLC0INT_SLC_FRHOST_BIT7_INT_CLR ᇂ໊ౢԢ SLC0INT_SLC_FRHOST_BIT7_INTᇏ؎bčᆺ + ཿĎ + + SLC0INT_SLC_FRHOST_BIT6_INT_CLR ᇂ໊ౢԢ SLC0INT_SLC_FRHOST_BIT6_INT ᇏ؎bčᆺ + ཿĎ + + SLC0INT_SLC_FRHOST_BIT5_INT_CLR ᇂ໊ౢԢ SLC0INT_SLC_FRHOST_BIT5_INT ᇏ؎bčᆺ + ཿĎ + + SLC0INT_SLC_FRHOST_BIT4_INT_CLR ᇂ໊ౢԢ SLC0INT_SLC_FRHOST_BIT4_INT ᇏ؎bčᆺ + ཿĎ + + SLC0INT_SLC_FRHOST_BIT3_INT_CLR ᇂ໊ౢԢ SLC0INT_SLC_FRHOST_BIT3_INT ᇏ؎bčᆺ + ཿĎ + + SLC0INT_SLC_FRHOST_BIT2_INT_CLR ᇂ໊ౢԢ SLC0INT_SLC_FRHOST_BIT2_INT ᇏ؎bčᆺ + ཿĎ + + ࠷թఖ૭ඍ༯၂်࠿࿃b 155 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) +ুᶈྐ༏॓࠯ ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.5. SLC0INT_CLR_REG (0x10) + + ࠿ഈ၂်࠷թఖ૭ඍb + SLC0INT_SLC_FRHOST_BIT1_INT_CLR ᇂ໊ౢԢ SLC0INT_SLC_FRHOST_BIT1_INT ᇏ؎bčᆺ + + ཿĎ + SLC0INT_SLC_FRHOST_BIT0_INT_CLR ᇂ໊ౢԢ SLC0INT_SLC_FRHOST_BIT0_INT ᇏ؎bčᆺ + + ཿĎ + + Register 8.6. SLC0RX_LINK_REG (0x3C) + + (reservSeLdC) 0RSLXC_S0LRSCLXC0__S0RLRXCXL0_I_SNRLKXC_L0RI_NERSKXT_LASINRTATKR_(TSreTsOePrved) 20 19 SLC0RX_SLC0_RXLINK_ADDR 0 + 0x000000 +31 30 29 28 27 Reset + +0 0 0 00 0 0 0 0 0 0 0 + +SLC0RX_SLC0_RXLINK_RESTART ࡼՎ໊ᇂູ 1đᇗఓѩ࠿࿃৽іҠቔট‫ؿ‬ෂЇbč‫؀‬/ཿĎ +SLC0RX_SLC0_RXLINK_START ࡼՎ໊ᇂູ 1đఓ‫৽׮‬іҠቔট‫ؿ‬ෂЇb‫ؿ‬ෂ֥ఏ൓ֹᆶႮ + + SLC0_RXLINK_ADDR ۳ԛbč‫؀‬/ཿĎ +SLC0RX_SLC0_RXLINK_STOP ࡼՎ໊ᇂູ 1đ๔ᆸ৽іҠቔbč‫؀‬/ཿĎ +SLC0RX_SLC0_RXLINK_ADDR Slave ‫ؿ‬Ї৽і֥ఏ൓ֹᆶ֥֮ 20 ໊bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 156 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.7. SLC0TX_LINK_REG (0x40) + + (reservSeLdC) 0TSXL_CS0LTSCXL0_C_S0TLTXCXL0_IN_STLKXC_LR0IN_ETSKXT_LASINRTATKR_TS(rTeOsePrved) 20 19 SLC0TX_SLC0_TXLINK_ADDR 0 + 0x000000 +31 30 29 28 27 Reset + +0 0 0 00 0 0 0 0 0 0 0 + + SLC0TX_SLC0_TXLINK_RESTART ࡼՎ໊ᇂູ 1đᇗఓѩ࠿࿃৽іҠቔটࢤ൬Їbč‫؀‬/ཿĎ + SLC0TX_SLC0_TXLINK_START ࡼՎ໊ᇂູ 1đఓ‫৽׮‬іҠቔটࢤ൬Їbࢤ൬֥ఏ൓ֹᆶႮ + + SLC0_TXLINK_ADDR ۳ԛbč‫؀‬/ཿĎ + SLC0TX_SLC0_TXLINK_STOP ࡼՎ໊ᇂູ 1đ๔ᆸ৽іҠቔbč‫؀‬/ཿĎ + SLC0TX_SLC0_TXLINK_ADDR Slave ൬Ї৽і֥ఏ൓ֹᆶ֥֮ 20 ໊bč‫؀‬/ཿĎ + + Register 8.8. SLCINTVEC_TOHOST_REG (0x4C) + + (reserved) (reserved) (reserved) SLCINTVEC_SLC0_TOHOST_INTVEC + +31 24 23 16 15 87 0 + + 0x000 00000000 0x000 0x000 Reset + + SLCINTVEC_SLC0_TOHOST_INTVEC Slave ᇏ؎ Host ֥ᇏ؎ཟਈbčᆺཿĎ + +ুᶈྐ༏॓࠯ 157 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.9. SLC0TOKEN1_REG (0x54) + + (reserved) SLC0TOKEN1_SLC0_TOKEN1 (reservSeLdC) 0TO(KreEsNe1rv_eSdL) C0_TOKEN1_INC_MORE SLC0TOKEN1_SLC0_TOKEN1_WDATA + +31 28 27 16 15 14 13 12 11 0 + + 0x00 0x0000 0 00 0 0x0000 Reset + + SLC0TOKEN1_SLC0_TOKEN1 ൬Ї buffer ֥৆࠹ඔਈbčᆺ‫؀‬Ď + SLC0TOKEN1_SLC0_TOKEN1_INC_MORE ৆࠹ॖႨ֥൬Ї buffer ֥ᆷൕྐ‫ݼ‬bčᆺཿĎ + SLC0TOKEN1_SLC0_TOKEN1_WDATA ॖႨ֥൬Ї buffer ඔਈbčᆺཿĎ + + Register 8.10. SLCCONF1_REG (0x60) + + (reserved) (reserved) (reserved) SLCCSOLNCFC1SO_LSNCLFCC1O0__SNRLFXC1_0_S_STTLIXCT_C0S_HTL_IETENCN_HA_UETNO_CLR + + 31 23 22 16 15 76 5 4 + + 0x000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Reset + + SLCCONF1_SLC0_RX_STITCH_EN Ԛ൓߄ູ 0b౨໿ྩ‫ڿ‬bč‫؀‬/ཿĎ + SLCCONF1_SLC0_TX_STITCH_EN Ԛ൓߄ູ 0b౨໿ྩ‫ڿ‬bč‫؀‬/ཿĎ + SLCCONF1_SLC0_LEN_AUTO_CLR Ԛ൓߄ູ 0b౨໿ྩ‫ڿ‬bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 158 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.11. SLC_RX_DSCR_CONF_REG (0x98) + + (reserved) SLC_SLC0_TOKEN_NO_REPLACE + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SLC_SLC0_TOKEN_NO_REPLACE Ԛ൓߄ູ 1b౨໿ྩ‫ڿ‬bč‫؀‬ĔཿĎ + + Register 8.12. SLC0_LEN_CONF_REG (0xE4) + + (reserved) (reserved) SLC0_LE(rNes_eINrvCe_dM) ORE DATA + SLC0_LEN_W +31 29 28 23 22 21 20 19 0x000000 0 + + 0x0 0 0 0 0 0 000 0 Reset + + SLC0_LEN_INC_MORE ৆࠹‫ؿ‬ෂ֥ЇӉ֥ᆷൕྐ‫ݼ‬bčᆺཿĎ 0 + SLC0_LEN_WDATA ‫ؿ‬ෂ֥ЇӉbčᆺཿĎ + Reset + Register 8.13. SLC0_LENGTH_REG (0xE8) + + (reserved) SLC0_LEN + 0x000000 +31 20 19 + + 0x0000 + + SLC0_LEN Slave ‫ؿ‬Ї֥৆࠹Ӊ؇bčᆺ‫؀‬Ď + +8.6 SLC Host ࠷թఖ + +SDIO ॥ᇅ࠷թఖֻ֥‫ؽ‬۱ॶ֥ఏ൓ֹᆶູ 0x3FF5_5000. + +ুᶈྐ༏॓࠯ 159 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.14. SLC0HOST_TOKEN_RDATA (0x44) + + (reserved) HOSTREG_SLC0_TOKEN1 (reserved) + 0x000 +31 28 27 16 15 0 + + 0x000 0x000 Reset + + HOSTREG_SLC0_TOKEN1 Slave ҧॖႨႿࢤ൬ Host ඔऌ֥ buffer ඔ֥৆ࡆᆴbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 160 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.15. SLC0HOST_INT_RAW_REG (0x50) + + (reserved) + (((rrrSSSeeeLLLsssCCCeee000rrrvvvHHHeeeOOOddd)))SSSTTT___SSSLLLCCC000___TRRXXX___OUNVEDFFW__II_NNPTTA__CRRKAAETWW_INT_RAW + SSSSSSSSLLLLLLLLCCCCCCCC00000000HHHHHHHHOOOOOOOOSSSSSSSSTTTTTTTT________SSSSSSSSLLLLLLLLCCCCCCCC00000000________TTTTTTTTOOOOOOOOHHHHHHHHOOOOOOOOSSSSSSSSTTTTTTTT________BBBBBBBBIIIIIIIITTTTTTTT01752634________IIIIIIIINNNNNNNNTTTTTTTT________RRRRRRRRAAAAAAAAWWWWWWWW + +31 26 25 24 23 22 18 17 16 15 87 6 5 4 3 2 1 0 + + 0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SLC0HOST_SLC0_RX_NEW_PACKET_INT_RAW SLC0HOST_SLC0_RX_NEW_PACKET_INT ֥ + ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TX_OVF_INT_RAW SLC0HOST_SLC0_TX_OVF_INT ֥ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_RX_UDF_INT_RAW SLC0HOST_SLC0_RX_UDF_INT ֥ჰ൓ᇏ؎໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT7_INT_RAW SLC0HOST_SLC0_TOHOST_BIT7_INT ֥ჰ൓ᇏ؎ + ໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT6_INT_RAW SLC0HOST_SLC0_TOHOST_BIT6_INT ֥ჰ൓ᇏ؎ + ໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT5_INT_RAW SLC0HOST_SLC0_TOHOST_BIT5_INT ֥ჰ൓ᇏ؎ + ໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT4_INT_RAW SLC0HOST_SLC0_TOHOST_BIT4_INT֥ ჰ ൓ ᇏ ؎ + ໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT3_INT_RAW SLC0HOST_SLC0_TOHOST_BIT3_INT ֥ჰ൓ᇏ؎ + ໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT2_INT_RAW SLC0HOST_SLC0_TOHOST_BIT2_INT ֥ჰ൓ᇏ؎ + ໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT1_INT_RAW SLC0HOST_SLC0_TOHOST_BIT1_INT ֥ჰ൓ᇏ؎ + ໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT0_INT_RAW SLC0HOST_SLC0_TOHOST_BIT0_INT ֥ჰ൓ᇏ؎ + ໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 161 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.16. SLC0HOST_INT_ST_REG (0x58) + + (reserved) + (((rrrSSSeeeLLLsssCCCeee000rrrvvvHHHeeeOOOddd)))SSSTTT___SSSLLLCCC000___TRRXXX___OUNVEDFFW__II_NNPTTA__CSSKTTET_INT_ST + SSSSSSSSLLLLLLLLCCCCCCCC00000000HHHHHHHHOOOOOOOOSSSSSSSSTTTTTTTT________SSSSSSSSLLLLLLLLCCCCCCCC00000000________TTTTTTTTOOOOOOOOHHHHHHHHOOOOOOOOSSSSSSSSTTTTTTTT________BBBBBBBBIIIIIIIITTTTTTTT56701342________IIIIIIIINNNNNNNNTTTTTTTT________SSSSSSSSTTTTTTTT + +31 26 25 24 23 22 18 17 16 15 87 6 5 4 3 2 1 0 + + 0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SLC0HOST_SLC0_RX_NEW_PACKET_INT_ST SLC0HOST_SLC0_RX_NEW_PACKET_INT ᇏ ؎ + ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TX_OVF_INT_ST SLC0HOST_SLC0_TX_OVF_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ + ‫؀‬Ď + + SLC0HOST_SLC0_RX_UDF_INT_ST SLC0HOST_SLC0_RX_UDF_INTᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ + ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT7_INT_ST SLC0HOST_SLC0_TOHOST_BIT7_INT ᇏ؎֥௠зᇏ + ؎ሑ෿໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT6_INT_ST SLC0HOST_SLC0_TOHOST_BIT6_INT ᇏ؎֥௠зᇏ + ؎ሑ෿໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT5_INT_ST SLC0HOST_SLC0_TOHOST_BIT5_INTᇏ ؎ ֥ ௠ з ᇏ + ؎ሑ෿໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT4_INT_ST SLC0HOST_SLC0_TOHOST_BIT4_INT ᇏ؎֥௠зᇏ + ؎ሑ෿໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT3_INT_ST SLC0HOST_SLC0_TOHOST_BIT3_INT ᇏ؎֥௠зᇏ + ؎ሑ෿໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT2_INT_ST SLC0HOST_SLC0_TOHOST_BIT2_INT ᇏ؎֥௠зᇏ + ؎ሑ෿໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT1_INT_ST SLC0HOST_SLC0_TOHOST_BIT1_INT ᇏ؎֥௠зᇏ + ؎ሑ෿໊bčᆺ‫؀‬Ď + + SLC0HOST_SLC0_TOHOST_BIT0_INT_ST SLC0HOST_SLC0_TOHOST_BIT0_INT ᇏ؎֥௠зᇏ + ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 162 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.17. SLCHOST_PKT_LEN_REG (0x60) + + SLCHOST_HOSTREG_SLC0_LEN_CHECK SLCHOST_HOSTREG_SLC0_LEN + 0x000 +31 20 19 0 + + 0x000 Reset + + SLCHOST_HOSTREG_SLC0_LEN_CHECK ᆴ ູ HOSTREG_SLC0_LEN[9:0] ࡆഈ + HOSTREG_SLC0_LEN[19:10]bčᆺ‫؀‬Ď + + SLCHOST_HOSTREG_SLC0_LEN Slave ‫ؿ‬ෂ֥ЇӉ֥৆࠹ᆴbᆺᄝ Host ‫؀‬౼ൈҌ߶۷ྍᆴb + + Register 8.18. SLCHOST_CONF_W0_REG (0x6C) + + SLCHOST_CONF3 SLCHOST_CONF2 SLCHOST_CONF1 SLCHOST_CONF0 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF3 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF2 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF1 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF0 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 163 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.19. SLCHOST_CONF_W1_REG (0x70) + + SLCHOST_CONF7 SLCHOST_CONF6 SLCHOST_CONF5 SLCHOST_CONF4 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF7 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF6 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF5 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF4 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + + Register 8.20. SLCHOST_CONF_W2_REG (0x74) + + SLCHOST_CONF11 SLCHOST_CONF10 SLCHOST_CONF9 SLCHOST_CONF8 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF11 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF10 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF9 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF8 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + + Register 8.21. SLCHOST_CONF_W3_REG (0x78) + + SLCHOST_CONF15 SLCHOST_CONF14 + + 31 24 23 16 + + 0x000 0x000 Reset + + SLCHOST_CONF15 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF14 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 164 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.22. SLCHOST_CONF_W4_REG (0x7C) + + SLCHOST_CONF19 SLCHOST_CONF18 + + 31 24 23 16 + + 0x000 0x000 Reset + + SLCHOST_CONF19 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF18 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + + Register 8.23. SLCHOST_CONF_W6_REG (0x88) + + SLCHOST_CONF27 SLCHOST_CONF26 SLCHOST_CONF25 SLCHOST_CONF24 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF27 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF26 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF25 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF24 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + + Register 8.24. SLCHOST_CONF_W7_REG (0x8C) + + SLCHOST_CONF31 (reserved) SLCHOST_CONF29 (reserved) + 0x000 0x000 +31 24 23 16 15 87 0 + +00000000 00000000 Reset + + SLCHOST_CONF31 Host ႨႿᇏ؎ Slave ֥ᇏ؎ཟਈbčᆺཿĎ + SLCHOST_CONF29 Host ႨႿᇏ؎ Slave ֥ᇏ؎ཟਈbčᆺཿĎ + +ুᶈྐ༏॓࠯ 165 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.25. SLCHOST_CONF_W8_REG (0x9C) + + SLCHOST_CONF35 SLCHOST_CONF34 SLCHOST_CONF33 SLCHOST_CONF32 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF35 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF34 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF33 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF32 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + + Register 8.26. SLCHOST_CONF_W9_REG (0xA0) + + SLCHOST_CONF39 SLCHOST_CONF38 SLCHOST_CONF37 SLCHOST_CONF36 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF39 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF38 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF37 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF36 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + + Register 8.27. SLCHOST_CONF_W10_REG (0xA4) + + SLCHOST_CONF43 SLCHOST_CONF42 SLCHOST_CONF41 SLCHOST_CONF40 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF43 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF42 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF41 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF40 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 166 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.28. SLCHOST_CONF_W11_REG (0xA8) + + SLCHOST_CONF47 SLCHOST_CONF46 SLCHOST_CONF45 SLCHOST_CONF44 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF47 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF46 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF45 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF44 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + + Register 8.29. SLCHOST_CONF_W12_REG (0xAC) + + SLCHOST_CONF51 SLCHOST_CONF50 SLCHOST_CONF49 SLCHOST_CONF48 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF51 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF50 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF49 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF48 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + + Register 8.30. SLCHOST_CONF_W13_REG (0xB0) + + SLCHOST_CONF55 SLCHOST_CONF54 SLCHOST_CONF53 SLCHOST_CONF52 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF55 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF54 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF53 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF52 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 167 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.31. SLCHOST_CONF_W14_REG (0xB4) + + SLCHOST_CONF59 SLCHOST_CONF58 SLCHOST_CONF57 SLCHOST_CONF56 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF59 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF58 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF57 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF56 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + + Register 8.32. SLCHOST_CONF_W15_REG (0xB8) + + SLCHOST_CONF63 SLCHOST_CONF62 SLCHOST_CONF61 SLCHOST_CONF60 + +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 0x000 Reset + + SLCHOST_CONF63 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF62 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF61 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + SLCHOST_CONF60 Host ა Slave ֥ྐ༏ࢌ޺࠷թఖbHost ა Slave ‫׻‬ॖ‫؀‬ཿbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 168 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.33. SLC0HOST_INT_CLR_REG (0xD4) + + (reserved) + (((rrrSSSeeeLLLsssCCCeee000rrrvvvHHHeeeOOOddd)))SSSTTT___SSSLLLCCC000___TRRXXX___OUNVEDFFW__II_NNPTTA__CCCKLLERRT_INT_CLR + SSSSSSSSLLLLLLLLCCCCCCCC00000000HHHHHHHHOOOOOOOOSSSSSSSSTTTTTTTT________SSSSSSSSLLLLLLLLCCCCCCCC00000000________TTTTTTTTOOOOOOOOHHHHHHHHOOOOOOOOSSSSSSSSTTTTTTTT________BBBBBBBBIIIIIIIITTTTTTTT76203145________IIIIIIIINNNNNNNNTTTTTTTT________CCCCCCCCLLLLLLLLRRRRRRRR + +31 26 25 24 23 22 18 17 16 15 87 6 5 4 3 2 1 0 + + 0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SLC0HOST_SLC0_RX_NEW_PACKET_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_RX_NEW_PACKET_INT + ᇏ؎bčᆺཿĎ + + SLC0HOST_SLC0_TX_OVF_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_TX_OVF_INT ᇏ؎bčᆺཿĎ + + SLC0HOST_SLC0_RX_UDF_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_RX_UDF_INT ᇏ؎bčᆺཿĎ + + SLC0HOST_SLC0_TOHOST_BIT7_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_TOHOST_BIT7_INT ᇏ + ؎bčᆺཿĎ + + SLC0HOST_SLC0_TOHOST_BIT6_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_TOHOST_BIT6_INT ᇏ + ؎bčᆺཿĎ + + SLC0HOST_SLC0_TOHOST_BIT5_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_TOHOST_BIT5_INT ᇏ + ؎bčᆺཿĎ + + SLC0HOST_SLC0_TOHOST_BIT4_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_TOHOST_BIT4_INT ᇏ + ؎bčᆺཿĎ + + SLC0HOST_SLC0_TOHOST_BIT3_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_TOHOST_BIT3_INT ᇏ + ؎bčᆺཿĎ + + SLC0HOST_SLC0_TOHOST_BIT2_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_TOHOST_BIT2_INT ᇏ + ؎bčᆺཿĎ + + SLC0HOST_SLC0_TOHOST_BIT1_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_TOHOST_BIT1_INT ᇏ + ؎bčᆺཿĎ + + SLC0HOST_SLC0_TOHOST_BIT0_INT_CLR ᇂ໊ౢԢ SLC0HOST_SLC0_TOHOST_BIT0_INT ᇏ + ؎bčᆺཿĎ + +ুᶈྐ༏॓࠯ 169 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + Register 8.34. SLC0HOST_FUNC1_INT_ENA_REG (0xDC) + + (reserved) + (((rrrSSSeeeLLLsssCCCeeerrr000vvvHHHeeeOOOddd)))SSSTTT___FFFNNN111___SSSLLLCCC000___TRRXXX___OUNVEDFFW__II_NNPTTA__CEEKNNEAAT_INT_ENA + SSSSSSSSLLLLLLLLCCCCCCCC00000000HHHHHHHHOOOOOOOOSSSSSSSSTTTTTTTT________FFFFFFFFNNNNNNNN11111111________SSSSSSSSLLLLLLLLCCCCCCCC00000000________TTTTTTTTOOOOOOOOHHHHHHHHOOOOOOOOSSSSSSSSTTTTTTTT________BBBBBBBBIIIIIIIITTTTTTTT24735061________IIIIIIIINNNNNNNNTTTTTTTT________EEEEEEEENNNNNNNNAAAAAAAA + +31 26 25 24 23 22 18 17 16 15 87 6 5 4 3 2 1 0 + + 0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT + ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SLC0HOST_FN1_SLC0_TX_OVF_INT_ENA SLC0HOST_FN1_SLC0_TX_OVF_INT ᇏ؎֥ᇏ؎൐ + ି໊bč‫؀‬/ཿĎ + + SLC0HOST_FN1_SLC0_RX_UDF_INT_ENA SLC0HOST_FN1_SLC0_RX_UDF_INT ᇏ؎֥ᇏ؎൐ + ି໊bč‫؀‬/ཿĎ + + SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT + ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT + ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT + ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT + ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT + ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT + ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT + ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT + ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 170 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 8 SDIO Ֆࠏ॥ᇅఖ + + Register 8.35. SLCHOST_CONF_REG (0x1F0) + + (reserved) SLCHOST_HSPEED_C(rOesNe_rEveNd) SLCHOST_FRC_POS_SAMPSLCHOST_FRC_NEG_SAMPSLCHOST_FRC_SDIO20 SLCHOST_FRC_SDIO11 + +31 28 27 26 20 19 15 14 10 9 54 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SLCHOST_HSPEED_CON_EN ᇂ໊Վ໊ުđ౏ HINF_HIGHSPEED_ENABLE ᇂ 1 ൈđSlave ߶ᄝ + ᇶࠏ஥ᇂ CCCR ᇏ֥ EHS ູ 1 ު఼ᇅഈശခൻԛbč‫؀‬/ཿĎ + + SLCHOST_FRC_POS_SAMP ᇂ໊ᄝൈᇒഈശခҐဢྐ‫ݼ‬bč‫؀‬/ཿĎ + SLCHOST_FRC_NEG_SAMP ᇂ໊ᄝൈᇒ༯ࢆခҐဢྐ‫ݼ‬bč‫؀‬/ཿĎ + SLCHOST_FRC_SDIO20 ᇂ໊ᄝൈᇒഈശခൻԛྐ‫ݼ‬bč‫؀‬/ཿĎ + SLCHOST_FRC_SDIO11 ᇂ໊ᄝൈᇒ༯ࢆခൻԛྐ‫ݼ‬bč‫؀‬/ཿĎ + +8.7 HINF ࠷թఖ + +SDIO ॥ᇅ࠷թఖֻ֥೘۱ॶ֥ఏ൓ֹᆶູ 0x3FF4_B000b + + Register 8.36. HINF_CFG_DATA1_REG (0x4) + + (reserved) HINF_HHINIGFH_SSPDEIOE_DIO_ERNEAABDLYE1 + + 31 32 1 + + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + HINF_HIGHSPEED_ENABLE Ԛ൓߄ູ 1b౨໿ྩ‫ڿ‬bč‫؀‬ĔཿĎ + HINF_SDIO_IOREADY1 Ԛ൓߄ູ 1b౨໿ྩ‫ڿ‬bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 171 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + +9 SD/MMC ᇶࠏ॥ᇅఖ + +9.1 ‫ۀ‬ඍ + +ESP32 թԥव॥ᇅఖิ‫܂‬ਔ၂۱٠໙νಆඔሳൻೆൻԛव (SDIO)aMMC व‫ ބ‬CE-ATA ഡС֥႗ࡱࢤ१đႨႿ +৵ࢤۚࠩຓຶഡСሹཌ (APB) ‫ބ‬ຓ҆թԥഡСbESP32 ᆦӻਆ۱ຓ҆वčव 0 ‫ބ‬व 1Ďb + +9.2 ᇶေหྟ + +ESP32 թԥव॥ᇅఖऎႵၛ༯หྟğ + • ᆦӻਆ۱ຓ҆व + • ᆦӻ SD թԥव 3.0 ‫ ބ‬3.01 ѓሙ + • ᆦӻ MMC ϱЧ 4.41a4.5a4.51 + • ᆦӻ CE-ATA ϱЧ 1.1 + • ᆦӻ 1-bita4-bit ‫ ބ‬8-bitčࣇव 0 ᆦӻĎଆൔ + +SD/MMC ຓഡ৵ࢤ֥ຉ௪ࢲ‫ܒ‬ೂ๭ 9-1 ෮ൕbթԥव॥ᇅఖᆦӻਆቆຓഡ‫۽‬ቔđ֌҂ᆦӻ๝ൈ‫۽‬ቔb + + ๭ 9­1. SD/MMC ຓഡ৵ࢤ֥ຉ௪ࢲ‫ܒ‬ + +9.3 SD/MMC ຓ҆ࢤ१ྐ‫ݼ‬ + +SD/MMC ֥ຓ҆ࢤ१ྐ‫ݼ‬ᇶေູ clkacmdadata ྐ‫֩ݼ‬đߎЇওवᇏ؎aव࡟ҩ‫ބ‬ཿЌ޹ྐ‫֩ݼ‬b۲۱ྐ‫ݼ‬ +֥ٚཟೂ๭ 9-2 ෮ൕbૄ۱ܵ࢖֥ٚཟ‫ބ‬૭ඍೂі 9-1 ෮ൕb + +ুᶈྐ༏॓࠯ 172 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + +ܵ࢖ ٚཟ ๭ 9­2. SD/MMC ຓ҆ࢤ१ྐ‫ݼ‬ +cclk_out ൻԛ +ccmd චཟ і 9­1. SD/MMC ܵ࢖૭ඍ +cdata චཟ +card_detect_n ൻೆ ૭ඍ +card_write_prt ൻೆ ᇶࠏൻԛ۳Ֆࠏ֥ൈᇒཌ + ᆷ਷ĔཙႋචཟԮൻཌ + ඔऌ‫؀‬ཿචཟԮൻཌ + ฐҩࢤ१ഈ൞‫ڎ‬Ⴕवթᄝ֥ൻೆཌ + वཿЌ޹ൻೆཌ + +9.4 ‫ିۿ‬૭ඍ + +9.4.1 SD/MMC ࡏ‫ܒ‬ + +SD/MMC ֥ࢲ‫ܒ‬ᇶေ‫ູٳ‬ሹཌࢤ१ֆჭ (BIU) ‫ބ‬वࢤ१ֆჭ (CIU) ਆ҆‫ٳ‬đೂ๭ 9-3 ෮ൕbఃᇏğ + +BIU ଆॶğิ‫࠷܂‬թఖ٠໙֥ APB ࢤ१aFIFO ٚൔ‫؀‬ཿඔऌđ‫ބ‬ඔऌ‫؀‬ཿҠቔ֥ DMA ٠໙b + +CIU ଆॶğ॥ᇅຓ҆թԥव֥ࢤ१ླྀၰđߎิ‫܂‬ൈᇒ॥ᇅb + +ুᶈྐ༏॓࠯ ๭ 9­3. SD/MMC ࠎЧࡏ‫ܒ‬ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + + 173 + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + +9.4.1.1 BIU ଆॶ + +‫ھ‬ଆॶ๙‫ݖ‬ᇶࠏࢤ१ֆჭ (HIU) APB ሹཌ֥ٚൔ٠໙࠷թఖ‫ބ‬ඔऌ FIFObՎຓđ෱๙‫ ݖ‬DMA ࢤ१ิ‫׿܂‬৫֥ +ඔऌ٠໙b๭ 9-3 ᇏᅚൕਔ BIU ࢲ‫ॿܒ‬๭b +BIU ิ‫܂‬ၛ༯‫ିۿ‬ଆॶğ + + • ᇶࠏࢤ१ + • DMA ࢤ१ + • ᇏ؎॥ᇅ + • ࠷թఖ٠໙ + • FIFO ٠໙ + • ഈ‫׈‬/ഈঘ॥ᇅ‫ބ‬व࡟ҩ + +9.4.1.2 CIU ଆॶ + +‫ھ‬ଆॶൌགྷ॥ᇅव֥ࢤ१ླྀၰbᄝ CIU ᇏđଁ਷๙ਫ਼ (Cmd Path) ॥ᇅֆჭ‫ބ‬ඔऌ๙ਫ਼ (Data Path) ॥ᇅֆჭࡼ +॥ᇅఖ৵ࢤ֞ SD/MMC/CE-ATA व֥ଁ਷‫ބ‬ඔऌ؊१bCIU ߎิ‫܂‬ൈᇒ॥ᇅઆࠠb๭ 9-3 ᅚൕਔ CIU ࢲ‫ॿܒ‬ +๭b +CIU Ї‫ݣ‬ၛ༯ᇶေ‫ିۿ‬ଆॶğ + + • ଁ਷๙ਫ਼ + • ඔऌ๙ਫ਼ + • SDIO ᇏ؎॥ᇅ + • ൈᇒ॥ᇅ + • Mux/Demux ֆჭ + +9.4.2 ଁ਷๙ਫ਼ + +‫ଁھ‬਷๙ਫ਼ऎႵၛ༯‫ିۿ‬ğ + • ഡᇂൈᇒҕඔ + • ഡᇂवଁ਷ҕඔ + • ཟवሹཌ‫ؿ‬ෂଁ਷čccmd_out ཌĎ + • ࢤ൬वሹཌཙႋčccmd_in ཌĎ + • ཟ BIU ‫ؿ‬ෂཙႋ + • ᄝଁ਷ཌഈ‫ؿ‬ෂ P-bit ໊ + +ଁ਷๙ਫ਼ሑ෿ࠏೂ๭ 9-4 ෮ൕb + +ুᶈྐ༏॓࠯ 174 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + ๭ 9­4. ଁ਷๙ਫ਼ሑ෿ࠏ + +9.4.3 ඔऌ๙ਫ਼ + +ඔऌ๙ਫ਼ଆॶᄝཿೆඔऌ‫ؿ‬ෂൈ֐ԛ FIFO ᇏ֥ඔऌѩᄝ cdata_out ഈ‫ؿ‬ෂඔऌĠࠇᆀᄝ‫؀‬౼ඔऌൈࢤ൬ +cdata_in ഈ֥ඔऌѩࡼః֝ೆ FIFObᆺႵඔऌ‫ؿ‬ෂଁ਷҂ᄎྛൈđඔऌ๙ਫ਼Ҍ߶ࡆᄛྍ֥ඔऌҕඔđЇও +expected dataa‫؀‬/ཿඔऌ‫ؿ‬ෂaੀ/ॶ‫ؿ‬ෂaॶնཬaሳࢫ࠹ඔaवো྘aӑൈ࠷թఖ֩b +ೂ‫ݔ‬ᄝଁ਷࠷թఖᇏഡᇂਔ data_expected ໊đᄵྍଁ਷൞ඔऌԮൻଁ਷đඔऌ๙ਫ਼ࡼष൓ᆳྛၛ༯Ҡ +ቔğ + + • ೏‫؀‬/ཿູ໊ 1 ൈđ‫ؿ‬ෂඔऌ + • ೏‫؀‬/ཿູ໊ 0 ൈđࢤ൬ඔऌ + +9.4.3.1 ඔऌ‫ؿ‬ෂ + +ඔऌ‫ؿ‬ෂሑ෿ࠏೂ๭ 9-5 ෮ൕbଆॶᄝࢤ൬֞ඔऌཿೆଁ਷֥ཙႋᆭު֥ਆ۱ൈᇒᇛ௹ष൓‫ؿ‬ෂඔऌĠࠧ൐ଁ +਷๙ਫ਼࡟ҩ֞ཙႋհ༂ࠇ࿖ߌ಺Ⴥ࡟Ұ (CRC) հ༂đ္߶ԛགྷᆃᇕ౦ঃbೂ‫ݔ‬ႮႿཙႋӑൈ‫ط‬ીႵՖवࢤ൬֞ +ཙႋđᄵ҂‫ؿ‬ෂඔऌb۴ऌଁ਷࠷թఖᇏ transfer_mode ໊֥ᆴđඔऌ‫ؿ‬ෂሑ෿ࠏࡼඔऌၛੀࠇॶ֥ྙൔ٢ᄝ +वඔऌሹཌഈb + + ๭ 9­5. ඔऌԮൻሑ෿ࠏ + +ুᶈྐ༏॓࠯ 175 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + +9.4.3.2 ඔऌࢤ൬ + +ඔऌࢤ൬ሑ෿ࠏೂ๭ 9-6 ෮ൕbଆॶᄝඔऌ‫؀‬౼ଁ਷ປӮު֥ਆ۱ൈᇒᇛ௹ष൓ࢤ൬ඔऌĠࠧ൐ଁ਷๙ਫ਼࡟ҩ +֞ཙႋհ༂ࠇཙႋ CRC հ༂đ္߶ೂՎbೂ‫ݔ‬ႮႿཙႋӑൈ‫ط‬ໃՖवࢤ൬֞ཙႋđପહ BIU ࢤ൬҂֞ඔऌԮ +ൻປӮ֥ྐ‫ݼ‬bೂ‫ ݔ‬CIU ‫ؿ‬ෂ֥ଁ਷൞व֥٤‫م‬Ҡቔđପહव໭‫؀م‬౼ඔऌđBIU ္҂߶ࢤ൬֞ඔऌԮൻປӮ +֥ྐ‫ݼ‬b +೏ᄝඔऌӑൈభໃࢤ൬֞ඔऌđᄵඔऌ๙ਫ਼ཟ BIU ‫ؿ‬ԛඔऌӑൈྐ‫ݼ‬ѩࢲඏඔऌԮൻb۴ऌଁ਷࠷թఖᇏ֥ +transfer_mode ໊֥ᆴđඔऌࢤ൬ሑ෿ࠏၛੀࠇॶ֥ྙൔՖवඔऌሹཌࠆ౼ඔऌb + + ๭ 9­6. ඔऌࢤ൬ሑ෿ࠏ + +9.5 CIU Ҡቔ֥ೈࡱཋᇅ + + • ၂Ցᆺି࿊ᄴ၂۱वࣉྛଁ਷ࠇඔऌԮൻb২ೂđ֒वԮෂඔऌൈđ҂ႋࡼྍଁ਷‫ؿ‬ෂ֞ਸ਼၂ᅦवb֌൞ + ྍଁ਷ॖၛ‫ؿ‬ෂ֞๝၂ᅦवđႨႿ‫؀‬౼ሑ෿ࠇ๔ᆸඔऌԮൻb + + • ၂Ցᆺି‫ؿ‬ԛ၂۱ඔऌԮൻଁ਷b + + • ᄝष٢ൔवཿҠቔ௹ࡗđೂ‫ݔ‬वൈᇒၹູ FIFO ູॢ‫ط‬๔ᆸđପહೈࡱсྶ൮༵ࡼඔऌแԉ֞ FIFO ᇏѩ + ఓ‫׮‬वൈᇒđಖުҌॖၛཟव‫ؿ‬ԛ၂۱๔ᆸ/ᇏᆸଁ਷b + + • ᄝ SDIO/COMBO वԮൻ௹ࡗđೂ‫ݔ‬व‫ିۿ‬ᄠ๔đѩ౏ೈࡱေ߫‫گ‬෮ᄠ๔֥Ԯൻđᄵсྶ൮༵ᇗᇂ FIFO + ѩఓ‫ଁگ߫׮‬਷đᆃ‫ބ‬ఓ‫׮‬၂۱ྍ֥ඔऌԮൻଁ਷ཌྷරb + + • ᄝࣉྛवԮൻൈ‫ؿ‬ԛव‫ଁ໊گ‬਷čCMD0aCMD15 ࠇᆀ CMD52_resetĎđೈࡱсྶᄝଁ਷࠷թఖഈഡᇂ + stop_abort_cmd ໊đЌᆣ CIU ॖၛᄝ‫ؿ‬ԛव‫ଁ໊گ‬਷ު๔ᆸඔऌԮൻb + + • ֒ᄝ RINTSTS ࠷թఖᇏഡᇂඔऌࢲඏ໊հ༂ൈđCIU ҂ିЌᆣ SDIO ᇏ؎b෮ၛೈࡱႋޭ੻ SDIO ᇏ؎đ + ѩཟव‫ؿ‬ԛ๔ᆸ/ᇏᆸଁ਷đ൐֤व๔ᆸࣉྛ‫؀‬౼ඔऌԮൻb + + • ೏ᄝ၂۱‫؀‬व‫ݖ‬ӱᇏၹູ FIFO ၘડ‫ط‬๔ᆸवൈᇒđೈࡱႋ‫ھ‬ᇀഒ‫؀‬౼ਆ۱ FIFO ֹᆶটᇗఓवൈᇒb + + • ᄝ၂Ցଁ਷/ඔऌԮൻᇏᆺି࿊౼၂۱ CE-ATA ഡСb২ೂđ֒၂۱ CE-ATA ഡСԮൻඔऌđః෱ CE-ATA + ഡС҂ॖԮൻྍଁ਷b + + • ൐ି CE-ATA ഡС֥ᇏ؎čnIEN = 0Ďđ೏ᄎྛൈႵᆞᄝࣉྛ֥ RW_BLK ଁ਷đᄵ҂ႋࡼྍ֥ RW_BLK ଁ + ਷‫ؿ‬ෂ֞๝၂ഡСčᄝՎඔऌ९ᇏ൐Ⴈ֥ RW_BLK ଁ਷൞Ⴎ CE-ATA ܿ۬඀‫ק‬ၬ֥ + RW_MULTIPLE_BLOCK MMC ଁ਷ĎbᆺႵᄝ֩ր CCS ൈॖၛ‫ؿ‬ෂ CCSDb + +ুᶈྐ༏॓࠯ 176 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + • ؓ๝၂ഡСটඪđ೏ᇏ؎ᄝ CE-ATA ഡСഈໃ൐ି (nIEN = 1)đᄵླေ၂۱ྍଁ਷ট‫؀‬౼ሑ෿ྐ༏b + • CE-ATA ഡС҂ᆦӻष٢ൔԮൻb + • CE-ATA Ԯൻ҂ᆦӻ send_auto_stop ྐ‫ݼ‬čೈࡱ҂ႋഡᇂ send_auto_stop ໊Ďb +֒ଁ਷ఏ൓໊Фᇂഈಀᆭުđᄝଁ਷Ф‫ؿ‬ෂԛಀᆭభၛ༯࠷թఖ֥ᆴ҂ି‫ڿ‬эğ + • CMD — ଁ਷ + • CMDARG — ଁ਷ҕඔ + • BYTCNT — ሳࢫ࠹ඔ + • BLKSIZ — ॶնཬ + • CLKDIV — ൈᇒ‫ٳ‬௔ఖ + • CKLENA — ൈᇒ൐ି + • CLKSRC — ൈᇒჷ + • TMOUT — ӑൈ + • CTYPE — वো྘ + +9.6 ൬‫ؿ‬ඔऌ RAM + +ඔऌ RAM ሰଆॶ൞၂۱൬‫ؿ‬ඔऌߏԊ౵đ‫ࢤູٳ‬൬‫ؿބ‬ෂਆ۱ֆჭb൬‫ؿ‬ൈॖၛ๙‫ ݖ‬CPU ֥ APB ࢤ१‫ބ‬ +DMA ਆᇕٚൔটࣉྛ‫؀‬ཿҠቔđDMA ٚൔᄝᅣࢫ 9.8 ᇏႵབྷ༥ࢺകb + +9.6.1 ‫ؿ‬ෂ RAM ଆॶ + +ཿඔऌႵਆᇕٚൔğDMA ٚൔ‫ ބ‬CPU ‫؀‬ཿb +ೂ‫ݔ‬൐ି SDIO ‫ؿ‬ෂđପહॖၛ๙‫ ݖ‬APB ሹཌࢤ१ࠇ DMA ٚൔࡼඔऌཿೆ֞‫ؿ‬ෂ֥ RAM ৚૫bఃᇏđAPB +֥ٚൔູ CPU ᆰࢤࡼඔऌཿೆ࠷թఖ EMAC_FIFOb + +9.6.2 ࢤ൬ RAM ଆॶ + +‫؀‬ඔऌႵਆᇕٚൔğDMA ٚൔ‫ ބ‬CPU ‫؀‬ཿb +֒ඔऌ๙ਫ਼ሰֆჭࢤ൬֞ඔऌൈđ‫ھ‬ሰඔऌ߶ཿೆࢤ൬֥ RAM ৚૫bᄝ‫؀‬౼؊ॖၛ๙‫ ݖ‬APB ሹཌࠇ DMA ֥ +ٚൔ‫؀‬ԛ٢ೆ RAM ᇏ֥ඔऌbఃᇏđAPB ֥ٚൔູ CPU ᆰࢤ‫؀‬౼࠷թఖ EMAC_FIFO ᇏ֥ᆴb + +9.7 ৽іߌࢲ‫ܒ‬ + +ૄ၂ቆ৽іႮਆ҆‫ٳ‬ቆӮğ৽іЧദ‫ބ‬ඔऌ bufferbૄ၂۱৽іᆷཟ၂۱ື၂֥ඔऌ buffer ‫ބ‬༯၂۱৽іb৽ +іߌࢲ‫ܒ‬ೂ๭ 9-7 ෮ൕb + +ুᶈྐ༏॓࠯ 177 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + ๭ 9­7. ৽іߌࢲ‫ܒ‬ + +9.8 ৽іࢲ‫ܒ‬ + +ૄ۱৽і֥ࢲ‫ܒ‬ೂ༯đૄ۱৽іႮ 4 ۱ word ቆӮđೂ๭ 9-8 ෮ൕbі 9-2aі 9-3aі 9-4aі 9-5 ູ৽і૭ +ඍb + + ๭ 9­8. ৽іࢲ‫ܒ‬ + +DES0 ֆჭЇ‫ݣ‬ਔ॥ᇅ‫ބ‬ሑ෿ྐ༏b + +໊ ଀ӫ і 9­2. DES0 ৽і૭ඍ + +31 OWN ૭ඍ + ֒ഡᇂൈđ‫໊ھ‬іૼ৽і݂ DMAC ෮Ⴕb֒‫໊ھ‬Ф + ᇗᇂđ‫໊ھ‬іૼ৽і݂ᇶࠏ෮ႵbDMAC ᄝປӮඔऌ + ԮൻުౢԢ‫໊ھ‬b + +ুᶈྐ༏॓࠯ 178 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + +໊ ଀ӫ ૭ඍ + ᆃུհ༂໊іૼਔव‫؀‬/ཿ֥ሑ෿b +30 CES (Card Error Summary) ᆃ္໊ུթᄝႿ RINTSTS ᆭᇏđCES ൞༯ਙ໊֥ࠇ + ᄎෘğ + + • EBEğࢲඏ໊հ༂ + • RTOğཙႋӑൈ + • RCRCğཙႋ CRC + • SBEğఏ൓໊հ༂ + • DRTOğ‫؀‬౼ඔऌӑൈ + • DCRCğႨႿࢤ൬֥ඔऌ࿖ߌ಺Ⴥ཮ဒ + • REğཙႋհ༂ + +29:6 Reserved Reserved + +5 ER (End of Ring) ᇂ ໊ ൈđ ‫ ໊ ھ‬і ൕ ৽ і ၘ ࣜ ֞ ղ ቋ ު ၂ ۱ ৽ іb + DMAC ْ߭֞৽і֥ࠎֹᆶđԷࡹ၂۱৽іߌb + +4 CH (Second Address Chained) ᇂ໊ൈđ‫໊ھ‬іൕ৽іֻ֥‫ؽ‬۱ֹᆶ൞༯၂۱৽іֹ + ᆶbᇂ໊‫໊ھ‬ൈđBS2 (DES1[25:13]) ႋ‫݂׻ھ‬ਬb + + ᇂ໊ൈđ‫໊ھ‬іൕ‫৽ھ‬іЇ‫ݣ‬ਔඔऌֻ֥၂ߏԊ౵b + +3 FD (First Descriptor) ೏ֻ၂۱ߏԊ౵֥նཬູ 0đᄵ༯၂۱৽іЇ‫ݣ‬ඔऌ + + ֥ष൓b + + ‫໊ھ‬ა DMA Ԯൻ֥ቋު၂۱ඔऌॶཌྷܱbᇂ໊ൈđ + + ‫໊ھ‬іൕ๙‫৽ھݖ‬іᆷཟ֥ߏԊ౵൞ඔऌ֥ቋު၂ + +2 LD (Last Descriptor) ۱ߏԊ౵bᄝ‫৽ھ‬іປӮᆭުđഺჅሳࢫ࠹ඔູ 0b + ߐओ߅ඪđջႵФᇂ໊֥ LD ໊֥৽іປӮᆭުđഺ + + Ⴥሳࢫ࠹ඔႋູ 0b + + ᇂ໊ൈđູਔЌ਽ᄝ‫৽ھ‬іᆷཟ֥ߏԊ౵ᇏࢲඏ֥ඔ + +1 DIC (Disable Interrupt on Completion) ऌđ‫ࡼ໊ھ‬ቅᆸ DMAC ሑ෿࠷թఖ (IDSTS) ഈ TI/RI + + ໊֥ഡᇂb + +0 Reserved Reserved + +DES1 ჭ෍Ї‫ݣ‬ਔߏԊ౵նཬb + + і 9­3. DES1 + +໊ ଀ӫ ૭ඍ +31:26 Reserved Reserved +25:13 Reserved Reserved + ᆃ໊ུіൕඔऌߏԊ౵ሳࢫնཬbߏԊ౵նཬсྶ൞ +12:0 BS1čBuffer 1 նཬĎ 4 ֥Пඔbೂ‫ߏݔ‬Ԋ౵նཬ҂൞ 4 ֥Пඔđఃࢲ‫ݔ‬ᄠ + ໃ‫ק‬ၬb‫ھ‬౵҂ႋູ 0b + +DES2 ჭ෍Ї‫ݣ‬ਔᆷཟඔऌߏԊ౵ֹ֥ᆶᆷᆌb + +ুᶈྐ༏॓࠯ 179 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + і 9­4. DES2 + +໊ ଀ӫ ૭ඍ + +31:0 Buffer Address Pointer 1 ᆃ໊ུіൕඔऌߏԊ౵֥໾৘ֹᆶb + čඔऌߏԊ౵ֹᆶᆷᆌĎ + +ೂ‫֒ݔ‬భ֥৽і҂൞৽іࢲ‫ܒ‬ᇏ֥ቋު၂۱৽іđପહ DES3 ჭ෍߶Ї‫ݣ‬ᆷཟ༯၂۱৽іֹ֥ᆶᆷᆌb + + і 9­5. DES3 + +໊ ଀ӫ ૭ඍ + + ೂ‫ݔ‬ᇂֻ໊‫ؽ‬۱ֹᆶ৽ሳࢫ (DES0[4])đᄵ‫߶໊ھ‬Ї‫ݣ‬ + +31:0 Next Descriptor Address ՎֹᆶЇ‫ݣ‬ᆷཟ༯၂۱৽іթᄝ֥໾৘ଽթ֥ᆷᆌb + + č༯၂۱৽іֹᆶĎ ೂ‫ݔ‬ᆃ҂൞ቋު၂۱৽іđᄵ༯၂۱৽іֹᆶᆷᆌс + + ྶડቀ DES3[1:0] Ģ 0b + +9.9 Ԛ൓߄ + +9.9.1 DMAC Ԛ൓߄ + +DMAC Ԛ൓߄ᄝၛ༯౦ঃԛགྷğ + + 1. ཟ DMAC Bus Mode Register (BMOD_REG) টഡᇂᇶࠏሹཌ٠໙ҕඔb + + 2. ཟ DMAC Interrupt Enable Register (IDINTEN) ཿೆඔऌট௠з҂сေ֥ᇏ؎ো྘b + + 3. ೈࡱ౺‫׮‬ఖԷࡹԮൻ৽іਙіࠇᆀࢤ൬৽іਙіbಖުཿೆ DMAC ৽іਙіࠎᆶ࠷թఖ (BDADDR)đູ + DMAC ิ‫܂‬ਙі֥ఏ൓ֹᆶb + + 4. DMAC ႄౣӇ൫Ֆ৽іਙіࠆ౼৽іb + +9.9.2 DMAC ඔऌ‫ؿ‬ෂԚ൓߄ + +൐Ⴈ DMAC ‫ؿ‬ෂႋ቎࿖ၛ༯஥ᇂğ + + 1. ೈࡱഡᇂႨႿ‫ؿ‬ෂ֥ჭ෍ (DES0-DES3)đഡᇂ OWN ໊ (DES0[31])đѩሙСਔඔऌߏԊ౵b + + 2. ೈࡱᄝ BIU ᇏ֥ CMD ࠷թఖᇏ஥ᇂཿඔऌଁ਷b + + 3. ೈࡱߎࡼഡᇂ෮ླ֥‫ؿ‬ෂᚐᆴնཬčࠧ FIFOTH ࠷թఖᇏ֥ TX_WMARK ሳ‫؍‬Ďb + + 4. DMAC ႄౣ‫؀‬౼৽іѩ࡟Ұ OWN ໊bೂ‫ ݔ‬OWN ໊ໃᇂ໊đᄵіૼೈࡱႚႵ৽іbᄝᆃᇕ౦ঃ༯đ + DMAC ‫ܫ‬ఏđѩᄝ IDSTS ࠷թఖᇏӁള Descriptor Unable ᇏ؎bՎൈđᇶࠏླေ๙‫ࡼݖ‬಩‫ޅ‬ᆴཿೆ + PLDMND_REG ট൤٢ DMACb + + 5. ಖުೈࡱ֩ր Command Done ໊đೂ‫ݔ‬ીႵհ༂Ֆ BIU БԛđᄵіૼॖၛປӮ‫ؿ‬ෂb + + 6. ಖު DMAC ႄౣ֩րটሱႿ BIU ֥ DMA ࢤ१౨౰ (dw_dma_req)b‫ھ‬౨౰ࡼࠎႿ஥ᇂ֥‫ؿ‬ෂᚐᆴളӮb + ؓႿ൐Ⴈ๬‫طؿ‬҂ି٠໙֥ቋު၂۱ሳࢫđᄵᄝ AHB ᇶࢤ१ഈᆳྛֆՑ‫ؿ‬ෂb + + 7. DMAC Ֆೈࡱଽթ֥ඔऌߏԊ౵‫؀‬౼‫ؿ‬ෂඔऌđѩ๙‫ ݖ‬FIFO ࡼఃԮೆवᇏb + + 8. ֒ඔऌॴᄀ‫؟‬۱৽іൈđDMAC ࡼࠆ౼༯၂۱৽іđѩ࠿࿃൐Ⴈ༯၂۱৽іؓఃࣉྛҠቔbቋު၂໊৽і + ໊іૼඔऌ൞‫ॴڎ‬ᄀ‫؟‬۱৽іb + +ুᶈྐ༏॓࠯ 180 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + 9. ֒ඔऌ‫ؿ‬ෂປӮൈđ๙‫ݖ‬ഡᇂ‫ؿ‬ෂᇏ؎ট۷ྍ IDSTS ࠷թఖᇏ֥ሑ෿ྐ༏bਸ਼ຓđOWN ໊Ⴎ DMAC ๙ + ‫ ؓݖ‬DES0 ᆳྛཿҠቔটౢਬb + +9.9.3 DMAC ඔऌࢤ൬Ԛ൓߄ + +൐Ⴈ DMAC ࢤ൬ႋ቎࿖ၛ༯஥ᇂğ + 1. ೈࡱູࢤ൬ඔऌࡹ৫ჭ෍ (DES0 - DES3)đഡᇂ OWN ໊ (DES0[31])b + 2. ೈࡱ๙‫ ݖ‬BIU ஥ᇂଁ਷࠷թఖᇏູ‫؀‬ඔऌଁ਷b + 3. ೈࡱഡᇂ෮ླ֥ࢤ൬ᚐᆴčFIFOTH ࠷թఖᇏ֥ RX_WMARK ሳ‫؍‬Ďb + 4. DMAC ႄౣ‫؀‬౼৽іѩ࡟Ұ OWN ໊bೂ‫ ݔ‬OWN ໊ໃഡᇂđᄵіૼೈࡱႚႵ৽іbᄝᆃᇕ౦ঃ༯đ + DMAC ‫ܫ‬ఏđѩᄝ IDSTS ࠷թఖᇏӁള Descriptor Unable ᇏ؎bՎൈđೈࡱླေ๙‫ࡼݖ‬಩‫ޅ‬ᆴཿೆ + PLDMND_REG ট൤٢ DMACb + 5. ಖުೈࡱ֩ր Command Done ໊đೂ‫ݔ‬ીႵհ༂Ֆ BIU БԛđᄵіૼॖၛປӮࢤ൬b + 6. DMAC ႄౣགྷᄝࡼ֩րটሱႿ BIU ֥ DMA ࢤ१౨౰ (dw_dma_req)b‫ھ‬౨౰ࡼࠎႿ஥ᇂ֥‫ؿ‬ෂᚐᆴളӮb + ؓႿ൐Ⴈ burst ‫ط‬҂ି٠໙֥ቋު၂۱ሳࢫđᄵᄝ AHB ഈᆳྛֆՑԮൻb + 7. DMAC ๙‫ ݖ‬FIFO ‫؀‬౼ඔऌđѩԮൻᇀೈࡱଽթb + 8. ֒ඔऌॴᄀ‫؟‬۱৽іൈđDMAC ࡼࠆ౼༯၂۱৽іđѩ࠿࿃൐Ⴈ༯၂۱৽іؓఃࣉྛҠቔbቋު၂໊৽і + ໊іૼඔऌ൞‫ॴڎ‬ᄀ‫؟‬۱৽іb + 9. ֒ඔऌԮൻປӮൈđ๙‫ݖ‬ഡᇂ‫ؿ‬ෂᇏ؎ট۷ྍ IDSTS ࠷թఖᇏ֥ሑ෿ྐ༏bਸ਼ຓđOWN ໊Ⴎ DMAC ๙ + ‫ ؓݖ‬DES0 ᆳྛཿҠቔটౢਬb + +9.10 ൈᇒཌྷ໊࿊ᄴ + +ೂ‫ݔ‬ൻೆྐ‫ࠇݼ‬ൻԛྐ‫֥ݼ‬ҐဢႵൈ྽໙ีđႨ޼ॖၛҕᅶ༯๭‫ڿ‬эൈᇒཌྷ໊b + +ুᶈྐ༏॓࠯ ๭ 9­9. ൈᇒཌྷ໊࿊ᄴ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + + 181 + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + +Ⴕܱൈᇒཌྷ໊࿊ᄴ࠷թఖ CLK_EDGE_SEL ֥ඪૼđ౨࡮࠷թఖᅣࢫb + +9.11 ᇏ؎ + +ᇏ؎ॖၛ๙‫ݖ‬۲ᇕ౦ঃӁളbIDSTS ࠷թఖЇ‫ݣ‬ਔॖି֝ᇁᇏ؎֥෮Ⴕ໊bIDINTEN ࠷թఖЇ‫ݣ‬ਔ၂۱ൡႨႿ +෮Ⴕି֝ᇁᇏ؎౦ঃ֥൐ି໊b + +IDSTS ࠷թఖᇏႵਆቆᇏ؎߸ሹiᆞӈᇏ؎߸ሹ bit8 NIS ‫ބ‬ၳӈᇏ؎߸ሹ bit9 AISbࡼ 1 ཿೆཌྷႋ໊֥đॖၛ +ౢԢᇏ؎b֒ଖቆᇏ֥෮Ⴕ൐ିᇏ؎‫׻‬ФౢԢđཌྷႋ֥߸ሹ໊ࡼФౢਬb֒ਆቆ֥߸ሹ໊‫׻‬Фౢਬđᇏ؎ྐ‫ݼ‬ +dmac_intr_o ࡼ౼ཨb + +ᇏ؎҂ஆ྽đೂ‫ݔ‬ᇏ؎ᄝ౺‫׮‬ӱ྽ཙႋᆭభ‫ؿ‬ളđᄵ҂߶Ӂളః෰ᇏ؎b২ೂđࢤ൬ᇏ؎ IDSTS [1] іൕ၂۱ࠇ +‫؟‬۱ඔऌၘԮൻ֞ᇶࠏߏԊ౵b + +‫؟‬۱൙ࡱ๝ൈᆺ߶Ӂള၂۱ᇏ؎b౺‫׮‬ӱ྽сྶೡ૭ IDSTS ࠷թఖটҰᅳ֝ᇁᇏ؎֥ჰၹb + +9.12 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + ॥ᇅ࠷թఖ 0x0000 R/W + ଀ӫ ൈᇒ‫ٳ‬௔஥ᇂ࠷թఖ 0x0008 R/W + CTRL_REG ൈᇒჷ࿊ᄴ࠷թఖ 0x000C R/W + CLKDIV_REG ൈᇒ൐ି࠷թఖ 0x0010 R/W + CLKSRC_REG ‫؀‬౼ඔऌ‫ބ‬ཙႋӑൈ஥ᇂ࠷թఖ 0x0014 R/W + CLKENA_REG वሹཌॺ؇஥ᇂ࠷թఖ 0x0018 R/W + TMOUT_REG वඔऌॶնཬ஥ᇂ࠷թఖ 0x001C R/W + CTYPE_REG ඔऌԮൻӉ؇஥ᇂ࠷թఖ 0x0020 R/W + BLKSIZ_REG SDIO ᇏ؎௠з࠷թఖ 0x0024 R/W + BYTCNT_REG ଁ਷ҕඔඔऌ࠷թఖ 0x0028 R/W + INTMASK_REG ଁ਷‫ބ‬ఓ‫׮‬஥ᇂ࠷թఖ 0x002C R/W + CMDARG_REG ཙႋඔऌ࠷թఖ 0x0030 RO + CMD_REG Ӊཙႋඔऌ࠷թఖ 0x0034 RO + RESP0_REG Ӊཙႋඔऌ࠷թఖ 0x0038 RO + RESP1_REG Ӊཙႋඔऌ࠷թఖ 0x003C RO + RESP2_REG ௠зᇏ؎ሑ෿࠷թఖ 0x0040 RO + RESP3_REG ჰ൓ᇏ؎ሑ෿࠷թఖ 0x0044 R/W + MINTSTS_REG SD/MMC ሑ෿࠷թఖ 0x0048 RO + RINTSTS_REG FIFO ஥ᇂ࠷թఖ 0x004C R/W + STATUS_REG व࡟ҩ࠷թఖ 0x0050 RO + FIFOTH_REG वཿЌ޹ (WP) ሑ෿࠷թఖ 0x0054 RO + CDETECT_REG Ԯൻሳࢫ࠹ඔ࠷թఖ 0x005C RO + WRTPRT_REG Ԯൻሳࢫ࠹ඔ࠷թఖ 0x0060 RO + TCBCNT_REG ஥ᇂಀ‫ݖ׮׵‬ੲൈࡗ 0x0064 R/W + TBBCNT_REG Ⴈ޼ IDčᄠթఖĎ࠷թఖ 0x0068 R/W + DEBNCE_REG व‫࠷໊گ‬թఖ 0x0078 R/W + USRID_REG burst ଆൔԮൻ஥ᇂ࠷թఖ 0x0080 R/W + RST_N_REG ੽࿘ླ౰஥ᇂ࠷թఖ 0x0084 WO + BMOD_REG ૭ඍ‫ֹࠎژ‬ᆶ࠷թఖ 0x0088 R/W + PLDMND_REG + DBADDR_REG + +ুᶈྐ༏॓࠯ 182 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ ૭ඍ ֹᆶ ٠໙ + IDMAC ሑ෿࠷թఖ 0x008C R/W + ଀ӫ IDMAC ᇏ؎൐ି࠷թఖ 0x0090 R/W + IDSTS_REG Host ૭ඍ‫ֹژ‬ᆶᆷᆌ 0x0094 RO + IDINTEN_REG Host buffer ֹᆶᆷᆌ࠷թఖ 0x0098 RO + DSCADDR_REG ൈᇒཌྷ໊࿊ᄴ࠷թఖ 0x0800 R/W + BUFADDR_REG + CLK_EDGE_SEL + +9.13 ࠷թఖ + +SD/MMC ࠷թఖ๙‫ ݖ‬CPU ֥ APB ሹཌ٠໙b + +ুᶈྐ༏॓࠯ 183 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.1. CTRL_REG (0x0000) + + (reserved) (reserved) (reserved) CEATAS_EDNEDVS_IEACNUEDT_AIO_NBC_TOSCETRSRSOTDRE_PUNR_PDCETRA_C_EIDRSSA_QDTDDA_(_ArTReWTUEsASAeSrIPvTINeOTdN_) SE(ENreAsBerLvDEeMd)A_FRIFEOS_ECRTOESNETTROLLER_RESET + 0x00 +31 25 24 23 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0x00 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + CEATA_DEVICE_INTERRUPT_STATUS ೈࡱႋᄝ CE-ATA ഡСഈ‫ࠇ໊گ׈‬ః෰‫ު໊گ‬ཿՎ໊bCE- + ATA ഡС֥ᇏ؎๙ӈФ࣌ି (nIEN = 1)bೂ‫ݔ‬ᇶࠏ൐ିᇏ؎đᄵೈࡱႋࡼՎ໊ᇂູ 1bč‫؀‬/ཿĎ + + SEND_AUTO_STOP_CCSD ൓ᇔࡼ send_auto_stop_ccsd ‫ ބ‬send_ccsd ၂ఏᇂ໊đ҂ି‫ٳ‬षֆ‫׿‬ + ᇂ໊bᇂ໊ൈđSD/MMC ሱ‫ؿ׮‬ෂଽ҆ളӮ֥ STOP ᆷ਷ (CMD12) ۳ CE-ATA ഡСb‫ؿ‬ෂ STOP + ᆷ਷ުđRINTSTS ৚֥ Auto Command Done (ACD) ໊Фᇂູ 1đೂ‫ ݔ‬ACD ᇏ؎ીႵ௠зđᄵ + ႨႿᇶࠏ֥ᇏ؎ࡼ߶ളӮb‫ؿ‬ෂ Command Completion Signal Disable (CCSD) ުđSD/MMC ሱ + ‫׮‬ౢਬ send_auto_stop_ccsd ໊bč‫؀‬ĔཿĎ + + SEND_CCSD ᇂ໊ൈđSD/MMC ‫ؿ‬ෂ CCSD ۳ CE-ATA ഡСbᆺႵᄝ֒భᆷ਷֩ր CCSčࠧ + RW_BLKĎѩ౏ CE-ATA ഡС֥ᇏ؎൐ିൈೈࡱҌ߶ࡼՎ໊ᇂ໊b၂֊ CCSD ଆൔ‫ؿ‬ෂ۳ഡСđ + SD/MMC ࣼ߶ሱ‫׮‬ౢਬ send_ccsd ໊bೂ‫ ݔ‬ACD ᇏ؎ીႵ௠зđᄵ࠷թఖ RINTSTS ৚֥ Com- + mand Done (CD) ໊߶Фᇂູ 1đ౏ᇶࠏ֥ᇏ؎ࡼ߶ളӮbඪૼğ၂֊ SEND_CCSD Фᇂ໊đླ + ေਆ۱वൈᇒᇛ௹ট౺‫ ׮‬CMD ཌഈ֥ CCSDbၹՎđࠧ൐ഡСၘࣜ‫ؿ‬ෂ CCS ྐ‫ݼ‬đᄝшࢸ่ + ࡱଽ CCSD ྐ‫ݼ‬ॖି߶‫ؿ‬ෂ۳ CE-ATA ഡСbč‫؀‬ĔཿĎ + + ABORT_READ_DATA ᄝ‫؀‬Ҡቔ௹ࡗđsuspend ᆷ਷‫ؿ‬ෂުđೈࡱ߶੽࿘वѩᅳԛ suspend ൙ࡱ൞ + Ֆ൉હൈީष൓֥b၂֊ suspend ൙ࡱष൓đೈࡱ߶‫໊گ‬ඔऌሑ෿ࠏđՎൈሑ෿ࠏᆞᄝ֩ր༯ + ၂۱ඔऌॶb֒ඔऌሑ෿ࠏ‫༽ॢູ໊گ‬ሑ෿ൈđՎ໊ሱ‫׮‬ౢਬbč‫؀‬ĔཿĎ + + SEND_IRQ_RESPONSE ཙႋ‫ؿ‬ෂުՎ໊ሱ‫׮‬ౢਬbູਔ֩ր MMC व‫ؿ‬ෂ֥ᇏ؎đᇶࠏ‫ؿ‬ෂ + CMD40đಖު֩ր MMC व֥ᇏ؎ཙႋb๝ൈđೂ‫ݔ‬ᇶࠏམေ SD/MMC ๼ԛ֩րᇏ؎֥ሑ෿đ + ᄵ߶ࡼՎ໊ᇂ 1đՎൈ SD/MMC ᆷ਷ሑ෿ࠏ‫ؿ‬ෂ CMD40 ཙႋѩْ߭ॢ༽ሑ෿bč‫؀‬ĔཿĎ + + READ_WAIT ‫ؿ‬ෂ‫؀‬Ҡቔ֩ր۳ SDIO वbč‫؀‬Ĕཿ + + INT_ENABLE ಆअᇏ؎൐ି/࣌ି໊b0ğ࣌ିĠ1ğ൐ିbč‫؀‬ĔཿĎ + + DMA_RESET ေ‫ ໊گ‬DMA ࢤ१đೈࡱႋࡼՎ໊ᇂູ 1bਆ۱ AHB ൈᇒުՎ໊ሱ‫׮‬ౢਬbč‫؀‬ĔཿĎ + + ࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 184 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.1. CTRL_REG (0x0000) + + ࠿ഈ၂်࠷թఖ૭ඍb + FIFO_RESET ေ‫ ໊گ‬FIFOđೈࡱႋࡼՎ໊ᇂູ 1b‫໊گ‬Ҡቔࢲඏުሱ‫׮‬ౢਬbඪૼğFIFO_RESET ౢ + + ਬުđᄜ‫ݖ‬ਆ۱༢๤ൈᇒᇛ௹‫ބ‬๝҄࿼Ӿčਆ۱वൈᇒᇛ௹ĎđFIFO ᆷᆌࡼ߶๼ԛ‫໊گ‬bč‫؀‬/ཿĎ + CONTROLLER_RESET ေ‫໊گ‬॥ᇅఖđೈࡱႋࡼՎ໊ᇂູ 1bਆ۱ AHB ൈᇒᇛ௹‫ބ‬ਆ۱ cclk_in ൈ + + ᇒᇛ௹ުՎ໊ሱ‫׮‬ౢਬbč‫؀‬ĔཿĎ + + Register 9.2. CLKDIV_REG (0x0008) + + CLK_DIVIDER3 CLK_DIVIDER2 CLK_DIVIDER1 CLK_DIVIDER0 + 0x000 +31 24 23 16 15 87 0 + + 0x000 0x000 0x000 Reset + + CLK_DIVIDER3 ൈᇒ divider-3 ֥ᆴbൈᇒ‫ٳ‬௔༢ඔູ 2*nđn=0 கਫ਼‫ٳ‬௔ఖč‫ٳ‬௔༢ඔູ 1Ďb২ + ೂđᆴູ 1 սі‫ٳ‬௔༢ඔູ 2*1 = 2đᆴູ 0xFF սі‫ٳ‬௔༢ඔູ 2*255 = 510đၛՎো๷bᄝ + MMC-Ver3.3-only ଆൔ༯đႮႿᆺᆦӻ၂۱ൈᇒ‫ٳ‬௔ఖđ෮ၛᆃུбห҂ᆳྛbč‫؀‬ĔཿĎ + + CLK_DIVIDER2 ൈᇒ divider-2 ֥ᆴbః෰๝ഈbč‫؀‬ĔཿĎ + + CLK_DIVIDER1 ൈᇒ divider-1 ֥ᆴbః෰๝ഈbč‫؀‬ĔཿĎ + + CLK_DIVIDER0 ൈᇒ divider-0 ֥ᆴbః෰๝ഈbč‫؀‬ĔཿĎ + + Register 9.3. CLKSRC_REG (0x000C) + + (reserved) CLKSRC_REG + +31 43 0 + + 0x000000 0x0 Reset + + CLKSRC_REG ൈᇒ‫ٳ‬௔ჷॖၛᆦӻ 2 ۱ SD वbૄ۱व‫ٳ‬஥Ⴕਆ۱бหb২ೂđbit[1:0] ‫ٳ‬஥۳व + 0đbit[3:2] ‫ٳ‬஥۳व 1bव 0 ۴ऌбหᆴࡼൈᇒ‫ٳ‬௔ఖ [0:3] ֥ൻԛྐ‫ݼ‬Ԯൻ۳ cclk_out[1:0] ܵ + ࢖b + 00ğൈᇒ‫ٳ‬௔ఖ 0Ġ + 01ğൈᇒ‫ٳ‬௔ఖ 1Ġ + 10ğൈᇒ‫ٳ‬௔ఖ 2Ġ + 11ğൈᇒ‫ٳ‬௔ఖ 3b + ᄝ MMC-Ver3.3-only ଆൔ༯đᆺᆦӻ၂۱ൈᇒ‫ٳ‬௔ఖbcclk_out ൈᇒটሱൈᇒ‫ٳ‬௔ఖ 0đѩ౏Վ + ࠷թఖ҂ᆳྛbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 185 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.4. CLKENA_REG (0x0010) + + (reserved) CCLK_ENABEL + +31 21 0 + + 0x00000 0x00000 Reset + + CCLK_ENABEL ൈᇒ൐ି॥ᇅॖᆦӻ 2 ۱ SD वൈᇒ‫ބ‬၂۱ MMC वൈᇒb + 0ğൈᇒ࣌ିĠ + 1ğൈᇒ൐ିb + ᄝ MMC-Ver3.3-only ଆൔ༯đႮႿᆺႵ၂۱ cclk_outđၹՎᆺ൐Ⴈ cclk_enable[0]bč‫؀‬ĔཿĎ + + Register 9.5. TMOUT_REG (0x0014) + + DATA_TIMEOUT RESPONSE_TIMEOUT + +31 87 0 + + 0x0FFFFFF 0x040 Reset + + DATA_TIMEOUT Վ໊ႨႿഡᇂवඔऌ‫؀‬౼ӑൈ֥ᆴđߎॖၛႨটഡᇂᇶࠏӑൈ֥‫ק‬ൈఖ֥ᆴbᆺ + Ⴕ֒वൈᇒ๔ᆸުӑൈ࠹ඔఖҌष൓ఓ‫׮‬bՎ໊֥ᆴၛवൻԛൈᇒඔটіൕđࠧФ࿊౼व֥ + cclk_outb + ඪૼğೂ‫ݔ‬ӑൈᆴ൞ 100 ms ቐႷđᄵႋ‫ھ‬൐Ⴈೈࡱ‫ק‬ൈఖbᆃᇕ౦ঃ༯đ‫؀‬ඔऌӑൈᇏ؎ႋ‫ھ‬ + Ф࣌ିbč‫؀‬ĔཿĎ + + RESPONSE_TIMEOUT Վ໊ႨႿഡᇂཙႋӑൈ֥ᆴđၛवൻԛൈᇒඔটіൕđࠧ cclk_outbč‫؀‬Ĕ + ཿĎ + +ুᶈྐ༏॓࠯ 186 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.6. CTYPE_REG (0x0018) + + (reserved) CARD_WIDTH8 (reserved) CARD_WIDTH4 + +31 18 17 16 15 21 0 + + 0x00000 0x00000 0x00000 0x00000 Reset + + CARD_WIDTH8 ૄ۱व၂۱бหđіૼव൞‫ڎ‬ԩႿ 8-bit ଆൔb + 0ğ٤ 8-bit ଆൔĠ + 1ğ8-bit ଆൔb + Bit[17:16] ‫ٳ‬љؓႋव [1:0]bč‫؀‬ĔཿĎ + + CARD_WIDTH4 ૄ۱व၂۱бหđіૼवԩႿ 1-bit ଆൔߎ൞ 4-bit ଆൔb + 0ğ1-bit ଆൔĠ + 1ğ4-bit ଆൔb + Bit[1:0] ‫ٳ‬љؓႋव [1:0]bᆺႵ NUM_CARDS*2 ۱бหФᆳྛbč‫؀‬ĔཿĎ + + Register 9.7. BLKSIZ_REG (0x001C) + + (reserved) BLOCK_SIZE + 0x00200 +31 16 15 0 + +0000000000000000 Reset + + BLOCK_SIZE ଆॶնཬbč‫؀‬ĔཿĎ + + Register 9.8. BYTCNT_REG (0x0020) + +31 0 + + 0x000000200 Reset + + BYTCNT_REG іૼԮൻ֥ሳࢫඔbؓႿଆॶ֥Ԯൻđᆴႋູଆॶնཬ֥ᆜඔПඔbؓႿໃ‫ק‬ၬሳ + ࢫӉ؇֥ඔऌԮൻđሳࢫ࠹ඔႋ‫ھ‬ഡᇂູ 0b֒ሳࢫ࠹ඔູ 0 ൈđᇶࠏႋ֒ૼಒ‫ؿ‬ෂ๔ᆸĔᇔᆸ + ᆷ਷ট๔ᆸඔऌԮൻbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 187 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.9. INTMASK_REG (0x0024) + + (reserved) SDIO_INT_MASK INT_MASK + +31 18 17 16 15 0 + + 0x00000 0x00000 0x00000 Reset + + SDIO_INT_MASK SDIO ᇏ؎֥௠з໊đૄ۱व၂۱бหbBit[17:16] ‫ٳ‬љؓႋव [1:0]b֒Ф௠зൈđ + SDIO ᇏ؎֥࡟ҩФ࣌ିbo0p௠зᇏ؎đo1p൐ିᇏ؎bᄝ MMC-Ver3.3-only ଆൔ༯đᆃུб + ห൓ᇔູ 0bč‫؀‬ĔཿĎ + + INT_MASK ᆃུбหႨႿ௠з҂མေ֥ᇏ؎bo0p௠зᇏ؎đo1p൐ିᇏ؎bč‫؀‬ĔཿĎ + Bit 15 (EBE): ࢲඏ໊հ༂đ‫؀‬Ĕཿč໭ CRCĎĠ + Bit 14 (ACD): ሱ‫׮‬ᆷ਷ࢲඏĠ + Bit 13 (SBE/BCI): ఓ‫ ׮‬Bit Error/Busy Clear ᇏ؎Ġ + Bit 12 (HLE): ႗ࡱ෭‫ק‬ཿೆհ༂ + Bit 11 (FRUN): FIFO underrun/overrun հ༂Ġ + Bit 10 (HTO): ᇶࠏแԉඔऌӑൈĔ Volt_switch_intĠ + Bit 9 (DRTO): ඔऌ‫؀‬౼ӑൈĠ + Bit 8 (RTO): ཙႋӑൈĠ + Bit 7 (DCRC): ඔऌ CRC հ༂Ġ + Bit 6 (RCRC): ཙႋ CRC հ༂Ġ + Bit 5 (RXDR): ࢤ൬ FIFO ඔऌ౨౰Ġ + Bit 4 (TXDR): ‫ؿ‬ෂ FIFO ඔऌ౨౰Ġ + Bit 3 (DTO): ඔऌԮൻࢲඏĠ + Bit 2 (CD): ᆷ਷ᆳྛປиĠ + Bit 1 (RE): ཙႋհ༂Ġ + Bit 0 (CD): व࡟ҩb + + Register 9.10. CMDARG_REG (0x0028) 0 + +31 Reset + + 0x000000000 + + CMDARG_REG Ԯ‫־‬۳व֥ଁ਷ҕඔbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 188 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.11. CMD_REG (0x002C) + +START(re_CseMrvUDeSdE) _H(reOsLeErv(reeds)erv(reeds)erv(reeds)erv(reeds)ervCeCdS) _REEXAPDEUC_CPTDEEDAATTAE__DCELVOICCKEC_ARREDG_ISNTUEMRBS_EORSNELYNDS_TINOITPIW_AALABIIZTOA_SRTPEITRON_VNDCDT_MARADTAUANT_ROSCEF_OAESMRDTDPO_/WMALPTEROATIDT_CEEEEHXEPCERKCE_TSREPEDROSENPSOSPENO_SLNEES_NECG_RETCXHPECCTMD_INDEX + +31 30 29 28 27 26 25 24 23 22 21 20 16 15 14 13 12 11 10 9 8 7 6 5 0 + +00100000000 0x00 0000000000 0x00 Reset + +START_CMD ष൓‫ؿ‬ෂଁ਷b၂֊ CIU ཙႋଁ਷đՎ໊ሱ‫׮‬ౢਬb֒Վ໊ᇂູ 1 ൈđᇶࠏ҂ႋӇ൫ + ཿ಩‫ଁޅ‬਷࠷թఖbೂ‫ݔ‬Ӈ൫ཿ࠷թఖđჰ൓ᇏ؎࠷թఖ֥႗ࡱ෭‫ק‬հ༂ࡼ߶Фᇂູ 1b၂֊ଁ + ਷Ф‫ؿ‬ෂѩ౏ࢤ൬֞ SD_MMC_CEATA व֥ཙႋđᄵჰ൓ᇏ؎࠷թఖ֥ Command Done бหࡼ + ߶Фᇂູ 1bč‫؀‬ĔཿĎ + +USE_HOLE Use Hold ࠷թఖbč‫؀‬ĔཿĎ + 0ğ‫ؿ‬ෂ۳व֥ CMD ‫ ބ‬DATA கਫ਼ Hold ࠷թఖĠ + 1ğ‫ؿ‬ෂ۳व֥ CMD ‫ ބ‬DATA ࣜ‫ ݖ‬Hold ࠷թఖb + +CCS_EXPECTED ყ௹ଁ਷ປӮྐ‫( ݼ‬CCS) ֥஥ᇂbč‫؀‬ĔཿĎ + 0ğCE-ATA ഡС֥ᇏ؎҂൐ିčATA ॥ᇅ࠷թఖᇏ nIEN = 1ĎĠࠇᆀᆷ਷҂֩րഡС֥ CCS ྐ + ‫ݼ‬b + 1ğCE-ATA ഡС֥ᇏ؎൐ି (nIEN = 0)đѩ౏ RW_BLK ᆷ਷֩ր CE-ATA ഡС֥ CCS ྐ‫ݼ‬b + ೂ‫ݔ‬ᆷ਷֩ր CE-ATA ഡС֥ CCS ྐ‫ݼ‬đೈࡱႋ‫ࡼھ‬Վ໊ᇂູ 1bSD/MMC ᇂ໊ RINTSTS ࠷թ + ఖ৚֥ Data Transfer Over (DTO) ໊ѩ౏ೂ‫ ݔ‬DTO ᇏ؎ીႵФ௠зđ߶Ӂളؓᇶࠏ֥ᇏ؎b + +READ_CEATA_DEVICE ‫؀‬Ҡቔѓᆽ໊bč‫؀‬ĔཿĎ + 0ğᇶࠏ҂ࣉྛؓႿ CE-ATA ഡС֥‫؀‬Ҡቔ (RW_REG ࠇ RW_BLK)Ġ + 1ğᇶࠏࣉྛؓႿ CE-ATA ഡС֥‫؀‬Ҡቔ (RW_REG ࠇ RW_BLK)b + ೈࡱႋࡼՎ໊ᇂູ 1 টіૼ CE-ATA ഡСᆞᄝФ٠໙ႨႿ‫؀‬ԮൻbՎ໊ႨႿᄝᆳྛ CE-ATA ‫؀‬Ԯ + ൻൈ࣌ି‫؀‬ඔऌӑൈᆷൕbI/O Ԯൻ࿼Ӿ֥ቋնᆴᇀഒູ 10 ૰bSD/MMC ᄝ֩րটሱ CE-ATA + ഡС֥ඔऌൈ҂ႋᆷൕ‫؀‬౼ඔऌӑൈbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 189 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.12. CMD_REG (continued) (0x002C) + +START(re_CseMrvUDeSdE) _H(reOsLeErv(reeds)erv(reeds)erv(reeds)erv(reeds)ervCeCdS) _REEXAPDEUC_CPTDEEDAATTAE__DCELVOICCKEC_ARREDG_ISNTUEMRBS_EORSNELYNDS_TINOITPIW_AALABIIZTOA_SRTPEITRON_VNDCDT_MARADTAUANT_ROSCEF_OAESMRDTDPO_/WMALPTEROATIDT_CEEEEHXEPCERKCE_TSREPEDROSENPSOSPENO_SLNEES_NECG_RETCXHPECCTMD_INDEX + +31 30 29 28 27 26 25 24 23 22 21 20 16 15 14 13 12 11 10 9 8 7 6 5 0 + +00100000000 0x00 0000000000 0x00 Reset + +UPDATE_CLOCK_REGISTERS_ONLY (R/W) + 0ğᆞӈᆷ਷྽ਙĠ + 1ğ҂‫ؿ‬ෂᆷ਷đࣇ۷ྍൈᇒ࠷թఖ֥ᆴ֞वൈᇒთଽbၛ༯࠷թఖ֥ᆴФԮൻ֞वൈᇒთଽğ + CLKDIVaCLRSRC ‫ ބ‬CLKENAč‫ٳ‬௔aൈᇒჷ‫ބ‬ൈᇒ൐ିĎbᆃ൞ູਔ‫ڿ‬эൈᇒ௔ੱࠇ๔ᆸൈ + ᇒđ‫ط‬҂с‫ؿ‬ෂଁ਷۳वb + ᄝᆞӈᆷ਷྽ਙ༯đ֒ update_clock_registers_only = 0đၛ༯॥ᇅ࠷թఖՖ BIU Ԯൻ֞ CIUğ + CMDaCMDARGaTMOUTaCTYPEaBLKSIZ ‫ ބ‬BYTCNTbCIU ູྍ֥ᆷ਷྽ਙ൐Ⴈྍ֥࠷թ + ఖ֥ᆴb֒Վ໊ᇂູ 1 ൈđႮႿીႵᆷ਷Ф‫ؿ‬ෂ۳ SD_MMC_CEATA वđ෮ၛીႵ Command + Done ᇏ؎bč‫؀‬ĔཿĎ + +CARD_NUMBER ൐Ⴈᇏ֥व‫ݼ‬đіൕᆞᄝ٠໙֥व֥໾৘ҬҢщ‫ݼ‬bᄝ MMC-Ver3.3-only ଆൔ༯đ + ቋ‫؟‬ᆦӻ 2 ᅦवbᄝࣇ SD ଆൔ༯đᆦӻ 2 ᅦवbč‫؀‬ĔཿĎ + +SEND_INITIALIZATION č‫؀‬ĔཿĎ + 0ğᄝ‫ؿ‬ෂᆷ਷భ҂‫ؿ‬ෂԚ൓߄྽ਙč80 ۱ᇛ௹ĎĠ + 1ğᄝ‫ؿ‬ෂᆷ਷భ‫ؿ‬ෂԚ൓߄྽ਙb + ഈ‫ު׈‬đ‫ؿ‬ෂ಩‫ଁޅ‬਷֞वᆭభđсྶཟव‫ؿ‬ෂ 80 ۱ൈᇒࣉྛԚ൓߄bᄝཟव‫ؿ‬ෂֻ၂۱ଁ਷ + ൈႋ‫ࡼھ‬Վ໊ᇂູ 1đၛь॥ᇅఖᄝཟव‫ؿ‬ෂଁ਷ᆭభԚ൓߄ൈᇒb + +STOP_ABORT_CMD č‫؀‬ĔཿĎ + 0ğ๔ᆸࠇᇏᆸଁ਷đ๔ᆸଁ਷‫ބ‬ᇏᆸଁ਷‫׻‬҂߶๔ᆸ֒భ֥ඔऌԮൻbೂ‫ݔ‬ᇏᆸ‫ؿ‬ෂ֞֒భ࿊ + ᄴ֥‫ࠇݼିۿ‬҂ᄝඔऌԮൻଆൔđᄵ‫໊ھ‬ႋഡᇂູ 0Ġ + 1ğ๔ᆸࠇᇏᆸଁ਷đႨႿ๔ᆸ֒భ֥ඔऌԮൻb֒ष٢ൔყ‫ק‬ၬඔऌԮൻᆞᄝࣉྛൈđѩ౏ᇶ + ࠏ‫ؿ‬ԛ๔ᆸࠇᇏᆸଁ਷ၛ๔ᆸඔऌԮൻൈđႋࡼՎ໊ᇂູ 1đၛ൐ CIU ֥ଁ਷/ඔऌሑ෿ࠏॖၛ + ᆞಒْ߭֞ॢ༽ሑ෿b + +ুᶈྐ༏॓࠯ 190 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.13. CMD_REG (continued) (0x002C) + +START(re_CseMrvUDeSdE) _H(reOsLeErv(reeds)erv(reeds)erv(reeds)erv(reeds)ervCeCdS) _REEXAPDEUC_CPTDEEDAATTAE__DCELVOICCKEC_ARREDG_ISNTUEMRBS_EORSNELYNDS_TINOITPIW_AALABIIZTOA_SRTPEITRON_VNDCDT_MARADTAUANT_ROSCEF_OAESMRDTDPO_/WMALPTEROATIDT_CEEEEHXEPCERKCE_TSREPEDROSENPSOSPENO_SLNEES_NECG_RETCXHPECCTMD_INDEX + +31 30 29 28 27 26 25 24 23 22 21 20 16 15 14 13 12 11 10 9 8 7 6 5 0 + +00100000000 0x00 0000000000 0x00 Reset + +WAIT_PRVDATA_COMPLETE č‫؀‬ĔཿĎ + 0ğࠧ൐ၛభ֥ඔऌԮൻഉໃປӮđ္৫ࠧ‫ؿ‬ෂଁ਷Ġ + 1ğ֩րభ૫֥ඔऌԮൻປӮުᄜ‫ؿ‬ෂᆷ਷b + wait_prvdata_complete = 0 ࿊ཛ๙ӈႨটᄝඔऌԮൻൈ࿘໙व֥ሑ෿ࠇ๔ᆸ֒భ֥ඔऌԮൻb + card_number ႋ‫ھ‬აഈ၂۱ᆷ਷ཌྷ๝b + +SEND_AUTO_STOP č‫؀‬ĔཿĎ + 0ğᄝඔऌԮൻࢲඏൈ҂‫ؿ‬ෂ๔ᆸଁ਷Ġ + 1ğᄝඔऌԮෂࢲඏൈ‫ؿ‬ෂ๔ᆸଁ਷b + +TRANSFER_MODE č‫؀‬ĔཿĎ + 0ğଆॶඔऌԮൻᆷ਷Ġ + 1: ੀඔऌԮൻᆷ਷bೂ‫ݔ‬҂֩րඔऌᄵູ໭ܱཛb + +READ/WRITE č‫؀‬ĔཿĎ + 0ğ‫؀‬वĠ + 1ğཿवb + ೂ‫ݔ‬҂֩րඔऌᄵູ໭ܱཛb + +DATA_EXPECTED č‫؀‬ĔཿĎ + 0ğ҂֩րඔऌԮൻĠ + 1ğ֩րඔऌԮൻb + +CHECK_RESPONSE_CRC č‫؀‬ĔཿĎ + 0ğ҂࡟ҰĠ + 1ğ࡟Ұཙႋ CRCb + Ⴕུᆷ਷ཙႋ҂߶ْ߭Ⴕི֥ CRC ໊bೈࡱႋ࣌ିؓႿᆃུᆷ਷֥ CRC ࡟Ұၛь࣌ି॥ᇅఖ + ࣉྛ CRC ࡟Ұb + +RESPONSE_LENGTH č‫؀‬ĔཿĎ + 0ğ֩րव֥؋ཙႋĠ + 1ğ֩րव֥Ӊཙႋb + +RESPONSE_EXPECT č‫؀‬ĔཿĎ + 0ğ҂֩րव֥ཙႋĠ + 1ğ֩րव֥ཙႋb + +CMD_INDEX ᆷ਷ᆷඔbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 191 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ 0 + + Register 9.14. RESP0_REG (0x0030) Reset + + 31 0 + + 0x000000000 Reset + + RESP0_REG ཙႋ֥ bit[31:0]bčᆺ‫؀‬Ď 0 + + Register 9.15. RESP1_REG (0x0034) Reset + + 31 0 + + 0x000000000 Reset + + RESP1_REG Ӊཙႋ֥ bit[63:32]bčᆺ‫؀‬Ď + + Register 9.16. RESP2_REG (0x0038) + + 31 + + 0x000000000 + + RESP2_REG Ӊཙႋ֥ bit[95:64]bčᆺ‫؀‬Ď + + Register 9.17. RESP3_REG (0x003C) + + 31 + + 0x000000000 + + RESP3_REG Ӊཙႋ֥ bit[127:96]bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 192 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.18. MINTSTS_REG (0x0040) + + (reserved) SDIO_INTERRUPT_MSK INT_STATUS_MSK + +31 18 17 16 15 0 + + 0 0x0 0x00000 Reset + + SDIO_INTERRUPT_MSK SDIO ᇏ؎֥௠з໊đૄ۱व၂۱бหbBit[17:16] ‫ٳ‬љؓႋव 1 ‫ބ‬व 0b + ᆺႵؓႋ֥ sdio_int_mask ໊Фᇂູ 1 ൈđSDIO ᇏ؎Ҍ߶൐ିčᇂ໊௠з໊൐ିᇏ؎Ďbčᆺ‫؀‬Ď + + INT_STATUS_MSK ᆺႵ֒ᇏ؎௠з࠷թఖᇏ֥ؓႋ໊Фᇂູ 1 ൈđᇏ؎Ҍ߶൐ିbčᆺ‫؀‬Ď + Bit 15 (EBE): ࢲඏ໊հ༂đ‫؀‬Ĕཿč໭ CRCĎĠ + Bit 14 (ACD): ሱ‫׮‬ᆷ਷ࢲඏĠ + Bit 13 (SBE/BCI): ఓ‫ ׮‬Bit Error/Busy Clear ᇏ؎Ġ + Bit 12 (HLE): ႗ࡱ෭‫ק‬ཿೆհ༂ + Bit 11 (FRUN): FIFO underrun/overrun հ༂Ġ + Bit 10 (HTO): ᇶࠏแԉඔऌӑൈĠ + Bit 9 (DRTO): ඔऌ‫؀‬౼ӑൈĠ + Bit 8 (RTO): ཙႋӑൈĠ + Bit 7 (DCRC): ඔऌ CRC հ༂Ġ + Bit 6 (RCRC): ཙႋ CRC հ༂Ġ + Bit 5 (RXDR): ࢤ൬ FIFO ඔऌ౨౰Ġ + Bit 4 (TXDR): ‫ؿ‬ෂ FIFO ඔऌ౨౰Ġ + Bit 3 (DTO): ඔऌԮൻࢲඏĠ + Bit 2 (CD): ᆷ਷ᆳྛປиĠ + Bit 1 (RE): ཙႋհ༂Ġ + Bit 0 (CD): व࡟ҩb + +ুᶈྐ༏॓࠯ 193 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.19. RINTSTS_REG (0x0044) + + (reserved) SDIO_INTERRUPT_RAW INT_STATUS_RAW + +31 16 17 16 15 0 + + 0x00000 0x0 0x00000 + + Reset + + SDIO_INTERRUPT_RAW টሱ SDIO व֥ᇏ؎đ၂۱व၂۱ᇏ؎bBit[17:16] ‫ٳ‬љؓႋव 1 ‫ބ‬व 0b + ᇂ໊ଖбหࣼϜཌྷႋ֥ᇏ؎໊ౢਬđཿ 0 ໭ིbč‫؀‬ĔཿĎ + 0ğીႵটሱव֥ SDIO ᇏ؎Ġ + 1ğႵটሱव֥ SDIO ᇏ؎b + ᄝ MMC-Ver3.3-only ଆൔ༯đᆃུбห൓ᇔູ 0bᆃུᇏ؎໊൞ჰ൓֥ᇏ؎đ‫ط‬҂ܵᇏ؎௠зሑ + ෿bč‫؀‬ĔཿĎ + + INT_STATUS_RAW ᇂ໊ଖбหࣼϜཌྷႋ֥ᇏ؎໊ౢਬđཿ 0 ໭ིb໭ંᇏ؎௠зሑ෿ೂ‫ޅ‬đᆃུ + ᇏ؎໊‫߶׻‬Ф࠺੣b(R/W) + Bit 15 (EBE): ࢲඏ໊հ༂đ‫؀‬Ĕཿč໭ CRCĎĠ + Bit 14 (ACD): ሱ‫׮‬ᆷ਷ࢲඏĠ + Bit 13 (SBE/BCI): ఓ‫ ׮‬Bit Error/Busy Clear ᇏ؎Ġ + Bit 12 (HLE): ႗ࡱ෭‫ק‬ཿೆհ༂ + Bit 11 (FRUN): FIFO underrun/overrun հ༂Ġ + Bit 10 (HTO): ᇶࠏแԉඔऌӑൈĠ + Bit 9 (DRTO): ඔऌ‫؀‬౼ӑൈĠ + Bit 8 (RTO): ཙႋӑൈĠ + Bit 7 (DCRC): ඔऌ CRC հ༂Ġ + Bit 6 (RCRC): ཙႋ CRC հ༂Ġ + Bit 5 (RXDR): ࢤ൬ FIFO ඔऌ౨౰Ġ + Bit 4 (TXDR): ‫ؿ‬ෂ FIFO ඔऌ౨౰Ġ + Bit 3 (DTO): ඔऌԮൻࢲඏĠ + Bit 2 (CD): ᆷ਷ᆳྛປиĠ + Bit 1 (RE): ཙႋհ༂Ġ + Bit 0 (CD): व࡟ҩb + +ুᶈྐ༏॓࠯ 194 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.20. STATUS_REG (0x0048) + + (reserv(reeds)erved) FIFO_COUNT RESPONSE_INDEXDATA_DSATTAAT_DEBA_UTMASC_Y3_B_SUTSAYTCUOSMMAND_FFSIMFO__SFFTIUAFOTLEL_FSEIMFOP_TFTYIXF_OW_RATXE_WRMATAERRKMARK + 0x000 +31 30 29 17 16 11 10 9 8 7 43 2 1 0 + +00 0x00 111 0x01 0 1 1 0 Reset + +FIFO_COUNT FIFO ࠹ඔ໊đFIFO ᇏФแԉֹ֥ᆶ֥ඔਈbčᆺ‫؀‬Ď + +RESPONSE_INDEX భ၂۱ཙႋ֥ᆷඔđЇওଽ‫ؿނ‬ෂ֥಩‫ޅ‬ሱ‫׮‬๔ᆸ֥ཙႋbčᆺ‫؀‬Ď + +DATA_STATE_MC_BUSY ඔऌ‫ؿ‬ෂࠇࢤ൬ሑ෿ࠏફbčᆺ‫؀‬Ď + +DATA_BUSY ჰ൓࿊ᄴ֥ card_data[0] ֥౼ّϱbčᆺ‫؀‬Ď + 0ğवඔऌ҂ફĠ + 1ğवඔऌફb + +DATA_3_STATUS ჰ൓࿊ᄴ֥ card_data[3]đ࡟Ұव൞‫ڎ‬թᄝbčᆺ‫؀‬Ď + 0ğव҂թᄝĠ + 1ğवթᄝb + +COMMAND_FSM_STATES ᆷ਷ FSM ሑ෿bčᆺ‫؀‬Ď + 0: ॢ༽Ġ + 1: ‫ؿ‬ෂԚ൓྽ਙĠ + 2: ‫ؿ‬ෂᆷ਷ष൓໊Ġ + 3: ‫ؿ‬ෂᆷ਷‫ؿ‬ෂ໊Ġ + 4: ‫ؿ‬ෂᆷ਷ᆷඔ‫ބ‬ҕඔĠ + 5: ‫ؿ‬ෂᆷ਷ CRC7Ġ + 6: ‫ؿ‬ෂᆷ਷ࢲඏ໊Ġ + 7: ࢤ൬ཙႋष൓໊Ġ + 8: ࢤ൬ཙႋ IRQ ཙႋĠ + 9: ࢤ൬ཙႋ‫ؿ‬ෂ໊Ġ + 10: ࢤ൬ཙႋᆷ਷ᆷඔĠ + 11: ࢤ൬ཙႋඔऌĠ + 12: ࢤ൬ཙႋ CRC7Ġ + 13: ࢤ൬ཙႋࢲඏ໊Ġ + 14: ᆷ਷ਫ਼ࣥ֩ր NCCĠ + 15: ֩րđᆷ਷-ཙႋ߭ሇb + +FIFO_FULL FIFO ູડ֥ሑ෿bčᆺ‫؀‬Ď + +FIFO_EMPTY FIFO ູॢ֥ሑ෿bčᆺ‫؀‬Ď + +FIFO_TX_WATERMARK FIFO ղ֞‫ؿ‬ෂᚐᆴđ҂൞ඔऌԮൻ֥сေ่ࡱbčᆺ‫؀‬Ď + +FIFO_RX_WATERMARK FIFO ղ֞ࢤ൬ᚐᆴđ҂൞ඔऌԮൻ֥сေ่ࡱbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 195 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.21. FIFOTH_REG (0x004C) + +(reserved) DMA_MULT(rIPesLeEr_vTeRd)ANSACTION_SIZE RX_WMARK (reserved) TX_WMARK + 0x0000 +31 30 28 27 26 16 15 12 11 0 + +0 0x0 0 x x x x x x x x x x x0 0 0 0 Reset + + DMA_MULTIPLE_TRANSACTION_SIZE ‫؟‬ՑԮൻ֥๬‫ؿ‬նཬđ஥ᇂ֥ᆴႋა DMA ॥ᇅఖ‫؟‬۱Ԯ + ൻնཬ SRC/DEST_MSIZE ཌྷ๝b000: 1 ሳࢫԮൻĠ001: 4 ሳࢫԮൻĠ010: 8 ሳࢫԮൻĠ011: 16 + ሳࢫԮൻĠ100: 32 ሳࢫԮൻĠ101: 64 ሳࢫԮൻĠ110: 128 ሳࢫԮൻĠ111: 256 ሳࢫԮൻbč‫؀‬ + ĔཿĎ + + RX_WMARK ֒ ࢤ ൬ ඔ ऌ ۳ व ൈ FIFO ֥ ᚐ ᆴb ֒ FIFO ඔ ऌ ࠹ ඔ ն Ⴟ ‫ ھ‬ඔ ᆴ + (FIFO_RX_WATERMARK) ൈđDMA/FIFO ౨ ౰ Ф ิ ԛb ᄝ ඔ ऌ Ї ࢲ ඏ ௹ ࡗđ ໭ ં ᚐ ᆴ ն ཬ + ೂ‫ޅ‬đ‫߶׻‬ളӮ౨౰đၛປӮഺჅ֥ඔऌԮൻbᄝ٤ DMA ଆൔ༯đ֒ࢤ൬ FIFO ᚐᆴ (RXDR) ᇏ + ؎൐ିൈđᄵ߶Ӂളᇏ؎đ‫ط‬҂൞ DMA ౨౰bೂ‫ݔ‬ᚐᆴնႿ಩‫ޅ‬ഺჅඔऌđᄵ҂Ӂളᇏ؎b֒ + ᇶࠏु࡮ඔऌ‫ؿ‬ෂࢲඏᇏ؎ൈđᇶࠏႋ‫؀ھ‬౼ഺ༯֥ඔऌbᄝ DMA ଆൔ༯đᄝඔऌЇࢲඏൈđ + ࠧ൐ഺჅ֥ሳࢫඔഒႿᚐᆴđDMA ౨౰္߶ᄝඔऌԮൻࢲඏᇏ؎ഡᇂᆭభࣉྛֆՑԮൻၛౢԢ + ෮ႵഺჅ֥ሳࢫbč‫؀‬ĔཿĎ + + TX_WMARK ֒ ‫ ؿ‬ෂ ඔ ऌ ۳ व ൈ FIFO ֥ ᚐ ᆴb ֒ FIFO ඔ ऌ ࠹ ඔ ཬ Ⴟ ֩ Ⴟ ‫ ھ‬ඔ ᆴ + (FIFO_TX_WATERMARK) ൈđDMA/FIFO ౨ ౰ Ф ิ ԛb ೂ ‫ ݔ‬൐ ି ᇏ ؎đ ᄵ ᇏ ؎ ‫ ؿ‬ളb ᄝ ඔ + ऌЇࢲඏ௹ࡗđ໭ંᚐᆴնཬೂ‫ޅ‬đ‫߶׻‬ളӮ౨౰bᄝ٤ DMA ଆൔ༯đ֒‫ؿ‬ෂ FIFO ᚐᆴ (TXDR) + ᇏ؎൐ିൈđᄵ߶Ӂളᇏ؎đ‫ط‬҂൞ DMA ౨౰bᄝඔऌЇࢲඏ௹ࡗđᄝቋު၂۱ᇏ؎ൈđᇶ + ࠏ‫ڵ‬ᄳࣇႨ෮ླ֥ഺჅሳࢫแԉ FIFOč҂൞ᄝ FIFO ડᆭభࠇᄝ CIU ປӮඔऌԮൻᆭުđၹູ + FIFO ॖି҂ູॢĎbᄝ DMA ଆൔ༯đᄝඔऌЇࢲඏൈđೂ‫ݔ‬ቋު၂ՑԮൻб๬‫ؿ‬ԮൻཬđDMA + ॥ᇅఖࡼᆳྛֆ۱ᇛ௹đᆰ֞Ԯൻ෮ླ֥ሳࢫbč‫؀‬ĔཿĎ + + Register 9.22. CDETECT_REG (0x0050) + + (reserved) CARD_DETECT_N + +31 21 0 + + 0x0 0x0 Reset + + CARD_DETECT_N card_detect_n ൻ ೆ ؊ १ čૄ ۱ व ၂ ۱ б หĎ ֥ ᆴb0 ս і व թ ᄝb ᆺ Ⴕ + NUM_CARDS ֥ཌྷႋ໊Фᆳྛbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 196 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.23. WRTPRT_REG (0x0054) + + (reserved) WRITE_PROTECT + +31 21 0 + + 0x0 0x0 Reset + + WRITE_PROTECT card_write_prt ൻ ೆ ؊ १ čૄ ۱ व ၂ ۱ б หĎ ֥ ᆴb1 і ൕ ཿ Ќ ޹b ᆺ Ⴕ + NUM_CARDS ֥ཌྷႋ໊Фᆳྛbčᆺ‫؀‬Ď + + Register 9.24. TCBCNT_REG (0x005C) 0 + +31 Reset + + 0x000000000 + + TCBCNT_REG CIU Ԯൻ۳व֥ሳࢫඔbčᆺ‫؀‬Ď + + Register 9.25. TBBCNT_REG (0x0060) 0 + +31 Reset + + 0x000000000 + + TBBCNT_REG ᇶࠏ/DMA ‫ ބ‬BIU FIFO ᆭࡗԮൻ֥ሳࢫඔbčᆺ‫؀‬Ď + + (reserved) Register 9.26. DEBNCE_REG (0x0064) + +31 24 23 DEBOUNCE_COUNT 0 + 0x0000000 +00000000 Reset + + DEBOUNCE_COUNT ‫׮׵‬ཨԢੲѯఖઆࠠ൐Ⴈ֥ᇶࠏൈᇒ (clk) ඔb‫֥྘ׅ‬ಀ‫׮׵‬ൈࡗູ 5 ~ 25 + msđٝᆸҬवࠇ၍Ԣव֥ൈީ֥҂໗‫ྟק‬bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 197 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.27. USRID_REG (0x0068) + +31 0 + + 0x000000000 Reset + + USRID_REG Ⴈ޼്љ࠷թఖđఃᆴႮႨ޼ഡᇂbՎ࠷թఖ္ॖၛቔູႨ޼֥ᄠթఖ࠷թఖ൐Ⴈčb‫؀‬ + ĔཿĎ + + Register 9.28. RST_N_REG (0x0078) + + (reserved) RST_CARD_RESET + +31 21 0 + + 0 0x1 Reset + + RST_CARD_RESET ႗ࡱ‫໊گ‬b1ğ‫۽‬ቔଆൔĠ0ğ‫໊گ‬bᆃུбหಞवࣉೆభॢ༽ሑ෿đᆃࡼေ౰෱ + ૌФᇗྍԚ൓߄bCARD_RESET[0] ႋФᇂູ 1’b0 ট‫໊گ‬व 0bCARD_RESET[1] ႋФᇂູ 1’b0 + ট‫໊گ‬व 1bФᆳྛ֥бหඔਈ൳ཋႿ NUM_CARDS ֥ᆴbč‫؀‬ĔཿĎ + + Register 9.29. BMOD_REG (0x0080) + + (reserved) BMOD_PBLBMOD_DE (reserved) BMODB_MFOBD_SWR + +31 11 10 876 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0x00 0 0 Reset + + BMOD_PBL ॖщӱ๬‫ؿ‬Ӊ؇bᆃ໊ུᆷൕᄝ၂۱ IDMAC Ԯൻᇏေᆳྛ֥ቋնࢫஅඔbIDMAC ૄ + Ցᄝᇶࠏሹཌഈष൓๬‫ؿ‬Ԯൻൈࡼሹ൞Ӈ൫ᄝ PBL ᇏᆷ‫֥ק‬๬‫ؿ‬ᆴbᄍྸ֥ᆴູ 1a4a8a16a + 32a64a128 ‫ ބ‬256b‫ھ‬ᆴ൞ FIFOTH ࠷թఖ֥ MSIZE ֥ࣤཞbေྩ‫ڿ‬Վᆴđࡼ෮ླ֥ᆴཿೆ + FIFOTH ࠷թఖbᆃ൞၂۱щ઒ᆴđೂ༯෮ൕğ000: 1 ሳࢫԮൻĠ001: 4 ሳࢫԮൻĠ010: 8 ሳࢫ + ԮൻĠ011: 16 ሳࢫԮൻĠ100: 32 ሳࢫԮൻĠ101: 64 ሳࢫԮൻĠ110: 128 ሳࢫԮൻĠ111: 256 + ሳࢫԮൻb + PBL ൞ᆺ‫؀‬ᆴđѩ౏ࣇൡႨႿඔऌ٠໙đ҂ൡႨႿ৽і٠໙bč‫؀‬ĔཿĎ + + BMOD_DE IDMAC ൐ି໊bᇂ໊ު IDMAC ൐ିbč‫؀‬ĔཿĎ + + BMOD_FB ‫קܥ‬๬‫ؿ‬b॥ᇅ AHB ᇶࢤ१൞‫ڎ‬ᆳྛ‫קܥ‬๬‫ؿ‬Ԯൻbᇂ໊ൈđAHB ࡼᄝᆞӈ๬‫ؿ‬Ԯൻ + ष൓௹ࡗࣇ൐Ⴈ SINGLEaINCR4aINCR8 ࠇ INCR16b֒‫໊گ‬ൈđAHB ࡼ൐Ⴈ SINGLE ‫ ބ‬INCR + ๬‫ؿ‬ԮൻҠቔbč‫؀‬ĔཿĎ + + BMOD_SWR ೈࡱ‫໊گ‬b֒ᇂ໊ൈđDMA ॥ᇅఖ‫໊گ‬෮Ⴕଽ҆࠷թఖb၂۱ൈᇒᇛ௹ުሱ‫׮‬ౢਬčb‫؀‬ + ĔཿĎ + +ুᶈྐ༏॓࠯ 198 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.30. PLDMND_REG (0x0080) + +31 0 + + 0x000000000 Reset + +PLDMND_REG ੽࿘ླ౰bೂ‫ݔ‬ીႵഡᇂ৽і֥ OWN ໊đᄵ FSM ࣉೆ‫ܫ‬ఏሑ෿bᇶࠏླေؓᆃ۱ + ࠷թఖཿೆ಩ၩᆴđၛ൐ IDMAC FSM ߫‫گ‬ᆞӈ৽і‫؀‬౼Ҡቔbᆃ൞၂۱ᆺཿ࠷թఖđPD ໊൞ + ᆺཿ໊bčᆺཿĎ + + Register 9.31. DBADDR_REG (0x0088) + +31 0 + + 0x000000000 Reset + +DBADDR_REG ৽іਙі֥ष൓bЇ‫ֻݣ‬၂۱৽і֥ࠎᆶbቋ໊ི֮ (LSB bit) [1:0] Фޭ੻đѩႮ + IDMAC ଽ҆ಆ҆౼ູਬđၹՎᆃུ LSB ໊ॖФ൪ູᆺ‫؀‬bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 199 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.32. IDSTS_REG (0x008C) + + (reserved) IDSTS_FSM IDSTS_FBEI_DCSOTSDID_EASITSS_N(rISeservedID) STSID_CSETSS(r_eDsUervIDeSd)TSID_FSBTESID_RSITS_TI + +31 17 16 13 12 10 9 8 7 65 4 3 2 1 0 + +000000000000000 0x00 0x0 0 0 0 0 0 0 0 0 0 0 Reset + + IDSTS_FSM DMAC FSM ֒భሑ෿bčᆺ‫؀‬Ď + 0: DMA_IDLE; 1: DMA_SUSPEND; 2: DESC_RD; 3: DESC_CHK; 4: DMA_RD_REQ_WAIT + 5: DMA_WR_REQ_WAIT; 6: DMA_RD; 7: DMA_WR; 8: DESC_CLOSE + + IDSTS_FBE_CODE ᇁଁሹཌհ༂ս઒bіૼ֝ᇁሹཌհ༂֥հ༂ো྘bࣇ֒ഡᇂᇁଁሹཌհ༂໊ + IDSTS[2] Фᇂ໊ൈႵིbՎሳ‫؍‬҂ളӮᇏ؎bčᆺ‫؀‬Ď + 3b001ğԮൻ௹ࡗࢤ൬֞ᇶࠏᇏᆸĠ + 3b010ğࢤ൬௹ࡗࢤ൬֞ᇶࠏᇏᆸĠ + ః෰ğЌ਽b + + IDSTS_AIS ၳӈᇏ؎߸ሹbၛ༯۲ཛ֥આࠠࠇğIDSTS[2]ğᇁଁሹཌᇏ؎đIDSTS[4]ğDU ໊ᇏ؎b + ᆺႵໃ௠з໊֥႕ཙ‫໊ھ‬bᆃ൞၂۱ᅔᇌ໊đсྶᄝૄՑౢਬႄఏ AIS ᇂ 1 ֥ཌྷႋ໊ൈౢਬbཿ + 1 ౢਬ‫໊ھ‬bč‫؀‬ĔཿĎ + + IDSTS_NIS ᆞӈᇏ؎߸ሹbၛ༯۲ཛ֥આࠠࠇğIDSTS[0]ğ‫ؿ‬ෂᇏ؎đIDSTS[1]ğࢤ൬ᇏ؎bᆺႵໃ + ௠з໊֥႕ཙ‫໊ھ‬bᆃ൞၂۱ᅔᇌ໊đсྶᄝૄՑౢਬႄఏ NIS ᇂ 1 ֥ཌྷႋ໊ൈౢਬbཿ 1 ౢ + ਬ‫໊ھ‬bč‫؀‬ĔཿĎ + + IDSTS_CES वհ༂߸ሹbᆷൕ‫ؿ‬ෂ/ࢤ൬व֥Ԯൻሑ෿đ္ԛགྷᄝ RINTSTS ᇏbіൕၛ༯໊֥આࠠ + ࠇğEBEğࢲඏ໊հ༂đRTOğཙႋӑൈ/ႄ֝ಒಪӑൈđRCRCğཙႋ CRCđSBEğఓ‫໊׮‬հ༂đ + DRTOğඔऌ‫؀‬౼ӑൈ/ BDS ӑൈđDCRCğႨႿࢤ൬֥ඔऌ CRCđREğཙႋհ༂b + ཿ 1 ౢਬ‫໊ھ‬bIDMAC ֥ᇏᆸ่ࡱ౼थႿՎ CES ໊֥஥ᇂbೂ‫ ݔ‬CES ໊Ф൐ିđᄵ IDMAC ᄝ + ཙႋհ༂ൈᇏᆸbč‫؀‬ĔཿĎ + + IDSTS_DU ৽і҂ॖႨᇏ؎b֒৽іႮႿ OWN ໊ = 0 (DES0 [31] = 0) ‫ط‬҂ॖႨൈđ‫໊ھ‬ᇂ 1bཿ 1 + ౢਬ‫໊ھ‬bč‫؀‬ĔཿĎ + + IDSTS_FBE ᇁଁሹཌհ༂ᇏ؎bіൕ‫ؿ‬ളሹཌհ༂ (IDSTS[12:10])b֒‫໊ھ‬ᇂ 1 ൈđDMA ࣌ᆸ෮Ⴕ + ሹཌ٠໙bཿ 1 ౢਬ‫໊ھ‬bč‫؀‬ĔཿĎ + + IDSTS_RI ࢤ൬ᇏ؎bіൕ৽і֥ඔऌࢤ൬ປӮbཿ 1 ౢਬ‫໊ھ‬bč‫؀‬ĔཿĎ + + IDSTS_TI ‫ؿ‬ෂᇏ؎bіൕ৽і֥ඔऌ‫ؿ‬ෂປӮbཿ 1 ౢਬ‫໊ھ‬bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 200 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.33. IDINTEN_REG (0x0090) + + (reserved) IDINTEIDNIN_ATIEN(_reNsIervedID) INTEIDNIN_CTE(EreNSs_eDrvIUDeIdN)TEIDNIN_FTBEIDENIN_RTEI N_TI + +31 10 9 8 7 65 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + IDINTEN_AI ၳӈᇏ؎߸ሹ൐ି໊bč‫؀‬ĔཿĎ + ᇂ 1 ൈđ൐ିၳӈᇏ؎b‫໊ھ‬൐ିၛ༯໊ğIDINTEN [2]ğᇁଁሹཌհ༂ᇏ؎ĠIDINTEN [4]ğDU + ᇏ؎b + + IDINTEN_NI ᇏ؎߸ሹ൐ି໊bč‫؀‬ĔཿĎ + ᇂ 1 ൈđ൐ିᆞӈᇏ؎bᇗᇂൈđ࣌ିᆞӈᇏ؎b‫໊ھ‬൐ିၛ༯໊ğ + IDINTEN[0]ğ‫ؿ‬ෂᇏ؎Ġ + IDINTEN[1]ğࢤ൬ᇏ؎b + + IDINTEN_CES वհ༂߸ሹᇏ؎൐ି໊bᇂ 1 ൈ൐ିवᇏ؎߸ሹbč‫؀‬ĔཿĎ + + IDINTEN_DU ৽і҂ॖႨᇏ؎b֒აၳӈᇏ؎߸ሹ൐ି໊၂ఏഡᇂൈđࡼ൐ି DU ᇏ؎bč‫؀‬ĔཿĎ + + IDINTEN_FBE ᇁଁሹཌհ༂൐ି໊b֒აၳӈᇏ؎߸ሹ൐ି໊၂ఏഡᇂൈđࡼ൐ିᇁଁሹཌհ༂ + ᇏ؎b‫໊گ‬ൈđᇁଁሹཌհ༂൐ିᇏ؎Ф࣌ିbč‫؀‬ĔཿĎ + + IDINTEN_RI ࢤ൬ᇏ؎൐ି໊b֒აᆞӈᇏ؎߸ሹ൐ି໊၂ఏഡᇂൈđࡼ൐ିࢤ൬ᇏ؎b‫໊گ‬ൈđࢤ + ൬ᇏ؎Ф࣌ିbč‫؀‬ĔཿĎ + + IDINTEN_TI ‫ؿ‬ෂᇏ؎൐ି໊b֒აᆞӈᇏ؎߸ሹ൐ି໊၂ఏഡᇂൈđࡼ൐ି‫ؿ‬ෂᇏ؎b‫໊گ‬ൈđ‫ؿ‬ + ෂᇏ؎Ф࣌ିbč‫؀‬/ཿĎ + + Register 9.34. DSCADDR_REG (0x0094) + +31 0 + + 0x000000000 Reset + + DSCADDR_REG ᇶࠏ৽іֹᆶᆷᆌđᄝҠቔ௹ࡗႮ IDMAC ۷ྍđѩᄝ‫໊گ‬ൈౢਬb‫࠷ھ‬թఖᆷཟ + Ⴎ IDMAC ‫؀‬౼֥֒భ৽і֥ఏ൓ֹᆶbčᆺ‫؀‬Ď + + Register 9.35. BUFADDR_REG (0x0098) + +31 0 + + 0x000000000 Reset + + BUFADDR_REG ᇶࠏߏԊ౵ֹᆶᆷᆌđᄝҠቔ௹ࡗႮ IDMAC ۷ྍđѩᄝ‫໊گ‬ൈౢਬb‫࠷ھ‬թఖᆷ + ཟႮ IDMAC ٠໙֥֒భඔऌߏԊ౵ֹᆶbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 201 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 9 SD/MMC ᇶࠏ॥ᇅఖ + + Register 9.36. CLK_EDGE_SEL (0x0800) + + (reserved) CCLKIN_EDGE_N CCLKIN_EDGE_L CCLKIN_EDGE_H CCLKIN_EDGE_SCLCFL_KSIENL_EDGE_SCACML_KSINE_LEDGE_DRV_SEL + +31 21 20 17 16 13 12 98 65 32 0 + + 0x000 0x1 0x0 0x1 0x0 0x0 0x0 Reset + + CCLKIN_EDGE_N ᆴა CCLKIN_EDGE_L ཌྷ๝bč‫؀‬/ཿĎ + + CCLKIN_EDGE_L ‫ٳ‬௔ൈᇒ֥֮‫׈‬௜đᆴႋб CCLKIN_EDGE_H նbč‫؀‬/ཿĎ + + CCLKIN_EDGE_H ‫ٳ‬௔ൈᇒ֥ۚ‫׈‬௜đᆴႋб CCLKIN_EDGE_L ཬbč‫؀‬/ཿĎ + + CCLKIN_EDGE_SLF_SEL ႨႿ࿊ᄴଽ҆ൈᇒྐ‫֥ݼ‬ཌྷ໊đ90 ؇ཌྷ໊a180 ؇ཌྷ໊ࠇ 270 ؇ཌྷ + ໊bč‫؀‬/ཿĎ + + CCLKIN_EDGE_SAM_SEL ႨႿ࿊ᄴൻೆൈᇒྐ‫֥ݼ‬ཌྷ໊đ90 ؇ཌྷ໊a180 ؇ཌྷ໊ࠇ 270 ؇ཌྷ + ໊bč‫؀‬/ཿĎ + + CCLKIN_EDGE_DRV_SEL ႨႿ࿊ᄴൻԛൈᇒྐ‫֥ݼ‬ཌྷ໊đ90 ؇ཌྷ໊a180 ؇ཌྷ໊ࠇ 270 ؇ཌྷ + ໊bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 202 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +10 ၛ෾ຩ (MAC) + +10.1 ‫ۀ‬ඍ + +Ethernet ᇶေหྟ +ࢹᇹຓ҆ၛ෾ຩ໾৘Ҫ (Ethernet PHY)đESP32 ॖၛ๙‫ݖ‬ၛ෾ຩࢺᇉ٠໙॥ᇅ (Ethernet MAC) οᅶ IEEE 802.3 +ѓሙ‫ؿ‬ෂ‫ࢤބ‬൬ඔऌbབྷ࡮๭ 10-1bၛ෾ຩ൞֒భႋႨቋ௴ђ֥अთຩ (LAN) ‫ܼބ‬თຩ (WAN) ࣉྛඔऌԮѬ֥ +ຩ઎ླྀၰb + + ๭ 10­1. Ethernet MAC ‫ۀିۿ‬ඍ + +ESP32 ၛ෾ຩ MAC ‫ކژ‬ၛ༯ѓሙğ + • IEEE 802.3-2002đႨႿၛ෾ຩ MACb + • IEEE 1588-2008 ѓሙđႨႿܿ‫ק‬৳ຩൈᇒ๝֥҄ࣚ؇b + • ‫ ކژ‬IEEE 802.3 ܿٓ‫۽‬ြѓሙࢤ१ğࢺᇉ‫׿‬৫ࢤ१ (MII) ‫ࢺ߄ࡥބ‬ᇉ‫׿‬৫ࢤ१ (RMII)b + +MAC Ҫหྟ + • ᆦӻຓ҆ PHY ࢤ१ൌགྷ 10/100 Mbit/s ඔऌԮൻ෎ੱ + • ॖ๙‫ ކژݖ‬IEEE802.3 ֥ MII ࢤ१‫ ބ‬RMII ࢤ१აຓ҆ॹ෎ၛ෾ຩ PHY ࣉྛ๙ྐ + • ᆦӻಆච‫϶ބ۽‬ච‫۽‬ଆൔ + – ᆦӻൡႨႿ϶ච‫۽‬ଆൔ֥ CSMA/CD ླྀၰ + – ᆦӻൡႨႿಆච‫۽‬ଆൔ֥ IEEE 802.3x ੀਈ॥ᇅ + – ಆච‫۽‬ଆൔൈॖၛࡼࢤ൬֥ᄠ๔॥ᇅᆠሇ‫֞ؿ‬Ⴈ޼ႋႨӱ྽ + – ϶ච‫۽‬ଆൔൈิ‫܂‬М࿢ੀਈ॥ᇅ + – ಆච‫۽‬Ҡቔᇏೂ‫ݔ‬ੀਈ॥ᇅൻೆྐ‫ݼ‬ཨാđࡼሱ‫ؿ׮‬ෂᄠ๔ൈࡗູਬ֥ᄠ๔ᆠ + • Б๨‫ބ‬ᆠఏ൓ඔऌ (SFD) ᄝ‫ؿ‬ෂਫ਼ࣥᇏҬೆaᄝࢤ൬ਫ਼ࣥᇏ೷Ԣ + • ॖᇯᆠ॥ᇅ CRC ‫ ބ‬pad ሱ‫׮‬ളӮ + • ೂ‫ݔ‬ඔऌູղ֞ቋཬᆠӉ؇đᄵሱ‫׮‬เࡆ pad + • ॖщӱᆠӉ؇đᆦӻۚղ 16 KB ֥ऍ྘ᆠ + +ুᶈྐ༏॓࠯ 203 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + • ॖщӱᆠࡗ‫( ۯ‬IFG)č40-96 ໊ൈࡗđၛ 8 ູ҄ӉĎ + • ᆦӻ‫؟‬ᇕਲࠃֹ֥ᆶ‫ݖ‬ੲଆൔ: + + – ۚղ 8 ۱ 48 ໊ປૅֹᆶ‫ݖ‬ੲఖđؓૄ۱ሳࢫࣉྛဃ઒Ҡቔ + – ۚղ 8 ۱ 48 ໊ SA ֹᆶбࢠ࡟Ұđؓૄ۱ሳࢫࣉྛဃ઒Ҡቔ + – ॖԮෂ෮Ⴕ‫؟‬Ѭֹᆶᆠ + – ᆦӻࠁ‫ކ‬ଆൔđၹՎॖԮෂ෮Ⴕᆠđ໭ླູຩ઎ࡓ൪ࣉྛ‫ݖ‬ੲ + – Ԯෂ෮ႵԮೆඔऌЇൈčૄՑ‫ݖ‬ੲൈĎन‫ڸ‬Ⴕ၂‫ٺ‬ሑ෿Бۡ + • ູ‫ؿ‬ෂ‫ࢤބ‬൬ඔऌЇ‫ٳ‬љْ߭ 32 ໊ሑ෿ + • ູႋႨӱ྽ิ‫܂‬ֆ‫ؿ֥׿‬ෂaࢤ൬‫ބ‬॥ᇅࢤ१ + • ൐Ⴈ MDIO ࢤ१஥ᇂ‫ܵބ‬৘ PHY ഡС + • ᄝࢤ൬‫ିۿ‬ᇏᆦӻؓࢤ൬֥֞Ⴎၛ෾ຩᆠ‫ٿ‬ል֥ IPv4 ‫ ބ‬TCP ඔऌЇࣉྛ཮ဒ‫ཱྀބ‬ᄛ + • ᄝࢤ൬‫ିۿ‬ᇏᆦӻ࡟Ұ IPv4 ๨཮ဒ‫ބ‬ၛࠣᄝ IPv4/IPv6 ඔऌЇᇏ‫ٿ‬ል֥ TCPaUDP ࠇ ICMP ཮ဒ‫ބ‬ + • ᆦӻၛ෾ຩᆠൈࡗՄčབྷ༥ҕॉ IEEE 1588-2008Ďbૄ۱ᆠᄝ‫ؿ‬ෂࠇࢤ൬ൈջႵ 64 ໊ൈࡗՄb + • ਆቆ FIFOğ၂۱ऎႵॖщӱᚐᆴ‫ ֥ିۿ‬2 KB ‫ؿ‬ෂ FIFO ‫ބ‬၂۱ऎႵॖ஥ᇂᚐᆴčଏಪູ 64 ۱ሳࢫĎ‫ۿ‬ + ି֥ 2 KB ࢤ൬ FIFO + • ࢤ൬ FIFO ࣉྛ‫؟‬ᆠթԥൈđᄝ EOF Ԯൻުđ๙‫ݖ‬ཟࢤ൬ FIFO Ҭೆࢤ൬ሑ෿൏ਈđՖ‫ط‬൐֤ࢤ൬ FIFO ໭ + ླթԥᆃུᆠ֥ࢤ൬ሑ෿ + • ᄝթԥሇ‫ؿ‬ଆൔ༯đॖၛᄝࢤ൬ൈ‫ݖ‬ੲ෮Ⴕ֥հ༂ᆠđ֌҂ࡼᆃུհ༂ᆠሇ‫ؿ‬۳ႋႨӱ྽ + • ॖၛሇ‫ݺ֥ཬݖؿ‬ᆠ + • ູࢤ൬ FIFO ᇏႮႿၮԛ‫ש‬ാࠇ෥ߊ֥ᆠളӮઝԊđࢹՎᆦӻඔऌ๤࠹ + • ཟ MAC ଽ‫ؿނ‬ෂඔऌൈᆦӻթԥሇ‫ࠏؿ‬ᇅ + • ‫ؿ‬ෂൈԩ৘Ԋ๬ᆠ֥ሱ‫׮‬ᇗྍ‫ؿ‬ෂč‫ކژ‬၂‫ࡱ่ק‬đབྷ࡮ 10.2.1.2Ď + • ‫ש‬ఙ࿼ӾԊ๬a‫ݖ‬؇Ԋ๬a‫ݖ‬؇࿼Ӿ‫ބ‬༯ၮ่ࡱ༯֥ᆠ + • ๙‫ݖ‬ೈࡱ॥ᇅ඗ྍ Tx FIFO + • ࠹ෘ IPv4 ๨཮ဒ‫ބ‬ა TCPaUDP ࠇ ICMP ཮ဒ‫ބ‬ѩࡼఃҬೆᄝթԥሇ‫ؿ‬ଆൔ༯‫ؿ‬ෂ֥ᆠᇏ + +ুᶈྐ༏॓࠯ 204 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +Ethernet ࢲ‫ॿܒ‬๭ +Ethernet ࢲ‫ॿܒ‬๭ೂ๭ 10-2 ෮ൕb + + ๭ 10­2. Ethernet ‫ॿିۿ‬๭ + +Ethernet MAC ҪᇶေЇও EMAC_COREđEMAC_MTL (MAC Transition Layer)đEMAC_DMA (Direct Memory +Access) ೘Ҫၛࠣ MAC Ҫ֥஥ᇂ࠷թఖଆॶđ෱ૌ‫ٳ‬љႵ Rx ‫ ބ‬Tx ਆ۱ٚཟđᄝྉோଽ҆๙‫ ݖ‬AHB ‫ ބ‬APB +ሹཌ‫ބ‬༢๤ཌྷ৵ࢤđᄝྉோຓ҆๙‫ ݖ‬MII ‫ ބ‬RMII ࢤ१‫ބ‬ຓ֥҆ PHY ࣉྛ๙ྐđቋᇔൌགྷၛ෾ຩ֥‫ିۿ‬b + +10.2 EMAC_CORE + +MAC ᆦӻྸ‫࡙؟‬ಸ PHY ྉோ֥ࢤ१b‫ ު໊گ‬PHY ࢤ१ᆺି࿊၂ՑbMAC ൐Ⴈ MAC ‫ؿ‬ෂࢤ१ (MTI)đMAC ࢤ +൬ࢤ१ (MRI) ‫ ބ‬MAC ॥ᇅࢤ१ (MCI) აႋႨҧčDMA ҧĎࣉྛ๙ྐb + +10.2.1 ԮൻҠቔ + +֒ MTL ႋႨӱ྽๷ෂඔऌѩ౏ SOFčᆠఏ൓Ďྐ‫ݼ‬ঘۚൈđఓ‫ؿ׮‬ෂҠቔb֒࡟ҩ֞ SOF ྐ‫ݼ‬ൈđMAC ࢤ൬ +ඔऌѩष൓‫ؿ‬ෂ֞ RMII ࠇ MIIbႋႨӱ྽ఓ‫׮‬Ԯൻᆭުࡼᆠඔऌ‫ؿ‬ෂ֞ RMII ࠇ MII ෮ླ֥ൈࡗ౼थႿ࿼Ӿၹ +෍đೂ IFG ࿼Ӿđ‫ؿ‬ෂБ๨ࠇ SFDčఏ൓ᆠ‫ژۯٳ‬Ď֥ൈࡗၛࠣ϶ච‫֥۽‬಩‫߭ޅ‬๼࿼ӾଆൔbᄝՎᆭభđ๙‫ݖ‬ +ঘ֮ඔऌࣼ࿂ྐ‫ݼ‬đMAC ҂ࢤ൬Ֆ MTL ࢤ൬֥֞ඔऌb + +ᄝ EOFčᆠࢲඏĎ‫ؿ‬ෂ֞ MAC ᆭުđMAC ປӮᆞӈԮൻđѩࡼԮൻሑ෿ (Transmit Status) ิ‫܂‬۳ MTLbೂ‫ݔ‬ +ᄝԮൻ‫ݖ‬ӱᇏčᄝ϶ච‫۽‬ଆൔ༯Ď‫ؿ‬ളᆞӈ֥Ԋ๬đᄵ MAC ൐ MTL ֥‫ؿ‬ෂሑ෿Ⴕིbಖު෱ࢤ൳ѩ೷Ԣ෮Ⴕ +ഺ༯֥ඔऌđᆰ֞ࢤ൬֞༯၂۱ SOFbᄝԮൻሑ෿ᇏ࡟ҩ֞ MAC ‫ؿ‬ԛ֥ᇗ൫౨౰ൈđMTL ଆॶႋ‫ھ‬Ֆ SOF ष +൓ᇗԮཌྷ๝֥ᆠb + +ೂ‫ ݔ‬MTL ҂ିᄝԮൻ௹ࡗ৵࿃ิ‫܂‬ඔऌđᄵ MAC ߶‫ؿ‬ԛ༯ၮሑ෿bᄝՖ MTL ᆞӈԮൻᆠ֥‫ݖ‬ӱᇏđೂ‫ݔ‬ +MAC ࢤ൬֞၂۱ SOF ‫ط‬ીႵ֤֞భ၂ᆠ֥ EOFđᄵޭ੻‫ ھ‬SOFđѩࡼ‫ྍھ‬ᆠ൪ູభ၂ᆠ֥࿼࿃b + +10.2.1.1 ‫ؿ‬ෂੀਈ॥ᇅ + +ᄝಆච‫۽‬ଆൔ༯đ֒‫ؿ‬ෂੀਈ॥ᇅ൐ି໊čFlow Control Register ᇏ֥ TFE/Transmit Flow Control ໊Ďᇂ 1 ൈđ +MAC ࡼളӮᄠ๔ᆠѩ۴ऌླေ‫ؿ‬ෂᄠ๔ᆠbᄠ๔ᆠა࠹ෘԛ֥ CRC ‫ࡆڸ‬ᄝ၂ఏѩ‫ؿ‬ෂbॖၛ๙‫ݖ‬ਆᇕٚൔఓ +‫׮‬ᄠ๔ᆠ֥ളӮb + +֒ႋႨӱ྽ࡼ Flow Control Register ᇏ֥ FCB (Flow Control Busy) ໊ᇂ 1 ࠇࢤ൬ FIFO ၘડൈđࡼ‫ؿ‬ෂᄠ๔ +ᆠb + +ুᶈྐ༏॓࠯ 205 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +• ೂ‫ݔ‬ႋႨӱ྽ၘ๙‫ ࡼݖ‬Flow Control Register ࠷թఖᇏ֥ FCB ໊ᇂ 1 ট౨౰ੀਈ॥ᇅđᄵ MAC ࡼളӮѩ + ‫ؿ‬ෂֆ۱ᄠ๔ᆠbളӮ֥ᆠᇏ֥ᄠ๔ൈࡗᆴູ Flow Control Register ᇏщӱ֥ᄠ๔ൈࡗᆴbေᄝ༵భ‫ؿ‬ෂ + ֥ᄠ๔ᆠᇏᆷ‫֥ק‬ൈࡗᆭభ࿼Ӊࠇࢲඏᄠ๔ൈࡗđႋႨӱ྽сྶၛൡ֥֒ᆴщӱᄠ๔ൈࡗᆴčFlow + Control Register ᇏ֥ PT/Pause TimeĎđಖު౨౰ਸ਼၂Ցᄠ๔ᆠ‫ؿ‬ෂb + +• ೂ‫ࢤݔ‬൬ FIFO แડൈႋႨӱ྽ၘ౨౰ੀਈ॥ᇅđᄵ MAC ࡼളӮѩ‫ؿ‬ෂᄠ๔ᆠbളӮ֥ᆠᇏ֥ᄠ๔ൈࡗ + ᆴູ Flow Control Register ᇏщӱ֥ᄠ๔ൈࡗᆴbೂ‫ݔ‬ᄝՎᄠ๔ൈࡗࢲඏభđࢤ൬ FIFO ᄝॖ஥ᇂ֥ൈ༣ + ඔčFlow Control Register ᇏ֥ PLT (Pause Low Threshold) ໊Ď௹ࡗЌӻแડሑ෿đࡼ‫ؿ‬ෂֻ‫ؽ‬۱ᄠ๔ᆠb + ᆺေࢤ൬ FIFO Ќӻแડሑ෿đ‫ݖھ‬ӱࡼ၂ᆰᇗ‫گ‬༯ಀbೂ‫ݔ‬ᄝҐဢൈࡗᆭభ҂ᄜડቀՎ่ࡱđMAC ࡼ‫ؿ‬ + ෂ၂۱ᄠ๔ൈࡗູਬ֥ᄠ๔ᆠđཟჹӱ؊іૼࢤ൬ߏԊ౵ၘሙС‫ࢤݺ‬൬ྍඔऌᆠb + +10.2.1.2 Ԋ๬௹ࡗ֥ᇗྍ‫ؿ‬ෂ + +ᄝ϶ච‫۽‬ଆൔ༯đཟ MAC Ԯൻᆠൈđॖିᄝ MAC ཌࢤ१ഈ‫ؿ‬ളԊ๬൙ࡱbMAC മᇀ߶ᄝࢤ൬֞ᆠࢲඏᆭభ +ࣼ۳ԛሑ෿টᆷൕᇗ൫bಖުࡼ൐ିᇗྍ‫ؿ‬ෂѩᄜՑࡼᆠՖ FIFO ᇏ֐ԛb֒ӑ‫ ݖ‬96 ۱ሳࢫ֐ཟ MAC ଽ‫ުނ‬đ +FIFO ॥ᇅఖࡼ൤٢‫ࡗॢھ‬đ൐ DMA ॖ๷ೆ۷‫؟‬ඔऌbᆃၩ໅ሢӑ‫ݖ‬ᚐᆴުࠇ MAC ଽ‫ނ‬ᆷൕ࿼ӾԊ๬൙ࡱൈđ +໭‫م‬ᇗྍ‫ؿ‬ෂb + +ႮႿஷሏđTx FIFO ༯ၮđᄛѯ‫ש‬ാđjabber ӑൈđ໭ᄛѯđ‫ݖ‬؇࿼ӾࠇӾԊ๬đMAC ‫ؿ‬ෂఖ‫׻‬ॖି߶ᇏᆸᆠ +֥Ԯൻb֒ᆠԮൻႮႿԊ๬‫ط‬ᇏᆸൈđMAC ౨౰ᇗ‫ؿ‬ᆠb + +10.2.2 ࢤ൬Ҡቔ + +֒ MAC ᄝ RMII ࠇ MII ഈ࡟ҩ֞ SFD ൈఓ‫ࢤ׮‬൬Ҡቔbᄝ࠿࿃ԩ৘ᆠᆭభđMAC Љಀభ֝઒‫ ބ‬SFDb࡟ҰБ +๨ሳ‫ݖ֥؍‬ੲ‫ބ‬ႨႿဒᆣᆠ֥ CRC ֥ FCS ሳ‫؍‬bࢤ൬֥ᆠթԥᄝߏԊఖᇏđᆰ֞ᆳྛֹᆶ‫ݖ‬ੲbೂ‫ݔ‬ᆠໃ๙ +‫ֹݖ‬ᆶ‫ݖ‬ੲđᄵᆠ‫ש‬ఙᄝ MAC ᇏb + +MAC ࢤ൬֥ᆠࡼ๷ೆ Rx FIFObՎ FIFO ֥ሑ෿၂֊ӑ‫ݖ‬஥ᇂ֥ࢤ൬ᚐᆴčOperation Mode ࠷թఖᇏ֥ +Receive Threshold Control/RTC ໊Ďđѩ๙ᆩ۳ DMAđᆃဢ DMA ॖཟ AHB ࢤ१‫ؿ‬ఏყ஥ᇂ֥๬‫ؿ‬Ԯൻb + +ᄝଏಪᆰ๙ଆൔ༯đ֒ FIFO ࢤ൬֞ 64 ۱ሳࢫč๙‫ ݖ‬Operation Mode ࠷թఖᇏ֥ Receive Threshold +Control/RTC ໊஥ᇂĎࠇປᆜ֥ඔऌЇൈđඔऌࡼ֐ԛđఃॖႨྟࡼ๙ᆩ۳ DMAbDMA ཟ AHB ࢤ१‫ؿ‬ఏԮൻ +ުđඔऌԮൻࡼՖ FIFO ӻ࿃ࣉྛđᆰ֞Ԯൻປᆜ۱ඔऌЇbປӮᆠ EOF ֥Ԯൻުđሑ෿ሳࡼ֐ԛѩ‫ؿ‬ෂ֞ +DMA ॥ᇅఖb + +ᄝ Rx FIFO թԥሇ‫ؿ‬ଆൔč๙‫ ݖ‬Operation Mode ࠷թఖᇏ֥ Receive Store and Forward/RSF ໊஥ᇂĎđᆃဢᆺ +߶‫؀‬ԛႵིᆠѩࡼఃሇ‫֞ؿ‬ႋႨӱ྽bᄝᆰ๙ଆൔ༯đଖུհ༂ᆠ҂߶Ф‫ש‬ఙđၹູᄝᆠࢲඏൈҌࢤ൬֞հ༂ +ሑ෿đ‫ط‬ՎൈᆠඔऌၘՖ FIFO ‫؀‬ԛb + +10.2.2.1 ࢤ൬ླྀၰ + +ࢤ൬ଆॶࢤ൬֞ЇᆭުđಀԢࢤ൬֥ᆠ֥Б๨‫ ބ‬SFDb࡟ҩ֞ SFD ުđMAC ष൓ཟࢤ൬ FIFO ‫ؿ‬ෂၛ෾ຩᆠඔ +ऌđՖ SFD ު૫ֻ֥၂۱ሳࢫčଢѓֹᆶĎष൓‫ؿ‬ෂbೂ‫ݔ‬൐ି IEEE 1588 ൈࡗՄ‫ିۿ‬đᄵᄝ MII ഈ࡟ҩ֞಩ +‫ޅ‬ᆠ֥ SFD ൈđ‫ࠆࡼ׻‬౼༢๤ൈࡗ֥ॹᅶbԢ٤ MAC ੲԛѩ‫ש‬ఙᆠđ‫ڎ‬ᄵՎൈࡗՄࡼԮ‫־‬۳ႋႨӱ྽b + +ೂ‫ࢤݔ‬൬֥ᆠӉ؇/ো྘ሳ‫ཬ؍‬Ⴟ 0x600 ѩ౏ູ MAC ൐ିਔሱ‫׮‬ಀԢ CRC/pad ࿊ཛđᄵ MAC ࡼཟࢤ൬ FIFO +‫ؿ‬ෂᆠඔऌčඔऌਈ҂ӑ‫ݖ‬Ӊ؇/ো྘ሳ‫؍‬ᇏᆷ‫֥ק‬ඔਈĎđಖުष൓‫ש‬ఙሳࢫčЇও FCS ሳ‫؍‬Ďbೂ‫ݔ‬Ӊ؇/ো +྘ሳ‫؍‬նႿࠇ֩Ⴟ 0x600đᄵ҂ܵ஥ᇂ֥ሱ‫ ׮‬CRC ಀԢ࿊ཛ֥ᆴೂ‫ޅ‬đMAC ‫߶׻‬ཟ Rx FIFO ‫ؿ‬ෂ෮Ⴕࢤ൬֞ +֥ၛ෾ຩᆠඔऌbଏಪ౦ঃ༯đ൐ି MAC ु૊‫קܐ‬ൈఖđࠧđӑ‫ ݖ‬2048 ۱ሳࢫčDA+SA+LT+ ඔऌ ++pad+FCSĎᆠ߶Ф్؎bॖ๙‫ ؓݖ‬MAC ஥ᇂ࠷թఖᇏ֥ु૊‫࣌ܐ‬ᆸ (WD/Watchdog Disable) ໊щӱট࣌ᆸՎ +‫ିۿ‬b֌൞đࠧ൐࣌ᆸु૊‫קܐ‬ൈఖđಯࡼ్؎նႿ 16 KB ֥ᆠѩ۳ԛु૊‫ܐ‬ӑൈሑ෿b + +ুᶈྐ༏॓࠯ 206 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + 10.2.2.2 ࢤ൬ᆠ॥ᇅఖ + + ೂ‫ ໊گݔ‬MAC ᆠ‫ݖ‬ੲ࠷թఖᇏ֥ RA (Receive All) ໊đᄵ MAC ࡼ۴ऌଢѓ/ჷֹᆶᆳྛᆠ‫ݖ‬ੲbೂ‫ݔ‬ႋႨӱ྽ + थ‫ק‬҂ࢤ൬಩‫ޅ‬҂ਅᆠđೂζᆠaCRC հ༂ᆠ֩đᄵಯླေᆳྛਸ਼၂֥֩ࠩ‫ݖ‬ੲb࡟ҩ֞‫ݖ‬ੲാϧൈđᆠࡼФ + ‫ש‬ఙ౏҂߶Ԯൻ֞ႋႨӱ྽b֒‫ݖ‬ੲҕඔ‫׮‬෿‫ڿ‬эൈđೂ‫( ݔ‬DA-SA) ‫ݖ‬ੲാϧđᄵഺჅ֥ᆠࡼФ‫ש‬ఙѩ౏ࢤ൬ + ሑ෿ሳࡼ৫ࠧ۷ྍčਬᆠӉ؇໊aCRC հ༂໊‫ބ‬ζᆠհ༂໊ࡼᇂ 1Ďđᆷൕ‫ݖ‬ੲാϧb + + 10.2.2.3 ࢤ൬ੀਈ॥ᇅ + + MAC ࡼ࡟ҩࢤ൬ᄠ๔ᆠѩᄠ๔ᆠ‫ؿ‬ෂđᄠ๔ൈࡗູࢤ൬֥ᄠ๔ᆠଽᆷ‫֥ק‬࿼Ӿčࣇཋಆච‫۽‬ଆൔĎbॖ๙‫ݖ‬ + Flow Control Register ᇏ֥ (Receive Flow Control Enable/RFCE) ໊൐ିࠇ࣌ᆸᄠ๔ᆠ࡟ҩ‫ିۿ‬b൐ିࢤ൬ੀਈ + ॥ᇅުđࡼष൓ࡓ൪ࢤ൬ᆠ֥ଢѓֹᆶ൞‫ڎ‬ა॥ᇅᆠ֥‫؟‬Ѭֹᆶ (0x0180 C200 0001) ௄஥bೂ‫࡟ݔ‬ҩ֞௄஥ +čࢤ൬֥ᆠ֥ଢѓֹᆶაЌ਽֥॥ᇅᆠ֥ଢѓֹᆶ௄஥ĎđMAC ࡼ۴ऌ Frame Filter Register ᇏ֥ (Pass Control + Frames/PCF) ໊টथ‫ק‬൞‫ࢤࡼڎ‬൬֥॥ᇅᆠԮൻႋႨӱ྽b + + MAC ߎࡼؓࢤ൬॥ᇅᆠ֥ো྘aҠቔ઒‫ބ‬ᄠ๔‫ק‬ൈఖሳ‫ࢳྛࣉ؍‬઒bೂ‫ݔ‬ሑ෿֥ሳࢫ࠹ඔᆷൕ 64 ۱ሳࢫđѩ + ౏҂թᄝ಩‫ ޅ‬CRC հ༂đᄵ MAC ‫ؿ‬ෂఖࡼᄠ๔಩‫ޅ‬ඔऌᆠ֥‫ؿ‬ෂđᄠ๔ൈࡗູࢳ઒֥ᄠ๔ൈࡗᆴӰၛൈ༣ +čؓႿ 10/100 Mbit/s ଆൔđनູ 64 ሳࢫĎb๝ൈđೂ‫࡟ݔ‬ҩ֞ਸ਼၂۱ਬᄠ๔ൈࡗᆴ֥ᄠ๔ᆠđMAC ࡼ‫໊گ‬ᄠ๔ + ൈࡗѩܵ৘ྍ֥ᄠ๔౨౰b + + ೂ‫ࢤݔ‬൬֥॥ᇅᆠაো྘ሳ‫( ؍‬0x8808)aҠቔ઒ (0x00001) ၛࠣሳࢫӉ؇č64 ሳࢫĎन҂௄஥đࠇթᄝ CRC + հ༂đᄵ MAC ҂߶ᄠ๔b + + ೂ‫ݔ‬ᄠ๔ᆠऎႵ‫؟‬ѬଢѓֹᆶđMAC ࡼ۴ऌֹᆶ௄஥ট‫ݖ‬ੲᆠb + + ؓႿऎႵֆѬଢѓֹᆶ֥ᄠ๔ᆠđMAC ࡼ۴ऌ DA ൞‫ڎ‬ა MAC ֹᆶ 0 ࠷թఖ֥ଽಸ௄஥ၛࠣ Flow Control + Register ᇏ֥ UPFD (Unicast Pause Frame Detect) ໊൞‫ڎ‬ᇂ 1č࡟ҩऎႵֆѬଢѓֹᆶ֥ᄠ๔ᆠĎটࣉྛ‫ݖ‬ੲb + PCF ࠷թఖ໊čFrame Filter Register ᇏ֥ Pass Control Frames ໊ [7:6]Ďॖؓ॥ᇅᆠ֥‫ݖ‬ੲၛֹࠣᆶ‫ݖ‬ੲࣉྛ + ॥ᇅb + + 10.2.2.4 ࢤ൬‫؟‬ᆠ֥Ҡቔԩ৘ + + ႮႿࢤ൬ඔऌުሑ෿৫ࠧॖႨđၹՎᆺေ FIFO ໃડđࣼॖၛཟఃᇏթԥᆠb + + 10.2.2.5 հ༂ԩ৘ + + ೂ‫ݔ‬ᄝՖ MAC ࢤ൬ EOF ඔऌᆭభ Rx FIFO ၘડđᄵࡼӁളഈၮѩ‫ש‬ఙᆜ۱ᆠbႮႿഈၮđሑ෿໊ + (RDESO[11]) ࡼᆷൕᆃ൞၂۱҆‫ٳ‬ᆠbೂ‫ݔ‬൐Ⴈ Operation Mode Register ᇏ֥ FTF (Flush Transmit FIFO) ‫ބ‬ + FUGF (Forward Undersized Good Frames) ໊൐ିཌྷႋ‫ିۿ‬đRx FIFO ॖ‫ݖ‬ੲհ༂ᆠ‫ཬݖބ‬ᆠbೂ‫ࢤࡼݔ‬൬ FIFO + ஥ᇂູᄝթԥሇ‫ؿ‬ଆൔ༯‫۽‬ቔđᄵॖ‫ݖ‬ੲѩ‫ש‬ఙ෮Ⴕհ༂ᆠb + + ᄝᆰ๙ଆൔ༯đೂ‫ݔ‬ᄝՖ Rx FIFO ‫؀‬౼ᆠ֥ SOF ൈđ‫ھ‬ᆠ֥ሑ෿‫ބ‬Ӊ؇ॖႨđᄵॖ‫ש‬ఙᆜ۱հ༂ᆠbDMA ॖ + ๙‫ݖ‬൐ିࢤ൬ᆠౢॢ໊টౢॢᆞᄝՖ FIFO ‫؀‬౼֥հ༂ᆠbಖު֞ႋႨ֥ඔऌԮൻࡼ๔ᆸđఃჅᆠࡼՖଽ҆‫؀‬ + ౼ѩ‫ש‬ఙbೂ‫ ݔ‬FIFO ॖႨđᄵॖၛఓ‫׮‬༯၂ᆠԮൻb + + 10.2.2.6 ࢤ൬ሑ෿ሳ + + ၛ෾ຩᆠࢤ൬ࢲඏൈđMAC ཟႋႨčDMA ҧĎൻԛࢤ൬ሑ෿bࢤ൬ሑ෿֥བྷ༥ඪૼა RDES0 ᇏ໊֥ [31:0] ཌྷ + ๝b + +ুᶈྐ༏॓࠯ 207 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +10.3 MAC ᇏ؎॥ᇅఖ + +MAC ଽ‫ނ‬ॖ๙‫ݖ‬۲ᇕ൙ࡱളӮ҂๝ᇏ؎b + +Interrupt Status ࠷թఖ૭ඍਔॖ֝ᇁ MAC ଽ‫ނ‬ളӮᇏ؎֥൙ࡱbॖ๙‫ࡼݖ‬ᇏ؎௠з࠷թఖᇏཌྷႋ֥௠з໊ᇂ 1 +টቅᆸ۲൙ࡱളӮᇏ؎b + +ᇏ؎࠷թఖ໊ࣇᆷൕ۲ᇕᇏ؎൙ࡱbсྶ‫؀‬౼ཌྷႋ֥ሑ෿࠷թఖ‫ބ‬ః෱࠷թఖҌିౢԢᇏ؎b২ೂđೂ‫ݔ‬ᇏ؎ +࠷թఖ໊֥ 3 ഡᇂູۚ‫׈‬௜đᄵᆷൕᄝ‫׈ו‬ଆൔ༯ࢤ൬֞ଊඌඔऌЇࠇຩ઎ߒྜᆠbсྶ‫؀‬౼ PMT Control +and Status ࠷թఖҌିౢԢՎᇏ؎൙ࡱb + +10.4 MAC ֹᆶ֥‫ݖ‬ੲ + +ֹᆶ‫ݖ‬ੲࡼ࡟Ұ෮Ⴕࢤ൬֥ᆠ֥ଢѓֹᆶ‫ބ‬ჷֹᆶѩཌྷႋБֹۡᆶ‫ݖ‬ੲሑ෿bֹᆶ࡟ҰࠎႿႋႨӱ྽࿊ᄴ֥҂ +๝ҕඔčᆠ‫ݖ‬ੲ࠷թఖĎbߎॖၛ്љ‫ݖ‬ੲ֥ᆠğ‫؟‬ѬᆠࠇܼѬᆠbֹᆶ‫ݖ‬ੲ൐Ⴈ֥໾৘ (MAC) ֹᆶࣉྛֹᆶ࡟ +Ұb + +10.4.1 ֆѬଢѓֹᆶ‫ݖ‬ੲ + +MAC ᆦӻ‫؟‬ղ 8 ۱ႨႿֆѬປૅ‫ݖ‬ੲ֥ MAC ֹᆶbೂ‫ݔ‬࿊ᄴປૅ‫ݖ‬ੲč‫໊گ‬ᆠ‫ݖ‬ੲ࠷թఖᇏ֥ bit[1]ĎđMAC +߶ࡼࢤ൬֥ֆѬֹᆶ֥෮Ⴕ 48 ໊აщӱ֥ MAC ֹᆶࣉྛбࢠটಒ‫ק‬൞‫ڎ‬௄஥bଏಪ౦ঃ༯đ൓ᇔ൐ି +EMACADDR0đః෱ֹᆶ EMACADDR0 ~ EMACADDR7 ᄵ๙‫ݖ‬ֆ‫֥׿‬൐ି໊ࣉྛ࿊ᄴbࡼః෱ֹᆶ +(EMACADDR0 ~ EMACADDR7) ֥۲۱ሳࢫაࢤ൬֥ཌྷႋ DA ሳࢫࣉྛбࢠൈđॖၛࡼ࠷թఖᇏཌྷႋ֥௠зሳ +ࢫ॥ᇅ໊ᇂ 1 ট௠з‫ھ‬ሳࢫbᆃႵᇹႿ DA ֥ቆֹᆶ‫ݖ‬ੲb + +10.4.2 ‫؟‬Ѭଢѓֹᆶ‫ݖ‬ੲ + +ॖ๙‫ࡼݖ‬ᆠ‫ݖ‬ੲ࠷թఖᇏ֥ PAM (Pass All MulticastĎ໊ᇂ 1đࡼ MAC щӱູ๙‫ݖ‬෮Ⴕ‫؟‬Ѭᆠbೂ‫ ݔ‬PAMčPass +All MulticastĎ໊‫໊گ‬đMAC ࡼ۴ऌᆠ‫ݖ‬ੲ࠷թఖᇏ֥ bit[2]čсྶЌӻ‫໊گ‬ᆴĎᆳྛؓ‫؟‬Ѭֹᆶ֥‫ݖ‬ੲb + +ᄝປૅ‫ݖ‬ੲଆൔ༯đࡼ‫؟‬Ѭֹᆶაщӱ֥ MAC ଢѓֹᆶ࠷թఖ EMACADDR0 ~ EMACADDR7 ࣉྛбࢠbቆֹ +ᆶ‫ݖ‬ੲ္൳֞ᆦӻb + +10.4.3 ܼѬֹᆶ‫ݖ‬ੲ + +ᄝଏಪଆൔ༯đMAC ҂‫ݖ‬ੲ಩‫ܼޅ‬Ѭᆠb֌൞đೂ‫ࡼݔ‬ᆠ‫ݖ‬ੲ࠷թఖᇏ֥ DBF (Disable Broadcast Frames) ໊ +ᇂ 1 টࡼ MAC щӱູऋध෮ႵܼѬᆠđᄵ߶‫ש‬ఙ಩‫ܼޅ‬Ѭᆠb + +10.4.4 ֆѬჷֹᆶ‫ݖ‬ੲ + +MAC ߎॖၛ۴ऌࢤ൬֥ᆠ֥ჷֹᆶሳ‫؍‬টᆳྛປૅ‫ݖ‬ੲbଏಪ౦ঃ༯đAFM ࡼ SA ሳ‫؍‬ა SA ࠷թఖᇏщӱ֥ +ᆴࣉྛ‫ݖ‬ੲbॖ๙‫ࡼݖ‬ཌྷႋ࠷թఖᇏ֥ bit[30] ᇂ 1đটࡼ MAC ֹᆶ࠷թఖ [1:3] ஥ᇂູЇ‫ ݣ‬SA ‫ط‬҂൞ DA ࣉ +ྛбࢠbջ SA ֥ቆֹᆶ‫ݖ‬ੲ္൳֞ᆦӻbೂ‫ݔ‬ᆠ‫ݖ‬ੲ࠷թఖᇏ֥ SAF (Source Address Filter Enable) ໊ᇂ 1đ +ᄵ MAC ࡼ‫ש‬ఙໃ๙‫ ݖ‬SA ‫ݖ‬ੲ֥ᆠb‫ڎ‬ᄵđSA ‫ݖ‬ੲ֥ࢲ‫ࡼݔ‬๙‫ࢤݖ‬൬ሑ෿ሳᇏ֥ሑ෿໊۳ԛčབྷ࡮і +10-11Ďb + +SAF (Source Address Filter Enable) ໊ᇂ 1 ൈđؓ SA ‫ݖ‬ੲ‫ ބ‬DA ‫ݖ‬ੲ֥ࢲ‫ྛࣉݔ‬აᄎෘđၛथ‫ק‬൞‫ླڎ‬ေሇ‫ؿ‬ +ᆠbᆃၩ໅ሢ಩‫ޅ‬၂۱‫ݖ‬ੲໃ๙‫שࡼ׻ݖ‬ఙᆠbਆ۱‫ݖ‬ੲсྶ‫׻‬๙‫ݖ‬đҌିࡼᆠሇ‫֞ؿ‬ႋႨb + +10.4.5 ّཟ‫ݖ‬ੲҠቔ + +ؓႿଢѓֹᆶ‫ބ‬ჷֹᆶ‫ݖ‬ੲđॖᄝቋᇔൻԛൈ࿊ᄴཌྷّ֥‫ݖ‬ੲ௄஥ࢲ‫ݔ‬bᆃ‫ٳ‬љႮᆠ‫ݖ‬ੲ࠷թఖᇏ֥ DAIF ‫ބ‬ +SAIF ໊॥ᇅbDAIF ໊๝ൈൡႨႿֆѬ‫؟ބ‬Ѭ DA ᆠbᄝّཟ‫ݖ‬ੲҠቔᇏđ֒ DAIF ໊ᇂ 1 ൈđࡼّሇֆѬ/‫؟‬Ѭ +ଢѓֹᆶ‫ݖ‬ੲ֥ࢲ‫ݔ‬bোරֹđ֒ SAIF ໊ᇂ 1 ൈđࡼّሇֆѬ SA ‫ݖ‬ੲ֥ࢲ‫ݔ‬b + +ুᶈྐ༏॓࠯ 208 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +༯૫ਆ۱іοᅶࢤ൬ᆠ֥ো྘߸ሹਔଢѓֹᆶ‫ބ‬ჷֹᆶ‫ݖ‬ੲb + і 10­1. ଢѓֹᆶ‫ݖ‬ੲ + +ᆠো྘ PM PF DAIF PAM DB DA ‫ݖ‬ੲࢲ‫ݔ‬ + ๙‫ݖ‬ + 1 X X X X ๙‫ݖ‬ + ҂๙‫ݖ‬ +ܼѬ 0 X X X 0 ๙‫ݖ‬෮Ⴕᆠ + ປૅ/ቆ‫ݖ‬ੲ௄஥ൈ๙‫ݖ‬ + 0 X X X 1 ປૅ/ቆ‫ݖ‬ੲ௄஥ൈ҂๙‫ݖ‬ + ປૅ/ቆ‫ݖ‬ੲ௄஥ൈ๙‫ݖ‬ + 1 X X X X ປૅ/ቆ‫ݖ‬ੲ௄஥ൈ҂๙‫ݖ‬ + ๙‫ݖ‬෮Ⴕᆠ + 0 X 0 X X ๙‫ݖ‬෮Ⴕᆠ + ປૅ/ቆ‫ݖ‬ੲ௄஥ൈ๙‫ݖ‬đѩᄝ PCF = 0x ൈ‫ש‬ఙᄠ๔ +ֆѬ 0 X 1 X X ॥ᇅᆠ + ປૅ/ቆ‫ݖ‬ੲ௄஥ൈ๙‫ݖ‬đѩᄝ PCF = 0x ൈ‫ש‬ఙᄠ๔ + 0 1 0 X X ॥ᇅᆠ + ປૅ/ቆ‫ݖ‬ੲ௄஥ൈ҂๙‫ݖ‬đѩᄝ PCF = 0x ൈ‫ש‬ఙᄠ + 0 1 1 X X ๔॥ᇅᆠ + ປૅ/ቆ‫ݖ‬ੲ௄஥ൈ҂๙‫ݖ‬đѩᄝ PCF = 0x ൈ‫ש‬ఙᄠ + 1 X X X X ๔॥ᇅᆠ + + X X X 1 X + + 0 X 0 0 X + +‫؟‬Ѭ 0 1 0 0 X + + 0 X 1 0 X + + 0 1 1 0 X + +і 10-1 ᇏđMAC ᆠ‫ݖ‬ੲ࠷թఖᇏ֥‫ݖ‬ੲҕඔೂ༯: + +ᆠো྘ඪૼ ҕඔഡᇂ +PMğ +PFğ Pass All Multicast/ ๙‫ݖ‬෮ႵቆѬ 1: ᇂ1 +DAIFğ Perfect Filter/ ປૅ‫ݖ‬ੲ +PAMğ Destination Address Inverse Filtering/ଢѓֹᆶّ‫ݖ‬ੲ 0: ౢਬ +DBğ Pass All Multicast/๙‫ݖ‬෮ႵቆѬ + Disable Broadcast Frames/ܱоܼѬᆠ + + і 10­2. ჷֹᆶ‫ݖ‬ੲ + +ᆠো྘ PM SAIF SAF SA ‫ݖ‬ੲҠቔ +ֆѬ + 1 X X ๙‫ݖ‬෮Ⴕᆠ + + 0 0 0 ປૅ /ቆ‫ݖ‬ੲ௄஥ൈ๙‫ݖ‬đ֌҂‫ש‬ఙໃ๙‫֥ݖ‬ᆠ + + 0 1 0 ປૅ /ቆ‫ݖ‬ੲ௄஥ൈ҂๙‫ݖ‬đ֌҂‫ש‬ఙໃ๙‫֥ݖ‬ᆠ + + 0 0 1 ປૅ /ቆ‫ݖ‬ੲఖ௄஥ൈ๙‫ݖ‬ѩࡼ҂๙‫֥ݖ‬ᆠ‫ש‬ఙ + + 0 1 1 ປૅ /ቆ‫ݖ‬ੲఖ௄஥ൈ҂๙‫ݖ‬ѩࡼ҂๙‫֥ݖ‬ᆠ‫ש‬ఙ + +і 10-2 ᇏđMAC ᆠ‫ݖ‬ੲ࠷թఖ֥‫ݖ‬ੲҕඔೂ༯ğ + +ᆠো྘ඪૼ ҕඔഡᇂ +PM: Pass All Multicast/๙‫ݖ‬෮ႵቆѬ +SAF: Source Address Filtering/ჷֹᆶ‫ݖ‬ੲ 1: ᇂ1 +SAIF: Source Address Inverse Filtering/ჷֹᆶّཟ‫ݖ‬ੲ + 0: ౢਬ + + X: ໭ܱ + +ুᶈྐ༏॓࠯ 209 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +10.4.6 ‫ؿ֥ݺ‬ෂᆠაࢤ൬ᆠ + +ೂ‫ݔ‬ᆠӮ‫ؿۿ‬ෂđᄵࡼ‫ؿ‬ෂ֥ᆠ൪ູo‫ݺ‬ᆠpbߐओ߅ඪđೂ‫ݔ‬ᆠ‫ؿ‬ෂ‫ݖ‬ӱીႵၹູၛ༯հ༂‫ط‬ᇏᆸđᄵಪູ‫ؿ‬ +ෂ֥ᆠ൞‫ݺ‬ᆠğ + + • Jabber ӑൈ + • ໭ᄛѯ /ᄛѯ‫ש‬ാ + • ࿼ӾԊ๬ + • ᆠ༯ၮ + • ‫ݖ‬؇࿼Ӿ + • ‫ݖ‬؇Ԋ๬ +ೂ‫ݔ‬҂թᄝၛ༯հ༂đᄵಪູࢤ൬ᆠ൞o‫ݺ‬ᆠpğ + • CRC հ༂ + • ζᆠč؋Ⴟ 64 ሳࢫĎ + • ؓఊհ༂čࣇཋ 10/100 Mbit/sĎ + • Ӊ؇հ༂čࣇཋ٤ো྘ᆠĎ + • ӑԛЇቋննཬٓຶčࣇཋ٤ো྘ᆠđӑ‫ݖ‬ቋննཬĎ + • MII_RXER ൻೆհ༂ +ቋնᆠնཬ౼थႿᆠো྘đೂ༯ğ + • ໭ѓ࠺ᆠ֥ቋննཬ = 1518 + • VLAN ᆠ֥ቋննཬ = 1522 + +10.5 EMAC_MTLčMAC ԮൻҪĎ + +MAC ԮൻҪิ‫ ܂‬FIFO թԥఖটߏԊ‫ࢫטބ‬ႋႨ༢๤թԥఖ‫ ބ‬MAC ᆭࡗ֥ᆠb෱ߎॖၛᄝႋႨൈᇒთ‫ ބ‬MAC +ൈᇒთᆭࡗԮൻඔऌbMTL ҪऎႵਆ่ඔऌਫ਼ࣥđࠧ‫ؿ‬ෂਫ਼ࣥ‫ࢤބ‬൬ਫ਼ࣥbචཟඔऌਫ਼໊ࣥॺູ 32đҐႨࡥֆ +֥ FIFO ླྀၰҠቔb + +10.6 PHY ࢤ१ + +DMA ‫ބ‬ᇶࠏ౺‫׮‬ӱ྽๙‫ݖ‬ၛ༯ਆ۱ඔऌࢲ‫ྛࣉܒ‬๙ྐğ + • ॥ᇅ‫ބ‬ሑ෿࠷թఖ (CSR) + • ૭ඍ‫ژ‬ਙі‫ބ‬ඔऌߏթ + +བྷ࡮ᅣࢫ࠷թఖਙі‫৽ބ‬і૭ඍ‫ژ‬b + +10.6.1 MIIčࢺᇉ‫׿‬৫ࢤ१Ď + +ࢺᇉ‫׿‬৫ࢤ१ (MII) ‫ק‬ၬਔ 10 Mbit/s ‫ ބ‬100 Mbit/s ֥ඔऌԮൻ෎ੱ༯ MAC ሰҪა PHY ᆭࡗ֥޺৵b + +ুᶈྐ༏॓࠯ 210 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +10.6.1.1 MII ა PHY ࡗ֥ࢤ१ྐ‫ݼ‬ + +MII ࢤ१ྐ‫ݼ‬ೂ๭ 10-3 ෮ൕb + + ๭ 10­3. MII ࢤ१ + +MII ࢤ१ྐ‫ݼ‬ඪૼğ + + • MII_TX_CLKğTx ൈᇒྐ‫ݼ‬b‫ ྛࣉ܂ิݼྐھ‬Tx ඔऌԮൻൈ֥ҕॉൈ྽b௔ੱ‫ູٳ‬ਆᇕğ෎ੱູ 10 + Mbit/s ൈູ 2.5 MHzĠ෎ੱູ 100 Mbit/s ൈູ 25 MHzb + + • MII_TXD[3:0]ğ‫ؿ‬ෂඔऌྐ‫ݼ‬b‫ݼྐھ‬൞ 4 ۱၂ቆ֥ඔऌྐ‫ݼ‬đႮ MAC ሰҪ๝҄౺‫׮‬đᄝ MII_TX_EN ྐ + ‫ݼ‬ႵིൈҌູႵིྐ‫ݼ‬čႵིඔऌĎbMII_TXD[0] ູቋ֮Ⴕ໊ིđMII_TXD[3] ູቋۚႵ໊ིbMII_TX_EN + ྐ‫ູ֮ݼ‬ൈđ‫ؿ‬ෂඔऌ҂߶ؓ PHY Ӂള಩‫ޅ‬႕ཙb + + • MII_TX_ENğ‫ؿ‬ෂඔऌ൐ିྐ‫ݼ‬b‫ݼྐھ‬іൕ MAC ֒భᆞᆌؓ MII ‫ؿ‬ෂ϶ሳࢫ (4 bits)b‫ݼྐھ‬сྶაБ + ๨֥భ϶ሳࢫࣉྛ๝҄ (MII_TX_CLK)đѩᄝ෮Ⴕր‫ؿ‬ෂ֥϶ሳࢫन‫ؿ‬ෂ֞ MII ൈсྶЌӻ๝҄b + + • MII_RX_CLKğRX ൈᇒྐ‫ݼ‬b‫ ྛࣉ܂ิݼྐھ‬RX ඔऌԮൻൈ֥ҕॉൈ྽b௔ੱ္‫ູٳ‬ਆᇕğ෎ੱູ 10 + Mbit/s ൈູ 2.5 MHzĠ෎ੱູ 100 Mbit/s ൈູ 25 MHzb + + • MII_RXD[3:0]ğࢤ൬ඔऌྐ‫ݼ‬b‫ݼྐھ‬൞ 4 ۱၂ቆ֥ඔऌྐ‫ݼ‬đႮ PHY ๝҄౺‫׮‬đᄝ MII_RX_DV ྐ‫ݼ‬Ⴕ + ིൈҌູႵིྐ‫ݼ‬čႵིඔऌĎbMII_RXD[0] ູቋ֮Ⴕ໊ིđMII_RXD[3] ູቋۚႵ໊ིb֒ MII_RX_DV ࣌ + ᆸaMII_RX_ER ൐ିൈđห‫ ֥ק‬MII_RXD[3:0] ᆴႨႿսіটሱ PHY ֥ห‫ྐק‬༏b + + • MII_RX_DVğࢤ൬ඔऌႵིྐ‫ݼ‬b‫ݼྐھ‬іൕ PHY ֒భᆞᆌؓ MII ࢤ൬ၘ߫‫گ‬ѩࢳ઒֥϶ሳࢫb‫ݼྐھ‬с + ྶა߫‫گ‬ᆠ֥๨϶ሳࢫࣉྛ๝҄Ⴟ MII_RX_CLKđѩ౏၂ᆰЌӻ๝҄֞߫‫گ‬ᆠ֥ቋު϶ሳࢫb‫ݼྐھ‬сྶ + ᄝቋު϶ሳࢫෛުֻ֥၂۱ൈᇒᇛ௹ᆭభ࣌ᆸbູਔᆞಒֹࢤ൬ᆠđMII_RX_DV ྐ‫ݼ‬сྶᄝൈࡗٓຶഈ + ‫ۂݤ‬ေࢤ൬֥ᆠđఃष൓ൈࡗ҂֤ӾႿ SFD ሳ‫؍‬ԛགྷ֥ൈࡗb + + • MII_CRSğᄛѯᆍ๐ྐ‫ݼ‬b֒‫ؿ‬ෂࠇࢤ൬ࢺᇉԩႿ٤ॢ༽ሑ෿ൈđႮ PHY ൐ି‫ݼྐھ‬b‫ؿ‬ෂ‫ࢤބ‬൬ࢺᇉ + नԩႿॢ༽ሑ෿ൈđႮ PHY ࣌ᆸ‫ݼྐھ‬bPHY сྶಒЌ MII_CS ྐ‫ݼ‬ᄝԊ๬่ࡱ༯ЌӻႵིሑ෿b‫ྐھ‬ + ‫ݼ‬໭ླა Tx ‫ ބ‬Rx ൈᇒЌӻ๝҄bᄝಆච‫۽‬ଆൔ༯đ‫ݼྐھ‬ીၩၬb + + • MII_COLğԊ๬࡟ҩྐ‫ݼ‬b࡟ҩ֞ࢺᇉഈթᄝԊ๬ުđPHY сྶ৫ࠧ൐ିԊ๬࡟ҩྐ‫ݼ‬đѩ౏ᆺေթᄝԊ + ๬่ࡱđԊ๬࡟ҩྐ‫ݼ‬сྶЌӻႵིሑ෿b‫ݼྐھ‬໭ླა Tx ‫ ބ‬Rx ൈᇒЌӻ๝҄bᄝಆච‫۽‬ଆൔ༯đ‫ھ‬ + ྐ‫ݼ‬ીၩၬb + +ুᶈྐ༏॓࠯ 211 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + • MII_RX_ERğࢤ൬հ༂ྐ‫ݼ‬b‫ݼྐھ‬сྶЌӻ၂۱ࠇ‫؟‬۱ᇛ௹ (MII_RX_CLK)đՖ‫ط‬ཟ MAC ሰҪᆷൕᄝᆠ + ֥ଖԩ࡟ҩ֞հ༂b + + • MDIO ‫ ބ‬MDCğܵ৘ඔऌൻೆൻԛଆॶ‫ܵބ‬৘ඔऌൈᇒbᆃਆ۱ྐ‫ܒݼ‬Ӯਔ‫ ކژ‬IEEE 802.3 ѓሙ֥ၛ෾ + ຩԱྛሹཌđႨႿࡼ॥ᇅ‫ބ‬ඔऌྐ༏Ԯൻ֞ PHYbབྷ࡮ Station Management Agent (SMA) Interfaceb + +10.6.1.2 MII ൈᇒ + +ᄝ MII ൈᇒଆൔ༯đMII ა PHY ֥ࢤ१Ⴕ Tx ‫ ބ‬Rx ਆ۱ٚཟ֥ൈᇒđMII_TX_CLK ႨႿ๝҄ Tx ֥ඔऌđ +MII_RX_CLK ႨႿ๝҄ Rx ֥ඔऌbఃᇏ MII_RX_CLK ൈᇒႮ PHY ิ‫܂‬đMII_TX_CLK Ⴎྉோଽ֥҆ PLL ิ‫ࠇ܂‬ +൞ྉோຓ֥҆ࣖᆒิ‫܂‬b๭ 10-4 ֥஥ᇂऎุҕॉ࠷թఖਙіᇏൈᇒཌྷܱ֥࠷թఖb + + ๭ 10­4. MII ൈᇒ + +10.6.2 RMIIčࣚࡥࢺᇉ‫׿‬৫ࢤ१Ď + +RMII ࢤ१ྐ‫ݼ‬ೂ๭ 10-5 ෮ൕb + +ুᶈྐ༏॓࠯ 212 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + ๭ 10­5. RMII ࢤ१ + +10.6.2.1 RMII ࢤ१ྐ‫ݼ‬૭ඍ + +ࣚࡥࢺᇉ‫׿‬৫ࢤ१ (RMII) ܿٓࢆ֮ਔ 10 Mbit/s ࠇ 100 Mbit/s ༯ັ॥ᇅఖၛ෾ຩຓഡაຓ҆ PHY ࡗ֥ႄ࢖ඔb +۴ऌ IEEE 802.3u ѓሙđMII Їও 16 ۱Ї‫ݣ‬ඔऌ‫ބ‬॥ᇅྐ‫֥ݼ‬ႄ࢖bRMII ܿٓࡼႄ࢖ඔࡨഒູ 7 ۱čႄ࢖ඔࡨ +ഒ 62.5%Ďb +RMII ऎႵၛ༯หྟğ + + • ᆦӻ 10 Mbit/s ‫ ބ‬100 Mbit/s ֥ᄎྛ෎ੱ + • ҕॉൈᇒ௔ੱсྶ൞ 50 MHz + • ཌྷ๝֥ҕॉൈᇒсྶՖຓ҆ิ‫܂‬۳ MAC ‫ބ‬ຓ҆ၛ෾ຩ PHYbPHY ิ‫܂‬ਔ‫׿‬৫֥ 2 ໊ॺ֥‫ؿ‬ෂ‫ࢤބ‬൬ඔ + + ऌ֥ਫ਼ࣥb + +10.6.2.2 RMII ൈᇒ + +RMII ൈᇒೂ๭ 10-6 ෮ൕb + +ুᶈྐ༏॓࠯ 213 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + ๭ 10­6. RMII ൈᇒ + +10.6.3 Station Management Agent (SMA) ࢤ१ + +ೂ๭ 10-4 ෮ൕđMAC ๙‫ ݖ‬MDC ‫ ބ‬MDIO ྐ‫ࡼݼ‬॥ᇅ‫ބ‬ඔऌྐ༏Ԯൻ֞ PHYbቋնൈᇒ௔ੱູ 2.5 MHzbൈ +ᇒႮႋႨൈᇒ๙‫ݖ‬ൈᇒ‫ٳ‬௔ఖ‫ٳ‬௔Ӂളbᄝ๙‫ ݖ‬MDIO ֥ཿ/‫؀‬Ҡቔ௹ࡗđPHY ‫ؿ‬ෂ࠷թఖඔऌb‫ݼྐھ‬ა +MDC ൈᇒ๝҄౺‫׮‬b +EMII ֹᆶ࠷թఖ‫ ބ‬EMII ඔऌ࠷թఖབྷ࡮࠷թఖਙіb + +10.6.4 RMII ࢤ१ൈ྽ေ౰ + +Чᅣࢫབྷ༥ඪૼਔ RMII ࢤ१֥ൈ྽ေ౰b + + ๭ 10­7. ࢤ൬ඔऌൈ྽๭ + + і 10­3. ࢤ൬ඔऌൈ྽ေ౰ + + ൈ྽ҕඔ ૭ඍ ቋཬᆴ ‫྘ׅ‬ᆴ ቋնᆴ ֆ໊ + tCY C ൈᇒᇛ௹ (Clock cycle) 20 20 20 ns + tSU ࡹ৫ൈࡗ (Setup time) 4 ⚶ ⚶ ns + tH Ќӻൈࡗ (Hold time) 1 ⚶ ⚶ ns + tID ൻೆ࿼Ӿ (Input delay) 3 5 8 ns + +ুᶈྐ༏॓࠯ 214 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + ๭ 10­8. ‫ؿ‬ෂඔऌൈ྽๭ + + і 10­4. ‫ؿ‬ෂඔऌൈ྽ေ౰ + + ൈ྽ҕඔ ૭ඍ ቋཬᆴ ‫྘ׅ‬ᆴ ቋնᆴ ֆ໊ + tCY C ൈᇒᇛ௹ (Clock cycle) 20 20 20 ns + tSU ࡹ৫ൈࡗ (Setup time) 4 ⚶ ⚶ ns + tH Ќӻൈࡗ (Hold time) 1 ⚶ ⚶ ns + tOD ൻԛ࿼Ӿ (Output delay) 6 9 12 ns + +10.7 ၛ෾ຩ DMA หྟ + +DMA ऎႵ‫׿‬৫֥‫ؿ‬ෂ‫ࢤބ‬൬ႄౣၛࠣ॥ᇅ‫ބ‬ሑ෿࠷թఖֹᆶbԮൻႄౣࡼඔऌՖ༢๤ଽթԮൻ֞ഡС؊१ +(MTL)đ‫ࢤط‬൬ႄౣࡼඔऌՖഡС؊१Ԯൻ֞༢๤ଽթb॥ᇅఖ൐Ⴈ૭ඍ‫ژ‬đၛቋഒ֥ᇶࠏ CPU ‫ۄ‬ყটႵֹི +ࡼඔऌՖჷ၍‫֞׮‬ଢֹ֥bDMA ႨႿၛඔऌЇູᇶ֥ඔऌԮൻđೂၛ෾ຩᇏ֥ᆠb॥ᇅఖॖၛ஥ᇂູᄝᆞӈ౦ +ঃ༯‫ؿ‬ᇏ؎۳ᇶ CPUđ২ೂປӮᆠ‫ؿ‬ෂࠇࢤ൬đࠇ‫ؿ‬ളհ༂ൈb + +10.8 ৽і૭ඍ‫ژ‬ + +Чࢫࢺക৽і‫ބ‬૭ඍ‫ܒࢲژ‬bૄ۱৽іႮ 8 ۱ word ቆӮb + +10.8.1 ‫ؿ‬ෂ૭ඍ‫ژ‬ + +‫ؿ‬ෂ৽іࢲ‫ܒ‬ೂ๭ 10-9 ෮ൕbі 10-5 ᇀі 10-10 ູ৽і૭ඍ‫ژ‬ඪૼb + + 31 0 + +TDES0 OWN Ctrl/status Status + TTSE [6:3] [2:0] + TTSS + Ctrl[30:26] Ctrl[24:18] Status[16:7] + Reserved +TDES1 Ctrl Transmit Buffer Size[12:0] + [31:29] + +TDES2 Buffer Address [31:0] + +TDES3 Next Descriptor Address[31:0] + +TDES4 Reserved + +TDES5 Reserved + +TDES6 Transmit Frame Timestamp Low[31:0] + +TDES7 Transmit Frame Timestamp High[31:0] + + ๭ 10­9. ‫ؿ‬ෂ૭ඍ‫ژ‬ + +ুᶈྐ༏॓࠯ 215 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + і 10­5. ‫ؿ‬ෂ૭ඍ‫ ژ‬0 (TDES0) + +໊ ଁ଀ ૭ඍ +[31] ‫໊ھ‬ᇂ 1 ൈđіൕ૭ඍ‫ژ‬Ⴎ DMA ႚႵb‫໊گ‬ൈđіൕ૭ඍ‫ژ‬Ⴎ +[30] OWN: Own Bit ᇶࠏႚႵb֒ DMA ປӮᆠԮൻࠇ‫ٳ‬஥ᄝ૭ඍ‫ژ‬ᇏ֥ߏթູॢൈđ +[29] DMA ࡼౢԢ‫໊ھ‬bᄝഡᇂඋႿ๝၂ᆠ֥෮Ⴕު࿃૭ඍ‫ژ‬ᆭުđႋ +[28] IC: Interrupt on Completion ഡᇂᆠֻ֥၂۱૭ඍ‫֥ژ‬॥ᇅ໊bᆃх૧ਔᄝࠆ౼૭ඍ‫ބژ‬౺‫׮‬ +[27] LS: Last Segment ӱ྽ഡᇂ॥ᇅ໊ᆭࡗ֥ॖି‫ؿ‬ള֥ࣩᆚb +[26] FS: First Segment ᇂ 1 ުđ‫໊ھ‬ᄝ‫ؿ‬ෂ֒భᆠᆭުഡᇂ‫ؿ‬ෂᇏ؎ (Operation Mode +[25] DC: Disable CRC Register[0])b‫ࣇ໊ھ‬ᄝ໊ TDES0 [29] ᇂ 1 ൈႵིb +[24] ᇂ 1 ൈđ‫໊ھ‬іൕߏթ౵ᇏЇ‫ھݣ‬ᆠ֥ቋު၂‫؍‬b֒‫໊ھ‬ᇂ 1 ൈđ + DP: Disable Pad TDES1 ᇏ֥ TBS1 ࠇ TBS2 ሳ‫֥؍‬ᆴ҂ູਬb +[23:22] TTSE: Transmit Timestamp ᇂ 1 ൈđ‫໊ھ‬іൕߏթ౵ᇏЇ‫ݣ‬ᆠֻ֥၂‫؍‬b + Enable ‫໊ھ‬ᇂ 1 ൈđMAC ҂߶ᄝ‫ؿ‬ෂᆠ֥ଌແ‫ࡆڸ‬࿖ߌ಺Ⴥ཮ဒ (CRC)b +[21] CRCR: CRC Replacement ᆃࣇᄝ໊ TDES0 [28] ᇂ 1 ൈႵིb +[20] Control ᇂ 1 ൈđMAC ҂߶ሱ‫׮‬ᄝ؋Ⴟ 64 ሳࢫ֥ᆠު૫ሱ‫׮‬เࡆ paddingb + ֒‫໊گ໊ھ‬ൈđDMA ሱ‫ ࡼ׮‬padding ‫ ބ‬CRC เࡆ֞؋Ⴟ 64 ۱ሳ + CIC: Checksum Insertion ࢫ֥ᆠᇏđѩ౏໭ં DC (TDES0 [27]) ໊֥ሑ෿ೂ‫ޅ‬đ‫߶׻‬เࡆ + Control CRC ሳ‫؍‬bᆺႵ໊֒ TDES0 [28] ᇂ 1 ൈҌႵིb + ᇂ 1 ൈđ‫໊ھ‬൐ି૭ඍ‫ژ‬ႄႨ֥‫ؿ‬ෂᆠ֥ IEEE1588 ႗ࡱൈࡗՄb + TER: Transmit End of Ring ‫ھ‬ሳ‫ࣇ؍‬ᄝ໊ TDES0 [28] ᇂ 1 ൈႵིb + TCH: Second Address ᇂ 1 ൈđMAC Ⴈᇗྍ࠹ෘ֥ CRC ሳࢫูߐ‫ؿ‬ෂ֥ඔऌЇ֥ቋު + Chained ඹ۱ሳࢫbᇶࠏႋಒЌ CRC ሳࢫᄝࡼေ‫ؿ‬ෂ֥ᆠ֥ߏթᇏb֒॥ + ᇅ໊ (TDES0 [28]) ᇂ 1 ൈđ‫໊ھ‬Ⴕིbਸ਼ຓđᆺႵ໊֒ TDES0 [27] + ᇂ 1 ൈҌࣉྛ CRC ูߐb + ᆃ໊ུ॥ᇅ཮ဒ‫࠹֥ބ‬ෘ‫ބ‬Ҭೆbၛ༯ਙі૭ඍਔ໊щ઒ğ + + • 2’b00ğܱо཮ဒ‫ބ‬Ҭೆb + • 2’b01ğࣇ൐ି IP Б๨཮ဒ‫࠹ބ‬ෘ‫ބ‬Ҭೆb + • 2’b10ğ൐ି IP Б๨཮ဒ‫ބ‬ၛࠣႵི‫ڵ‬ᄛ཮ဒ֥࠹ෘ‫ބ‬Ҭೆđ + + ເБ๨཮ဒ҂ᄝ႗ࡱᇏ࠹ෘb + • 2’b11ğ൐ି IP Б๨཮ဒ‫ބ‬ၛࠣႵི‫ڵ‬ᄛ཮ဒ֥࠹ෘ‫ބ‬Ҭೆđ + + ֌൞ເБ๨཮ဒᄝ႗ࡱᇏ࠹ෘb + ֒॥ᇅ໊ TDES0 [28] ᇂ 1 ൈđՎሳ‫؍‬Ⴕིb + ᇂ 1 ൈđ‫໊ھ‬іൕ૭ඍ‫ژ‬ਙіၘղ֞ቋު၂۱৽і૭ඍ‫ژ‬bDMA + ْ߭֞৽і֥ࠎֹᆶđԷࡹ၂۱૭ඍ‫ߌژ‬b + ᇂ 1 ൈđ‫໊ھ‬ᆷൕ૭ඍ‫ژ‬ᇏֻ֥‫ؽ‬۱ֹᆶ൞༯၂۱૭ඍ‫ֹژ‬ᆶb֒ + TDES0 [20] ᇂ 1 ൈđTBS2 (TDES1 [28:16]) ൞၂۱o໭ܱpᆴbTDES0 + [21] Ⴊ༵Ⴟ TDES0 [20]bՎ໊сྶᇂ 1b + +ুᶈྐ༏॓࠯ 216 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +໊ ଁ଀ ૭ඍ + ᇂ 1 ൈđᆃ໊ུ౨౰ MAC ᄝԮൻᆠᆭభյഈ VLAN ѓ࠺ࠇ౼ཨ + VLIC: VLAN Insertion ѓ࠺bೂ‫ݔ‬ᆠФյഈ VLAN ѓ࠺đᄵ MAC ߶ሱ‫׮‬ᇗྍ࠹ෘѩูߐ +[19:18] CRC ሳࢫbၛ༯ູᆃ໊ུ֥ඪૼğ + + Control • 2’b00ğ҂ࡆഈ VLAN ѓ࠺b + • 2’b01ğᄝԮൻᆭభಀ‫ ו‬VLAN ѓ࠺đᆺႨႿ VLAN ᆠb + TTSS: Transmit • 2’b10ğҬೆ VLAN ѓ࠺đѓ࠺֥ᆴᄝ VLAN ѓ࠺Ҭೆ‫ูބ‬ +[17] + ߐ࠷թఖᇏ஥ᇂb + Timestamp Status • 2’b11ğႨ VLAN ѓ࠺Ҭೆ‫࠷ߐูބ‬թఖᇏ֥ѓ࠺ᆴูߐᆠ +[16] IHE: IP Header Error + ֒ᇏ֥ VLAN ѓ࠺b‫ھ‬࿊ཛᆺିႨႿ VLAN ᆠb +[15] ES: Error Summary ‫ھ‬ሳ‫؍‬Ⴈቔሑ෿໊ၛᆷൕູ෮૭ඍ֥‫ؿ‬ෂᆠѽࠆਔ၂۱ൈࡗՄb + ֒‫໊ھ‬ᇂ 1 ൈđTDES2 ‫ ބ‬TDES3 ऎႵѽࠆ‫ؿ‬ෂᆠ֥ൈࡗՄᆴb‫ھ‬ +[14] JT: Jabber Timeout ሳ‫ࣇ؍‬ᄝ૭ඍ‫֥ژ‬॥ᇅ໊ TDES0 [29] ᇂ 1 ൈႵིb +[13] FF: Frame Flushed ᇂ 1 ൈđ‫໊ھ‬ᆷൕ MAC ‫ؿ‬ෂఖᄝ IP Б๨ᇏ࡟ҩ֞հ༂b‫ؿ‬ෂఖ +[12] IPE: IP Payload Error ࡟Ұ IPv4 ඔऌЇᇏ֥Б๨Ӊ؇აՖႋႨӱ྽ࢤ൬֥֞Б๨ሳࢫ֥ +[11] LOC: Loss of Carrier ඔਈđೂ‫ݔ‬҂௄஥đᄵᆷൕհ༂ሑ෿bؓႿ IPv6 ᆠđೂ‫ݔ‬Б๨Ӊ؇ +[10] NC: No Carrier ҂൞ 40 ۱ሳࢫđᄵᆷൕБ๨հ༂bՎຓđIPv4 ࠇ IPv6 ᆠ֥oၛ෾ + ຩӉ؇/ো྘pሳ‫؍‬ᆴсྶაࢤ൬֥֞ IP Б๨ϱЧ௄஥bؓႿ IPv4 + ᆠđೂ‫ݔ‬oБ๨Ӊ؇pሳ‫֥؍‬ᆴཬႿ 0x5đᄵᆷൕհ༂ሑ෿b + Վ໊սіၛ༯ bit ֥આࠠࠇ: + + • TDES0[14]: Jabber ӑൈ + • TDES0[13]: ᆠ඗ྍ + • TDES0[11]: ᄛѯ‫ש‬ാ + • TDES0[10]: ໭ᄛѯ + • TDES0[9]: ࿼ӾԊ๬ + • TDES0[8]: ‫ݖ‬؇Ԋ๬ + • TDES0[2]: ‫ݖ‬؇࿼Ӿ + • TDES0[1]: ༯ၮհ༂ + • TDES0[16]: IP Б๨հ༂ + • TDES0[12]: IP Ⴕི‫ڵ‬ᄛհ༂ + ᇂ 1 ൈđ‫໊ھ‬іൕ MAC ‫ؿ‬ෂఖ‫ؿ‬ളਔ jabber ӑൈbᆺႵᄝ EMAC- + CONFIG_REG ֥ EMACJABBER ໊čܱо JabberĎໃᇂ 1 ൈđ‫ھ‬ + ໊ᇂ 1b + ᇂ 1 ൈđ‫໊ھ‬іൕ DMA ࠇ MTL ၘࣜοᅶ CPU ۳ԛ֥඗ྍଁ਷඗ + ྍᆠb + ᇂ 1 ൈđ‫໊ھ‬іൕ MAC ‫ؿ‬ෂఖᄝ TCPđUDP ࠇ ICMP IP ඔऌБ + Ⴕིᄛ‫ހ‬ᇏ࡟ҩ֞հ༂b + ‫ؿ‬ෂఖ࡟Ұ IPv4 ࠇ IPv6 Б๨ᇏ൬֥֞Ⴕི‫ڵ‬ᄛӉ؇აՖႋႨӱ + ྽ࢤ൬֥֞ TCPđUDP ࠇ ICMP ඔऌЇሳࢫ֥ൌ࠽ඔਈđѩᄝ‫ؿ‬ + ള҂௄஥ൈᆷൕհ༂ሑ෿b + ᇂ 1 ൈđ‫໊ھ‬ᆷൕᄝᆠԮൻ௹ࡗ‫ؿ‬ളᄛѯ‫ש‬ാčࠧđᄝᆠԮൻ௹ + ࡗđ၂۱ࠇ‫؟‬۱Ԯൻൈᇒᇛ௹ଽđMII_CRS ྐ‫ݼ‬໭ིĎb֒ MAC + ԩႿ϶ච‫۽‬ଆൔൈđᆺؓԮൻᇏીႵԊ๬֥ᆠႵིb + ᇂ 1 ൈđ‫໊ھ‬ᆷൕᄝԮൻ‫ݖ‬ӱᇏটሱ PHY ֥ᄛѯᆍ๐ྐ‫ݼ‬ໃФঘ + ֮b + +ুᶈྐ༏॓࠯ 217 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +໊ ଁ଀ ૭ඍ + ᇂ 1 ൈđ‫໊ھ‬ᆷൕႮႿԊ๬Գ१čᄝ MII ଆൔ༯đЇওБ๨ᄝଽ‫܋‬ +[9] LC: Late Collision 64 ሳࢫൈࡗđ‫ ބ‬512 ሳࢫൈࡗđЇওБ๨‫ބ‬ᄛѯঔᅚĎᆭު‫ؿ‬ള + Ԋ๬‫ؿط‬ള֥ᆠԮൻФᇏᆸbೂ‫ݔ‬༯ၮհ༂໊ᇂ 1đᄵ‫໊ھ‬໭ིb +[8] EC: Excessive Collision ᇂ 1 ൈđ‫໊ھ‬іൕᄝӇ൫Ԯෂ֒భᆠ‫ؿ‬ള 16 Ց৵࿃Ԋ๬ᆭުԮൻ + Фᇏᆸbೂ‫ ݔ‬EMACCONFIG_REG ֥ EMACRETRY ໊ᇂ 1đᄵ‫ھ‬ +[7] VF: VLAN Frame ໊ᄝֻ၂ՑԊ๬ުᇂ 1đѩ౏ᆠԮൻФᇏᆸb + ᇂ 1 ൈđіൕԮൻ֥ᆠ൞ VLAN ো྘֥ᆠb +[6:3] Ctrl/status ᆃ ུ ሑ ෿ ໊ ᆷ ൕ ᆠ ‫ ؿ‬ෂ ᆭ భ ‫ ؿ‬ള ֥ Ԋ ๬ Ց ඔb ֒ ‫ ݖ‬؇ Ԋ ๬ ໊ + (TDES0 [8]) ᇂ 1 ൈđՎ࠹ඔ໭ིbCPU ᆺᄝ϶ච‫۽‬ଆൔ༯۷ྍ +[2] ED: Excessive Deferral ᆃ۱ሑ෿ሳ‫؍‬b + ᇂ 1 ൈđೂ‫ ݔ‬MAC ஥ᇂ࠷թఖ EMACCONFIG_REG ֥ EMACDE- +[1] UF: Underflow Error FERRALCHECKč࿼Ӿ࡟ҩĎ໊ᇂູۚđᄵ‫໊ھ‬іൕԮൻၘࣜࢲඏđ + ჰၹ൞ᄝ൐ିऍᆠ֥౦ঃ༯đ‫ݖ‬؇࿼Ӿӑ‫ ݖ‬24,288 бหൈࡗb +[0] DB: Deferred Bit ᇂ 1 ൈđ‫໊ھ‬іൕႮႿඔऌՖᇶࠏթԥఖ࿼Ӿ֞ղđMAC ᇏᆸਔ + ᆠ‫ؿ‬ෂb༯ၮհ༂іൕ DMA ᄝԮൻᆠൈმ֞ॢ֥ԮൻߏթbԮൻ + ‫ݖ‬ӱࣉೆᄠ๔ሑ෿ѩࡼԮൻ༯ၮ࠷թఖčሑ෿࠷թఖ bit[5]Ď‫ބ‬Ԯ + ൻᇏ؎࠷թఖčሑ෿࠷թఖ bit[0]Ďᇂ 1b + ᇂ 1 ൈđ‫໊ھ‬іൕ MAC ႮႿᄛѯ֥թᄝ‫ط‬Ԯൻ࿼Ӿb‫ࣇ໊ھ‬ᄝ϶ + ච‫۽‬ଆൔ༯Ⴕིb + + і 10­6. ‫ؿ‬ෂ૭ඍ‫ ژ‬1 (TDES1) + +໊ ଀ӫ ૭ඍ + ᆃ ུ ໊ ౨ ౰ MAC ൐ Ⴈ GMACADDR0HIGH_REGđ +[31:29] SAIC: SA Insertion Control GMACADDR0LOW_REGđGMACADDR1HIGH_REGđ + GMACADDR1HIGH_REG ࠷ թ ఖ ᇏ ۳ ‫ ֥ ק‬ᆴ เ ࡆ ࠇ ู ߐ ၛ ෾ +[28:16] Reserved ຩᆠᇏ֥ჷֹᆶሳ‫؍‬bೂ‫ݔ‬oჷֹᆶpሳ‫؍‬ᄝᆠᇏФྩ‫ڿ‬đᄵ +[15:13] Reserved MAC ߶ሱ‫׮‬ᇗྍ࠹ෘѩูߐ CRC ሳࢫb໊ 31 ᆷ‫ק‬ႨႿҬೆࠇ + TBS1: Transmit Buffer ูߐჷֹᆶ֥ MAC ֹᆶ࠷թఖᆴč1 ࠇ 0Ďbၛ༯ਙі૭ඍਔ໊ +[12:0] Size [30:29] ֥ᆴğ + + • 2’b00ğ҂ࡆೆჷֹᆶb + • 2’b01ğҬೆჷֹᆶbູಒЌԮൻ֥ॖौྟđႋႨӱ྽сྶิ + + ‫܂‬ીႵჷֹᆶ֥ᆠb + • 2’b10ğูߐჷֹᆶbູಒЌԮൻ֥ॖौྟđႋႨӱ྽сྶิ + + ‫܂‬ջႵჷֹᆶ֥ᆠb + • 2’b11ğЌ਽ + ֒॥ᇅ໊ TDES0 [28] ᇂ 1 ൈđᆃ໊ུႵིb + Ќ਽ + Ќ਽ + ৽іඔऌߏթ֥նཬđၛሳࢫູֆ໊bೂ‫ھݔ‬ሳ‫ ູ؍‬0đᄵ DMA + ࡼޭ੻Վߏթđѩ൐Ⴈ༯၂۱૭ඍ‫ژ‬b + +ুᶈྐ༏॓࠯ 218 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + і 10­7. ‫ؿ‬ෂ૭ඍ‫ ژ‬2 (TDES2) + +໊ ଀ӫ ૭ඍ + ߏթ֥໾৘ֹᆶb +[31:0] Buffer Address Pointer + + і 10­8. ‫ؿ‬ෂ૭ඍ‫ ژ‬3 (TDES3) + +໊ ଀ӫ ૭ඍ + ‫ֹھ‬ᆶЇ‫ݣ‬༯၂۱૭ඍ‫ژ‬෮ᄝ໾৘ଽթ֥ᆷᆌb +[31:0] Next Descriptor Address + +໊ ଀ӫ і 10­9. ‫ؿ‬ෂ૭ඍ‫ ژ‬6 (TDES6) + + TTSL: Transmit Frame ૭ඍ +[31:0] ‫ھ‬ሳ‫؍‬Ⴎ DMA ۷ྍđູཌྷႋԮൻᆠѽࠆ֥ൈࡗՄ֥ቋ֮Ⴕི 32 + ໊bᆺႵ֒૭ඍ‫ژ‬ᇏ֥ቋު‫( ؍‬LS) ໊Фᇂ 1 ൈ౏ൈࡗՄሑ෿ + Timestamp Low (TTSS) ໊ᇂ 1 ൈđ‫ھ‬ሳ‫؍‬ҌऎႵൈࡗՄb + + і 10­10. ‫ؿ‬ෂ૭ඍ‫ ژ‬7 (TDES7) + +໊ ଀ӫ ૭ඍ + ‫ھ‬ሳ‫؍‬Ⴎ DMA ۷ྍđູཌྷႋࢤ൬ᆠѽࠆ֥ൈࡗՄ֥ቋ֮Ⴕི 32 + TTSH: Transmit Frame ໊bᆺႵ֒૭ඍ‫ژ‬ᇏ֥ LS ໊Фᇂ 1 ൈ౏ TTSS ໊ᇂ 1 ൈđ‫ھ‬ሳ‫؍‬ +[31:0] ҌऎႵൈࡗՄb + + Timestamp High + +10.8.2 ࢤ൬૭ඍ‫ژ‬ + +ࢤ൬৽іࢲ‫ܒ‬ೂ๭ 10-10 ෮ൕbі 10-11 ᇀі 10-17 ູ৽і૭ඍb + + 31Ctrl OWN 0 + Res + RDES0 Reserved[30:16] Status[30:0] Receive Buffer Size[12:0] + RDES1 + RDES2 Ctrl + [15:14] + + Buffer Address [31:0] + + RDES3 Next Descriptor Address[31:0] + + RDES4 Extended Status[31:0] + + RDES5 Reserved + + RDES6 Receive Frame Timestamp Low[31:0] + + RDES7 Receive Frame Timestamp High[31:0] + + ๭ 10­10. ࢤ൬৽іࢲ‫ܒ‬ + +ুᶈྐ༏॓࠯ 219 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + і 10­11. ࢤ൬૭ඍ‫ ژ‬0 (RDES0) + +໊ ଀ӫ ૭ඍ +[31] OWN: Own Bit ᇂ 1 ൈđ‫໊ھ‬іൕ૭ඍ‫ژ‬Ⴎ DMA ෮Ⴕb֒‫໊گ໊ھ‬ൈđ‫໊ھ‬іൕ +[30] AFM: Destination Address ૭ඍ‫ژ‬ႮᇶࠏႚႵbDMA ᄝປӮᆠࢤ൬ࠇაՎ৽іႵܱ֥ߏթၘ +[29:16] Filter Fail ડൈౢԢ‫໊ھ‬b + FL: Frame Length +[15] ᇂ 1 ൈđ‫໊ھ‬іൕ MAC ᇏ DA ੲѯఖാϧ֥ᆠb + ES: Error Summary +[14] ᆃ໊ུіൕ‫ؿ‬ෂ֞ CPU ଽթ֥ࢤ൬ᆠ֥ሳࢫӉ؇b֒ RDES0 [8] +[13] DE: Descriptor Error Фᇂ 1 ౏૭ඍ‫ژ‬հ༂໊ RDES0 [14] ࠇၮԛհ༂໊Ф‫໊گ‬ൈđ‫ھ‬ +[12] SAF: Source Address Filter ሳ‫؍‬Ⴕིb֒൐ି IP ཮ဒ‫࠹ބ‬ෘčো྘ 1Ďѩ౏෮ࢤ൬֥ᆠ҂൞ +[11] Fail MAC ॥ᇅᆠൈđᆠӉ؇ߎЇও‫֞ࡆڸ‬ၛ෾ຩᆠ֥ਆ۱ሳࢫb +[10] LE: Length Error ‫ھ‬ሳ‫؍‬іൕၛ༯໊֥આࠠࠇğ +[9] OE: Overflow Error +[8] VLAN: VLAN Tag • RDES0[1]ğCRC հ༂ + FS: First Descriptor • RDES0[3]ğࢤ൳հ༂ + LS: Last Descriptor • RDES0[4]ğु૊‫ܐ‬ӑൈ + • RDES0[6]ğ࿼ӾԊ๬ + • RDES0[7]ğऍᆠ + • RDES4[4:3]ğIP Б๨ࠇ‫ڵ‬ᄛհ༂ + • RDES0[11]ğഈၮհ༂ + • RDES0[14]ğ૭ඍ‫ژ‬հ༂ + ᆺႵ RDES0 [8] ᇂ 1 ൈđ‫ھ‬ሳ‫؍‬Ⴕིb + ᇂ 1 ൈđ‫໊ھ‬іൕႮᆠնཬӑ‫֒ݖ‬భ૭ඍ‫ߏژ‬թ֥ᆠФࢩ؎đѩ + ౏ DMA ҂ႚႵ༯၂۱૭ඍ‫ژ‬b‫ھ‬ᆠФࢩ؎bᆺႵ໊֒ RDES0 [8] + ᇂ 1 ൈđ‫ھ‬ሳ‫؍‬ҌႵིb + + ᇂ 1 ൈđ‫໊ھ‬іൕᆠ֥ SA ሳ‫؍‬ໃ๙‫ ݖ‬MAC ᇏ֥ SA ‫ݖ‬ੲb + + ᇂ 1 ൈđ‫໊ھ‬іൕࢤ൬֥֞ᆠ֥ൌ࠽Ӊ؇‫ބ‬Ӊ؇/ো྘ሳ‫؍‬҂௄஥b + ‫ࣇ໊ھ‬ᄝᆠো྘ (RDES0 [5]) ໊‫໊گ‬ൈႵིb + ᇂ 1 ൈđ‫໊ھ‬іൕႮႿ MTL ᇏ֥ߏթၮԛ‫֝ط‬ᇁࢤ൬֥֞ᆠФ෥ + ߊb + ᇂ 1 ൈđ‫໊ھ‬іൕ‫ھ‬૭ඍ‫ژ‬෮ᆷཟ֥ᆠ൞Ⴎ MAC ѓ࠺֥ VLAN + ᆠbVLAN ѓ࠺౼थႿ۴ऌ VLAN ѓ࠺࠷թఖഡᇂ࡟Ұࢤ൬֥֞ᆠ + ֥ VLAN ሳ‫؍‬b + ᇂ 1 ൈđ‫໊ھ‬іൕ‫ھ‬૭ඍ‫ژ‬Ї‫ݣ‬ᆠֻ֥၂۱ߏթ౵bೂ‫ֻݔ‬၂۱ + ߏթ౵֥նཬ൞ 0đᄵ‫ھ‬ᆠՖֻ‫ؽ‬۱ߏթष൓bೂ‫ؽֻݔ‬۱ߏթ֥ + նཬ္൞ 0đᄵ༯၂۱૭ඍ‫ژ‬Ї‫ھݣ‬ᆠ֥ᆠ๨b + ᇂ 1 ൈđ‫໊ھ‬іൕ‫ھ‬૭ඍ‫ژ‬ᆷཟ֥ߏթ൞‫ھ‬ᆠ֥ቋު၂۱ߏթ౵b + +ুᶈྐ༏॓࠯ 220 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +໊ ଀ӫ ૭ඍ + + ۚࠩൈࡗՄ‫ିۿ‬թᄝൈđᇂ 1 ൈđ‫໊ھ‬іൕൈࡗՄ֥ॹᅶཿೆ૭ + + ඍ‫ژ‬ሳ 6 (RDES6) ‫ ބ‬7 (RDES7)bᆺႵ໊ RDES0 [8] Фᇂ 1 ൈҌႵ + + ིb + + ֒࿊ᄴ IP ཮ဒ‫ބ‬ႄౣčো྘ 1Ďൈđ‫໊ھ‬ᇂ 1 іൕၛ༯౦ঃᆭ၂ğ + + • MAC ଽ‫࠹ނ‬ෘ֥ 16 ໊ IPv4 Б๨཮ဒ‫ބ‬ა൬֥֞཮ဒ‫ބ‬ሳ + + Timestamp Available, ࢫ҂௄஥b + +[7] IP Checksum Error (Type1), • ٤ IPv4 ᆠಡ‫ݖ‬Б๨཮ဒ‫࡟ބ‬Ұb + + or Giant Frame ೏ၛഈਆᇕ౦ঃ‫׻‬҂‫ކژ‬đᄵ‫໊ھ‬ᇂ 1 іൕऍᆠሑ෿bؓႿ௴๙ + + ᆠđնႿ 1,518 ሳࢫ֥ᆠູऍᆠč೏‫௴ھ‬๙ᆠູ VLAN ᆠđᄵն + + Ⴟ 1,522 ሳࢫ֥ᆠູऍᆠĠ֒ GMAC_CONFIGREG bit[27] ູ 1 ൈđ + + նႿ 2,000 ሳࢫ֥ᆠູऍᆠĎb֒൐ିऍᆠԩ৘ൈđնႿ 9,018 ሳ + + ࢫ֥ᆠູऍᆠč೏‫ھ‬ऍᆠູ VLAN ᆠđᄵնႿ 9,022 ሳࢫ֥ᆠູ + + ऍᆠĎb + +[6] LC: Late Collision ᇂ 1 ൈđ‫໊ھ‬іൕᄝ϶ච‫۽‬ଆൔ༯ࢤ൬ᆠൈ‫ؿ‬ള࿼ӾԊ๬b + + ᇂ 1 ൈđ‫໊ھ‬іൕࢤ൬ᆠ൞ၛ෾ຩো྘֥ᆠčLT ሳ‫؍‬նႿࠇ֩Ⴟ + +[5] FT: Frame Type 1,536 ሳࢫĎb֒‫໊گ໊ھ‬ൈđіൕࢤ൬֥֞ᆠ൞ IEEE 802.3 ᆠb + + Վ໊ؓႿཬႿ 14 ۱ሳࢫ֥ζᆠ໭ིb + + RWT: Receive ᇂ 1 іൕࢤ൬ु૊‫קܐ‬ൈఖᄝ൬֞֒భᆠൈၘࣜӑൈđ֒భᆠᄝ +[4] ु૊‫ܐ‬ӑൈުФࢩ؎b + + Watchdog Timeout + +[3] RE: Receive Error ᇂ 1 ൈđ‫໊ھ‬іൕᄝࢤ൬ᆠ௹ࡗ೏ MII_RXDV Фᇂ 1đᄵ‫ؿ‬ԛ + MII_RXERb + +[2] DE: Dribble Bit Error ᇂ 1 ൈđ‫໊ھ‬іൕࢤ൬֥֞ᆠऎႵ٤ᆜඔП֥ሳࢫčఅඔ۱϶ሳ + ࢫĎb‫ࣇ໊ھ‬ᄝ MII ଆൔ༯Ⴕིb + +[1] CE: CRC Error ᇂ 1 ൈđ‫໊ھ‬іൕᄝࢤ൬֥֞ᆠഈ‫ؿ‬ള࿖ߌ಺Ⴥ཮ဒ (CRC) հ༂b + ᆺႵ໊ RDES0 [8] ᇂ 1 ൈđ‫ھ‬ሳ‫؍‬ҌႵིb + + ֒ۚࠩൈࡗՄࠇ IP ཮ဒ‫ཱྀބ‬ᄛčো྘ 2Ďթᄝൈđ‫໊ھ‬ᇂ 1 ൈі + + ૼঔᅚሑ෿ᄝ૭ඍ‫ژ‬ሳ 4 (RDES4) ᇏॖႨbᆺႵ໊ RDES0 [8] ᇂ 1 + + ൈҌႵིb໊ 30 ᇂ 1 ൈ‫໊ھ‬໭ིb + + ֒ IP ཮ဒ‫ཱྀބ‬ᄛčো྘ 2Ďթᄝൈđࠧ൐ᄝ IP ཮ဒ‫ཱྀބ‬ᄛႄౣ + +[0] Extended Status Available/ ಡ‫ࢤݖ‬൬ᆠ֥ԩ৘đ‫္໊ھ‬Фᇂ 1bಡ‫ݖ‬ॖି൞ၹູ٤ IP ᆠࠇ٤ + + Rx MAC Address TCP/UDP/ICMP Ⴕིᄛ‫ ֥ހ‬IP ᆠb + + ֒ۚࠩൈࡗՄ‫ ࠇିۿ‬IPC ಆཱྀ҆ᄛໃФ࿊ᄴൈđ‫໊ھ‬іൕ Rx MAC + + ֹᆶሑ෿bᇂ 1 ൈđ‫໊ھ‬іൕ Rx MAC ֹᆶ࠷թఖᆴč1 ᇀ 15Ď + + აᆠ֥ DA ሳ‫؍‬ཌྷ௄஥b‫໊گ‬ൈđ‫໊ھ‬іൕ Rx MAC ֹᆶ࠷թఖ 0 + + ֥ᆴა DA ሳ‫؍‬௄஥b + +໊ ଀ӫ і 10­12. ࢤ൬૭ඍ‫ ژ‬1 (RDES1) + +[31] Ctrl ૭ඍ + ᇂ 1 ൈđ‫໊ھ‬ቅᆸᆠ֥ሑ෿࠷թఖ֥ RI ໊ (CSR5 [6]) Фᇂ 1đ൐ +[30:29] Reserved ֤൬֥֞ᆠᄝ֒భ૭ඍ‫ژ‬෮ᆷ֥ߏթଽࢲඏbՖ‫࣌ط‬ᆸႮႿ‫ھ‬ᆠ +[28:16] Reserved ֥ RI ཟᇶࠏ֥ᇏ؎Ԩ‫ؿ‬b + Ќ਽ + Ќ਽ + +ুᶈྐ༏॓࠯ 221 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +໊ ଀ӫ ૭ඍ +[15] RER: Receive End of Ring ᇂ 1 ൈđ‫໊ھ‬іൕ૭ඍ‫ژ‬ਙіၘղ֞ఃቋު၂۱૭ඍ‫ژ‬bDMA ْ +[14] ߭֞ਙі֥ࠎֹᆶđԷࡹ၂۱૭ඍ‫ߌژ‬b +[13] RCH: Second Address ᇂ 1 ൈđ‫໊ھ‬іൕ૭ඍ‫ژ‬ᇏֻ֥‫ؽ‬۱ֹᆶ൞༯၂۱૭ඍ‫ֹژ‬ᆶđՎ +[12:0] Chained ໊сྶᇂ 1b֒‫໊ھ‬ᇂ 1 ൈđRBS2 (RDES1 [28:16]) ൞၂۱o໭ܱp + Reserved ᆴbRDES1 [15] Ⴊ༵ࠩۚႿ RDES1 [14]b + Ќ਽ + RBS1: Receive Buffer 1 іൕֻ၂۱ඔऌߏթ֥նཬčሳࢫĎbࠧ൐ RDES2čbuffer1 ֹᆶ + Size ᆷᆌĎ֥ᆴໃؓఊđߏթնཬ္сྶ൞ 4 ֥Пඔb֒ߏթնཬ҂൞ + 4 ֥Пඔൈđࢲ‫ݔ‬൞҂ಒ‫֥ק‬bೂ‫ھݔ‬ሳ‫ ູ؍‬0đᄵ DMA ࡼޭ੻ + Վߏթđѩ۴ऌ RCH ֥ᆴ (bit[14]) ൐Ⴈߏթ 2 ࠇ༯၂۱૭ඍ‫ژ‬b + + і 10­13. ࢤ൬૭ඍ‫ ژ‬2 (RDES2) + +໊ ଀ӫ ૭ඍ + ᆃ໊ུіൕߏթ֥໾৘ֹᆶb +[31:0] Buffer Address Pointer + + і 10­14. ࢤ൬૭ඍ‫ ژ‬3 (RDES3) + +໊ ଀ӫ ૭ඍ + ‫ֹھ‬ᆶЇ‫ݣ‬ᆷཟ༯၂۱૭ඍ‫ژ‬෮ᄝ໾৘ଽթ֥ᆷᆌb +[31:0] Next Descriptor Address + +໊ ଀ӫ і 10­15. ࢤ൬૭ඍ‫ ژ‬4 (RDES4) +[31:28] Reserved +[27:26] Reserved ૭ඍ +[25] Reserved Ќ਽ +[24] Reserved Ќ਽ +[23:21] Reserved Ќ਽ +[20:18] Reserved Ќ਽ +[17] Reserved Ќ਽ +[16] Reserved Ќ਽ +[15] Reserved Ќ਽ + Ќ਽ +[14] Timestamp Dropped Ќ਽ + ᇂ 1 ൈđ‫໊ھ‬іൕ‫ھ‬ᆠ֥ൈࡗՄФѽࠆđ֌‫ھ‬ൈࡗՄ߶ႮႿၮԛ +[13] PTP Version ‫ط‬ᄝ MTL Rx FIFO ᇏ‫ש‬ఙb + ᇂ 1 ൈđ‫໊ھ‬іൕࢤ൬֥֞ PTP ཨ༏ऎႵ IEEE 1588 ϱЧ 2 ۬ൔb +[12] PTP Frame Type ‫໊گ‬ൈđ෱ऎႵϱЧ 1 ۬ൔđࣇ֒ཨ༏ো྘ູ٤ 0 ൈႵིb + ᇂ 1 ൈđ‫໊ھ‬іൕ PTP ཨ༏ᆰࢤ๙‫ݖ‬ၛ෾ຩ‫ؿ‬ෂb֒‫໊ھ‬ౢਬ౏ + ཨ༏ো྘҂ູਬൈđіൕ‫ھ‬ཨ༏൞๙‫ ݖ‬UDP-IPv4 ࠇ UDP-IPv6 ‫ؿ‬ + ෂ֥bႵܱ IPv4 ࠇ IPv6 ֥ྐ༏ॖၛՖ bit[6] ‫ ބ‬bit[7] ᇏࠆ֤b + +ুᶈྐ༏॓࠯ 222 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +໊ ଀ӫ ૭ඍ + ᆃ໊ུФщ઒Ӯ෮ࢤ൬ཨ༏֥ো྘b +[11:8] Message Type + • 3’b0000ğໃ൬֞ PTP message received +[7] IPv6 Packet Received • 3’b0001ğSYNC (෮Ⴕൈᇒো྘) +[6] IPv4 Packet Received • 3’b0010ğFollow_Up (෮Ⴕൈᇒো྘) +[5] IP Checksum Bypassed • 3’b0011ğDelay_Req (෮Ⴕൈᇒো྘) +[4] IP Payload Error • 3’b0100ğDelay_Resp (෮Ⴕൈᇒো྘) +[3] IP Header Error • 3’b0101ğPdelay_Req (ׄؓׄ๩ૼൈᇒ) + • 3’b0110ğPdelay_Resp (ׄؓׄ๩ૼൈᇒ) +[2:0] IP Payload Type • 3’b0111ğPdelay_Resp_Follow_Up (ׄؓׄ๩ૼൈᇒ) + • 3’b1000ğAnnounce + • 3’b1001ğManagement + • 3’b1010ğSignaling + • 3’b1011-3’b1110ğЌ਽ + • 3’b1111ğ‫ݣ‬ႵЌ਽ྐ༏֥ PTP Ї + ᇂ 1 ൈđ‫໊ھ‬іൕࢤ൬֥֞ඔऌЇ൞၂۱ IPv6 ඔऌЇb‫ࣇ໊ھ‬ᄝ + ࠷թఖčMAC ஥ᇂ࠷թఖĎ֥ bit[10] (IPC) ᇂ 1 ൈ۷ྍb + ᇂ 1 ൈđіൕࢤ൬֥֞ඔऌЇ൞ IPv4 ඔऌЇb‫ࣇ໊ھ‬ᄝ࠷թఖ + čMAC ஥ᇂ࠷թఖĎ֥ bit[10] (IPC) ᇂ 1 ൈ۷ྍb + ᇂ 1 ൈđ‫໊ھ‬іൕ཮ဒ‫ཱྀބ‬ᄛႄౣФகਫ਼b + ᇂ 1 ൈđ‫໊ھ‬іൕ MAC ଽ‫࠹ނ‬ෘ֥ 16 ໊ IP Ⴕི‫ڵ‬ᄛ཮ဒ‫ބ‬čࠧ + TCPđUDP ࠇ ICMP ཮ဒ‫ބ‬Ďაࢤ൬֥‫؍‬ᇏؓႋ֥཮ဒ‫ބ‬ሳ‫؍‬҂ + ௄஥b֒ TCPđUDP ࠇ ICMP ‫֥؍‬Ӊ؇ა IP Header ሳ‫؍‬ᇏ֥‫ڵ‬ + ᄛӉ؇ᆴ҂௄஥ൈđ‫໊ھ‬ᇂ 1b֒ bit[7] ࠇ bit[6] ᇂ 1 ൈđ‫໊ھ‬Ⴕ + ིb + ᇂ 1 ൈđ‫໊ھ‬іൕႮ MAC ଽ‫࠹ނ‬ෘ֥ 16 ໊ IPv4 Б๨཮ဒ‫ބ‬ა + ࢤ൬֥཮ဒ‫ބ‬ሳࢫ҂௄஥đࠇ IP ඔऌБϱЧაၛ෾ຩো྘ᆴ҂၂ + ᇁb֒ bit[7] ࠇ bit[6] Фᇂ 1 ൈđ‫໊ھ‬Ⴕིb + ᆃ໊ུіൕ‫ٿ‬ልᄝႮࢤ൬཮ဒ‫ཱྀބ‬ᄛႄౣ (COE) ԩ৘֥ IP ඔऌБ + ᇏ֥Ⴕིᄛ‫֥ހ‬ো྘bೂ‫ ݔ‬COE ႮႿ IP Б๨հ༂ࠇ‫ ؍ٳ‬IP ‫ط‬҂ + ԩ৘ IP ඔऌБ֥Ⴕིᄛ‫ހ‬đCOE ္ࡼᆃ໊ུᇂູ 2’b00b + • 3’b000ğໃᆩࠇໃԩ৘ IP ‫ڵ‬ᄛ + • 3’b001ğUDP + • 3’b010ğTCP + • 3’b011ğICMP + • 3’b1xxğЌ਽ + ໊֒ 7 ࠇ໊ 6 ᇂ 1 ൈđ‫໊ھ‬Ⴕིb + + і 10­16. ࢤ൬૭ඍ‫ ژ‬6 (RDES6) + +໊ ଀ӫ ૭ඍ + ‫ھ‬ሳ‫؍‬Ⴈؓႋࢤ൬ᆠѽࠆ֥ൈࡗՄ֥ቋ֮Ⴕི 32 ໊b‫ھ‬ሳ‫ࣇ؍‬Ⴎ + RTSH: Receive Frame ቋު၂۱૭ඍ‫ژ‬ሑ෿໊ RDES0 [8] ᆷൕ֥ࢤ൬ᆠ֥ቋު၂۱৽і +[31:0] ๙‫ ݖ‬DMA ۷ྍb + + Timestamp Low + +ুᶈྐ༏॓࠯ 223 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + і 10­17. ࢤ൬૭ඍ‫ ژ‬7 (RDES7) + +໊ ଀ӫ ૭ඍ + ‫ھ‬ሳ‫؍‬Ⴎ DMA ۷ྍđႨؓႋࢤ൬ᆠѽࠆ֥ൈࡗՄ֥ቋ֮Ⴕི 32 + RTSH: Receive Frame ໊۷ྍb‫ھ‬ሳ‫ࣇ؍‬Ⴎቋު၂۱૭ඍ‫ژ‬ሑ෿໊ RDES0 [8] ᆷൕ֥ࢤ +[31:0] ൬ᆠ֥ቋު၂۱৽і๙‫ ݖ‬DMA ۷ྍb + + Timestamp High + +10.9 ࠷թఖਙі + +ห‫࠷ק‬թఖ֥ห‫ק‬ሳ‫໊ࠇ؍‬ऎႵ҂๝֥٠໙උྟbၛ༯ਙіູ࠷թఖ૭ඍᇏ൐Ⴈ֥උྟ෪ཿb + +• Read Only (RO) ᆺ‫؀‬ +• Write Only (WO) ᆺཿ + +• Read and Write (R/W) ‫؀‬/ཿ + +• Read, Write, and Self Clear (R/W/SC) ‫؀‬/ཿ/ሱ‫׮‬ౢԢ +• Read, Self Set, and Write Clear (R/SS/WC) ‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢ +• Read, Write Set, and Self Clear (R/WS/SC) ‫؀‬/ཿഡᇂ/ሱ‫׮‬ౢԢ +• Read, Self Set, and Self Clear or Write Clear (R/SS/SC/WC) ‫؀‬/ሱ‫׮‬ഡᇂ/ሱ‫׮‬ౢԢ/ཿౢԢ + +• Read Only and Write Trigger (RO/WT) ᆺ‫؀‬/ཿԨ‫ؿ‬ + +• Read, Self Set, and Read Clear (R/SS/RC) ‫؀‬/ሱ‫׮‬ഡᇂ/‫؀‬ౢԢ +• Read, Write, and Self Update (R/W/SU) ‫؀‬/ཿ/ሱ‫׮‬۷ྍ +• Latched-low (LL) ֮෭թ +• Latched-high (LH) ۚ෭թ + +଀ӫ ૭ඍ ֹᆶ ٠໙ +DMA ஥ᇂ‫ބ‬॥ᇅ࠷թఖ +DMABUSMODE_REG ஥ᇂሹཌଆൔ 0x3FF69000 R/WS/SC +DMATXPOLLDEMAND_REG ඔऌԮൻᆷ਷ 0x3FF69004 RO/WT +DMARXPOLLDEMAND_REG ඔऌࢤ൬ᆷ਷ 0x3FF69008 RO/WT +DMARXBASEADDR_REG ֻ၂۱ࢤ൬૭ඍ‫ֹࠎ֥ژ‬ᆶ 0x3FF6900C R/W +DMATXBASEADDR_REG ֻ၂۱Ԯൻ૭ඍ‫ֹࠎ֥ژ‬ᆶ 0x3FF69010 R/W +DMASTATUS_REG ᇏ؎đհ༂‫ބ‬ః෰൙ࡱ֥ࠎֹᆶ 0x3FF69014 R/SS/WC +DMAOPERATION_MODE_REG ൬‫ؿ‬Ҡቔଆൔ‫ଁބ‬਷࠷թఖ 0x3FF69018 R/SS/WC +DMAIN_EN_REG ᇏ؎ܱо/൐ି 0x3FF6901C R/W +DMAMISSEDFR_REG ‫ש‬ാᆠ‫ߏބ‬թၮԛ࠹ඔఖ 0x3FF69020 R/W +DMARINTWDTIMER_REG ࢤ൬ु૊‫࠹ܐ‬ඔఖ 0x3FF69024 R/W +DMATXCURRDESC_REG ᆷཟ֒భԮൻ૭ඍ‫֥ژ‬ᆷᆌ 0x3FF69048 RO +DMARXCURRDESC_REG ᆷཟ֒భࢤ൬૭ඍ‫֥ژ‬ᆷᆌ 0x3FF6904C RO +DMATXCURRADDR_BUF_REG ᆷཟ֒భԮൻߏթ֥ᆷᆌ 0x3FF69050 RO +DMARXCURRADDR_BUF_REG ᆷཟ֒భࢤ൳ߏթ֥ᆷᆌ 0x3FF69054 RO +MAC ஥ᇂ‫ބ‬॥ᇅ࠷թఖ + +ুᶈྐ༏॓࠯ 224 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + +଀ӫ ૭ඍ ֹᆶ ٠໙ +EMACCONFIG_REG MAC ஥ᇂ 0x3FF6A000 R/W +EMACFF_REG ᆠ‫ݖ‬ੲഡᇂ 0x3FF6A004 R/W +EMACMIIADDR_REG PHY ஥ᇂ٠໙ಃཋ 0x3FF6A010 R/WS/SC +EMACMIIDATA_REG PHY ඔऌ‫؀‬ཿ 0x3FF6A014 R/W + R/WS/SC(FCB) +EMACFC_REG ᆠੀ॥ᇅ 0x3FF6A018 R/W(BPA) + RO +EMACDEBUG_REG ሑ෿‫ט‬൫໊ 0x3FF6A024 RO + 0x3FF6A028 RO +PMT_RWUFFR_REG ჹӱߒྜੲѯఖ 0x3FF6A02C RO + 0x3FF6A030 RO +PMT_CSR_REG ‫ܵݻۿ‬৘॥ᇅ‫ބ‬ሑ෿࠷թఖ 0x3FF6A034 RO + 0x3FF6A038 R/W +EMACLPI_CSR_REG LPI ॥ᇅ‫ބ‬ሑ෿࠷թఖ 0x3FF6A03C R/W + 0x3FF6A040 R/W +EMACLPITIMERSCONTROL_REG LPI ࠹ൈఖ॥ᇅఖ 0x3FF6A044 R/W + 0x3FF6A048 R/W +EMACINTS_REG ᇏ؎ሑ෿ 0x3FF6A04C R/W + 0x3FF6A050 R/W +EMACINTMASK_REG ᇏ؎௠з 0x3FF6A054 R/W + 0x3FF6A058 R/W +EMACADDR0HIGH_REG ֻ၂۱ 6 ሳࢫ MAC ֹᆶ֥ۚ 16 ໊ 0x3FF6A05C R/W + 0x3FF6A060 R/W +EMACADDR0LOW_REG ֻ၂۱ 6 ሳࢫ MAC ֹᆶ֥֮ 32 ໊ 0x3FF6A064 R/W + 0x3FF6A068 R/W +EMACADDR1HIGH_REG ֻ‫ؽ‬۱ 6 ሳࢫ MAC ֹᆶ֥ۚ 16 ໊ 0x3FF6A06C R/W + 0x3FF6A070 R/W +EMACADDR1LOW_REG ֻ‫ؽ‬۱ 6 ሳࢫ MAC ֹᆶ֥֮ 32 ໊ 0x3FF6A074 R/W + 0x3FF6A078 R/W +EMACADDR2HIGH_REG ֻ೘۱ 6 ሳࢫ MAC ֹᆶ֥ۚ 16 ໊ 0x3FF6A07C RO + 0x3FF6A0D8 R/W +EMACADDR2LOW_REG ֻ೘۱ 6 ሳࢫ MAC ֹᆶ֥֮ 32 ໊ 0x3FF6A0DC R/W + 0x3FF69800 R/W +EMACADDR3HIGH_REG ֻඹ۱ 6 ሳࢫ MAC ֹᆶ֥ۚ 16 ໊ 0x3FF69804 R/W + 0x3FF69808 +EMACADDR3LOW_REG ֻඹ۱ 6 ሳࢫ MAC ֹᆶ֥֮ 32 ໊ + +EMACADDR4HIGH_REG ֻ໴۱ 6 ሳࢫ MAC ֹᆶ֥ۚ 16 ໊ + +EMACADDR4LOW_REG ֻ໴۱ 6 ሳࢫ MAC ֹᆶ֥֮ 32 ໊ + +EMACADDR5HIGH_REG ֻੂ۱ 6 ሳࢫ MAC ֹᆶ֥ۚ 16 ໊ + +EMACADDR5LOW_REG ֻੂ۱ 6 ሳࢫ MAC ֹᆶ֥֮ 32 ໊ + +EMACADDR6HIGH_REG ֻ௾۱ 6 ሳࢫ MAC ֹᆶ֥ۚ 16 ໊ + +EMACADDR6LOW_REG ֻ௾۱ 6 ሳࢫ MAC ֹᆶ֥֮ 32 ໊ + +EMACADDR7HIGH_REG ֻϖ۱ 6 ሳࢫ MAC ֹᆶ֥ۚ 16 ໊ + +EMACADDR7LOW_REG ֻϖ۱ 6 ሳࢫ MAC ֹᆶ֥֮ 32 ໊ + +EMACCSTATUS_REG ৵ࢤ๙࿟ሑ෿ + +EMACWDOGTO_REG ु૊‫ܐ‬ӑൈ॥ᇅ + +EMAC_EX_CLKOUT_CONF_REG RMII ൈᇒ‫ٳ‬௔ഡᇂ + +EMAC_EX_OSCCLK_CONF_REG RMII ൈᇒ϶ᆜඔ‫ބ‬ᆜඔ‫ٳ‬௔ഡᇂ + +EMAC_EX_CLK_CTRL_REG ൈᇒ൐ି‫ބ‬ຓ҆/ଽ҆ൈᇒ࿊ᄴ + +PHY ো྘‫ ބ‬SRAM ஥ᇂ࠷թఖ + +EMAC_EX_PHYINF_CONF_REG MII/RMII PHY ࿊ᄴ 0x3FF6980C R/W + 0x3FF69810 R/W +EMAC_PD_SEL_REG ൐ିܱо Ethernet RAMđඔऌ҂‫ש‬ാ + +10.10 ࠷թఖ + +ඪૼğ෮Ⴕ reserved ࠷թఖ֥ᆴсྶЌӻ‫໊گ‬ᆴb + +ুᶈྐ༏॓࠯ 225 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.1. DMABUSMODE_REG (0x0000) + + (reserved) DMAMDIMXEADAPBDBUDLRRXSA8UT_LSMIEBO_ESADEEP_PBL RX_DMA_PBL FIXED_BPURRIS_RTATIO PROG_BURST_LENALT_DESC_SIZEDESC_SKIP_LENDMA_SAWRB_R_SSCT H + +31 27 26 25 24 23 22 17 16 15 14 13 876 21 0 + +00 0 0 00 0 0 0 0x01 0 0x0 0x01 0 0x00 0 1 Reset + +DMAMIXEDBURST ֒Վ໊ᇂູۚ‫׈‬௜౏ FB(FIXED_BURST) ູ໊֮‫׈‬௜ൈđAHB ᇶࠏࢤ१ࡼ൐Ⴈ + INCRčໃ‫ק‬ၬ burstĎष൓෮ႵӉ؇ӑ‫ ݖ‬16 ֥๬‫ؿ‬ଆൔđ‫ط‬๬‫ؿ‬Ӊ؇ູ 16 ࠇഒႿ 16 ֥ AHB ᇶ + ࢤ१ൡႨ‫קܥ‬๬‫ؿ‬ԮൻčINCRx ‫ ބ‬SINGLEĎbč‫؀‬/ཿĎ + +DMAADDRALIBEA ֒Վ໊ᇂۚ౏ FB ູ໊ 1 ൈđAHB ࢤ१ࡼӁളაఏ൓ֹᆶ LS ໊ؓఊ֥෮Ⴕ๬ + ‫ؿ‬bೂ‫ ݔ‬FB ໊֩Ⴟ 0đᄵֻ၂۱๬‫ؿ‬č٠໙ඔऌߏԊ౵֥ఏ൓ֹᆶĎໃؓఊđ֌ෛު֥๬‫ؿ‬ა + ֹᆶؓఊbč‫؀‬/ཿĎ + +PBLX8_MODE ᇂູۚ‫׈‬௜ൈđ‫ࡼ໊ھ‬щӱ֥ PBL(PROG_BURST_LEN) ᆴčBit [22:17] ‫ ބ‬Bit [13ğ + 8]ĎӰၛ 8bၹՎđDMA ۴ऌ PBL ᆴၛ 8đ16đ32đ64đ128 ‫ ބ‬256 ࢫஅԮൻඔऌbč‫؀‬/ཿĎ + +USE_SEP_PBL ‫໊ھ‬ᇂ໊ൈđRx DMA ൐Ⴈ Bit [22:17] ᇏ஥ᇂ֥ᆴቔູ PBLbBit [13ğ8] ᇏ֥ PBL ᆴ + ࣇൡႨႿ Tx DMA Ҡቔb֒‫׈ູ໊֮گ‬௜ൈđBit [13ğ8] ᇏ֥ PBL ᆴൡႨႿਆ۱ DMA ႄౣčb‫؀‬/ཿĎ + +RX_DMA_PBL ‫ھ‬ሳ‫؍‬іൕᄝ၂۱ Rx DMA ԮൻᇏԮෂ֥ቋնࢫஅඔbᆃ൞ᄝֆՑ‫ࠇ؀‬ཿ֥ቋ + նᆴbૄՑᄝᇶࠏሹཌഈष൓๬‫ؿ‬ԮൻൈđRx DMA ሹ൞߶Ӈ൫οᅶ RPBL ໊֥ᆴࣉྛԮൻb + RPBL(RX_DMA_PBL) ᆴॖ஥ᇂູ 1đ2đ4đ8đ16 ‫ ބ‬32b಩‫ޅ‬ః෰ᆴ‫֝߶׻‬ᇁໃ‫ק‬ၬ֥ྛູb‫ھ‬ + ሳ‫ࣇ؍‬ᄝ USP(USE_SEP_PBL) ᇂູۚൈႵིbč‫؀‬/ཿĎ + +FIXED_BURST ‫໊ھ‬थ‫ ק‬AHB ᇶࢤ१൞‫ڎ‬ᆳྛ‫קܥ‬๬‫ؿ‬Ԯൻbᇂ 1 ൈđᄝᆞӈ๬‫ؿ‬Ԯൻष൓ൈđ + AHB ࢤ१ᆺ൐Ⴈ SINGLEđINCR4đINCR8 ࠇ INCR16 ଆൔb‫໊گ‬ൈđAHB ࢤ१൐Ⴈ SINGLE ‫ބ‬ + INCR ๬‫ؿ‬ԮൻҠቔbč‫؀‬/ཿĎ + +PRI_RATIO ᆃ໊ུ॥ᇅ Rx DMA ‫ ބ‬Tx DMA ᆭࡗ֥ࡆಃ‫ט‬؇ᇏ֥Ⴊ༵ࠩбੱbᆺႵ໊֒ 1čDAĎ‫گ‬ + ໊ൈđᆃ໊ུҌႵིbRx ა Tx Ⴊ༵ࠩбೂ༯ğč‫؀‬/ཿĎ + + • 2’b00 i1ğ1 + + • 2’b01 i2ğ0 + + • 2’b10 i3ğ1 + + • 2’b11 i4ğ1 + +PROG_BURST_LEN ᆃ໊ུіൕᄝ၂Ց DMA ԮൻᇏေԮෂ֥ቋնࢫஅඔbೂ‫ݔ‬ေԮൻ֥ࢫஅඔն + Ⴟ 32đᄵᆳྛၛ༯҄ᇧğ1. ഡᇂ PBLx8 ଆൔĠ2. ஥ᇂ PBL(PROG_BURST_LEN) ᆴbč‫؀‬/ཿĎ + +࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 226 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.1. DMABUSMODE_REG (0x0000) + + ࠿ഈ၂်࠷թఖ૭ඍb + ALT_DESC_SIZE ᇂ 1 ൈđ૭ඍ‫֥ژ‬նཬᄹࡆ֞ 32 ۱ሳࢫbč‫؀‬/ཿĎ + DESC_SKIP_LEN ‫໊ھ‬ᆷ‫ק‬ᄝਆ۱ໃ৽ࢤ֥૭ඍ‫ژ‬ᆭࡗ๋‫֥ݖ‬ሳ֥ඔਈbֹᆶՖ֒భ૭ඍ‫ࢲژ‬ແ๋ + + ሇ֞༯၂۱૭ඍ‫ژ‬ष൓b֒ DSL(DESC_SKIP_LEN) ᆴ֩Ⴟਬൈđ૭ඍ‫ژ‬іᄝߌଆൔ༯Ф DMA ൪ + ູ৵࿃֥bč‫؀‬/ཿĎ + DMA_ARB_SCH Վ໊ᆷ‫ؿק‬ෂਫ਼ࣥ‫ࢤބ‬൬ਫ਼ࣥᆭࡗ֥ᇘҊٚσb1’b0ğႨ RXğTX ࠇ TXğRX ࣉྛ + ࿖ߌ‫ט‬؇đPRčBit [15:14]Ďᆷ‫ק‬Ⴊ༵ࠩđ1’b1 ‫קܥ‬Ⴊ༵ࠩčRx Ⴊ༵Ⴟ TxĎbč‫؀‬/ཿĎ + SW_RST ֒‫໊ھ‬ᇂ 1 ൈđMAC DMA ॥ᇅఖᇗᇂ MAC ֥આࠠ‫ބ‬෮Ⴕ MAC ଽ҆࠷թఖbᄝ෮Ⴕ + ETH_MAC ൈᇒთᇏ֥‫໊گ‬ҠቔປӮުđ‫໊ھ‬ሱ‫׮‬ౢਬbᄝؓ ETH_MAC ֥಩‫࠷ޅ‬թఖࣉྛᇗྍ + щӱᆭభđႋ‫ھ‬ᄝ‫؀໊ھ‬౼၂۱ਬᆴbč‫؀‬/ཿഡᇂ/ሱ‫׮‬ౢԢĎ + + Register 10.2. DMATXPOLLDEMAND_REG (0x0004) + +31 0 + + 0x000000000 Reset + +TRANS_POLL_DEMAND ֒ᆃ໊ུФཿൈđDMA ࡼ‫؀‬౼࠷թఖč֒భᇶࠏ‫ؿ‬ෂ૭ඍ‫࠷ژ‬թఖĎᆷ + ཟ֥֒భ૭ඍ‫ژ‬bೂ‫ھݔ‬૭ඍ‫ژ‬҂ॖႨčႮᇶࠏႚႵĎđᄵԮൻْ߭‫ܫ‬ఏሑ෿đѩ౏࠷թఖčሑ + ෿࠷թఖĎ֥ Bit[2]čTUĎФᇂ 1bೂ‫ݔ‬૭ඍ‫ژ‬ॖႨđᄵԮൻ࠿࿃bčᆺ‫؀‬/ཿԨ‫ؿ‬Ď + + Register 10.3. DMARXPOLLDEMAND_REG (0x0008) + +31 0 + + 0x000000000 Reset + +RECV_POLL_DEMAND ֒ᆃ໊ུФཿೆൈđDMA ࡼ‫؀‬౼࠷թఖč֒భᇶࠏࢤ൬૭ඍ‫࠷ژ‬թఖĎᆷ + ཟ֥֒భ૭ඍ‫ژ‬bೂ‫ھݔ‬૭ඍ‫ژ‬҂ॖႨčႮᇶࠏႚႵĎđᄵࢤ൬ْ߭֞ᄠ๔ሑ෿đѩ౏ሑ෿࠷թ + ఖ֥ Bit[7]čRUĎФᇂ 1bೂ‫ݔ‬૭ඍ‫ژ‬ॖႨđᄵ Rx DMA ْ߭֞ࠗࠃሑ෿bčᆺ‫؀‬/ཿԨ‫ؿ‬Ď + + Register 10.4. DMARXBASEADDR_REG (0x000C) + +31 0 + + 0x000000000 Reset + +START_RECV_LIST ‫ھ‬ሳ‫؍‬Ї‫ࢤݣ‬൬૭ඍ‫ژ‬ਙіᇏֻ၂۱૭ඍ‫ֹࠎ֥ژ‬ᆶbDMA ֥ LSB Bit[1:0] Ф + ޭ੻đѩФଽ҆൪ູಆਬbၹՎđᆃུ LSB ໊ᆺ‫؀‬bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 227 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.5. DMATXBASEADDR_REG (0x0010) + +31 0 + + 0x000000000 Reset + +START_TRANS_LIST ‫ھ‬ሳ‫؍‬Ї‫ؿݣ‬ෂ૭ඍ‫ژ‬ਙіᇏֻ၂۱૭ඍ‫ֹࠎ֥ژ‬ᆶbLSB Bit[1:0] Фޭ੻đ + ᄝଽ҆Ф DMA ൪ູಆਬbၹՎđᆃུ LSB ໊ᆺ‫؀‬bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 228 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.6. DMASTATUS_REG (0x0014) + + (reservedT)S_TREIM_INACT_P(rMesTe_rINveTd) ERROR_BITS TRANS_PROC_SRTEACTEV_PRONCO_SRTMAA_BTINENT_E_INSATUR_MLSYFUMA_MRTAEMLC_VB_(UrIeNSsT_eErvReRdE)_AINRTLYR_ETCRVAR_NWESCD_VTIRN__PETTRCOOVR_CBE_CUSVFTT__ORUINPANTNARSVAE_UCILNVT_DROFAVLNFOTLSWRO_AJWANBTSRB_ABENRUT_SFRT__OUAPNRNOSA_VCIAN_ISLTTOP + +31 30 29 28 27 26 25 23 22 20 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0x0 0x0 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +TS_TRI_INT ‫໊ھ‬іൕ ETH_MAC ֥ൈࡗՄളӮఖଆॶᇏ֥ᇏ؎൙ࡱbೈࡱсྶ‫؀‬౼ ETH_MAC ᇏ + ཌྷႋ֥࠷թఖၛࠆ֤ᇏ؎֥ಒ్ჰၹѩౢԢఃჷđၛࡼ‫ ູ໊گ໊ھ‬1’b0bčᆺ‫؀‬Ď + +EMAC_PMT_INT ‫໊ھ‬іൕ ETH_MAC ֥ PMT ଆॶᇏ֥ᇏ؎൙ࡱbೈࡱсྶ‫؀‬౼ MAC ᇏ֥ PMT + ॥ᇅ‫ބ‬ሑ෿࠷թఖҌି֤֞ಒ్֥ᇏ؎ჰၹѩౢԢఃটჷđࡼ‫ ູ໊گ໊ھ‬1’b0bčᆺ‫؀‬Ď + +ERROR_BITS ‫ھ‬ሳ‫؍‬ᆷൕ֝ᇁሹཌհ༂֥հ༂ো྘đ২ೂ AHB ࢤ१ഈ֥հ༂ཙႋb‫ھ‬ሳ‫ࣇ؍‬ᄝ + Bit[13]čFBIĎᇂ 1 ൈႵིb‫ھ‬ሳ‫؍‬҂߶ളӮᇏ؎bčᆺ‫؀‬Ď + • 3’b000ğRx DMA ཿඔऌԮൻ௹ࡗԛհb + • 3’b011ğTx DMA ‫؀‬ඔऌԮൻ௹ࡗԛհb + • 3’b100ğ‫ ؀‬Rx DMA ૭ඍ‫ژ‬௹ࡗԛհb + • 3’b101ğཿ Tx DMA ૭ඍ‫ژ‬௹ࡗԛհb + • 3’b110ğ‫؀‬౼ Rx DMA ૭ඍ‫ژ‬௹ࡗԛհb + • 3’b111ğ‫؀‬౼ Tx DMA ૭ඍ‫ژ‬௹ࡗԛհb + +TRANS_PROC_STATE ‫ھ‬ሳ‫؍‬іൕ‫ؿ‬ෂ DMA FSM ሑ෿b‫ھ‬ሳ‫؍‬҂߶ളӮᇏ؎b + • 3’b000ğ๔ᆸğ‫ࠇ໊گ‬๔ᆸ‫ؿ‬ԛ֥‫ؿ‬ෂଁ਷b + • 3’b001ğᄎྛğࠆ౼‫ؿ‬ෂԮൻ૭ඍ‫ژ‬b + • 3’b010ğЌ਽b + • 3’b011ğᆞᄝᄎྛğᆞᄝ֩ր‫ؿ‬ෂඔऌЇb + • 3’b100ğᄠ๔ğ‫ؿ‬ෂ૭ඍ‫ژ‬҂ॖႨb + • 3’b101ğᄎྛğܱо‫ؿ‬ෂ૭ඍ‫ژ‬b + • 3’b110ğTIME_STAMP ཿೆሑ෿b + • 3’b111ğᄎྛğࡼ‫ؿ‬ෂඔऌЇඔऌՖ‫ؿ‬ෂߏթԮൻ֞ᇶࠏଽթb + +࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 229 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.6. DMASTATUS_REG (0x0014) + +࠿ഈ၂်࠷թఖ૭ඍb + +RECV_PROC_STATE ‫ھ‬ሳ‫؍‬іൕࢤ൬ DMA FSM ሑ෿b‫ھ‬ሳ‫؍‬҂߶ളӮᇏ؎bčᆺ‫؀‬Ď + +• 3’b000ğ๔ᆸğ‫ࠇ໊گ‬๔ᆸ‫ؿ‬ԛ֥ࢤ൬ଁ਷b + +• 3’b001ğᄎྛğࠆ౼ࢤ൬Ԯൻ૭ඍ‫ژ‬b + +• 3’b010ğЌ਽b + +• 3’b011ğᆞᄝᄎྛğᆞᄝ֩րࢤ൬ඔऌЇb + +• 3’b100ğᄠ๔ğࢤ൬૭ඍ‫ژ‬҂ॖႨb + +• 3’b101ğᄎྛğܱоࢤ൬૭ඍ‫ژ‬b + +• 3’b110ğTIME_STAMP ཿೆሑ෿b + +• 3’b111ğᄎྛğࡼࢤ൬ඔऌЇඔऌՖࢤ൬ߏթԮൻ֞ᇶࠏଽթb + +NORM_INT_SUMM ֒൐ିᇏ؎൐ି࠷թఖᇏ֥ཌྷႋᇏ؎ൈđᆞӈᇏ؎ࠢ‫໊֥ކ‬ᆴ൞ၛ༯໊֥આࠠ + ࠇğ + +• Bit[0]ğ‫ؿ‬ෂᇏ؎b + +• Bit[2]ğ‫ؿ‬ෂߏթ҂ॖႨb + +• Bit[6]ğࢤ൬ᇏ؎b + +• Bit[14]ğิభࢤ൬ᇏ؎b + +ᆺႵໃФ௠з໊֥߶႕ཙᆞӈᇏ؎ࠢ‫໊ކ‬bᆃ൞၂۱ᅔᇌ໊đсྶᄝૄՑႄఏ NIS ᇂ໊֥ཌྷႋ໊ +ౢਬč๙‫ݖ‬ཟ‫໊ھ‬ཿೆ 1ĎФౢԢbč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + +ABN_INT_SUMM ֒ᇏ؎൐ି࠷թఖᇏ֥ؓႋᇏ؎൐ିൈđ٤ᆞӈᇏ؎ࠢ‫໊֥ކ‬ᆴ൞ၛ༯આࠠࠇğ + +• Bit[1]ğ‫ؿ‬ෂࣉӱၘ๔ᆸb + +• Bit[3]ğԮෂ Jabber ӑൈb + +• Bit[4]ğࢤ൬ FIFO ၮԛb + +• Bit[5]ğԮൻ༯ၮb + +• Bit[7]ğࢤ൬ߏԊఖ҂ॖႨb + +• Bit[8]ğࢤ൬ࣉӱၘ๔ᆸb + +• Bit[9]ğࢤ൬ु૊‫ܐ‬ӑൈb + +• Bit[10]ğิభ‫ؿ‬ෂᇏ؎b + +• Bit[13]ğ࿸ᇗሹཌհ༂b + +ᆺႵໃФ௠з໊֥߶႕ཙ٤ᆞӈᇏ؎ࠢ‫໊ކ‬bᆃ൞၂۱ᅔᇌ໊đсྶᄝૄՑႄఏ AIS ᇂ໊֥ཌྷႋ +໊ౢਬൈčཟ‫໊ھ‬ཿೆ 1ĎౢԢbč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + +࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 230 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.6. DMASTATUS_REG (0x0014) + + ࠿ഈ၂်࠷թఖ૭ඍb + + EARLY_RECV_INT ‫໊ھ‬іൕ DMA แԉਔඔऌЇֻ֥၂۱ඔऌߏԊ౵b֒ೈࡱཟ‫໊ھ‬ཿೆ 1 ࠇ‫ھ‬ + ࠷թఖ֥ Bit[6]čRIĎᇂ 1 ൈđ‫໊ھ‬ౢਬbč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + + FATAL_BUS_ERR_INT ‫໊ھ‬іൕ‫ؿ‬ള Bit[25:23] ෮ඍ֥ሹཌհ༂b֒‫໊ھ‬ᇂ 1 ൈđཌྷႋ֥ DMA ႄ + ౣܱоః෮Ⴕ֥ሹཌ٠໙bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + + EARLY_TRANS_INT ‫໊ھ‬іൕေ‫ؿ‬ෂ֥ᆠФປಆԮෂ֞ MTL ‫ؿ‬ෂ FIFObč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + RECV_WDT_TO ᇂ 1 іൕࢤ൬ु૊‫קܐ‬ൈఖᄝࢤ൬֞֒భᆠൈၘࣜ‫ݖ‬௹đ֒భᆠᄝु૊‫ܐ‬ӑൈު + + Фࢩ؎bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + + RECV_PROC_STOP ࢤ൬ࣉӱࣉೆ๔ᆸሑ෿ൈđ‫໊ھ‬ᇂ 1bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + RECV_BUF_UNAVAIL ‫໊ھ‬іൕᇶࠏႚႵࢤ൬ਙіᇏ֥༯၂۱૭ඍ‫ژ‬đѩ౏ DMA ໭‫ࠆم‬౼‫ھ‬૭ඍ + + ‫ژ‬bࢤ൬‫ݖ‬ӱФᄠ๔bေ߫‫گ‬ԩ৘ࢤ൬૭ඍ‫ژ‬đᇶࠏႋ۷‫ڿ‬૭ඍ‫֥ژ‬෮Ⴕಃѩ‫ؿ‬ԛoࢤ൬੽࿘ླ + ౰pଁ਷bೂ‫ݔ‬ીႵ൬֞੽࿘౨౰đᄵࢤ൬ࣉӱᄝ൬֞༯၂۱്љ֥Ԯೆᆠൈ߫‫گ‬bᆺႵ֒ DMA + ႚႵభ၂۱ࢤ൬૭ඍ‫ژ‬ൈđ‫໊ھ‬ҌФᇂ 1bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + + RECV_INT ‫໊ھ‬іൕᆠࢤ൬ၘປӮb֒ࢤ൬ປӮൈđRDES1 ֥ Bit[31] ᄝቋު֥૭ඍ‫ژ‬ᇏФ‫໊گ‬đѩ + ౏ห‫֥ק‬ᆠሑ෿ྐ༏ᄝ૭ඍ‫ژ‬ᇏФ۷ྍbࢤ൬ԩႿᄎྛሑ෿bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + + TRANS_UNDFLOW ‫ ໊ ھ‬і ൕ ‫ ؿ‬ෂ ߏ թ ᄝ ᆠ Ԯ ൻ ௹ ࡗ ऎ Ⴕ ༯ ၮb ‫ ؿ‬ෂ ᄠ ๔đ ѩ ࡼ ༯ ၮ հ ༂ ໊ + TDES0[1] ᇂ 1bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + + RECV_OVFLOW ‫໊ھ‬іൕࢤ൬ߏթᄝᆠࢤ൬‫ݖ‬ӱᇏႵၮԛbೂ‫ٳ҆ݔ‬ᆠФԮෂ֞ႋႨӱ྽đᄵၮ + ԛሑ෿ࡼᄝ RDES0 [11] ᇏᇂ 1bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + + TRANS_JABBER_TO ‫໊ھ‬іൕ‫ؿ‬ෂ Jabber ‫ק‬ൈఖӑൈđ֒ᆠնཬӑ‫ ݖ‬2048 ሳࢫč֒ Jumbo ᆠ + Ф൐ିൈູ 10,240 ሳࢫĎൈ‫ؿ‬ളb֒‫ؿ‬ള Jabber ӑൈൈđԮൻ‫ݖ‬ӱФᇏᆸѩࣉೆ๔ᆸሑ෿bᆃ + ߶֝ᇁ‫ؿ‬ෂ Jabber ӑൈ TDES0 [14] ѓᆽᇂ 1bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + + TRANS_BUF_UNAVAIL ‫໊ھ‬іൕᇶࠏᄝ‫ؿ‬ෂਙіᇏႚႵ༯၂۱૭ඍ‫ژ‬đѩ౏ DMA ໭‫ࠆم‬౼෱bԮ + ൻФᄠ๔bBit[22:20] іൕ‫ؿ‬ෂࣉӱሑ෿ሇߐbေ߫‫گ‬ԩ৘Ԯൻ૭ඍ‫ژ‬đᇶࠏႋ๙‫ݖ‬ഡᇂ TDES0 + [31] ট۷‫ڿ‬૭ඍ‫֥ژ‬෮Ⴕಃđಖު‫ؿ‬ԛԮൻ੽࿘ླ౰ଁ਷bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + + TRANS_PROC_STOP Ԯൻ๔ᆸൈ‫໊ھ‬Фᇂ 1bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + TRANS_INT ‫໊ھ‬іൕᆠԮൻၘປӮbԮൻປӮުđTDES0 ֥ Bit[31]čOWNĎ‫໊گ‬đѩᄝ૭ඍ‫ژ‬ᇏ + + ۷ྍห‫֥ק‬ᆠሑ෿ྐ༏bč‫؀‬/ሱ‫׮‬ഡᇂ/ཿౢԢĎ + +ুᶈྐ༏॓࠯ 231 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.7. DMAOPERATION_MODE_REG (0x0018) + + (reserved) DIS_DRRXO_PS_TDTOISCR_PEFI(_PLreFU_sOESeRRHrv(RWr_ee_RdAsFE)eRRCrDvATVeXM_d_F)SRTFARLM_UFESWSHD_TX_(rFeIsFeOrved) TX_THRESHS_TACRTRT_LS(rTeOsePrv_eTdR)AN(reSsMeIrSveSdI(Or)eNse_rCvFOeWdMD) M_FEAWRNDRD__DFURRNOADMPE_ERG_RFGXRF_MTHROESPHT__SSCETTACRROLT(Nre_DSse_TrFOvRePAd_)MRXE + +31 27 26 25 24 23 22 21 20 19 17 16 14 13 12 11 10 98 7 6 54 32 1 0 + +0 0 0 0 00 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 Reset + + DIS_DROP_TCPIP_ERR_FRAM ᇂ 1 ൈđETH_MAC ҂߶‫ש‬ఙ checksum հ༂֥Їbᇂ 1 ൈđѩ౏ + FWD_ERR_FRAME ູ໊ 0 ൈđ෮Ⴕհ༂֥Ї‫߶׻‬Ф‫ש‬ఙbč‫؀‬/ཿĎ + + RX_STORE_FORWARD ֒Վູ໊ 1 ൈđMTL Ҫ߶ᆰࢤϜཿ֞ RX FIFO ֥Їሇ‫ؿ‬ԛಀbč‫؀‬/ཿĎ + + DIS_FLUSH_RECV_FRAMES ֒Վູ໊ 1 ൈđRX DAM ҂߶Ԋ඗‫ו‬ၹູ৽іࠇߏթ౼҂ॖႨ֥ + Їbč‫؀‬/ཿĎ + + TX_STR_FWD ֒Վູ໊ 1 ൈđѩ౏ᆜ۱‫ؿ‬ෂ֥ᆠၘࣜթԥ֞ TX FIFO ᇏൈđष൓ԮෂЇbՎൈđ + TX_THRESH_CTRL ᇏ֥ᆴФޭ੻bč‫؀‬/ཿĎ + + FLUSH_TX_FIFO ᇂ 1 ൈđTX FIFO ᇏ֥෮ႵᆴФౢԢູଏಪᆴb֒ౢԢປӮުđՎ໊ሱ‫׮‬ౢ + ਬbč‫؀‬/ཿഡᇂ/ሱ‫׮‬ౢԢĎ + + TX_THRESH_CTRL ֒ TX FIFO ᇏ֥ᆴնႿՎ࠻թఖᇏ֥ᚐᆴᆴđष൓‫ؿ‬ෂᆠb֒ᆜᆠ֥նཬཬႿ + ᆃ۱ᚐᆴൈđՎᆠ္ࡼФ‫ؿ‬ෂbࣇࣇ TX_STR_FWD ࠷թఖູ 0 ൈđՎࣇ࠷թఖҌႵིbᚐᆴն + ཬğ3’b000ğ64Ġ3’b001ğ128Ġ3’b010ğ192Ġ3’b011ğ256Ġ3’b100ğ40Ġ3’b101ğ32Ġ3’b110ğ + 24Ġ3’b111ğ1bč‫؀‬/ཿĎ + + START_STOP_TRANSMISSION_COMMAND ֒ TX FIFO ᇏ֥ᆴնႿՎ࠻թఖᇏ֥ᚐᆴᆴđष൓‫ؿ‬ + ෂᆠb֒ᆜᆠ֥նཬཬႿᆃ۱ᚐᆴൈđՎᆠ္ࡼФ‫ؿ‬ෂbࣇ֒ TX_STR_FWD ࠷թఖູ 0 ൈđՎ + ࠷թఖҌႵིbᚐᆴնཬğ000ğ64, 001ğ128, 010ğ192, 011ğ256, 100ğ40, 101ğ32, 110ğ + 24, 111ğ16bč‫؀‬/ཿĎ + + FWD_ERR_FRAME ֒Վູ໊ 0 ൈđRX FIFO ߶ౢԢ‫ו‬෮Ⴕհ༂ᆠčCRC հđԊ๬հđӑնᆠհđ + ु૊‫ܐ‬ӑൈհđၮԛհĎđ‫ڎ‬ᄵ߶ሇ‫ؿ‬ᆃུհ༂ᆠbč‫؀‬/ཿĎ + + FWD_UNDER_GF ֒Վ໊ᇂ 1 ൈđRX FIFO ߶ሇ‫ؿ‬Їও PAD ‫ ބ‬CRC ֥ࢠཬᆠčӉ؇ཬႿ 64 ሳࢫ + ֥ᆞಒᆠĎđ‫ڎ‬ᄵ҂߶ሇ‫ؿ‬b + + DROP_GFRM ֒Վ໊ᇂ 1 ൈđETH_MAC ߶‫ וש‬RX FIFO ᇏ֥ӑնᆠbč‫؀‬/ཿĎ + + ࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 232 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.7. DMAOPERATION_MODE_REG (0x0018) + + ࠿ഈ၂်࠷թఖ૭ඍb + RX_THRESH_CTRL 2’b00ğ64đ2’b01ğ32đ2’b10ğ96đ2’b11ğ128. ֒ RX FIFO ᇏ֥ᆴնႿᆃ۱ + + ᚐᆴൈđ߶Ԩ‫ ؿ‬DMA ष൓ࢤ൳Վᆠ֥ඔऌ֞ߏթᇏb2’b00ğ64Ġ2’b01ğ32Ġ2’b10ğ96Ġ2’b11ğ + 128bč‫؀‬/ཿĎ + OPT_SECOND_FRAME ֒Վ໊ᇂ 1 ൈđᄝభ၂ᆠ֥Ԯෂሑ෿Ф႗ࡱࠆ౼ᆭభ TX DMA ष൓ԩ৘༯ + ၂ᆠ֥ඔऌbč‫؀‬/ཿĎ + START_STOP_RX ᇂ 1 ൈđRX DMA ष൓ࢤ൬ඔऌđ֒Վູ໊ 0 ൈđRX DMA ࢤ൬ປ֒భᆞᄝࢤ൬ + ֥ᆠᆭު๔ᆸࢤ൬ྍ֥ᆠbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 233 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.8. DMAIN_EN_REG (0x001C) + + (reserved) DMAIND_MNAISINDE_MAAISINDE_MEARINIE_F(rBesEeErvedD) MAIND_MEATIINDE_MRAWINDT_MERASINDE_MRABINDU_MERAIEIND_MUAIEIND_MOAIEIND_MTAJITNDE_MTABIUNDE_MTASIEN_TIE + +31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + DMAIN_NISE ‫໊ھ‬ᇂ 1 ൈđ൐ିᆞӈᇏ؎ࠢ‫ކ‬b֒‫໊گ໊ھ‬ൈđܱоᆞӈᇏ؎ࠢ‫ކ‬b‫໊ھ‬൐ିሑ෿ + ࠷թఖᇏ֥ၛ༯ᇏ؎ğሑ෿࠷թఖ Bit[0]ğ‫ؿ‬ෂᇏ؎bሑ෿࠷թఖ Bit[2]ğ‫ؿ‬ෂߏթ҂ॖႨbሑ෿ + ࠷թఖ Bit[6]ğࢤ൬ᇏ؎bሑ෿࠷թఖ Bit[14]ğᄪ௹ࢤ൬ᇏ؎bč‫؀‬/ཿĎ + + DMAIN_AISE ‫໊ھ‬ᇂ 1 ൈđ൐ି٤ᆞӈᇏ؎߸ሹb‫໊گ໊ھ‬ൈđܱо٤ᆞӈᇏ؎ࠢ‫ކ‬b‫໊ھ‬൐ିሑ + ෿࠷թఖᇏ֥ၛ༯ᇏ؎ğ + + • ሑ෿࠷թఖ Bit[1]ğԮෂࣉӱ๔ᆸb + + • ሑ෿࠷թఖ Bit[3]ğԮෂ Jabber ӑൈb + + • ሑ෿࠷թఖ Bit[4]ğࢤ൬ၮԛb + + • ሑ෿࠷թఖ Bit[5]ğ‫ؿ‬ෂ༯ၮb + + • ሑ෿࠷թఖ Bit[7]ğࢤ൬ߏթ౵҂ॖႨb + + • ሑ෿࠷թఖ Bit[8]ğࢤ൬ࣉӱ๔ᆸb + + • ሑ෿࠷թఖ Bit[9]ğࢤ൬ु૊‫ܐ‬ӑൈb + + • ሑ෿࠷թఖ Bit[10]ğิభ‫ؿ‬ෂᇏ؎b + + • ሑ෿࠷թఖ Bit[13]ğ࿸ᇗ֥ሹཌհ༂bč‫؀‬/ཿĎ + + DMAIN_ERIE ֒‫໊ھ‬๙‫ݖ‬ᆞӈᇏ؎ࠢ‫ކ‬ေ൐ି໊čBit[16]Ďᇂ 1 ൈđ൐ିิభࢤ൬ᇏ؎b֒‫گ໊ھ‬ + ໊ൈđܱоิభࢤ൬ᇏ؎bč‫؀‬/ཿĎ + + DMAIN_FBEE ֒‫໊ھ‬๙‫ݖ‬٤ᆞӈᇏ؎ࠢ‫ކ‬൐ିčBit[15]Ďᇂ 1 ൈđ൐ି࿸ᇗሹཌհ༂ᇏ؎b֒‫໊ھ‬ + ‫໊گ‬ൈđܱоᇁଁሹཌհ༂൐ିᇏ؎bč‫؀‬/ཿĎ + + DMAIN_ETIE ֒‫໊ھ‬๙‫ݖ‬٤ᆞӈᇏ؎ࠢ‫ކ‬൐ି໊čBit[15]Ďᇂ 1 ൈđ൐ିิభ‫ؿ‬ෂᇏ؎b֒‫گ໊ھ‬ + ໊ൈđܱоิభ‫ؿ‬ෂᇏ؎bč‫؀‬/ཿĎ + + DMAIN_RWTE ֒‫໊ھ‬๙‫ݖ‬٤ᆞӈᇏ؎ࠢ‫ކ‬൐ି໊čBit 15Ďᇂ 1 ൈđࢤ൬ु૊‫ܐ‬ӑൈᇏ؎൐ିb֒ + ‫໊گ໊ھ‬ൈđܱоࢤ൬ु૊‫ܐ‬ӑൈᇏ؎bč‫؀‬/ཿĎ + + DMAIN_RSE ֒‫໊ھ‬Ⴎ٤ᆞӈᇏ؎ࠢ‫ކ‬൐ି໊čBit[15]Ďᇂ 1 ൈđ൐ିࢤ൬๔ᆸᇏ؎b֒‫໊گ໊ھ‬ + ൈđܱоࢤ൬๔ᆸᇏ؎bč‫؀‬/ཿĎ + + DMAIN_RBUE ֒‫໊ھ‬๙‫ݖ‬٤ᆞӈᇏ؎ࠢ‫ކ‬൐ି໊čBit[15]Ďᇂ 1 ൈđ൐ିࢤ൬ߏթ҂ॖႨᇏ؎b֒ + ‫໊گ໊ھ‬ൈđܱоࢤ൬ߏթ౵҂ॖႨᇏ؎bč‫؀‬/ཿĎ + + DMAIN_RIE ֒‫໊ھ‬๙‫ݖ‬ᆞӈᇏ؎ࠢ‫ކ‬൐ି໊čBit[16]Ďᇂ 1 ൈđ൐ିࢤ൬ᇏ؎b֒‫໊گ໊ھ‬ൈđܱ + оࢤ൬ᇏ؎bč‫؀‬/ཿĎ + + ࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 234 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.8. DMAIN_EN_REG (0x001C) + + ࠿ഈ၂်࠷թఖ૭ඍb + DMAIN_UIE ֒‫໊ھ‬๙‫ݖ‬٤ᆞӈᇏ؎ࠢ‫ކ‬൐ି໊čBit[15]Ďᇂ 1 ൈđ൐ି‫ؿ‬ෂ༯ၮᇏ؎b֒‫໊گ໊ھ‬ + + ൈđܱо༯ၮᇏ؎bč‫؀‬/ཿĎ + DMAIN_OIE ֒Վ໊๙‫ݖ‬٤ᆞӈᇏ؎ࠢ‫ކ‬൐ି໊čBit[15]Ďᇂ 1 ൈđ൐ିࢤ൬ၮԛᇏ؎b֒‫໊گ໊ھ‬ + + ൈđܱоၮԛᇏ؎bč‫؀‬/ཿĎ + DMAIN_TJTE ֒‫໊ھ‬๙‫ݖ‬ၳӈᇏ؎ࠢ‫ކ‬൐ି໊čBit[15]Ďᇂ 1 ൈđ൐ି‫ؿ‬ෂ Jabber ӑൈᇏ؎b֒ + + ‫໊گ໊ھ‬ൈđܱо‫ؿ‬ෂ Jabber ӑൈᇏ؎bč‫؀‬/ཿĎ + DMAIN_TBUE ֒‫໊ھ‬๙‫ݖ‬ᆞӈᇏ؎ࠢ‫ކ‬൐ି໊čBit[16]Ďᇂ 1 ൈđ൐ି‫ؿ‬ෂߏթ҂ॖႨᇏ؎b֒‫ھ‬ + + ໊‫໊گ‬ൈđܱо‫ؿ‬ෂߏթ҂ॖႨᇏ؎bč‫؀‬/ཿĎ + DMAIN_TSE ֒Վ໊๙‫ݖ‬ၳӈᇏ؎ࠢ‫ކ‬൐ି໊čBit[15]Ďᇂ 1 ൈđ൐ି‫ؿ‬ෂ๔ᆸᇏ؎b֒‫໊گ໊ھ‬ + + ൈđܱо‫ؿ‬ෂ๔ᆸᇏ؎bč‫؀‬/ཿĎ + DMAIN_TIE ֒‫໊ھ‬๙‫ݖ‬ᆞӈᇏ؎ࠢ‫ކ‬൐ି໊čBit[16]Ďᇂ 1 ൈđ൐ି‫ؿ‬ෂᇏ؎b֒‫໊گ໊ھ‬ൈđܱ + + о‫ؿ‬ෂᇏ؎bč‫؀‬/ཿĎ + + Register 10.9. DMAMISSEDFR_REG (0x0020) + + (reservedO) verflow_BFOC Overflow_FC Overflow_BMFC Missed_FC 0 + 0x0 0x0 +30 29 28 27 17 16 10 Reset + +0 0 0x0 0x0 + +Overflow_BFOC ֒࠷թఖ Overflow_FC (Bits[27:17]) ၮԛൈđՎ໊ᇂ 1b္ࣼ൞ඪ RX FIFO ၮԛđ๝ + ൈၮԛᆠ࠹ඔఖղ֞ਔቋնᆴbᄝᆃᇕ౦ঃ༯đၮԛᆠ࠹ඔఖ߶‫໊گ‬Ӯ 0đՎ໊іൕ‫ؿ‬ളၮԛྛ + ູbč‫؀‬/ሱ‫׮‬ഡᇂ/‫؀‬ౢԢĎ + +Overflow_FC Վ໊іൕၮԛ‫ުݖ‬Ⴕ‫؟‬ഒ۱ᆠၮԛ‫ש‬ാ‫ط‬ીႵഈԮ۳ഈҪႋႨӱ྽đMTL ֥ FIFO ૄ + ၮԛ၂Ցđᆃ۱࠹ඔఖࣼ߶৆ࡆ 1đૄՑ‫؀‬౼‫࠷ھ‬թఖđ࠹ඔఖࣼ߶ౢԢbč‫؀‬/ሱ‫׮‬ഡᇂ/‫؀‬ౢԢĎ + +Overflow_BMFC ֒࠷ఖ Missed_FC (Bits[15:0]) ၮԛൈđՎ໊ᇂ 1b္ࣼ൞ඪՎൈႋႨ؊ߏթ౼҂ + ॖႨđ๝ൈ‫ש‬ാᆠ࠹ඔఖղ֞ਔቋնᆴbᄝᆃᇕ౦ঃ༯đ‫ש‬ാᆠ࠹ඔఖ߶‫໊گ‬Ӯ 0đՎ໊іൕ‫ؿ‬ + ള࠹ඔఖ‫ؿ‬ളၮԛྛູbč‫؀‬/ሱ‫׮‬ഡᇂ/‫؀‬ౢԢĎ + +Missed_FC Վ໊іൕࢤ൬؊ߏթ౵҂ॖႨđ֝ᇁႵ‫؟‬ഒ۱ᆠ‫ש‬ാ‫ط‬ીႵഈԮ۳ഈҪႋႨӱ྽đDMA + ૄ‫ש‬ఙ၂ᆠđᆃ۱࠹ඔఖࣼ߶৆ࡆ 1đૄՑ‫؀‬౼‫࠷ھ‬թఖđ࠹ඔఖࣼ߶ౢԢbč‫؀‬/ሱ‫׮‬ഡᇂ/‫؀‬ౢ + ԢĎ + +ুᶈྐ༏॓࠯ 235 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.10. DMARINTWDTIMER_REG (0x0024) + + (reserved) RIWTC + 0x000 +31 87 0 + +000000000000000000000000 Reset + + RIWTC ‫໊ھ‬іൕ༢๤ൈᇒᇛ௹ඔӰၛ 256bᄝ Rx DMA ປӮԮෂႮႿཌྷႋ૭ඍ‫ ژ‬RDES1 [31] ᇏ֥ + ഡᇂ‫ط‬ໃഡᇂ RI ሑ෿໊֥ᆠުđु૊‫קܐ‬ൈఖࡼၛщӱᆴԨ‫ؿ‬bु૊‫קܐ‬ൈఖ࠹ඔ๔ᆸުđRI + ໊ᇂ 1đ‫ק‬ൈఖ๔ᆸb֒ႮႿࢤ൬ᆠ֥ RDES1[31] ֥ RI ഡᇂđRI (RECV_INT) ໊Фᇂູۚ‫׈‬௜ൈđ + ु૊‫קܐ‬ൈఖ‫໊گ‬bč‫؀‬/ཿĎ + + Register 10.11. DMATXCURRDESC_REG (0x0048) + +31 0 + + 0x000000000 Reset + + TRANS_DECR_ADDR_PTR ‫໊گ‬ൈౢਬbҠቔ௹ࡗႮ DMA ۷ྍᆷᆌb֒భ‫ؿ‬ෂ৽іֹ֥ᆶbčᆺ + ‫؀‬Ď + + Register 10.12. DMARXCURRDESC_REG (0x004C) + +31 0 + + 0x000000000 Reset + + RECV_DECR_ADDR_PTR ‫໊گ‬ൈౢਬbҠቔ௹ࡗႮ DMA ۷ྍᆷᆌb֒భࢤ൬৽іֹ֥ᆶbčᆺ‫؀‬Ď + + Register 10.13. DMATXCURRADDR_BUF_REG (0x0050) + +31 0 + + 0x000000000 Reset + + TRANS_BUFF_ADDR_PTR ‫໊گ‬ൈౢਬbҠቔ௹ࡗႮ DMA ۷ྍᆷᆌb֒భ‫ؿ‬ෂ৽іֹ֥ᆶbčᆺ + ‫؀‬Ď + + Register 10.14. DMARXCURRADDR_BUF_REG (0x0054) + +31 0 + + 0x000000000 Reset + + RECV_BUFF_ADDR_PTR ‫໊گ‬ൈౢਬbҠቔ௹ࡗႮ DMA ۷ྍᆷᆌb֒భࢤ൬৽іֹ֥ᆶbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 236 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.15. EMACCONFIG_REG (0x1000) + +(reserved) SAIRC ASS2KP (reserved) EMACEWMAATCC(rJeHAsDBeOrBvEGEeMdRA) CJUMBEOMFARCAINMTEEREMFRAACEMDMEISAGACAEBMPMLIEIACCERFMSEASCPEERMEXADOCWELMNOAOCPEDBMUAAPCCLEKREMXXAIPCC(rReOEsFeTFrRvELYeMOdAA) DCPAEDMCARCCBSAETCMRKIAPOCEFDMFELAFIMCEERITTMXRAACLRCXHPELTCFK + +31 30 28 27 26 24 23 22 21 20 19 17 16 15 14 13 12 11 10 9 8 7 6 54 3 21 0 + +0 0x0 00 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 0 0x0 Reset + + SAIRC ‫ھ‬ሳ‫؍‬॥ᇅ෮ႵԮൻᆠ֥ჷֹᆶҬೆࠇูߐbBit[30] ۴ऌ Bit[29:28] ֥ᆴᆷ‫ࡼק‬ଧ۱ MAC + ֹᆶ࠷թఖč0 ࠇ 1ĎႨႿჷֹᆶҬೆࠇูߐbč‫؀‬/ཿĎ + + • 2’b0xğൻೆྐ‫ ݼ‬mti_sa_ctrl_i ‫ ބ‬ati_sa_ctrl_i ॥ᇅ SA ሳ‫֥؍‬ളӮb + + • 2’b10ğೂ‫ ࡼݔ‬Bit[30] ᇂ 0đᄵ MAC ࡼ MAC ֹᆶ 0 ࠷թఖ֥ଽಸҬೆ֞෮ႵԮൻᆠ֥ SA + ሳ‫؍‬ᇏbೂ‫ ࡼݔ‬Bit[30] ᇂ 1đᄵ MAC ࡼ MAC ֹᆶ 1 ࠷թఖ֥ଽಸҬೆ෮ႵԮൻᆠ֥ SA + ሳ‫؍‬b + + • 2’b11ğೂ‫ ࡼݔ‬Bit[30] ᇂ 0đᄵ MAC ูߐ෮ႵԮൻᆠ֥ SA ሳ‫؍‬ᇏ֥ MAC ֹᆶ 0 ࠷թఖ + ֥ଽಸbೂ‫ ࡼݔ‬Bit[30] ᇂ 1đᄵ MAC ูߐ෮ႵԮൻᆠ֥ SA ሳ‫؍‬ᇏ֥ MAC ֹᆶ 1 ࠷թఖ + ֥ଽಸb + + ASS2KP ᇂ 1 ൈđMAC ࡼ෮ႵӉ؇҂ӑ‫ ݖ‬2,000 ۱ሳࢫ֥ᆠ൪ູ௴๙ඔऌЇb֒ Bit[20]čJEĎໃ + ᇂ 1 ൈđMAC ࡼ෮Ⴕࢤ൬֥֞նႿ 2K ሳࢫ֥ᆠ൪ູऍᆠb֒Վ໊‫ ౏໊گ‬Bit[20]čJEĎໃᇂ 1 + ൈđMAC ࡼ෮Ⴕ൬֥֞նཬӑ‫ ݖ‬1,518 ሳࢫčѓ࠺ູ 1,522 ሳࢫĎ֥ᆠ൪ູऍᆠb֒ Bit[20] ᇂ + 1 ൈđ‫໊ؓھ‬ऍᆠሑ෿ીႵ႕ཙbč‫؀‬/ཿĎ + + EMACWATCHDOG ֒‫໊ھ‬ᇂ 1 ൈđMAC ܱоࢤ൬ఖഈ֥ु૊‫קܐ‬ൈఖbMAC ॖၛࢤ൬ቋ‫ ؟‬16,383 + ሳࢫ֥ᆠb֒‫໊گ໊ھ‬ൈđMAC ҂ࢤ൬ӑ‫ ݖ‬2048 ሳࢫčೂ‫ ݔ‬JE ໊ᇂۚđᄵູ 10,240 ሳࢫĎ֥ + ࢤ൬ᆠࠇु૊‫ܐ‬ӑൈ࠷թఖᇏഡᇂ֥ᆴbMAC ్؎ӑԛु૊‫ܐ‬ཋᇅٓຶᆭުࢤ൬֥֞಩‫ޅ‬ሳࢫ + ඔbč‫؀‬/ཿĎ + + EMACJABBER ֒‫໊ھ‬ᇂ 1 ൈđMAC ܱо‫ؿ‬ෂఖഈ֥ Jabber ‫ק‬ൈఖbMAC ॖၛԮൻӉղ 16,383 + ሳࢫ֥ᆠb֒Վ໊‫໊گ‬ൈđೂ‫ݔ‬ႋႨӱ྽ᄝԮൻ‫ݖ‬ӱᇏ‫ؿ‬ෂਔӑ‫ ݖ‬2048 ሳࢫčೂ‫ ݔ‬JE ഡᇂູ + ۚ‫׈‬௜đᄵູ 10240 ሳࢫĎ֥ඔऌđMAC ࡼ్؎‫ؿ‬ෂఖbč‫؀‬/ཿĎ + + EMACJUMBOFRAME ֒‫໊ھ‬ᇂ 1 ൈđMAC ᄍྸ 9,018 ሳࢫ֥ऍᆠčࠇ 9,022 ሳࢫ֥ VLAN ѓ࠺ + ᆠĎđ‫ط‬҂ᄝࢤ൬ᆠሑ෿ᇏБۡऍնᆠհ༂bč‫؀‬/ཿĎ + + EMACINTERFRAMEGAP ᆃ໊ུ॥ᇅԮൻൈᆠࡗ֥ቋཬ IFGbč‫؀‬/ཿĎ + + • 3’b000ğ96 бหൈࡗb + + • 3’b001ğ88 бหൈࡗb + + • 3’b010ğ80 бหൈࡗb + + • 3’b111ğ40 бหൈࡗbᄝ϶ච‫۽‬ଆൔ༯đቋཬ֥ IFG ູ 64 бหൈࡗčIFG = 100Ďb + + ࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 237 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 10 ၛ෾ຩ (MAC) + + Register 10.15. EMACCONFIG_REG (0x1000) + + ࠿ഈ၂်࠷թఖ૭ඍb + + EMACDISABLECRS ֒‫໊ھ‬ᇂۚൈđMAC ‫ؿ‬ෂఖᄝ϶ච‫۽‬ଆൔ༯֥ᆠ‫ؿ‬ෂ௹ࡗޭ੻ MII CRS ྐ‫ݼ‬b + Վ౨౰҂߶֝ᇁᄝԮൻ‫ݖ‬ӱᇏႮႿᄛѯ‫ש‬ാࠇ໭ᄛѯ‫ط‬Ӂള֥հ༂b֒Վູ໊֮ൈđMAC ‫ؿ‬ෂ + ఖႮႿᄛѯᆍ๐‫ط‬Ӂളᆃဢ֥հ༂đമᇀॖၛᇏᆸԮൻbč‫؀‬/ཿĎ + + EMACMII ‫໊ھ‬࿊ᄴၛ෾ຩྐ‫ݼ‬ཌ෎؇bؓႿ 10 ࠇ 100 Mbps Ҡቔđ‫໊ھ‬ᇂ 1bᄝ 10 ࠇ 100 Mbps + ҠቔᇏđՎ໊ა FES(EMACFESPEED) ໊၂ఏ࿊ᄴྐ‫ݼ‬ཌ෎ੱbč‫؀‬/ཿĎ + + EMACFESPEED ‫໊ھ‬࿊ᄴ MIIđRMII ࢤ१෎؇b0ğ10 MbpsĠ1ğ100 Mbpsbč‫؀‬/ཿĎ + + EMACRXOWN ‫໊ھ‬ᇂ 1 ൈđᄝ϶ච‫۽‬ଆൔ༯֒ TX_EN Ԩ‫ؿ‬ᇏ؎ൈđMAC ܱоࢤ൬ᆠb‫໊گ໊ھ‬ൈđ + MAC ࡼᄝԮൻൈࢤ൬ PHY ‫ؿ‬ԛ֥෮ႵඔऌЇbMAC ԩႿಆච‫۽‬ଆൔൈđ‫໊ھ‬҂ൡႨbč‫؀‬/ཿĎ + + EMACLOOPBACK ‫໊ھ‬ᇂ 1 ൈđMAC ൐Ⴈ߭‫ט‬ଆൔ MIIbMII ࢤ൬ൈᇒൻೆྐ‫ݼ‬čCLK_RXĎ൞ߌ + ߭ᆞӈ‫۽‬ቔ෮сླ֥đၹູ‫ؿ‬ෂൈᇒᄝଽ҆ીႵߌ߭bč‫؀‬/ཿĎ + + EMACDUPLEX ‫໊ھ‬ᇂ 1 ൈđMAC ‫۽‬ቔᄝಆච‫۽‬ଆൔ༯đॖၛ๝ൈ‫ؿ‬ෂ‫ࢤބ‬൬ඔऌb‫໊ھ‬ᄝಆච + ‫۽‬ଆൔ༯ູ ROđଏಪᆴູ 1’b1bč‫؀‬/ཿĎ + + EMACRXIPCOFFLOAD ֒‫໊ھ‬ᇂ 1 ൈđMAC ࠹ෘ෮Ⴕࢤ൬֥ၛ෾ຩᆠႵིᄛ‫ ֥ހ‬16 ໊֥Ҁ઒‫ބ‬đ + ᄜؓཌྷࡆ‫ބ‬౼Ҁb෱ߎ࡟Ұ IPv4 Б๨཮ဒ‫ބ‬čࢤ൬֥֞ၛ෾ຩᆠ֥ሳࢫ 25/26 ࠇ 29/30čVLAN + ѓ࠺Ď൞‫ࢤؓڎ‬൬ᆠ൞ᆞಒ֥đѩᄝࢤ൬ሑ෿ሳᇏ۳ԛሑ෿bMAC ߎࡼ IP Б๨ඔऌБႵི‫ڵ‬ᄛ + + čIPv4 Б๨ު֥ሳࢫĎ16 ໊཮ဒ‫֞ࡆڸބ‬ႋႨӱ྽֥ၛ෾ຩᆠ֒ᇏč֒౼ཨ࿊ᄴো྘ 2 COE ൈĎb + ‫໊گ໊ھ‬ൈđ‫ିۿھ‬Ф࣌ᆸbč‫؀‬/ཿĎ + + EMACRETRY ֒‫໊ھ‬ᇂ 1 ൈđMAC ᆺӇ൫၂ՑԮൻb֒ MII ࢤ१ഈ‫ؿ‬ളԊ๬ൈđMAC ࡼޭ੻֒భ + ᆠԮൻđѩᄝԮൻᆠሑ෿ᇏБۡႮႿԛགྷ‫؟ݖ‬Ԋ๬հ༂֥ᆠᇔᆸb֒‫໊گ໊ھ‬ൈđMAC ࡼ۴ऌ + BL ሳ‫؍‬čBit [6:5]Ď֥ഡᇂӇ൫ᇗ൫b‫ࣇ໊ھ‬ൡႨႿ϶ච‫۽‬ଆൔbč‫؀‬/ཿĎ + + EMACPADCRCSTRIP ֒‫໊ھ‬ᇂ 1 ൈđᆺႵᄝӉ؇ሳ‫֥؍‬ᆴཬႿ 1,536 ሳࢫ֥౦ঃ༯đMAC Ҍಀ + ԢԮೆᆠഈ֥ Pad ࠇ FCS ሳ‫؍‬b෮Ⴕࢤ൬֥֞Ӊ؇ሳ‫؍‬նႿࠇ֩Ⴟ 1,536 ሳࢫ֥ᆠࡼФԮෂ֞ + ႋႨӱ྽đ‫ط‬҂ಀԢ Pad ࠇ FCS ሳ‫؍‬b֒‫໊گ໊ھ‬ൈđMAC ࡼ෮Ⴕࢤ൬֥ᆠԮ‫־‬۳ᇶࠏđ‫ط‬҂ + ྩ‫ڿ‬෱ૌbč‫؀‬/ཿĎ + + EMACBACKOFFLIMIT ๼хࠞཋथ‫ק‬ᄝ‫ؿ‬ളԊ๬ުđᄝᇗ൫ൈᇗྍνஆԮൻᆭభđMAC ֩ր֥ൈ + ༣ൈࡗ࿼Ӿč10/100 Mbps ֥ 512 бหൈࡗĎ֥ෛࠏᆜඔčrĎb‫ࣇ໊ھ‬ൡႨႿ϶ච‫۽‬ଆൔb00ğ + k = minčnđ10Ďb01ğk = minčnđ8Ďb10ğk = minčnđ4Ďb11ğk = minčnđ1Ďđఃᇏ n = ᇗ + ԮӇ൫Ցඔbෛࠏᆜඔ r ֥౼ᆴٓຶູ 0 = 8 * fBCKb + + ๭ 12­2. I2S ൈᇒ + +I2Sn_CLK ֥௔ੱ fi2s ა‫ٳ‬௔ఖൈᇒჷ௔ੱ fpll ࡗ֥ܱ༢ೂ༯ğ + + fi2s = fpll + + N + b + a + +ఃᇏđN>=2đN ؓႋ I2S_CLKM_CONF_REG ࠷թఖᇏ֥ I2S_CLKM_DIV_NUM[7:0] ໊đb ູ +I2S_CLKM_DIV_B[5:0] ໊đa ູ I2S_CLKM_DIV_A[5:0] ໊b + +ᄝᇶࠏଆൔ༯đI2S ଆॶ֥Աྛൈᇒ BCK Ⴎ I2Sn_CLK ‫ٳ‬௔ࠆ֤bࠧğ + + fBCK = fi2s + M + +ఃᇏđM>=2đᄝᇶࠏ‫ؿ‬ෂଆൔ༯đM ູ࠷թఖ I2S_SAMPLE_RATE_CONF_REG ֥ +I2S_TX_BCK_DIV_NUM[5:0] ໊đᄝᇶࠏࢤ൬ଆൔ༯đM ູ࠷թఖ I2S_SAMPLE_RATE_CONF_REG ֥ +I2S_RX_BCK_DIV_NUM[5:0] ໊b + +ুᶈྐ༏॓࠯ 283 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + +12.4 I2S ଆൔ + +ESP32 I2S ଆॶଽᇂඔऌ A ੰ࿢෪/ࢳ࿢෪ଆॶđႨႿؓࢤ൬֥֞ၻ௔ඔऌࣉྛ A ੰ෪/ࢳ࿢෪Ҡቔbೂ‫ݔ‬ေ൐ +Ⴈ A ੰ෪/ࢳ࿢෪ଆॶđླေࡼ I2S_CONF1_REG ࠷թఖ֥ RX_PCM_BYPASS бห‫ ބ‬TX_PCM_BYPASS бห +ౢਬb + +12.4.1 ᆦӻ֥ၻ௔ѓሙ + +I2S ଆൔ༯đBCK ູԱྛൈᇒĠWS ູ๙֡࿊ᄴྐ‫ݼ‬đႨႿіൕቐႷല్֥֡ߐĠSD ູԱྛඔऌྐ‫ݼ‬đԮൻၻ +௔ඔऌbWS ྐ‫ ބݼ‬SD ྐ‫ݼ‬ᄝ BCK ֥༯ࢆခ‫ؿ‬ളэ߄đѩᄝ BCK ֥ഈശခҐဢ SD ྐ‫ݼ‬bೂ‫࠷ࡼݔ‬թఖ +I2S_CONF_REG ֥ I2S_RX_RIGHT_FIRST бห‫ ބ‬I2S_TX_RIGHT_FIRST бห‫׻‬ᇂ 1đіൕ I2S ଆॶ൮༵ࢤ൬‫ބ‬ +‫ؿ‬ෂ֥൞Ⴗല֡ඔऌđ‫ڎ‬ᄵູ൮༵ࢤ൬‫ؿބ‬ෂ֥൞ቐല֡ඔऌb + +12.4.1.1 Philips ѓሙ + + ๭ 12­3. Philips ѓሙ + +ೂ๭ 12-3 ෮ൕđᄝ Philips ѓሙ༯đᄝ BCK ֥༯ࢆခđWS ྐ‫༵ݼ‬Ⴟ SD ྐ‫ݼ‬၂۱ BCK ൈᇒᇛ௹ष൓э߄đࠧ +WS ྐ‫ݼ‬Ֆ֒భ๙֡ඔऌֻ֥၂۱໊ᆭభ֥၂۱ൈᇒष൓Ⴕིđѩᄝ֒భ๙֡ඔऌ‫ؿ‬ෂࢲඏభ၂۱ BCK ൈᇒᇛ +௹э߄bSD ྐ‫ݼ‬ཌ൮༵Ԯൻၻ௔ඔऌ֥ቋۚႵ໊ིbೂ‫ٳݔ‬љࡼ࠷թఖ I2S_CONF_REG ֥ +I2S_RX_MSB_SHIFT бห‫ ބ‬I2S_TX_MSB_SHIFT бหᇂ 1đI2S ଆॶࢤ൬ඔऌ‫ؿބ‬ෂඔऌࡼ൐Ⴈ Philips ѓ +ሙb + +12.4.1.2 MSB ؓఊѓሙ + + ๭ 12­4. MSB ؓఊѓሙ + +ೂ๭ 12-4 ෮ൕđMSB ؓఊѓሙ༯đᄝ BCK ༯ࢆခđWS ྐ‫ ބݼ‬SD ྐ‫ݼ‬๝ൈэ߄bWS ӻ࿃֞֒భ๙֡ඔऌ +‫ؿ‬ෂࢲඏđSD ྐ‫ݼ‬ཌഈ൮༵Ԯൻၻ௔ඔऌ֥ቋ໊ۚbೂ‫࠷ݔ‬թఖ I2S_CONF_REG ֥ I2S_RX_MSB_SHIFT б +ห‫ ބ‬I2S_TX_MSB_SHIFT бหౢਬđᄵ I2S ଆॶࢤ൬ඔऌ‫ؿބ‬ෂඔऌࡼ൐Ⴈ MSB ؓఊѓሙb + +ুᶈྐ༏॓࠯ 284 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + +12.4.1.3 PCM ѓሙ + + ๭ 12­5. PCM ѓሙ + +ೂ๭ 12-5 ෮ൕđᄝ PCM ѓሙ֥؋ᆠ๝҄ଆൔ༯đᄝ BCK ֥༯ࢆခđWS ྐ‫༵ݼ‬Ⴟ SD ྐ‫ݼ‬၂۱ BCK ൈᇒᇛ +௹ष൓э߄đࠧ WS ྐ‫ݼ‬Ֆ֒భ๙֡ඔऌֻ֥၂۱໊ᆭభ֥၂۱ൈᇒष൓Ⴕིđѩӻ࿃ 1 ۱ BCK ൈᇒᇛ௹b +SD ྐ‫ݼ‬ཌഈ൮༵Ԯൻၻ௔ඔऌ֥ቋ໊ۚbೂ‫࠷ࡼݔ‬թఖ I2S_CONF_REG ֥ I2S_RX_SHORT_SYNC бห‫ބ‬ +I2S_TX_SHORT_SYNC бหᇂ 1đପહ I2S ଆॶࢤ൬ඔऌ‫ؿބ‬ෂඔऌࡼ൐Ⴈ؋ᆠ๝҄ଆൔb + +12.4.2 ଆॶ‫໊گ‬ + +࠷թఖ I2S_CONF_REG ᇏ֥֮ඹ۱бหູ I2S_TX_RESET бหaI2S_RX_RESET бหaI2S_TX_FIFO_RESET +бห‫ ބ‬I2S_RX_FIFO_RESET бหđ‫ٳ‬љіൕؓࢤ൬ଆॶa‫ؿ‬ෂଆॶ‫ބ‬ఃؓႋ֥ FIFO ࣉྛ‫໊گ‬bປӮ၂Ց‫໊گ‬ +Ҡቔླေ༵ࡼؓႋбหᇂ 1đಖުౢਬb + +12.4.3 FIFO Ҡቔ + +I2S ၂Ց FIFO Ҡቔđཿೆ/‫؀‬౼ඔऌЇӉ؇ູ 32 ໊bඔऌЇ۬ൔႮ࠷թఖ஥ᇂbႮ๭ 12-1 ॖᆩđր‫ؿ‬ෂඔऌ +‫ࢤބ‬൬֥֞ඔऌđ‫׻‬ေ༵ཿೆ FIFOđಖުᄜ‫؀‬ԛb‫؀‬ཿ FIFO ֥ٚൔႵਆᇕđ၂ᇕ൞൐Ⴈ CPU ᆰࢤࣉྛ‫؀‬ཿđ +ਸ਼၂ᇕ൞൐Ⴈ DMA ॥ᇅఖࣉྛ‫؀‬ཿb + +၂Ϯ౦ঃ༯ I2S_FIFO_CONF_REG ࠷թఖ֥ I2S_RX_FIFO_MOD_FORCE_EN бห‫ބ‬ +I2S_TX_FIFO_MOD_FORCE_EN бหनླေᇂູ 1bI2S_TX_DATA_NUM[5:0] бห‫ ބ‬I2S_RX_DATA_NUM[5:0] +бหႨႿ॥ᇅ FIFO ߏԊ‫ؿ‬ෂඔऌ‫ࢤބ‬൬ඔऌ֥Ӊ؇b႗ࡱሱ‫࡟׮‬Ұ FIFO ߏթ֥ࢤ൬ඔऌӉ؇ RX_LEN ‫ؿބ‬ෂ +ඔऌӉ؇ TX_LENb + +֒ RX_LEN > I2S_RX_DATA_NUM[5:0] ൈđіൕ FIFO ߏթ֥ࢤ൬ඔऌၘࣜղ֞ഡ‫ק‬ᚐᆴđླေࠣൈ౼ሼb֒ +TX_LEN < I2S_TX_DATA_NUM[5:0] ൈđіൕ FIFO ߏթ֥‫ؿ‬ෂඔऌߎໃղ֞ഡ‫ק‬ᚐᆴđॖၛ࠿࿃ཟ FIFO ᇏแԉ +ඔऌb + +12.4.4 ‫ؿ‬ෂඔऌ + +ESP32 I2S ‫ؿ‬ෂඔऌ‫ູٳ‬೘۱ࢨ‫؍‬ğ + + • ֻ၂ࢨ‫؍‬Ֆଽթᇏ‫؀‬ԛඔऌѩཿೆ FIFOĠ + + • ֻ‫ࡼ؍ࢨؽ‬ր‫ؿ‬ෂඔऌՖ FIFO ᇏ‫؀‬ԛĠ + + • ֻ೘ࢨ‫؍‬đᄝ I2S ଆൔ༯đࡼր‫ؿ‬ෂඔऌሇߐູԱྛඔऌੀൻԛĠᄝ LCD ଆൔ༯đࡼր‫ؿ‬ෂඔऌሇߐູ + ໊ॺ‫֥קܥ‬ѩྛඔऌੀൻԛb + +ুᶈྐ༏॓࠯ 285 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + ๭ 12­6. ‫ؿ‬ෂ FIFO ඔऌଆൔ + +Tx FIFO mode0 і 12­2. ࠷թఖ஥ᇂ ૭ඍ +Tx FIFO mode1 16 ໊ච๙֡ඔऌ + I2S_TX_FIFO_MOD[2:0] 32 ໊ච๙֡ඔऌ + 0 32 ໊ֆ๙֡ඔऌ + 2 16 ໊ֆ๙֡ඔऌ + 3 + 1 + +ᄝֻ၂ࢨ‫؍‬đր‫ؿ‬ෂඔऌཿೆ FIFO ֥ଆൔႵਆᇕbTx FIFO mode0 ่ࡱ༯đր‫ؿ‬ෂඔऌ Tx data οൈࡗ༵ުФ +ᆰࢤཿೆ FIFOĠTx FIFO mode1 ่ࡱ༯đր‫ؿ‬ෂඔऌФ‫ٳ‬Ӯۚ 16 бห‫ ֮ބ‬16 бหđᇗྍቆ‫ުކ‬ᄜཿೆ FIFO, +ೂ๭ 12-6 ෮ൕ, ؓႋ࠷թఖೂі 12-2 ෮ൕbDn′ Ⴎ Dn ֥ۚ 16 бห‫ ބ‬16 ۱ 0 ቆӮđDn′′ Ⴎ Dn ֥֮ 16 бห +‫ ބ‬16 ۱ 0 ቆӮđࠧğDn′ = {Dn[31 : 16], 16′h0}đDn′′ = {Dn[15 : 0], 16′h0}b + +ᄝֻ‫؍ࢨؽ‬đ༢๤߶οᅶཌྷܱ࠷թఖ஥ᇂࡼր‫ؿ‬ෂඔऌՖ FIFO ‫؀‬ԛbՖ FIFO ‫؀‬ԛඔऌ֥ଆൔა +I2S_TX_FIFO_MOD[2.0] ‫ ބ‬I2S_TX_CHAN_MOD[2:0] ֥౼ᆴႵܱbI2S_TX_FIFO_MOD[2.0] थ‫ק‬ඔऌ൞ 16 ໊ߎ +൞ 32 ໊ĠI2S_TX_CHAN_MOD[2:0] थ‫ק‬ր‫ؿ‬ෂඔऌ֥۬ൔđೂі 12-3 ෮ൕb + + і 12­3. ‫ؿ‬ෂ๙֡ଆൔ + +I2S_TX_CHAN_MOD[2:0] ૭ඍ +0 චല֡ଆൔ +1 ֆല֡ଆൔ + I2S_TX_MSB_RIGHT=0 ൈđቐല֡‫ބ‬Ⴗല֡ඔऌनູቐല֡ඔऌb +2 I2S_TX_MSB_RIGHT=1 ൈđቐല֡‫ބ‬Ⴗല֡ඔऌनູႷല֡ඔऌb + ֆല֡ଆൔ +3 I2S_TX_MSB_RIGHT=0 ൈđቐല֡‫ބ‬Ⴗല֡ඔऌनູႷല֡ඔऌb + I2S_TX_MSB_RIGHT=1 ൈđቐല֡‫ބ‬Ⴗല֡ඔऌनູቐല֡ඔऌb +4 ֆല֡ଆൔ + I2S_TX_MSB_RIGHT=0 ൈđቐല֡ඔऌູӈඔ REG[31:0]b + I2S_TX_MSB_RIGHT=1 ൈđႷല֡ඔऌູӈඔ REG[31:0]b + ֆല֡ଆൔ + I2S_TX_MSB_RIGHT=0 ൈđႷല֡ඔऌູӈඔ REG[31:0]b + I2S_TX_MSB_RIGHT=1 ൈđቐല֡ඔऌູӈඔ REG[31:0]b + +ఃᇏ REG[31:0] ູ࠷թఖ I2S_CONF_SINGLE_DATA_REG[31:0] ֥ᆴb + +ুᶈྐ༏॓࠯ 286 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + +ֻ೘ࢨ‫؍‬ൻԛႮ I2S ֥ଆൔ‫࠷ބ‬թఖ I2S_SAMPLE_RATE_CONF_REG ֥ I2S_TX_BITS_MOD[5:0] бหथ +‫ק‬b + +12.4.5 ࢤ൬ඔऌ + +ESP32 I2S ࢤ൬ඔऌ္‫ູٳ‬೘۱ࢨ‫؍‬ğ + • ֻ၂ࢨ‫؍‬đᄝ I2S ଆൔ༯đൻೆ֥Աྛбหੀඔऌ߶Фၛല֡උྟሇߐӮॺ؇ູ 64 ໊֥ѩྛඔऌੀĠᄝ + LCD ଆൔ༯đൻೆ໊֥ॺ‫֥קܥ‬ѩྛඔऌੀ߶ФঔᅚӮॺ؇ູ 64 ໊֥ѩྛඔऌੀĠ + • ֻ‫ࡼ؍ࢨؽ‬րࢤ൬֥ඔऌཿೆ FIFOĠ + • ֻ೘ࢨ‫ࡼ؍‬րࢤ൬֥ඔऌՖ FIFO ᇏ‫؀‬ԛđѩཿೆଽթb + +ᄝֻ၂ࢨ‫؍‬đࢤ൬ଆॶο I2SnI_WS_outčࠇ I2SnI_WS_inĎྐ‫׈ݼ‬௜֥֮ۚđࡼࢤ൬֞ඔऌੀঔᅚӮۚ‫׈‬௜ؓ +ႋ 32 ໊‫׈֮ބ‬௜ؓႋ 32 ໊֥ѩྛඔऌੀđ҂ቀ֥Ҁ 0b࠷թఖ I2S_CONF_REG ֥ I2S_RX_MSB_RIGHT бห +ႨႿಒ‫ק‬ঔᅚުඔऌ֥ஆਙٚൔb + + ๭ 12­7. ֻ၂ࢨ‫ࢤ؍‬൬ඔऌ + +২ೂđೂ๭ 12-7 ෮ൕđೂ‫ݔ‬Աྛඔऌॺ؇ູ 16 ໊đ֒ I2S_RX_RIGHT_FIRST = 1 ൈđପહඔऌ Data0 ࡼ߶Ф +‫ש‬ఙđI2S ࡼՖ Data1 ष൓ࢤ൬ඔऌĠՎൈ೏ I2S_RX_MSB_RIGHT = 1đପહֻ၂ࢨ‫؍‬ඔऌູ +{0xF EDC0000, 0x32100000}đ೏ I2S_RX_MSB_RIGHT = 0đପહֻ၂ࢨ‫؍‬ඔऌູ +{0x32100000, 0xF EDC0000}b֒ I2S_RX_RIGHT_FIRST = 0 ൈđI2S ࡼՖ Data0 ष൓ࢤ൬ඔऌĠೂ‫ݔ‬ +I2S_RX_MSB_RIGHT = 1đପહֻ၂ࢨ‫؍‬ඔऌູ {0xF EDC0000, 0x76540000}đೂ‫ ݔ‬I2S_RX_MSB_RIGHT = 0đ +ପહֻ၂ࢨ‫؍‬ඔऌູ {0x76540000, 0xF EDC0000}b + +ᄝֻ‫؍ࢨؽ‬đࡼࢤ൬ଆॶࢤ൬֥֞ඔऌཿೆ FIFObࢤ൬ඔऌཿೆ FIFO ֥ଆൔ‫܋‬Ⴕඹᇕđؓႋ +I2S_RX_FIFO_MOD[2:0] бห౼ᆴđೂі 12-4 ‫ބ‬๭ 12-8 ෮ൕb + + і 12­4. ࢤ൬ඔऌཿೆ FIFO ଆൔ‫ؓބ‬ႋ࠷թఖ஥ᇂ + +I2S_RX_FIFO_MOD[2:0] ඔऌ۬ൔ +0 16 ໊ච๙֡ඔऌ +1 16 ໊ֆ๙֡ඔऌ +2 32 ໊ච๙֡ඔऌ +3 32 ໊ֆ๙֡ඔऌ + +ুᶈྐ༏॓࠯ 287 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + ๭ 12­8. ࢤ൬ඔऌཿೆ FIFO ଆൔ + +ᄝֻ೘ࢨ‫؍‬đCPU ࠇᆀ DMA ߶ࡼඔऌՖ FIFO ᇏ‫؀‬ԛđѩᆰࢤཿ֞ଽ҆թԥ౵თb۲ଆൔؓႋ࠷թఖ஥ᇂ࡮і +12-5b + + і 12­5. 4 ᇕଆൔؓႋ࠷թఖ஥ᇂ + +I2S_RX_MSB_RIGHT I2S_RX_CHAN_MOD mode0 mode1 mode2 mode3 +0 0 - - + 1 ቐല֡ ቐല֡ + ቐല֡ ቐല֡ + +1 + Ⴗല֡ ቐല֡ + Ⴗല֡ ቐല֡ + 2 Ⴗല֡ + Ⴗല֡ + + 3 Ⴗല֡ Ⴗല֡ Ⴗല֡ Ⴗല֡ + 0 + ቐല֡ - + ቐല֡ - + 1 - - + Ⴗല֡ + Ⴗല֡ + + 2 Ⴗല֡ Ⴗല֡ + 3 ቐല֡ + ቐല֡ + + ቐല֡ ቐല֡ + - - + +12.4.6 I2S ᇶࠏ/Ֆࠏଆൔ + +I2S ଆॶॖၛ஥ᇂູᇶࠏࢤ൬/‫ؿ‬ෂࢤ१đᆦӻ϶ච‫۽‬ଆൔ‫ބ‬ಆච‫۽‬ଆൔĠ္ॖၛ஥ᇂູՖࠏࢤ൬/‫ؿ‬ෂࢤ१đ္ +ᆦӻ϶ච‫۽‬ଆൔ‫ބ‬ಆච‫۽‬ଆൔb + +࠷թఖ I2S_CONF_REG ֥ I2S_RX_SLAVE_MOD бห‫ ބ‬I2S_TX_SLAVE_MOD бห‫ٳ‬љႨႿࡼ I2S ஥ᇂູՖࠏ +ࢤ൬‫ބ‬Ֆࠏ‫ؿ‬ෂଆൔb + +࠷թఖ I2S_CONF_REG ᇏ֥ I2S_TX_START ໊ႨႿఓ‫׮‬၂Ց‫ؿ‬ෂҠቔb֒ I2S ູᇶࠏ‫ؿ‬ෂଆൔൈđ೏‫໊ھ‬ᇂ +1đ‫ؿ‬ෂଆॶ߶၂ᆰൻԛൈᇒྐ‫ބݼ‬ቐႷല֡ඔऌbೂ‫ ݔ‬FIFO ࡼ෮Ⴕཿೆ֥ඔऌ‫ؿ‬ෂປиđѩ౏ીႵྍඔऌแ +ೆđପહඔऌཌഈ߶࿖ߌൻԛቋު၂ᆠඔऌb֒‫໊ھ‬Фౢਬൈđᇶࠏ๔ᆸൻԛൈᇒ‫ބ‬ඔऌb֒ I2S Ф஥ᇂູՖ +ࠏ‫ؿ‬ෂൈđ೏‫໊ھ‬Фᇂ 1đ‫ؿ‬ෂଆॶ߶֩րᇶࠏ BCK ൈᇒđটఓ‫ؿ׮‬ෂҠቔb + +࠷թఖ I2S_CONF_REG ᇏ֥ I2S_RX_START ໊ႨႿఓ‫׮‬၂Ցࢤ൬Ҡቔb֒ I2S ູᇶࠏࢤ൬ଆൔൈđ೏‫໊ھ‬ᇂ +1đࢤ൬ଆॶ߶၂ᆰൻԛൈᇒྐ‫ݼ‬đѩؓൻೆඔऌࣉྛҐဢđᆰ֞‫໊ھ‬Фౢਬbೂ‫ ݔ‬I2S ஥ᇂູՖࠏࢤ൬ଆൔ +ൈđ೏‫໊ھ‬Фᇂ 1đࢤ൬ଆॶ߶֩րᇶࠏ BCK ൈᇒđটఓ‫ࢤ׮‬൬Ҡቔb + +ুᶈྐ༏॓࠯ 288 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + +12.4.7 I2S PDM ଆൔ + +ೂ๭ 12-1 ෮ൕđESP32 I2S0 ଽ҆ࠢӮਔ PDM ଆॶđႨႿ PCM щ઒ྐ‫ ބݼ‬PDM щ઒ྐ‫ݼ‬ᆭࡗཌྷ޺ሇ +ߐb +PDM ଆॶൻԛൈᇒྐ‫ݼ‬႘ഝ֞ I2S0*_WS_out ྐ‫ݼ‬đః஥ᇂٚൔ‫ ބ‬I2S ଆൔ༯֥ BCK ཌྷ๝đऎุ౨ҕॉᅣࢫ +12.3bI2S PDM ࢤ൬‫ؿބ‬ෂ֥ PCM ྐ‫ݼ‬ඔऌ໊ॺनູ 16 ໊b + + ๭ 12­9. PDM ‫ؿ‬ෂଆॶ + +PDM ‫ؿ‬ෂଆॶႨႿࡼ PCM ྐ‫ݼ‬ሇߐູ PDM ྐ‫ݼ‬đೂ๭ 12-9 ෮ൕbHPF ູۚ๙ੲѯఖđLPF ູ֮๙ੲѯఖb +PCM ྐ‫ݖࣜݼ‬ഈҐဢ‫ބ‬ੲѯđቋᇔൻԛ PDM ྐ‫ݼ‬b࠷թఖ I2S_PDM_CONF_REG ֥ +I2S_TX_PDM_HP_BYPASS ྐ‫ݼ‬ႨႿ࿊ᄴ PCM ྐ‫ݼ‬൞‫ ݖࣜڎ‬HPF ଆॶbFilter group0 ଆॶऎႵഈҐဢ‫ିۿ‬b +ࡌഡ PDM ྐ‫֥ݼ‬௔ੱູ fpdm, PCM ྐ‫֥ݼ‬௔ੱູ fpcm, ପહ fpdm ა fpcm ᆭࡗ֥ܱ༢ູğ + + I2S_T X_P DM _F P + fpdm = 64×fpcm× I2S_T X_P DM _F S + +ఃᇏ 64 ູభ૫ਆՑ‫ݖ‬Ґဢੱ֥Ӱࠒb + +ೂі 12-6 ෮ൕđ҂๝ PCM ྐ‫֥ݼ‬௔ੱ༯đॖၛ๙‫ݖ‬஥ᇂ࠷թఖ I2S_PDM_FREQ_CONF_REG ֥ +I2S_TX_PDM_FP бห‫ ބ‬I2S_TX_PDM_FS бหđ֤֞ൻԛ௔ੱनູ 48×128 KHz ֥ PDM ྐ‫ݼ‬b + + і 12­6. ‫ݖ‬Ґဢੱ஥ᇂ + +fpcm (KHz) I2S_TX_PDM_FP I2S_TX_PDM_FS fpdm (KHz) +48 960 480 48×128 +44.1 960 441 +32 960 320 +24 960 240 +16 960 160 +8 960 80 + +࠷թఖ I2S_PDM_CONF_REG ֥ I2S_TX_PDM_SINC_OSR2 бหіൕ Filter group0 ଆॶ֥‫ݖ‬Ґဢੱb + I2S_T X_P DM _F P + + I2S_T X_P DM _SIN C_OSR2 = I2S_T X_P DM _F S + +֒൐Ⴈ PDM ‫ؿ‬ෂଆॶൈđླေࡼ࠷թఖ I2S_PDM_CONF_REG ֥ I2S_TX_PDM_EN бหა +I2S_PCM2PDM_CONV_EN бหಆ҆ᇂ 1đೂ๭ 12-10 ෮ൕb࠷թఖ I2S_PDM_CONF_REG ֥ +I2S_TX_PDM_SIGMADELTA_IN_SHIFT бหaI2S_TX_PDM_SINC_IN_SHIFT бหaI2S_TX_PDM_LP_IN_SHIFT +бห‫ ބ‬I2S_TX_PDM_HP_IN_SHIFT бหႨႿ‫ט‬ᆜ۲۱ੲѯଆॶ֥ൻೆྐ‫֥ݼ‬նཬb + +ুᶈྐ༏॓࠯ 289 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + ๭ 12­10. PDM ‫ؿ‬ෂྐ‫ݼ‬ + +֒൐Ⴈ PDM ࢤ൬ଆॶൈđླေࡼ࠷թఖ I2S_PDM_CONF_REG ֥ I2S_RX_PDM_EN бหა +I2S_PDM2PCM_CONV_EN бหಆ҆ᇂູ 1đೂ๭ 12-11 ෮ൕbPDM ࢤ൬ଆॶࢲ‫ࢤࡼܒ‬൬֥֞ PDM ྐ‫ݼ‬ሇߐ +ູ 16 бห֥ PCM ྐ‫ݼ‬b๭ 12-12 ᇏ Filter group1 ႨႿؓ PDM ྐ‫ྛࣉݼ‬༯Ґဢđ࠷թఖ +I2S_PDM_CONF_REG ֥ I2S_RX_PDM_SINC_DSR_16_EN ႨႿ‫ט‬ᆜ༯ҐဢੱbPDM ࢤ൬ଆॶ֥ൻೆ PDM ྐ +‫ݼ‬௔ੱླေູ PCM ྐ‫ ݼ‬128 ࠇ 64 Пb + + ๭ 12­11. PDM ࢤ൬ྐ‫ݼ‬ + + ๭ 12­12. PDM ࢤ൬ଆॶ + +༯і 12-7 ۳ԛ҂๝ PDM ྐ‫֥ݼ‬௔ੱ༯đPDM ྐ‫ݼ‬ሇ PCM ྐ‫ ֥ݼ‬I2S_RX_PDM_SINC_DSR_16_EN бห஥ +ᇂb + + і 12­7. ༯Ґဢ஥ᇂ + +PDM freq (KHz) I2S_RX_PDM_SINC_DSR_16_EN PCM freq (KHz) +fpcm×128 1 fpcm +fpcm×64 0 + +12.5 Camera­LCD ॥ᇅఖ + +ESP32 I2S ֥ LCD ଆൔ‫ູٳ‬ğ + • LCD ᇶࠏ‫ؿ‬ෂଆൔ + • Camera Ֆࠏࢤ൬ଆൔ + • ADC/DAC ଆൔ + +LCD ଆൔ֥ൈᇒ஥ᇂა I2S ଆൔ֥ൈᇒ஥ᇂ၂ᇁbLCD ଆൔ༯đWS ௔ੱູ fBCK ֥၂϶b + +ুᶈྐ༏॓࠯ 290 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + +ADC/DAC ଆൔ༯đေ൐Ⴈ PLL_D2_CLK ቔູൈᇒჷb + +12.5.1 LCD ᇶࠏ‫ؿ‬ෂଆൔ + +ೂ๭ 12-13 ෮ൕđᄝ LCD ᇶࠏ‫ؿ‬ෂଆൔ༯đLCD ֥ WR ྐ‫ ࢤݼ‬I2S ଆॶ֥ WS ྐ‫ݼ‬đඔऌྐ‫ݼ‬ཌॺ؇ູ 24 б +หb + + ๭ 12­13. LCD ᇶࠏ‫ؿ‬ෂଆൔ + +൮༵ࡼ࠷թఖ I2S_CONF2_REG ֥ I2S_LCD_EN бหᇂູ 1đѩ౏ࡼ࠷թఖ I2S_CONF_REG ֥ +I2S_TX_SLAVE_MOD бหᇂ 0đ൐֤ I2S ଆॶ‫۽‬ቔᄝ LCD ᇶࠏ‫ؿ‬ෂଆൔb๝ൈđ۴ऌླေ஥ᇂ࠷թఖ +I2S_CONF_CHAN_REG ֥ I2S_TX_CHAN_MOD[2:0] бห‫࠷ބ‬թఖ I2S_FIFO_CONF_REG ֥ +I2S_TX_FIFO_MOD[2:0] бหđၛ൐Ⴈᆞಒ֥ଆൔ‫ؿ‬ෂඔऌbWS ྐ‫ ݖࣜݼ‬GPIO ࢌߐइᆔൻԛൈླေّཌྷbབྷ +౦౨ҕॉᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔbᄝ LCD ଆൔᇶࠏ‫ؿ‬ෂଆൔ༯đߎླေ๙‫ݖ‬஥ᇂ࠷թఖ +I2S_CONF2_REG ֥ I2S_LCD_TX_SDX2_EN бห‫ ބ‬I2S_LCD_TX_WRX2_EN бหđ൐֤‫ؿ‬ෂඔऌ‫ ބ‬WR ྐ‫ݼ‬ +‫۽‬ቔᄝླေ֥ଆൔ༯b +ೂ๭ 12-14 ‫ބ‬๭ 12-15 ෮ൕđඔऌᆠ۬ൔ 1 ༯đླေࡼ I2S_LCD_TX_WRX2_EN бหᇂ 1đ +I2S_LCD_TX_SDX2_EN бหᇂ 0 bඔऌᆠ۬ൔ 2 ༯đླေࡼ I2S_LCD_TX_SDX2_EN бห‫ބ‬ +I2S_LCD_TX_WRX2_EN бห‫׻‬ᇂ 1b + + ๭ 12­14. LCD ᇶࠏ‫ؿ‬ෂඔऌᆠ۬ൔ 1 + + ๭ 12­15. LCD ᇶࠏ‫ؿ‬ෂඔऌᆠ۬ൔ 2 + +12.5.2 Camera Ֆࠏࢤ൬ଆൔ + +ESP32 I2S ॖၛ஥ᇂӮ Camera ՖࠏଆൔđၛՎൌགྷაຓ҆ camera ଆॶ֥ۚ෎ඔऌԮൻbᄝՎଆൔ༯đI2S ଆ +ॶູՖࠏࢤ൬ଆൔđԢਔ 16 ਫ਼ඔऌྐ‫ݼ‬ሹཌ I2SnI_Data_in ຓđߎႵ I2Sn_H_SYNCaI2Sn_V_SYNC ‫ބ‬ +I2Sn_H_ENABLE ྐ‫ݼ‬b + +Camera ֥ PCLK ࢤ I2S ଆॶ֥ I2SnI_WS_in ྐ‫ݼ‬đೂ๭ 12-16 ෮ൕb + +ুᶈྐ༏॓࠯ 291 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + ๭ 12­16. Camera Ֆࠏࢤ൬ଆൔ + +֒ I2S ູ Camera Ֆࠏࢤ൬ଆൔൈđѩ౏֒ I2Sn_H_SYNCaI2S_V_SYNC ‫ ބ‬I2S_H_REF नູۚ‫׈‬௜ൈđಪູ +ᇶࠏष൓Ԯൻඔऌđࠧğ + + transmission_start = (I2Sn_H_SY N C == 1)&&(I2Sn_V _SY N C == 1)&&(I2Sn_H_EN ABLE == 1) + +ࠧᄝԮൻඔऌ‫ݖ‬ӱᇏđᆃ೘۱ྐ‫ླݼ‬ေЌӻۚ‫׈‬௜b২ೂଖॻ camerađI2Sn_V_SYNC ྐ‫ݼ‬ᄝԮൻඔऌ‫ݖ‬ӱᇏ +ູ֮‫׈‬௜đପહᄝൻೆ I2S ଆॶൈ I2Sn_V_SYNC ླေ౼ّbESP32 ᆦӻྐ‫ ݖࣜݼ‬GPIO ࢌߐइᆔൈ౼ّbབྷ +౦౨ҕॉᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔb + +ູਔ൐ I2S ‫۽‬ቔᄝ Camera ଆൔđ࠷թఖ I2S_CONF2_REG ֥ I2S_LCD_EN бห‫ ބ‬I2S_CAMERA_EN бหླေ +ᇂູ 1đѩ౏ࡼ࠷թఖ I2S_CONF_REG ֥ I2S_RX_SLAVE_MOD бหᇂ 1đI2S_RX_MSB_RIGHT бห‫ބ‬ +I2S_RX_RIGHT_FIRST бหनഡᇂູ 0đ൐֤ I2S ଆॶ‫۽‬ቔᄝ LCD Ֆࠏࢤ൬ଆൔb๝ൈđླေࡼ࠷թఖ +I2S_CONF_CHAN_REG ֥ I2S_RX_CHAN_MOD[2:0] бห‫࠷ބ‬թఖ I2S_FIFO_CONF_REG ֥ +I2S_RX_FIFO_MOD[2:0] бหन஥ᇂӮ 1đၛ൐Ⴈᆞಒ֥ଆൔࢤ൬ඔऌb + +12.5.3 ADC/DAC ଆൔ + +LCD ଆൔ൐֤ோഈ ADC ଆॶࢤ൬֥֞ඔऌॖၛ൐Ⴈ I2S0 ଆॶϬ֞ଽ҆թԥ౵đ္ॖၛ൐Ⴈ I2S0 ଆॶࡼଽ҆ +թԥ౵֥ඔऌϬ֞ோഈ DAC ଆॶb֒ I2S0 ଆॶ৵ࢤோഈ ADC ൈđླေࡼ I2S0 ଆॶ஥ᇂູᇶࠏࢤ൬ଆൔb๭ +12-17 ູ I2S0 ଆॶა ADC ॥ᇅఖᆭࡗ֥ྐ‫ݼ‬৵ࢤb + + ๭ 12­17. I2S ֥ ADC ࢤ१ + +൮༵ࡼ࠷թఖ I2S_CONF2_REG ֥ I2S_LCD_EN бหᇂູ 1đѩ౏ࡼ࠷թఖ I2S_CONF_REG ֥ +I2S_RX_SLAVE_MOD бหᇂ 0đ൐֤ I2S0 ଆॶ‫۽‬ቔᄝ LCD ᇶࠏࢤ൬ଆൔđ஥ᇂ I2S0 ଆॶൈᇒđ൐֤ I2S0 ֥ +WS ྐ‫ݼ‬ൻԛ‫ކ‬ൡ֥௔ੱbಖުࡼ APB_CTRL_APB_SARADC_CTRL_REG ࠷թఖ֥ +APB_CTRL_SARADC_DATA_TO_I2S бหᇂ 1 bᄝ஥ᇂ‫ ݺ‬SARADC ཌྷܱ࠷թఖުఓ‫ ׮‬I2S ࢤ൬ඔऌbབྷ౦౨ +ҕॉᅣࢫோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘b + +ুᶈྐ༏॓࠯ 292 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + ๭ 12­18. I2S ֥ DAC ࢤ१ + + ๭ 12­19. I2S DAC ࢤ१ඔऌൻೆ + +֒ I2S0 ଆॶࢤோଽ DAC ൈđླေࡼ I2S0 ଆॶ஥ᇂӮᇶࠏ‫ؿ‬ෂଆൔb๭ 12-18 ູ I2S0 ଆॶა DAC ॥ᇅఖᆭ +ࡗ֥ྐ‫ݼ‬৵ࢤbDAC ॥ᇅଆॶၛ I2S_CLK ູൈᇒđՎൈ I2S_CLK ቋູۚ APB_CLK/2bೂ๭ 12-19 ෮ൕđ֒ඔ +ऌሹཌཟ DAC ॥ᇅଆॶൻೆඔऌൈđDAC ॥ᇅఖ߶ࡼႷല֡ඔऌൻೆ DAC1 ଆॶđࡼቐല֡ඔऌൻೆ DAC2 +ଆॶb൐Ⴈ I2S DMA ଆॶൈđླေࡼր‫ؿ‬ෂ֥ 8 ໊ඔऌቐ၍ 8 ໊แೆ DMA ֥චሳࢫো྘ buffer ᇏb + +൐Ⴈ I2S0 ֥ DAC ଆൔൈđ൮༵ࡼ࠷թఖ I2S_CONF2_REG ֥ I2S_LCD_EN бหᇂູ 1đ‫ٳ‬љࡼ +I2S_RX_SHORT_SYNCaI2S_TX_SHORT_SYNCaI2S_CONF_REGaI2S_RX_MSB_SHIFT ‫ބ‬ +I2S_TX_MSB_SHIFT ౢਬđѩ౏ࡼ࠷թఖ +I2S_CONF_REG ֥ I2S_TX_SLAVE_MOD бหᇂ 0đ൐֤ I2S0 ଆॶ‫۽‬ቔᄝ LCD ᇶࠏ‫ؿ‬ෂଆൔbοᅶԮൻ 16 ໊ +ඔऌ֥ѓሙđ࿊ᄴ‫ކ‬ൡ֥‫ؿ‬ෂଆൔb஥ᇂ I2S0 ଆॶൈᇒđ൐֤ I2S ֥ I2S_CLK ‫ ބ‬WS ൻԛ‫ކ‬ൡ֥௔ੱbᄝ஥ +ᇂ‫ ݺ‬DAC ཌྷܱ࠷թఖުđఓ‫ ׮‬I2S0 ‫ؿ‬ෂඔऌb + +12.6 I2S ᇏ؎ + +12.6.1 FIFO ᇏ؎ + + • I2S_TX_HUNG_INT: ֒‫ؿ‬ෂඔऌӑൈࠧԨ‫ؿ‬Վᇏ؎b + + • I2S_RX_HUNG_INT: ֒ࢤ൬ඔऌӑൈࠧԨ‫ؿ‬Վᇏ؎b + + • I2S_TX_REMPTY_INT: ֒‫ؿ‬ෂ FIFO ູॢൈࠧԨ‫ؿ‬Վᇏ؎b + + • I2S_TX_WFULL_INT: ֒‫ؿ‬ෂ FIFO ડൈࠧԨ‫ؿ‬Վᇏ؎b + + • I2S_RX_REMPTY_INT: ֒ࢤ൬ FIFO ູॢൈࠧԨ‫ؿ‬Վᇏ؎b + + • I2S_RX_WFULL_INT: ֒ࢤ൬ FIFO ડൈࠧԨ‫ؿ‬Վᇏ؎b + + • I2S_TX_PUT_DATA_INT: ֒‫ؿ‬ෂ FIFO ࡼေॢൈࠧԨ‫ؿ‬Վᇏ؎b + +ুᶈྐ༏॓࠯ 293 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + • I2S_RX_TAKE_DATA_INT: ֒ࢤ൬ FIFO ࡼေડൈࠧԨ‫ؿ‬Վᇏ؎b + +12.6.2 DMA ᇏ؎ + + • I2S_OUT_TOTAL_EOF_INT: ֒෮Ⴕ‫ؿ‬ෂ৽і൐ႨປиൈࠧԨ‫ؿ‬Վᇏ؎b + • I2S_IN_DSCR_EMPTY_INT: ໭Ⴕིࢤ൬৽іॖႨൈࠧԨ‫ؿ‬Վᇏ؎b + • I2S_OUT_DSCR_ERR_INT: ֒მ֞໭ིࢤ൬৽і૭ඍ‫ژ‬ൈࠧԨ‫ؿ‬Վᇏ؎b + • I2S_IN_DSCR_ERR_INT: ֒მ֞໭ི‫ؿ‬ෂ৽і૭ඍ‫ژ‬ൈࠧԨ‫ؿ‬Վᇏ؎b + • I2S_OUT_EOF_INT: ֒ࢤ൬৽іປӮ‫ؿ‬ෂ၂۱ඔऌЇൈࠧԨ‫ؿ‬Վᇏ؎b + • I2S_OUT_DONE_INT: ֒෮Ⴕ‫ؿ‬ෂߏթඔऌФ‫؀‬౼ປиުࠧԨ‫ؿ‬Վᇏ؎b + • I2S_IN_SUC_EOF_INT: ֒෮Ⴕඔऌࢤ൬ປиൈࠧԨ‫ؿ‬Վᇏ؎b + • I2S_IN_DONE_INT: ֒భ‫ؿ‬ෂ৽і૭ඍ‫ژ‬Фԩ৘ൈࠧԨ‫ؿ‬Վᇏ؎b + +12.7 ࠷թఖਙі ૭ඍ I2S0 I2S1 ٠໙ + + ଀ӫ ཿೆ I²S ‫ؿ‬ෂ FIFO ֥ඔऌ 0x3FF4F000 0x3FF6D000 ᆺཿ + I²S FIFO ࠷թఖ թԥ I²S ࢤ൬ FIFO ֥ඔऌ 0x3FF4F004 0x3FF6D004 ᆺ‫؀‬ + I2S_FIFO_WR_REG + I2S_FIFO_RD_REG ஥ᇂაष൓/๔ᆸ໊ 0x3FF4F008 0x3FF6D008 ‫؀‬/ཿ + ஥ᇂ࠷թఖ PCM ஥ᇂ࠷թఖ 0x3FF4F0A0 0x3FF6D0A0 ‫؀‬/ཿ + I2S_CONF_REG ADC/LCD/Camera ஥ᇂ࠷թ + I2S_CONF1_REG ఖ 0x3FF4F0A8 0x3FF6D0A8 ‫؀‬/ཿ + ྐ‫ݼ‬࿼Ӿ‫ބ‬ൈ྽ҕඔ + I2S_CONF2_REG FIFO ஥ᇂ 0x3FF4F01C 0x3FF6D01C ‫؀‬/ཿ + ࣡෿๙֡ൻԛᆴ 0x3FF4F020 0x3FF6D020 ‫؀‬/ཿ + I2S_TIMING_REG ๙֡஥ᇂ 0x3FF4F028 0x3FF6D028 ‫؀‬/ཿ + I2S_FIFO_CONF_REG ӑൈ࡟ҩ஥ᇂ 0x3FF4F02C 0x3FF6D02C ‫؀‬/ཿ + I2S_CONF_SINGLE_DATA_REG Bitclock ஥ᇂ 0x3FF4F074 0x3FF6D074 ‫؀‬/ཿ + I2S_CONF_CHAN_REG Ґဢੱ஥ᇂ 0x3FF4F0AC 0x3FF6D0AC ‫؀‬/ཿ + I2S_LC_HUNG_CONF_REG Power-down ࠷թఖ 0x3FF4F0B0 0x3FF6D0B0 ‫؀‬/ཿ + I2S_CLKM_CONF_REG I²S ሑ෿ 0x3FF4F0A4 0x3FF6D0A4 ‫؀‬/ཿ + I2S_SAMPLE_RATE_CONF_REG 0x3FF4F0BC 0x3FF6D0BC ᆺ‫؀‬ + I2S_PD_CONF_REG + I2S_STATE_REG DMA ஥ᇂ࠷թఖ 0x3FF4F060 0x3FF6D060 ‫؀‬/ཿ + ᇏ؎࠷թఖ ࢤ൬ඔऌ࠹ඔఖ 0x3FF4F024 0x3FF6D024 ‫؀‬/ཿ + DMA ࠷թఖ DMA ‫ؿ‬ෂ৽і஥ᇂ‫ֹބ‬ᆶ 0x3FF4F030 0x3FF6D030 ‫؀‬/ཿ + I2S_LC_CONF_REG DMA ࢤ൬৽і஥ᇂ‫ֹބ‬ᆶ 0x3FF4F034 0x3FF6D034 ‫؀‬/ཿ + I2S_RXEOF_NUM_REG ളӮ EOF ֥‫ؿ‬ෂ৽і૭ඍ‫ژ‬ + I2S_OUT_LINK_REG ֹᆶ 0x3FF4F038 0x3FF6D038 ᆺ‫؀‬ + I2S_IN_LINK_REG ളӮ EOF ֥ࢤ൬৽і૭ඍ‫ژ‬ + ֹᆶ 0x3FF4F03C 0x3FF6D03C ᆺ‫؀‬ + I2S_OUT_EOF_DES_ADDR_REG + + I2S_IN_EOF_DES_ADDR_REG + +ুᶈྐ༏॓࠯ 294 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + +I2S_OUT_EOF_BFR_DES_ADDR_REG ളӮ EOF ֥ࢤ൬ߏթֹᆶ 0x3FF4F040 0x3FF6D040 ᆺ‫؀‬ +I2S_INLINK_DSCR_REG ֒భࢤ൬৽і૭ඍ‫ֹ֥ژ‬ᆶ 0x3FF4F048 0x3FF6D048 ᆺ‫؀‬ + ༯၂۱ࢤ൬৽і૭ඍ‫ֹ֥ژ‬ 0x3FF4F04C 0x3FF6D04C ᆺ‫؀‬ +I2S_INLINK_DSCR_BF0_REG ᆶ + ༯၂۱ࢤ൬৽іඔऌ buffer 0x3FF4F050 0x3FF6D050 ᆺ‫؀‬ +I2S_INLINK_DSCR_BF1_REG ֹ֥ᆶ 0x3FF4F054 0x3FF6D054 ᆺ‫؀‬ + ֒భ‫ؿ‬ෂ৽і૭ඍ‫ֹ֥ژ‬ᆶ 0x3FF4F058 0x3FF6D058 ᆺ‫؀‬ +I2S_OUTLINK_DSCR_REG ༯၂۱‫ؿ‬ෂ৽і૭ඍ‫ֹ֥ژ‬ + ᆶ 0x3FF4F05C 0x3FF6D05C ᆺ‫؀‬ +I2S_OUTLINK_DSCR_BF0_REG ༯၂۱‫ؿ‬ෂ৽іඔऌ buffer 0x3FF4F06C 0x3FF6D06C ᆺ‫؀‬ + ֹ֥ᆶ 0x3FF4F070 0x3FF6D070 ᆺ‫؀‬ +I2S_OUTLINK_DSCR_BF1_REG DMA ࢤ൬ሑ෿ + DMA ‫ؿ‬ෂሑ෿ 0x3FF4F0B4 0x3FF6D0B4 ‫؀‬/ཿ +I2S_LC_STATE0_REG 0x3FF4F0B8 0x3FF6D0B8 ‫؀‬/ཿ +I2S_LC_STATE1_REG PDM ஥ᇂ 0x3FF4F00C 0x3FF6D00C ᆺ‫؀‬ +ઝԊૡ؇ (DE) ‫ט‬ᇅ࠷թఖ PDM ௔ੱ 0x3FF4F010 0x3FF6D010 ᆺ‫؀‬ +I2S_PDM_CONF_REG ჰ൓ᇏ؎ሑ෿ 0x3FF4F014 0x3FF6D014 ‫؀‬/ཿ +I2S_PDM_FREQ_CONF_REG ௠зᇏ؎ሑ෿ 0x3FF4F018 0x3FF6D018 ᆺཿ +I2S_INT_RAW_REG ᇏ؎൐ି໊ +I2S_INT_ST_REG ᇏ؎ౢԢ໊ +I2S_INT_ENA_REG +I2S_INT_CLR_REG + +ুᶈྐ༏॓࠯ 295 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + +12.8 ࠷թఖ + +Чཬࢫও‫ݼ‬ᇏֹ֥ᆶनູཌྷؓႿ I2S ࠎֹᆶֹ֥ᆶொ၍ਈčཌྷֹؓᆶĎđऎุࠎֹᆶ࡮ᅣࢫ 1 ༢๤‫ބ‬թԥఖ ᇏ +֥і 1-6 ຓഡֹᆶ႘ഝb࠷թఖधֹؓᆶ࡮ᅣࢫ 12.7 ࠷թఖਙіb + + Register 12.1. I2S_FIFO_WR_REG (0x0000) + + R_REG + I2S_FIFO_W + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 + +I2S_FIFO_WR_REG ཿೆ I2S ‫ؿ‬ෂ FIFO ֥ඔऌbčᆺཿĎ + + Register 12.2. I2S_FIFO_RD_REG (0x0004) + + I2S_FIFO_RD_REG + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 + +I2S_FIFO_RD_REG թԥ I2S ࢤ൬ FIFO ֥ඔऌbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 296 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.3. I2S_CONF_REG (0x0008) + + (reserved) I2S_SII2GS__LROIX2O_SPM_BTSIAX2B_CS_MK_RRSIGIBX2H_S_MRT_TIOGIX2NH_SOMT_ROIX2N_SOS_HTIXO2_SRS_THR_IOXS2_RSYMN_TT_SCIXS2B_YS_MN_SRSCHIBX2IF_S_TRS_ITHGIXI2HF_STRT__IRGFIX2IHR_STSS__TLTFAIXI2RV_SSSE_T_LRMAIX2VO_SESD__TTMAIX2OR_SSTD_TRAIX2R_STF_ITFIXO2_S_FR_IFREOIXS2__SERRT_EETXSS_EERTTESET + +31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_SIG_LOOPBACK ᇂ 1 ൈđ‫ؿ‬ෂଆॶ‫ࢤބ‬൬ଆॶ‫܋‬ཚ WS ‫ ބ‬BCK ྐ‫ݼ‬bč‫؀‬/ཿĎ + I2S_RX_MSB_RIGHT Վ໊ᇂ 1 ൈđࡼࢤ൬֥֞Ⴗല֡ඔऌ٢ᄝ FIFO ֥ቋۚႵ໊ིbč‫؀‬/ཿĎ + I2S_TX_MSB_RIGHT Վ໊ᇂ 1 ൈđࡼေ‫ؿ‬ෂ֥Ⴗല֡ඔऌ٢ᄝ FIFO ֥ቋۚႵ໊ིbč‫؀‬/ཿĎ + I2S_RX_MONO ᇂ໊൐ି PCM ѓሙଆൔ༯ࢤ൬ଆॶ֥ֆല֡ଆൔbč‫؀‬/ཿĎ + I2S_TX_MONO ᇂ໊൐ି PCM ѓሙଆൔ༯‫ؿ‬ෂଆॶ֥ֆല֡ଆൔbč‫؀‬/ཿĎ + I2S_RX_SHORT_SYNC ᇂ໊൐ି PCM ѓሙଆൔ༯֥ࢤ൬ఖbč‫؀‬/ཿĎ + I2S_TX_SHORT_SYNC ᇂ໊൐ି PCM ѓሙଆൔ༯֥‫ؿ‬ෂఖbč‫؀‬/ཿĎ + I2S_RX_MSB_SHIFT ᇂ໊൐ି Philips ѓሙଆൔ༯֥ࢤ൬ఖbč‫؀‬/ཿĎ + I2S_TX_MSB_SHIFT ᇂ໊൐ି Philips ѓሙଆൔ༯֥‫ؿ‬ෂఖbč‫؀‬/ཿĎ + I2S_RX_RIGHT_FIRST ࡼՎ໊ᇂ 1đ༵ࢤ൬Ⴗല֡ඔऌbč‫؀‬/ཿĎ + I2S_TX_RIGHT_FIRST ࡼՎ໊ᇂ 1đ༵‫ؿ‬ෂႷല֡ඔऌbč‫؀‬/ཿĎ + I2S_RX_SLAVE_MOD ࡼՎ໊ᇂ 1đ൐ିՖࠏࢤ൬ଆൔbč‫؀‬/ཿĎ + I2S_TX_SLAVE_MOD ࡼՎ໊ᇂ 1đ൐ିՖࠏ‫ؿ‬ෂଆൔbč‫؀‬/ཿĎ + I2S_RX_START ᇂ໊ष൓ࢤ൬ඔऌbč‫؀‬/ཿĎ + I2S_TX_START ᇂ໊ष൓‫ؿ‬ෂඔऌbč‫؀‬/ཿĎ + I2S_RX_FIFO_RESET ᇂ໊ᇗᇂࢤ൬ FIFObč‫؀‬/ཿĎ + I2S_TX_FIFO_RESET ᇂ໊ᇗᇂ‫ؿ‬ෂ FIFObč‫؀‬/ཿĎ + I2S_RX_RESET ᇂ໊ᇗᇂࢤ൬ఖbč‫؀‬/ཿĎ + I2S_TX_RESET ᇂ໊ᇗᇂ‫ؿ‬ෂఖbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 297 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.4. I2S_INT_RAW_REG (0x000c) + + (reserved) I2S_OIU2ST__ITNIO2_STDA_SOLCI_U2RESTO___EFIDNM_IS2_IPNSCDT_TRSYO__CI_RU2ERIANSRT_W_T_REOE__R(ROUrIRNeAFTs_TW__eI_NIDrNRvITO2TeA_Sd_NWR_R)EAIAN_IW2WI_NSST_U_INCRI2__ASDEW_OOTFNIX2_E_SIHN__IUTRN_INXT2R__GSAHR__WTAUINIXWN2T_SG_R_R_ETIANMIX2W_TPSW_T_RRYFAIU_X2WI_SLNRL_T_ER_IIMXNR2_SATPW__WTTRYFIXA2U__ISWLNP_LTUR__TIXNR__ATDT_WAARTKAAEW__IDNATT_AR_AINWT_RAW + +31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_OUT_TOTAL_EOF_INT_RAW I2S_OUT_TOTAL_EOF_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_IN_DSCR_EMPTY_INT_RAW I2S_IN_DSCR_EMPTY_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_OUT_DSCR_ERR_INT_RAW I2S_OUT_DSCR_ERR_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_IN_DSCR_ERR_INT_RAW I2S_IN_DSCR_ERR_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_OUT_EOF_INT_RAW I2S_OUT_EOF_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_OUT_DONE_INT_RAW I2S_OUT_DONE_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_IN_SUC_EOF_INT_RAW I2S_IN_SUC_EOF_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_IN_DONE_INT_RAW I2S_IN_DONE_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_TX_HUNG_INT_RAW I2S_TX_HUNG_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_RX_HUNG_INT_RAW I2S_RX_HUNG_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_TX_REMPTY_INT_RAW I2S_TX_REMPTY_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_TX_WFULL_INT_RAW I2S_TX_WFULL_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_RX_REMPTY_INT_RAW I2S_RX_REMPTY_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_RX_WFULL_INT_RAW I2S_RX_WFULL_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_TX_PUT_DATA_INT_RAW I2S_TX_PUT_DATA_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_RX_TAKE_DATA_INT_RAW TI2S_RX_TAKE_DATA_INT ֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 298 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.5. I2S_INT_ST_REG (0x0010) + + (reserved) I2S_OIU2ST__ITNIO2_STDA_SOLCI_U2RESTO___EFIDNM_IS2_IPNSCDT_TRSYO__CI_SU2ERITNSRT__T_REOE__R(SOUrIRNeTFTs_T__eI_NIDrNSvITO2TeT_Sd_NS_S)ETITN_I2I_NSST_U_TCSIX2_T_SED_OOTFIXN2__SEIHN__UTIRN_INX2TS_GS_TH_S_TUITNIXN2T_SG_R_S_ETITNMIX2_TPSW_T_SRYFTIU_X2I_SLNRL_T_ER_IIMXNS2_STTPW__TTSYFIXT2U__ISLNP_LTUR__TIXNS__TTDT_AASTKTAE__IDNATT_AS_TINT_ST + +31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_OUT_TOTAL_EOF_INT_ST I2S_OUT_TOTAL_EOF_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_IN_DSCR_EMPTY_INT_ST I2S_IN_DSCR_EMPTY_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_OUT_DSCR_ERR_INT_ST I2S_OUT_DSCR_ERR_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_IN_DSCR_ERR_INT_ST I2S_IN_DSCR_ERR_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_OUT_EOF_INT_ST I2S_OUT_EOF_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_OUT_DONE_INT_ST I2S_OUT_DONE_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_IN_SUC_EOF_INT_ST I2S_IN_SUC_EOF_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_IN_DONE_INT_ST I2S_IN_DONE_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_TX_HUNG_INT_ST I2S_TX_HUNG_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_RX_HUNG_INT_ST I2S_RX_HUNG_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_TX_REMPTY_INT_ST I2S_TX_REMPTY_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_TX_WFULL_INT_ST I2S_TX_WFULL_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_RX_REMPTY_INT_ST I2S_RX_REMPTY_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_RX_WFULL_INT_ST I2S_RX_WFULL_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_TX_PUT_DATA_INT_ST I2S_TX_PUT_DATA_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + I2S_RX_TAKE_DATA_INT_ST I2S_RX_TAKE_DATA_INT ֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 299 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.6. I2S_INT_ENA_REG (0x0014) + + (reserved) I2S_OIU2ST__ITNIO2_STDA_SOLCI_U2RESTO___EFIDNM_IS2_IPNSCDT_TRSYO__CI_EU2ERINNSRT_A_T_REOE__R(EOUrIRNeNFTs_TA__eI_NIDrNEvITO2TeN_Sd_NAE_E)ENINN_IA2AI_NSST_U_INCEI2_N_SDEA_OOTFNIX2_E_SIHN__IUTRN_INXT2E__GSNHE__ANTUINIXAN2T_SG_R_E_ETINNMIX2A_TPSW_T_ERYFNIU_X2AI_SLNRL_T_ER_IIMXNE2_SNTPW__ATTEYFIXN2U__ISALNP_LTUR__TIXNE__NTDT_AAAETKNAEA__IDNATT_AE_NINAT_ENA + +31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_OUT_TOTAL_EOF_INT_ENA I2S_OUT_TOTAL_EOF_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_IN_DSCR_EMPTY_INT_ENA I2S_IN_DSCR_EMPTY_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_OUT_DSCR_ERR_INT_ENA I2S_OUT_DSCR_ERR_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_IN_DSCR_ERR_INT_ENA I2S_IN_DSCR_ERR_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_OUT_EOF_INT_ENA I2S_OUT_EOF_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_OUT_DONE_INT_ENA I2S_OUT_DONE_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_IN_SUC_EOF_INT_ENA I2S_IN_SUC_EOF_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_IN_DONE_INT_ENA I2S_IN_DONE_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_TX_HUNG_INT_ENA I2S_TX_HUNG_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_RX_HUNG_INT_ENA I2S_RX_HUNG_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_TX_REMPTY_INT_ENA I2S_TX_REMPTY_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_TX_WFULL_INT_ENA I2S_TX_WFULL_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_RX_REMPTY_INT_ENA I2S_RX_REMPTY_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_RX_WFULL_INT_ENA I2S_RX_WFULL_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_TX_PUT_DATA_INT_ENA I2S_TX_PUT_DATA_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + I2S_RX_TAKE_DATA_INT_ENA I2S_RX_TAKE_DATA_INT ֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 300 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.7. I2S_INT_CLR_REG (0x0018) + + (reserved) I2S_OIU2ST__ITNIO2_STDA_SOLCI_U2RESTO___EFIDNM_IS2_IPNSCDT_TRSYO__CI_CU2ERINLSRT_R_T_REOE__R(COUrIRNeLFTs_TR__eI_NIDrNCvITO2TeL_Sd_NRC_C)EILNL_IR2RI_NSST_U_INCCI2__LSDER_OOTFNIX2_E_SIHN__IUTRN_INXT2C__GSLHC__RTULINIXRN2T_SG_R_C_ETILNMIX2R_TPSW_T_CRYFLIU_X2RI_SLNRL_T_ER_IIMXNC2_STPLW_R_TTCYFIXL2U__RISLNP_LTUR__TIXNC__TLDTR_AACTKLAER__IDNATT_AC_LIRNT_CLR + +31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_OUT_TOTAL_EOF_INT_CLR I2S_OUT_TOTAL_EOF_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_IN_DSCR_EMPTY_INT_CLR I2S_IN_DSCR_EMPTY_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_OUT_DSCR_ERR_INT_CLR I2S_OUT_DSCR_ERR_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_IN_DSCR_ERR_INT_CLR I2S_IN_DSCR_ERR_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_OUT_EOF_INT_CLR I2S_OUT_EOF_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_OUT_DONE_INT_CLR I2S_OUT_DONE_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_IN_SUC_EOF_INT_CLR I2S_IN_SUC_EOF_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_IN_DONE_INT_CLR I2S_IN_DONE_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_TX_HUNG_INT_CLR I2S_TX_HUNG_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_RX_HUNG_INT_CLR I2S_RX_HUNG_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_TX_REMPTY_INT_CLR I2S_TX_REMPTY_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_TX_WFULL_INT_CLR I2S_TX_WFULL_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_RX_REMPTY_INT_CLR I2S_RX_REMPTY_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_RX_WFULL_INT_CLR I2S_RX_WFULL_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_TX_PUT_DATA_INT_CLR I2S_TX_PUT_DATA_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + I2S_RX_TAKE_DATA_INT_CLR I2S_RX_TAKE_DATA_INT ֥ᇏ؎ౢԢ໊bčᆺཿĎ + +ুᶈྐ༏॓࠯ 301 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.8. I2S_TIMING_REG (0x001c) + + (reserved) I2S_TX_BI2CSK_D_IANT_AII2N_SVE_NRAIX2B_SDL_EST_XYD_NDEIC2LSS_AY_SYNRWCX__BSCWIK2S_O_RUXT__WDESIL2_ASOY_UTTX__DSEDL_I2AOSYU_TTX_D_WELSAI_2YOS_UTTX__DBECLIKA2_YSO_RUXT__SDDEIL_2IASNY__RDXE_LWAYSI2_SIN__RDXE_LBACYIK2S_I_NT_XD_EWLSAI_2YISN__TDXE_LBACYK_IN_DELAY + +31 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 65 43 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_TX_BCK_IN_INV ࡼՎ໊ᇂ 1đ֒ BCK ྐ‫ࣉݼ‬ೆՖࠏ‫ؿ‬ෂଆॶൈ߶Фّሇbč‫؀‬/ཿĎ + I2S_DATA_ENABLE_DELAY ඔऌႵིѓᆽ໊֥࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + I2S_RX_DSYNC_SW ࡼՎ໊ᇂ 1đᄝ double sync ଆൔ༯ࡼྐ‫ݼ‬๝҄Ⴟࢤ൬ଆॶᇏbč‫؀‬/ཿĎ + I2S_TX_DSYNC_SW ࡼՎ໊ᇂ 1đᄝ double sync ଆൔ༯ࡼྐ‫ݼ‬๝҄Ⴟ‫ؿ‬ෂଆॶᇏbč‫؀‬/ཿĎ + I2S_RX_BCK_OUT_DELAY ࢤ൬ଆൔ༯ BCK ൻԛ֥࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + I2S_RX_WS_OUT_DELAY ࢤ൬ଆൔ༯ WS ྐ‫֥ݼ‬࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + I2S_TX_SD_OUT_DELAY ‫ؿ‬ෂଆൔ༯ SD ྐ‫֥ݼ‬࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + I2S_TX_WS_OUT_DELAY ‫ؿ‬ෂଆൔ༯ WS ྐ‫֥ݼ‬࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + I2S_TX_BCK_OUT_DELAY ‫ؿ‬ෂଆൔ༯ BCK ྐ‫֥ݼ‬࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + I2S_RX_SD_IN_DELAY ࢤ൬ଆൔ༯ SD ൻೆ֥࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + I2S_RX_WS_IN_DELAY ࢤ൬ଆൔ༯ WS ൻೆ֥࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + I2S_RX_BCK_IN_DELAY ࢤ൬ଆൔ༯ BCK ൻೆ֥࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + I2S_TX_WS_IN_DELAY Ֆࠏ‫ؿ‬ෂଆൔ༯ WS ྐ‫֥ݼ‬࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + I2S_TX_BCK_IN_DELAY Ֆࠏ‫ؿ‬ෂଆൔ༯ BCK ൻೆ֥࿼Ӿᇛ௹ඔbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 302 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.9. I2S_FIFO_CONF_REG (0x0020) + + (reserved) I2S_RIX2_SF_ITFXO__FMIFOOI2D_S_M_FROOXDR__CFFIEFO_ORE_CNMEO_I2EDSN_TX_FIFOI2_SM_DOSDCR_EN I2S_TX_DATA_NUM I2S_RX_DATA_NUM + +31 21 20 19 18 16 15 13 12 11 65 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 1 32 32 Reset + + I2S_RX_FIFO_MOD_FORCE_EN Վ໊Ⴅჹᇂ 1bč‫؀‬/ཿĎ + I2S_TX_FIFO_MOD_FORCE_EN Վ໊Ⴅჹᇂ 1bč‫؀‬/ཿĎ + I2S_RX_FIFO_MOD ࢤ൬ FIFO ଆൔ஥ᇂ໊bč‫؀‬/ཿĎ + I2S_TX_FIFO_MOD ‫ؿ‬ෂ FIFO ଆൔ஥ᇂ໊bč‫؀‬/ཿĎ + I2S_DSCR_EN ᇂ໊൐ି I2S DMA ଆൔbč‫؀‬/ཿĎ + I2S_TX_DATA_NUM ‫ؿ‬ෂ FIFO ඔऌӉ؇֥ᚐᆴbč‫؀‬/ཿĎ + I2S_RX_DATA_NUM ࢤ൬ FIFO ඔऌӉ؇֥ᚐᆴbč‫؀‬/ཿĎ + + Register 12.10. I2S_RXEOF_NUM_REG (0x0024) + +31 0 + + 64 Reset + + I2S_RXEOF_NUM_REG րࢤ൬ඔऌ֥Ӊ؇b߶Ԩ‫ ؿ‬I2S_IN_SUC_EOF_INT ᇏ؎bč‫؀‬/ཿĎ + + Register 12.11. I2S_CONF_SINGLE_DATA_REG (0x0028) + +31 0 + + 0 Reset + + I2S_CONF_SINGLE_DATA_REG ቐല֡ࠇႷല֡۴ऌ TX_CHAN_MOD ‫ ބ‬I2S_TX_MSB_RIGHT ൻ + ԛЌթᄝՎ࠷թఖ֥ӈਈᆴbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 303 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.12. I2S_CONF_CHAN_REG (0x002c) + + (reserved) I2S_RX_CHANI2_SM_OTDX_CHAN_MOD + +31 54 32 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_RX_CHAN_MOD I2S ࢤ൬๙֡ଆൔ஥ᇂ໊đབྷ౦౨ҕॉᅣࢫ 12.4.5bč‫؀‬/ཿĎ + I2S_TX_CHAN_MOD I2S ‫ؿ‬ෂ๙֡ଆൔ஥ᇂ໊đབྷ౦౨ҕॉᅣࢫ 12.4.4bč‫؀‬/ཿĎ + + Register 12.13. I2S_OUT_LINK_REG (0x0030) + + (reservI2eSd_) OIU2ST_LOINIU2KST__LROINEUSKTT_LASINRTATKR_TSTOP (reserved) I2S_OUTLINK_ADDR + 0x000000 +31 30 29 28 27 20 19 0 + +0 0 0 00 0 0 0 0 0 0 0 Reset + + I2S_OUTLINK_RESTART ᇂ໊ᇗఓ‫ؿ‬ෂ৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + I2S_OUTLINK_START ᇂ໊ष൓‫ؿ‬ෂ৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + I2S_OUTLINK_STOP ᇂ໊๔ᆸ‫ؿ‬ෂ৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + I2S_OUTLINK_ADDR ֻ၂۱‫ؿ‬ෂ৽і૭ඍ‫ֹ֥ژ‬ᆶbč‫؀‬/ཿĎ + + Register 12.14. I2S_IN_LINK_REG (0x0034) + + (reservI2eSd_) INI2LSIN_KINI_2LRSINE_SKINT_LASINRTATKR_TSTOP (reserved) I2S_INLINK_ADDR + 0x000000 +31 30 29 28 27 20 19 0 + +0 0 0 00 0 0 0 0 0 0 0 Reset + + I2S_INLINK_RESTART ᇂ໊ᇗఓࢤ൬৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + I2S_INLINK_START ᇂ໊ष൓ࢤ൬৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + I2S_INLINK_STOP ᇂ໊๔ᆸࢤ൬৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ + I2S_INLINK_ADDR ֻ၂۱ࢤ൬৽і૭ඍ‫ֹ֥ژ‬ᆶbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 304 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) 0 + + Register 12.15. I2S_OUT_EOF_DES_ADDR_REG (0x0038) Reset + + 31 + + 0x000000000 + + I2S_OUT_EOF_DES_ADDR_REG ളӮ EOF ֥‫ؿ‬ෂ৽і૭ඍ‫ֹ֥ژ‬ᆶbčᆺ‫؀‬Ď + + Register 12.16. I2S_IN_EOF_DES_ADDR_REG (0x003c) 0 + +31 Reset + + 0x000000000 + + I2S_IN_EOF_DES_ADDR_REG ളӮ EOF ֥ࢤ൬৽і૭ඍ‫ֹژ‬ᆶbčᆺ‫؀‬Ď + + Register 12.17. I2S_OUT_EOF_BFR_DES_ADDR_REG (0x0040) + +31 0 + + 0x000000000 Reset + + I2S_OUT_EOF_BFR_DES_ADDR_REG ളӮ EOF ֥‫ؿ‬ෂ৽і૭ඍ‫ؓژ‬ႋ֥ߏթֹ֥ᆶbčᆺ‫؀‬Ď + + Register 12.18. I2S_INLINK_DSCR_REG (0x0048) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_INLINK_DSCR_REG ֒భࢤ൬৽і૭ඍ‫ֹ֥ژ‬ᆶbčᆺ‫؀‬Ď + + Register 12.19. I2S_INLINK_DSCR_BF0_REG (0x004c) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_INLINK_DSCR_BF0_REG ༯၂۱ࢤ൬৽і૭ඍ‫ֹ֥ژ‬ᆶbčᆺ‫؀‬Ď + + Register 12.20. I2S_INLINK_DSCR_BF1_REG (0x0050) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_INLINK_DSCR_BF1_REG ༯၂۱ࢤ൬৽іඔऌ buffer ֹ֥ᆶbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 305 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.21. I2S_OUTLINK_DSCR_REG (0x0054) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_OUTLINK_DSCR_REG ֒భ‫ؿ‬ෂ৽і૭ඍ‫ֹ֥ژ‬ᆶbčᆺ‫؀‬Ď + + Register 12.22. I2S_OUTLINK_DSCR_BF0_REG (0x0058) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_OUTLINK_DSCR_BF0_REG ༯၂۱‫ؿ‬ෂ৽і૭ඍ‫ֹ֥ژ‬ᆶbčᆺ‫؀‬Ď + + Register 12.23. I2S_OUTLINK_DSCR_BF1_REG (0x005c) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + I2S_OUTLINK_DSCR_BF1_REG ༯၂۱‫ؿ‬ෂ৽іඔऌ buffer ֹ֥ᆶbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 306 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.24. I2S_LC_CONF_REG (0x0060) + + (reserved) I2S_CIH2SE_COKIU2_SOT__WIDNINA2DSTESA_RC_OBRIU2U_STBR_DUOSS(RTUrCe_STRsET_e_N_ErBvIEO2eUNSFdR__)SMOITU2O_STDE__NEOAIUU2STTO__ILN_IOW2_SOLR_OPBA_OIAH2TPCSEB_KS_MTATE_IH2SRSBTS_MTO_IU2FSTIF__OIRN_S_RTRSSTT + +31 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Reset + + I2S_CHECK_OWNER ᇂ໊đ႗ࡱҰु owner bitbč‫؀‬/ཿĎ + + I2S_OUT_DATA_BURST_EN ‫ؿ‬ෂඔऌଆൔ஥ᇂ໊bč‫؀‬/ཿĎ + 1ğ‫ؿ‬ෂඔऌ൐Ⴈ burst ଆൔĠ + 0ğ‫ؿ‬ෂඔऌ൐Ⴈሳࢫଆൔb + + I2S_INDSCR_BURST_EN DMA ࢤ൬৽і૭ඍ‫ژ‬Ԯൻଆൔ஥ᇂ໊bč‫؀‬/ཿĎ + 1ğ൐Ⴈ burst ଆൔĠ + 0ğ൐Ⴈሳࢫଆൔb + + I2S_OUTDSCR_BURST_EN DMA ‫ؿ‬ෂ৽і૭ඍ‫ژ‬Ԯൻଆൔ஥ᇂ໊bč‫؀‬/ཿĎ + 1ğ൐Ⴈ burst ଆൔĠ + 0ğ൐Ⴈሳࢫ‫؀‬౼ଆൔb + + I2S_OUT_EOF_MODE Ӂള I2S_OUT_EOF_INT ֥ଆൔbč‫؀‬/ཿĎ + 1ğDMA Ֆ FIFO ᇏ֐ԛ෮ႵඔऌĠ + 0ğAHB ࡼ෮Ⴕඔऌ๷ೆ FIFO ᇏb + + I2S_OUT_AUTO_WRBACK ࡼՎ໊ᇂ 1đ֒‫ؿ‬ෂ buffer ᇏ֥ඔऌ‫ؿ‬ෂປиൈđሱ‫߭׮‬ཿ‫ؿ‬ෂ৽ + іbč‫؀‬/ཿĎ + + I2S_OUT_LOOP_TEST ᇂ໊࿖ߌҩ൫‫ؿ‬ෂ৽іbč‫؀‬/ཿĎ + + I2S_IN_LOOP_TEST ᇂ໊࿖ߌҩ൫ࢤ൬৽іbč‫؀‬/ཿĎ + + I2S_AHBM_RST ᇂ໊ᇗᇂ DMA ֥ AHB ࢤ१bč‫؀‬/ཿĎ + + I2S_AHBM_FIFO_RST ᇂ໊ᇗᇂ DMA ֥ AHB ࢤ१ cmdFIFObč‫؀‬/ཿĎ + + I2S_OUT_RST ᇂ໊ᇗᇂ‫ؿ‬ෂ DMA FSMbč‫؀‬/ཿĎ + + I2S_IN_RST ᇂ໊ᇗᇂࢤ൬ DMA FSMbč‫؀‬/ཿĎ + + Register 12.25. I2S_LC_STATE0_REG (0x006c) 0 + +31 Reset + + 0x000000000 + + I2S_LC_STATE0_REG ࢤ൬ DMA ๙֡ሑ෿࠷թఖbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 307 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) 0 + + Register 12.26. I2S_LC_STATE1_REG (0x0070) Reset + + 31 + + 0x000000000 + + I2S_LC_STATE1_REG ‫ؿ‬ෂ DMA ๙֡ሑ෿࠷թఖbčᆺ‫؀‬Ď + + Register 12.27. I2S_LC_HUNG_CONF_REG (0x0074) + + (reserved) I2S_LC_FIFIO2S_T_ILMCE_OFIUFOT__ETNIMAEOUT_SHIFTI2S_LC_FIFO_TIMEOUT + +31 12 11 10 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 010 0 0 0x010 Reset + + I2S_LC_FIFO_TIMEOUT_ENA FIFO ӑൈ֥൐ି໊bč‫؀‬/ཿĎ + + I2S_LC_FIFO_TIMEOUT_SHIFT Ⴈ Ⴟ ഡ ᇂ ࠹ ඔ ఖ ֥ ᚐ ᆴb ֒ ࠹ ඔ ఖ ֥ ᆴ >= + + 88000/2i2s_lc_fifo_timeout_shift ൈđ࠹ඔఖᇗᇂbč‫؀‬/ཿĎ + + I2S_LC_FIFO_TIMEOUT ֒ FIFO hung ࠹ඔఖ֩ႿՎ໊֥ᆴൈđ‫ؿ‬ෂඔऌӑൈᇏ؎ࠇࢤ൬ඔऌӑൈ + ᇏ؎ФԨ‫ؿ‬bč‫؀‬/ཿĎ + + Register 12.28. I2S_CONF1_REG (0x00a0) + + (reserved) I2S_TIX2_SS_TROXP_P_ECNIM2S__BRYXP_APSCSIM2S__CTOXN_PFCIM2S_B_TYXP_APSCSM_CONF + +31 98 76 432 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 1 0x0 1 0x1 Reset + + I2S_TX_STOP_EN ࡼՎ໊ᇂ 1đ֒‫ؿ‬ෂ FIFO ູॢൈđ‫ؿ‬ෂଆॶ๔ᆸൻԛ BCK ‫ ބ‬WS ྐ‫ݼ‬bč‫؀‬/ཿĎ + + I2S_RX_PCM_BYPASS ᇂ໊൐ࢤ൬ඔऌಡ‫ݖ‬࿢෪/ࢳ࿢෪ଆॶbč‫؀‬/ཿĎ + + I2S_RX_PCM_CONF ࿢෪/ࢳ࿢෪ଆॶ஥ᇂ໊bč‫؀‬/ཿĎ + 0ğࢳ࿢෪ࢤ൬ඔऌĠ + 1ğ࿢෪ࢤ൬ඔऌb + + I2S_TX_PCM_BYPASS ᇂ໊൐‫ؿ‬ෂඔऌಡ‫ݖ‬࿢෪/ࢳ࿢෪ଆॶbč‫؀‬/ཿĎ + + I2S_TX_PCM_CONF ࿢෪/ࢳ࿢෪ଆॶ஥ᇂ໊bč‫؀‬/ཿĎ + 0ğࢳ࿢෪‫ؿ‬ෂඔऌĠ + 1ğ࿢෪‫ؿ‬ෂඔऌb + +ুᶈྐ༏॓࠯ 308 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.29. I2S_PD_CONF_REG (0x00a4) + + (reserved) (reserv(reeds)ervI2eSd_) FII2FOS__FFIOFOR_CFEO_RPUCE_PD + +31 43 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Reset + + I2S_FIFO_FORCE_PU ఼ᇅषఓ FIFObč‫؀‬/ཿĎ + I2S_FIFO_FORCE_PD ఼ᇅܱо FIFObč‫؀‬/ཿĎ + + Register 12.30. I2S_CONF2_REG (0x00a8) + + (reserved) I2S_INI2TSE_RE_IX2VTSA__LALIDDC_CDE(__rNeSEsTNeArRveTd_I2)ESN_LIC2DS__TLICX2_DSS__DTCXXA2_MW_EERNRXA2__EENN + +31 87 6 54 32 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Reset + + I2S_INTER_VALID_EN ᇂ໊൐ି camera ֥ଽ҆ಪᆣbč‫؀‬/ཿĎ + I2S_EXT_ADC_START_EN ᇂ໊൐ିຓ҆ ADCbč‫؀‬/ཿĎ + I2S_LCD_EN ᇂ໊൐ି LCD ଆൔbč‫؀‬/ཿĎ + I2S_LCD_TX_SDX2_EN ᇂ໊đᄝ LCD ଆൔ༯‫گ‬ᇅඔऌؓčඔऌᆠđForm 2Ďbč‫؀‬/ཿĎ + I2S_LCD_TX_WRX2_EN LCD ଆൔ༯đ၂۱ඔऌཿਆՑbč‫؀‬/ཿĎ + I2S_CAMERA_EN ᇂ໊൐ି camera ଆൔbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 309 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.31. I2S_CLKM_CONF_REG (0x00ac) + + (reserved) I2S_C(LreKsAe_rvEeNdA) I2S_CLKM_DIV_A I2S_CLKM_DIV_B I2S_CLKM_DIV_NUM + +31 22 21 20 19 14 13 87 0 + +00000000000000 0 0 0x00 0x00 4 Reset + + I2S_CLKA_ENA ᇂ໊൐ି clk_apllbč‫؀‬/ཿĎ + I2S_CLKM_DIV_A ཬඔ‫ٳ‬௔ఖ֥‫ٳ‬ଛᆴbč‫؀‬/ཿĎ + I2S_CLKM_DIV_B ཬඔ‫ٳ‬௔ఖ֥‫ٳ‬ሰᆴbč‫؀‬/ཿĎ + I2S_CLKM_DIV_NUM I2S ൈᇒ‫ٳ‬௔ఖ֥ᆜඔᆴbč‫؀‬/ཿĎ + + Register 12.32. I2S_SAMPLE_RATE_CONF_REG (0x00b0) + + (reserved) I2S_RX_BITS_MOD I2S_TX_BITS_MOD I2S_RX_BCK_DIV_NUM I2S_TX_BCK_DIV_NUM + +31 24 23 18 17 12 11 65 0 + +00000000 16 16 6 6 Reset + + I2S_RX_BITS_MOD ᇂ໊஥ᇂࢤ൬๙֥֡бหӉ؇bč‫؀‬/ཿĎ + I2S_TX_BITS_MOD ᇂ໊஥ᇂ‫ؿ‬ෂ๙֥֡бหӉ؇bč‫؀‬/ཿĎ + I2S_RX_BCK_DIV_NUM ࢤ൬ଆൔ༯֥бหൈᇒ஥ᇂ໊bč‫؀‬/ཿĎ + I2S_TX_BCK_DIV_NUM ‫ؿ‬ෂଆൔ༯֥бหൈᇒ஥ᇂ໊bč‫؀‬/ཿ + +ুᶈྐ༏॓࠯ 310 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.33. I2S_PDM_CONF_REG (0x00b4) + + (reserved) I2S_TIX2_SP_DRMX__IPH2DSPM__TB_XYS_PINPADCSMI_S2DS_SS_RTIGX_M_1P6A_DDEMIE2NSL_TS_ATIN_XIC_NP__IDSNMIH_2SIS_FHL_TPTIFX_TI_NP_DSMH_IFHTP_IN_SHIFT(reserved) I2S_TX_PDM_IS2ISN_CP_ID2OSMS_2RPPI2C2CSMM_2R_PCIX2DO_SMP_NDT_VCXM__OE_PNNEDNVM_E_ENN + +31 26 25 24 23 22 21 20 19 18 17 16 15 87 43 2 1 0 + +0 0 0 0 0 0 0 1 0x1 0x1 0x1 0x1 0 0 0 0 0 0 0 0 0x02 1 1 0 0 Reset + + I2S_TX_PDM_HP_BYPASS ᇂ໊ಡ‫ؿݖ‬ෂ PDM HP ‫ݖ‬ੲఖbč‫؀‬/ཿĎ + + I2S_RX_PDM_SINC_DSR_16_EN Filter group1 ֥ PDM ༯Ґဢੱbč‫؀‬/ཿĎ + 1ğ༯Ґဢੱ = 128Ġ + 0ğ༯Ґဢੱ = 64b + + I2S_TX_PDM_SIGMADELTA_IN_SHIFT ‫ט‬ᆜൻೆ֞ Filter ଆॶ֥ྐ‫ݼ‬նཬbč‫؀‬/ཿĎ + 0ğԢၛ 2Ġ1: Ӱၛ 1Ġ2: Ӱၛ 2Ġ3: Ӱၛ 4b + + I2S_TX_PDM_SINC_IN_SHIFT ‫ט‬ᆜൻೆ֞ Filter ଆॶ֥ྐ‫ݼ‬նཬbč‫؀‬/ཿĎ + 0ğԢၛ 2Ġ1: Ӱၛ 1Ġ2: Ӱၛ 2Ġ3: Ӱၛ 4b + + I2S_TX_PDM_LP_IN_SHIFT ‫ט‬ᆜൻೆ֞ Filter ଆॶ֥ྐ‫ݼ‬նཬbč‫؀‬/ཿĎ + 0ğԢၛ 2Ġ1: Ӱၛ 1Ġ2: Ӱၛ 2Ġ3: Ӱၛ 4b + + I2S_TX_PDM_HP_IN_SHIFT ‫ט‬ᆜൻೆ֞ Filter ଆॶ֥ྐ‫ݼ‬նཬbč‫؀‬/ཿĎ + 0ğԢၛ 2Ġ1: Ӱၛ 1Ġ2: Ӱၛ 2Ġ3: Ӱၛ 4b + + I2S_TX_PDM_SINC_OSR2 ഈҐဢੱ = 64×i2s_tx_pdm_sinc_osr2bč‫؀‬/ཿĎ + + I2S_PDM2PCM_CONV_EN ࡼՎ໊ᇂ 1đ൐ି PDM-PCM ሇߐఖbč‫؀‬/ཿĎ + + I2S_PCM2PDM_CONV_EN ࡼՎ໊ᇂ 1đ൐ି PCM-PDM ሇߐఖbč‫؀‬/ཿĎ + + I2S_RX_PDM_EN ࡼՎ໊ᇂ 1đ൐ିࢤ൬ PDM ଆൔbč‫؀‬/ཿĎ + + I2S_TX_PDM_EN ࡼՎ໊ᇂ 1đ൐ି‫ؿ‬ෂ PDM ଆൔbč‫؀‬/ཿĎ + + Register 12.34. I2S_PDM_FREQ_CONF_REG (0x00b8) + + (reserved) I2S_TX_PDM_FP I2S_TX_PDM_FS + 441 +31 20 19 10 9 0 + +000000000000 960 Reset + + I2S_TX_PDM_FP PCM-PDM ሇߐఖ֥ PDM ௔ੱҕඔbč‫؀‬/ཿĎ + I2S_TX_PDM_FS PCM-PDM ሇߐఖ֥ PCM ௔ੱҕඔbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 311 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 12 I2S ॥ᇅఖ (I2S) + + Register 12.35. I2S_STATE_REG (0x00bc) + + (reserved) I2S_RIX2_SF_ITFIXO2_S_FR_IFTEOXS__EIRDTE_LBSEAETC_KBACK + +31 32 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset + + I2S_RX_FIFO_RESET_BACK Վ໊ႨႿಒಪࢤ൬ FIFO ‫໊گ‬൞‫ڎ‬ປӮb1ğ‫໊گ‬ໃປӮĠ0ğ‫ၘ໊گ‬ + ປӮbčᆺ‫؀‬Ď + + I2S_TX_FIFO_RESET_BACK Վ໊ႨႿಒಪ‫ؿ‬ෂ FIFO ‫໊گ‬൞‫ڎ‬ປӮb1ğ‫໊گ‬ໃປӮĠ0ğ‫ၘ໊گ‬ + ປӮbčᆺ‫؀‬Ď + + I2S_TX_IDLE ‫ؿ‬ෂഡС֥ሑ෿໊b1ğ‫ؿ‬ෂഡСູॢ༽ሑ෿Ġ0ğ‫ؿ‬ෂഡСູ‫۽‬ቔሑ෿bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 312 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + +13 UART ॥ᇅఖ (UART) + +13.1 ‫ۀ‬ඍ + +ళೆൔႋႨ๙ӈေ౰၂۱ࡥֆ֥ѩ౏ᅝႨ༢๤ሧჷഒ֥ٚ‫م‬টԮൻඔऌb๙Ⴈၳ҄൬‫ؿ‬Ԯൻఖ (UART) ࠧॖၛ +ડቀᆃུေ౰đ෱ି‫ܔ‬ਲࠃֹაຓ҆ഡСࣉྛಆච‫۽‬ඔऌࢌߐbESP32 ྉோᇏႵ 3 ۱ UART ॥ᇅఖॖ‫܂‬൐Ⴈđ +ѩ౏࡙ಸ҂๝֥ UART ഡСbਸ਼ຓđUART ߎॖၛႨቔ‫ޣ‬ຓඔऌࢌߐ (IrDA) ࠇ RS-485 ‫ט‬ᇅࢳ‫ט‬ఖb +3 ۱ UART ॥ᇅఖႵ၂ቆ‫ିۿ‬ཌྷ๝֥࠷թఖbЧ໓ၛ UARTn ᆷս 3 ۱ UART ॥ᇅఖđn ູ 0a1a2b + +13.2 ᇶေหྟ + + • ॖщӱ൬‫ؿ‬ѯหੱ + • 3 ۱ UART ֥‫ؿ‬ෂ FIFO ၛࠣࢤ൬ FIFO ‫܋‬ཚ 1024 × 8-bit RAM + • ಆච‫۽‬ၳ҄๙ྐ + • ᆦӻൻೆྐ‫ݼ‬ѯหੱሱ࡟‫ିۿ‬ + • ᆦӻ 5/6/7/8 ໊ඔऌӉ؇ + • ᆦӻ 1/1.5/2/3 ۱๔ᆸ໊ + • ᆦӻఅ୽཮ဒ໊ + • ᆦӻ RS485 ླྀၰ + • ᆦӻ IrDA ླྀၰ + • ᆦӻ DMA ۚ෎ඔऌ๙ྐ + • ᆦӻ UART ߒྜଆൔ + • ᆦӻೈࡱੀ॥‫ބ‬႗ࡱੀ॥ + +13.3 ‫ିۿ‬૭ඍ + +13.3.1 UART ࡥࢺ + +UART ൞၂ᇕၛሳ‫ູ֝ژ‬ཟ֥๙Ⴈඔऌ৽đॖၛൌགྷഡСࡗ֥๙ྐbၳ҄Ԯൻ֥ၩන൞҂ླေᄝ‫ؿ‬ෂඔऌഈเ +ࡆൈᇒྐ༏bᆃ္ေ౰‫ؿ‬ෂ؊‫ࢤބ‬൬؊֥෎ੱa๔ᆸ໊aఅ୽཮ဒ໊֩‫׻‬ေཌྷ๝đ๙ྐҌିӮ‫ۿ‬b +၂۱‫ ֥྘ׅ‬UART ᆠष൓Ⴟ၂۱ఏ൓໊đࣅࢤሢ൞Ⴕིඔऌđಖު൞అ୽཮ဒ໊čॖႵॖ໭Ďđቋު൞๔ᆸ໊b +ESP32 ഈ֥ UART ॥ᇅఖᆦӻ‫؟‬ᇕሳ‫ژ‬Ӊ؇‫ބ‬๔ᆸ໊bਸ਼ຓđ॥ᇅఖߎᆦӻೈ႗ࡱੀ॥‫ ބ‬DMAđॖၛൌགྷ໭ +‫ۚډ‬෎֥ඔऌԮൻbष‫ؿ‬ᆀॖၛ൐Ⴈ‫؟‬۱ UART ؊१đ๝ൈႻିЌᆣ‫ޓ‬ഒ֥ೈࡱषཧb + +ুᶈྐ༏॓࠯ 313 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + +13.3.2 UART ࡏ‫ܒ‬ + + ๭ 13­1. UART ࠎЧࡏ‫ܒ‬๭ + +๭ 13-1 ູ UART ࠎЧࡏ‫ܒ‬๭bUART Ⴕਆ۱ൈᇒჷğ80-MHz APB_CLK ၛࠣҕॉൈᇒ REF_TICK čབྷ౦౨ҕ +ॉᅣࢫ‫ބ໊گ‬ൈᇒĎbॖၛ๙‫ݖ‬஥ᇂ UART_TICK_REF_ALWAYS_ON ট࿊ᄴൈᇒჷbൈᇒᇏ֥‫ٳ‬௔ఖႨႿؓൈ +ᇒჷࣉྛ‫ٳ‬௔đಖުӁളൈᇒྐ‫ݼ‬ট౺‫ ׮‬UART ଆॶbUART_CLKDIV_REG ࡼ‫ٳ‬௔༢ඔ‫ٳ‬Ӯਆ۱҆‫ٳ‬ğ +UART_CLKDIV ႨႿ஥ᇂᆜඔ҆‫ٳ‬đUART_CLKDIV_FRAG ႨႿ஥ᇂཬඔ҆‫ٳ‬b + +UART ॥ᇅఖॖၛ‫ູٳ‬ਆ۱‫ॶିۿ‬ğ‫ؿ‬ෂॶ‫ࢤބ‬൬ॶb + +‫ؿ‬ෂॶЇ‫ݣ‬၂۱‫ؿ‬ෂ FIFO ႨႿߏթր‫ؿ‬ෂ֥ඔऌbೈࡱॖၛ๙‫ ݖ‬APB ሹཌཿ Tx_FIFOđ္ॖၛ๙‫ ݖ‬DMA ࡼඔ +ऌϬೆ Tx_FIFObTx_FIFO_Ctrl ႨႿ॥ᇅ Tx_FIFO ֥‫؀‬ཿ‫ݖ‬ӱđ֒ Tx_FIFO ٤ॢൈđTx_FSM ๙‫ ݖ‬Tx_FIFO_Ctrl +‫؀‬౼ඔऌđѩࡼඔऌοᅶ஥ᇂ֥ᆠ۬ൔሇ߄Ӯбหੀbбหੀൻԛྐ‫ ݼ‬txd_out ॖၛ๙‫ݖ‬஥ᇂ UART_TXD_INV +࠷թఖൌགྷ౼ّ‫ିۿ‬b + +ࢤ൬ॶЇ‫ݣ‬၂۱ࢤ൬ FIFO ႨႿߏթրԩ৘֥ඔऌbൻೆбหੀ rxd_in ॖၛൻೆ֞ UART ॥ᇅఖbॖၛ๙‫ݖ‬ +UART_RXD_INV ࠷թఖൌགྷ౼ّbBaudrate_Detect ๙‫࡟ݖ‬ҩቋཬбหੀൻೆྐ‫֥ݼ‬ઝॺটҩਈൻೆྐ‫֥ݼ‬ѯ +หੱbStart_Detect ႨႿ࡟ҩඔऌ֥ START ໊đ֒࡟ҩ֞ START ໊ᆭުđRX_FSM ๙‫ ݖ‬Rx_FIFO_Ctrl ࡼᆠࢳ +༅ު֥ඔऌթೆ Rx_FIFO ᇏb + +ೈࡱॖၛ๙‫ ݖ‬APB ሹཌ‫؀‬౼ Rx_FIFO ᇏ֥ඔऌbູਔิۚඔऌԮൻིੱđॖၛ൐Ⴈ DMA ٚൔࣉྛඔऌ‫ؿ‬ෂࠇ +ࢤ൬b + +HW_Flow_Ctrl ๙‫ݖ‬ѓሙ UART RTS ‫ ބ‬CTSčrtsn_out ‫ ބ‬ctsn_inĎੀ॥ྐ‫ݼ‬ট॥ᇅ rxd_in ‫ ބ‬txd_out ֥ඔऌੀb +SW_Flow_Ctrl ๙‫ݖ‬ᄝ‫ؿ‬ෂඔऌੀᇏҬೆห൹ሳ‫ژ‬ၛࠣᄝࢤ൬ඔऌੀᇏ࡟ҩห൹ሳ‫ژ‬টࣉྛඔऌੀ֥॥ᇅb֒ +UART ԩႿ Light-sleepčབྷ౦౨ҕॉᅣࢫ֮‫ܵݻۿ‬৘Ďሑ෿ൈđWakeup_Ctrl ष൓࠹ෘ rxd_in ֥ઝԊ۱ඔđ֒ +ൻೆ RxD ခэ߄֥ՑඔնႿ֩Ⴟ (UART_ACTIVE_THRESHOLD+2) ൈӁള wake_up ྐ‫ݼ‬۳ RTC ଆॶđႮ RTC +টߒྜ UART ॥ᇅఖbᇿၩğᆺႵ UART0 ‫ ބ‬UART1 ऎႵ Light-sleep ‫ିۿ‬đ౏ rxd_in ҂ି๙‫ ݖ‬GPIO ࢌߐइᆔ +ൻೆđᆺି๙‫ ݖ‬IO_MUX ൻೆb + +ুᶈྐ༏॓࠯ 314 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + +13.3.3 UART RAM + + ๭ 13­2. UART ‫܋‬ཚ RAM ๭ + +ྉோᇏ 3 ۱ UART ॥ᇅఖ‫܋‬Ⴈ 1024x8-bit RAM ॢࡗbೂ๭ 13-2 ෮ൕđRAM ၛ block ູֆ໊ࣉྛ‫ٳ‬஥đ1 block +ູ 128×8 bitb๭ 13-2 ෮ൕູଏಪ౦ঃ༯ 3 ۱ UART ॥ᇅఖ֥ Tx_FIFO ‫ ބ‬Rx_FIFO ᅝႨ RAM ֥౦ঃb๙‫ݖ‬஥ +ᇂ UART_TX_SIZE ॖၛؓ UARTn ֥ Tx_FIFO ࣉྛঔᅚđ๙‫ݖ‬஥ᇂ UART_RX_SIZE ॖၛؓ UARTn ֥ Rx_FIFO +ࣉྛঔᅚđླေᇿၩ֥൞֒ঔᅚଖ၂۱ UART ֥ FIFO ॢࡗൈॖି߶ᅝႨః෰ UART ֥ FIFO ॢࡗb +֒ 3 ۱ UART ॥ᇅఖ‫׻‬҂‫۽‬ቔൈđॖၛ๙‫ݖ‬ᇂ໊ UART_MEM_PDaUART1_MEM_PD ၛࠣ UART2_MEM_PD +ট൐ RAM ࣉೆ֮‫ݻۿ‬ሑ෿b +UART0 ֥ Tx_FIFO ‫ ބ‬Rx_FIFO ॖၛ๙‫ݖ‬ᇂ໊ UART_TXFIFO_RST ‫ ބ‬UART_RXFIFO_RST ট‫໊گ‬bUART1 ֥ +Tx_FIFO ‫ ބ‬Rx_FIFO ॖၛ๙‫ݖ‬ᇂ໊ UART1_TXFIFO_RST ‫ ބ‬UART1_RXFIFO_RST ট‫໊گ‬b + + ඪૼğ + UART2 ֥ Tx_FIFO ‫ ބ‬Rx_FIFO ીႵཌྷႋ֥࠷թఖট‫໊گ‬bਸ਼ຓđUART1 ֥ UART1_TXFIFO_RST ‫ ބ‬UART1_RXFIFO_RST + ॖି߶႕ཙ UART2 ֥ྟିbၹՎđUART1 ֥ UART1_TXFIFO_RST ‫ ބ‬UART1_RXFIFO_RST ᆺିᄝ UART2 ֥ Tx_FIFO + ‫ ބ‬Rx_FIFO ‫׻‬ીႵඔऌ֥ൈީ൐Ⴈb + +3 ۱ UARTn ॖ๙‫࠷ݖ‬թఖ UART_FIFO_REG ٠໙ؓႋ֥ FIFOb + +13.3.4 ѯหੱ࡟ҩ + +ᇂ໊ UART_AUTOBAUD_EN ॖၛषఓ UART ѯหੱሱ࡟ҩ‫ିۿ‬b๭ 13-1 ᇏ֥ Baudrate_Detect ॖၛੲԢྐ‫ݼ‬ +ઝॺཬႿ UART_GLITCH_FILT ֥ᄮലb +ᄝ UART චٚࣉྛ๙ྐᆭభॖၛ๙‫ؿݖ‬ෂࠫ۱ෛࠏඔऌಞऎႵѯหੱ࡟ҩ‫֥ିۿ‬ඔऌࢤ൬ٚࣉྛѯหੱ‫ٳ‬༅b +UART_LOWPULSE_MIN_CNT թԥਔቋཬ֮‫׈‬௜ઝԊॺ؇đUART_HIGHPULSE_MIN_CNT թԥਔቋཬۚ‫׈‬௜ +ઝԊॺ؇đೈࡱॖၛ๙‫؀ݖ‬౼ᆃਆ۱࠷թఖࠆ౼‫ؿ‬ෂ֥ٚѯหੱb + +ুᶈྐ༏॓࠯ 315 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + +13.3.5 UART ඔऌᆠ + + ๭ 13­3. UART ඔऌᆠࢲ‫ܒ‬ + +๭ 13-3 ෮ൕູࠎЧඔऌᆠ۬ൔđඔऌᆠՖ START ໊ष൓ၛ STOP ໊ࢲඏbSTART ᅝႨ 1 bitđSTOP ໊ॖၛ๙ +‫ݖ‬஥ᇂ UART_STOP_BIT_NUMaUART_DL1_EN ‫ ބ‬UART_DL0_EN ൌགྷ 1/1.5/2/3 ໊ॺbSTART ູ֮‫׈‬௜đ +STOP ູۚ‫׈‬௜b + +ඔऌ໊ॺ (BIT0 ~ BITn) ູ 5 ~ 8 bitđॖၛ๙‫ ݖ‬UART_BIT_NUM ࣉྛ஥ᇂb֒ᇂ໊ UART_PARITY_EN ൈđඔऌ +ᆠ߶ᄝඔऌᆭުเࡆ၂໊అ୽཮ဒ໊bUART_PARITY ႨႿ࿊ᄴఅ཮ဒࠇ൞୽཮ဒb֒ࢤ൬ఖ࡟ҩ֞ൻೆඔऌ +֥཮ဒ໊հ༂ൈ߶Ӂള UART_PARITY_ERR_INT ᇏ؎đ֒ࢤ൬ఖ࡟ҩ֞ඔऌᆠ۬ൔհ༂ൈ߶Ӂള +UART_FRM_ERR_INT ᇏ؎b + +Tx_FIFO ᇏඔऌ‫ؿ׻‬ෂປӮު߶Ӂള UART_TX_DONE_INT ᇏ؎bᇂ໊ UART_TXD_BRK ൈđ‫ؿ‬ෂඔऌປӮު +‫ؿ‬ෂ؊߶‫ؿ‬ෂࠫ۱৵࿃֥ห൹ඔऌᆠ NULLđNULL ֥ඔਈॖႮ UART_TX_BRK_NUM ࣉྛ஥ᇂb‫ؿ‬ෂఖ‫ؿ‬ෂປ +෮Ⴕ֥ NULL ᆭު߶Ӂള UART_TX_BRK_DONE_INT ᇏ؎bඔऌᆠᆭࡗॖၛ๙‫ݖ‬஥ᇂ UART_TX_IDLE_NUM Ќ +ӻቋཬࡗ‫ۯ‬ൈࡗb֒၂ᆠඔऌᆭު֥ॢ༽ൈࡗնႿ֩Ⴟ UART_TX_IDLE_NUM ࠷թఖ֥஥ᇂᆴൈᄵӁള +UART_TX_BRK_IDLE_DONE_INT ᇏ؎b + + ๭ 13­4. AT_CMD ሳ‫۬ژ‬ൔ + +๭ 13-4 ູ၂ᇕห൹֥ AT_CMD ሳ‫۬ژ‬ൔb֒ࢤ൬ఖ৵࿃൬֞ UART_AT_CMD_CHAR ሳ‫౏ژ‬ሳ‫ژ‬ᆭࡗડቀೂ +༯่ࡱൈࡼ߶Ӂള UART_AT_CMD_CHAR_DET_INT ᇏ؎b + + • ࢤ൬ֻ֥֞၂۱ UART_AT_CMD_CHAR აഈ၂۱٤ UART_AT_CMD_CHAR ᆭࡗᇀഒЌӻ + UART_PER_IDLE_NUM ۱ APB ൈᇒb + + • UART_AT_CMD_CHAR ሳ‫ژ‬ᆭࡗсྶཬႿ UART_RX_GAP_TOUT ۱ APB ൈᇒb + + • ࢤ൬֥ UART_AT_CMD_CHAR ሳ‫ژ‬۱ඔсྶնႿ֩Ⴟ UART_CHAR_NUMb + + • ࢤ൬֥֞ቋު၂۱ UART_AT_CMD_CHAR ሳ‫ژ‬ა༯၂۱٤ UART_AT_CMD_CHAR ᆭࡗᇀഒЌӻ + UART_POST_IDLE_NUM ۱ APB ൈᇒb + +13.3.6 ੀ॥ + +UART ॥ᇅఖႵਆᇕඔऌੀ॥ٚൔğ႗ࡱੀ॥‫ބ‬ೈࡱੀ॥b႗ࡱੀ॥ᇶေ๙‫ݖ‬ൻԛྐ‫ ݼ‬rtsn_out ၛࠣൻೆྐ‫ݼ‬ +dsrn_in ࣉྛඔऌੀ॥ᇅbೈࡱੀ॥ᇶေ๙‫ݖ‬ᄝ‫ؿ‬ෂඔऌੀᇏҬೆห൹ሳ‫ژ‬ၛࠣᄝࢤ൬ඔऌੀᇏ࡟ҩห൹ሳ‫ژ‬ট +ൌགྷඔऌੀ॥‫ିۿ‬b + +ুᶈྐ༏॓࠯ 316 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + +13.3.6.1 ႗ࡱੀ॥ + + ๭ 13­5. ႗ࡱੀ॥๭ + +๭ 13-5 ູ UART ႗ࡱੀ॥๭b֒൐Ⴈ႗ࡱੀ॥‫ିۿ‬ൈđൻԛྐ‫ ݼ‬rtsn_out ູۚ‫׈‬௜іൕ౨౰ؓٚ‫ؿ‬ෂඔऌđ +rtsn_out ູ֮‫׈‬௜іൕ๙ᆩؓٚᇏᆸඔऌ‫ؿ‬ෂᆰ֞ rtsn_out ߫‫׈ۚگ‬௜b‫ؿ‬ෂఖ֥႗ࡱੀ॥Ⴕਆᇕٚൔb + + • UART_RX_FLOW_EN ֩Ⴟ 0ğॖၛ๙‫ݖ‬஥ᇂ UART_SW_RTS ‫ڿ‬э rtsn_out ֥‫׈‬௜b + + • UART_RX_FLOW_EN ֩Ⴟ 1ğ֒ Rx_FIFO ᇏ֥ඔऌնႿ UART_RX_FLOW_THRHD ൈঘ֮ rtsn_out ֥‫׈‬ + ௜b + +֒ UART ࡟ҩ֞ൻೆྐ‫ ݼ‬ctsn_in ֥ခэ߄ൈ߶Ӂള UART_CTS_CHG_INT ᇏ؎ѩ౏ᄝ‫ؿ‬ෂປ֒భඔऌު๔ᆸ +ࢤ༯ট֥ඔऌ‫ؿ‬ෂb + +ൻԛྐ‫ ݼ‬dtrn_out ູۚ‫׈‬௜іൕ‫ؿ‬ෂٚඔऌၘࣜሙСປиđUART ᄝ࡟ҩ֞ൻೆྐ‫ ݼ‬dsrn_in ֥ခэ߄ൈ߶Ӂ +ള UART_DSR_CHG_INT ᇏ؎bೈࡱᄝ࡟ҩ֞ᇏ؎ުđ๙‫؀ݖ‬౼ UART_DSRN ॖၛࠆ౼ dsrn_in ֥ൻೆྐ‫׈ݼ‬ +௜đՖ‫ط‬஑؎֒భ൞‫ڎ‬ॖၛࢤ൬ඔऌb + +ᇂ໊ UART_LOOPBACK ࠧषఓ UART ֥߭ߌҩ൫‫ିۿ‬bՎൈ UART ֥ൻԛྐ‫ ݼ‬txd_out ‫ބ‬ఃൻೆྐ‫ ݼ‬rxd_in +ཌྷ৵đrtsn_out ‫ ބ‬ctsn_in ཌྷ৵đdtrn_out ‫ ބ‬dsrn_out ཌྷ৵b֒ࢤ൬֥ඔऌა‫ؿ‬ෂ֥ඔऌཌྷ๝ൈіૼ UART ି +‫ܔ‬ᆞӈ‫ؿ‬ෂ‫ࢤބ‬൬ඔऌb + +13.3.6.2 ೈࡱੀ॥ + +ೈࡱॖၛ๙‫ݖ‬ᇂ໊ UART_FORCE_XOFF ট఼ᇅ๔ᆸ‫ؿ‬ෂఖ‫ؿ‬ෂඔऌđ္ॖၛ๙‫ݖ‬ᇂ໊ UART_FORCE_XON ট +఼ᇅ‫ؿ‬ෂఖ‫ؿ‬ෂඔऌb + +UART ߎॖၛ๙‫ݖ‬Ԯൻห൹ሳ‫ྛࣉژ‬ೈࡱੀ॥bᇂ໊ UART_SW_FLOW_CON_EN ॖၛषఓೈࡱੀ॥‫ିۿ‬b֒ +UART ࢤ൬֥ඔऌሳࢫඔӑ‫ ݖ‬UART_XOFF ֥ᚐᆴൈđॖၛ๙‫ؿݖ‬ෂ UART_XOFF_CHAR টۡᆩؓٚ๔ᆸ‫ؿ‬ෂ +ඔऌb + +ুᶈྐ༏॓࠯ 317 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + +ᄝ UART_SW_FLOW_CON_EN ູ 1 ൈđೈࡱॖၛᄝ಩ၩൈީ‫ؿ‬ෂੀ॥ሳ‫ژ‬bᇂ໊ UART_SEND_XOFFđ‫ؿ‬ෂ +ఖ߶ᄝ‫ؿ‬ෂປ֒భඔऌᆭުҬೆ‫ؿ‬ෂ၂۱ UART_XOFF_CHARĠᇂ໊ UART_SEND_XONđ‫ؿ‬ෂఖ߶ᄝ‫ؿ‬ෂປ֒ +భඔऌᆭުҬೆ‫ؿ‬ෂ၂۱ UART_XON_CHARb + +13.3.7 UDMA + +ESP32 ྉோଽ҆Ⴕਆ۱ UDMA (UART DMA)đ۷‫ྐ؟‬༏౨࡮ᅣࢫ DMA ॥ᇅఖb + +13.3.8 UART ᇏ؎ + + • UART_AT_CMD_CHAR_DET_INT: ֒ࢤ൬ఖ࡟ҩ֞ at_cmd ሳ‫ژ‬ൈԨ‫ؿ‬Վᇏ؎b + • UART_RS485_CLASH_INT: ᄝ RS-485 ଆൔ༯࡟ҩ֞‫ؿ‬ෂఖ‫ࢤބ‬൬ఖᆭࡗ֥Ԋ๬ൈԨ‫ؿ‬Վᇏ؎b + • UART_RS485_FRM_ERR_INT: ᄝ RS-485 ଆൔ༯࡟ҩ֞ඔऌᆠհ༂ൈԨ‫ؿ‬Վᇏ؎b + • UART_RS485_PARITY_ERR_INT: ᄝ RS-485 ଆൔ༯࡟ҩ֞཮ဒ໊հ༂ൈԨ‫ؿ‬Վᇏ؎b + • UART_TX_DONE_INT: ֒‫ؿ‬ෂఖ‫ؿ‬ෂປ FIFO ᇏ֥෮ႵඔऌൈԨ‫ؿ‬Վᇏ؎b + • UART_TX_BRK_IDLE_DONE_INT: ֒‫ؿ‬ෂఖᄝቋު၂۱ඔऌ‫ؿ‬ෂުЌӻਔቋ؋֥ࡗ‫ۯ‬ൈࡗൈԨ‫ؿ‬Վᇏ؎b + • UART_TX_BRK_DONE_INT: ֒‫ؿ‬ෂ FIFO ᇏ֥ඔऌ‫ؿ‬ෂປᆭު‫ؿ‬ෂఖປӮਔ‫ؿ‬ෂ NULL ᄵԨ‫ؿ‬Վᇏ؎b + • UART_GLITCH_DET_INT: ֒ࢤ൬ఖ࡟ҩ֞ఏ൓໊ൈԨ‫ؿ‬Վᇏ؎b + • UART_SW_XOFF_INT: UART_SW_FLOW_CON_EN ᇂ໊ൈđ֒ࢤ൬ఖࢤ൬֞ Xon ሳ‫ژ‬ൈԨ‫ؿ‬Վᇏ؎b + • UART_SW_XON_INT: UART_SW_FLOW_CON_EN ᇂ໊ൈđ֒ࢤ൬ఖࢤ൬֞ Xoff ሳ‫ژ‬ൈԨ‫ؿ‬Վᇏ؎b + • UART_RXFIFO_TOUT_INT: ֒ࢤ൬ఖࢤ൬၂۱ሳࢫ֥ൈࡗնႿ RX_TOUT_THRHD ൈԨ‫ؿ‬Վᇏ؎b + • UART_BRK_DET_INT: ֒ࢤ൬ఖᄝ๔ᆸ໊ᆭު࡟ҩ֞ NULL ൈԨ‫ؿ‬Վᇏ؎b + • UART_CTS_CHG_INT: ֒ࢤ൬ఖ࡟ҩ֞ CTSn ྐ‫֥ݼ‬ခэ߄ൈԨ‫ؿ‬Վᇏ؎b + • UART_DSR_CHG_INT: ֒ࢤ൬ఖ࡟ҩ֞ DSRn ྐ‫֥ݼ‬ခэ߄ൈԨ‫ؿ‬Վᇏ؎b + • UART_RXFIFO_OVF_INT: ֒ࢤ൬ఖࢤ൬֥֞ඔऌਈ‫؟‬Ⴟ FIFO ֥թԥਈൈԨ‫ؿ‬Վᇏ؎b + • UART_FRM_ERR_INT: ֒ࢤ൬ఖ࡟ҩ֞ඔऌᆠհ༂ൈԨ‫ؿ‬Վᇏ؎b + • UART_PARITY_ERR_INT: ֒ࢤ൬ఖ࡟ҩ֞཮ဒ໊հ༂ൈԨ‫ؿ‬Վᇏ؎b + • UART_TXFIFO_EMPTY_INT: ֒‫ؿ‬ෂ FIFO ᇏ֥ඔऌਈഒႿ [tx_mem_cnt, txfifo_cnt] ෮ᆷ‫֥ק‬ᆴൈԨ‫ؿ‬Վᇏ + + ؎b + • UART_RXFIFO_FULL_INT: ֒ࢤ൬ఖࢤ൬֥֞ඔऌ‫؟‬Ⴟ [rx_flow_thrhd_h3, rx_flow_thrhd] ෮ᆷ‫֥ק‬ᆴൈԨ + + ‫ؿ‬Վᇏ؎b + +13.3.9 UHCI ᇏ؎ + + • UHCI_SEND_A_REG_Q_INT: ֒൐Ⴈ always_send ‫ؿ‬ෂ၂Ա؋ЇđDMA ‫ؿ‬ෂਔ؋ЇުԨ‫ؿ‬Վᇏ؎b + • UHCI_SEND_S_REG_Q_INT: ֒൐Ⴈ single_send ‫ؿ‬ෂ၂Ա؋ЇđDMA ‫ؿ‬ෂਔ؋ЇުԨ‫ؿ‬Վᇏ؎b + • UHCI_OUT_TOTAL_EOF_INT: ֒෮Ⴕඔऌ‫ؿၘ׻‬ෂൈԨ‫ؿ‬Վᇏ؎b + • UHCI_OUTLINK_EOF_ERR_INT: ֒࡟ҩ֞‫ؿ‬ෂ৽і૭ඍ‫ژ‬ᇏ֥ EOF Ⴕհ༂ൈԨ‫ؿ‬Վᇏ؎b + +ুᶈྐ༏॓࠯ 318 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + +• UHCI_IN_DSCR_EMPTY_INT: ֒ DMA ીႵቀ‫ࢤ֥ܔ‬൬৽і૭ඍ‫ژ‬ൈԨ‫ؿ‬Վᇏ؎b +• UHCI_OUT_DSCR_ERR_INT: ֒ࢤ൬৽і૭ඍ‫ژ‬৚Ⴕհ༂ൈԨ‫ؿ‬Վᇏ؎b +• UHCI_IN_DSCR_ERR_INT: ֒‫ؿ‬ෂ৽і૭ඍ‫ژ‬৚Ⴕհ༂ൈԨ‫ؿ‬Վᇏ؎b +• UHCI_OUT_EOF_INT: ֒భ૭ඍ‫ ֥ژ‬EOF ູ໊ 1 ൈԨ‫ؿ‬Վᇏ؎b +• UHCI_OUT_DONE_INT: ֒‫ؿ‬ෂ৽і૭ඍ‫ژ‬ປӮൈԨ‫ؿ‬Վᇏ؎b +• UHCI_IN_ERR_EOF_INT: ֒ࢤ൬৽і૭ඍ‫ژ‬ᇏ֥ EOF Ⴕհ༂ൈԨ‫ؿ‬Վᇏ؎b +• UHCI_IN_SUC_EOF_INT: ֒ࢤ൬၂۱ඔऌЇൈԨ‫ؿ‬Վᇏ؎b +• UHCI_IN_DONE_INT: ֒၂۱ࢤ൬৽і૭ඍ‫ژ‬ປӮൈԨ‫ؿ‬Վᇏ؎b +• UHCI_TX_HUNG_INT: ֒ DMA Ֆ RAM ᇏ‫؀‬౼ඔऌ֥ൈࡗ‫ݖ‬ӉൈԨ‫ؿ‬Վᇏ؎b +• UHCI_RX_HUNG_INT: ֒ DMA ࢤ൬ඔऌ֥ൈࡗ‫ݖ‬ӉൈԨ‫ؿ‬Վᇏ؎b +• UHCI_TX_START_INT: ֒ DMA ࡟ҩ֞‫ژۯٳ‬ൈԨ‫ؿ‬Վᇏ؎b +• UHCI_RX_START_INT: ֒‫ؿၘژۯٳ‬ෂൈԨ‫ؿ‬Վᇏ؎b + +13.4 ࠷թఖਙі ૭ඍ UART0 UART1 UART2 ٠໙ + +13.4.1 UART ࠷թఖ ஥ᇂ࠷թఖ 0 0x3FF40020 0x3FF50020 0x3FF6E020 ‫؀‬/ཿ + ஥ᇂ࠷թఖ 1 0x3FF40024 0x3FF50024 0x3FF6E024 ‫؀‬/ཿ + ଀ӫ ൈᇒ‫ٳ‬௔஥ᇂ 0x3FF40014 0x3FF50014 0x3FF6E014 ‫؀‬/ཿ + ஥ᇂ࠷թఖ ೈࡱੀ॥஥ᇂ 0x3FF40034 0x3FF50034 0x3FF6E034 ‫؀‬/ཿ + UART_CONF0_REG ೈࡱੀ॥ሳ‫ژ‬஥ᇂ 0x3FF4003C 0x3FF5003C 0x3FF6E03C ‫؀‬/ཿ + UART_CONF1_REG ඤ૤ଆൔ஥ᇂ 0x3FF40038 0x3FF50038 0x3FF6E038 ‫؀‬/ཿ + UART_CLKDIV_REG ᆠࢲඏॢ༽஥ᇂ 0x3FF40040 0x3FF50040 0x3FF6E040 ‫؀‬/ཿ + UART_FLOW_CONF_REG RS485 ଆൔ஥ᇂ 0x3FF40044 0x3FF50044 0x3FF6E044 ‫؀‬/ཿ + UART_SWFC_CONF_REG + UART_SLEEP_CONF_REG UART ሑ෿࠷թఖ 0x3FF4001C 0x3FF5001C 0x3FF6E01C ᆺ‫؀‬ + UART_IDLE_CONF_REG + UART_RS485_CONF_REG ѯหੱሱ࡟࠷թఖ஥ᇂ 0x3FF40018 0x3FF50018 0x3FF6E018 ‫؀‬/ཿ + ሑ෿࠷թఖ ࠷թఖ + UART_STATUS_REG ѯหੱሱ࡟ቋ֮֮‫׈‬௜ 0x3FF40028 0x3FF50028 0x3FF6E028 ᆺ‫؀‬ + ѯหੱሱ࡟࠷թఖ ઝԊӻ࿃ൈࡗ࠷թఖ 0x3FF4002C 0x3FF5002C 0x3FF6E02C ᆺ‫؀‬ + ѯหੱሱ࡟ቋ؋ۚ‫׈‬௜ 0x3FF40068 0x3FF50068 0x3FF6E068 ᆺ‫؀‬ + UART_AUTOBAUD_REG ઝԊӻ࿃ൈࡗ࠷թఖ 0x3FF4006C 0x3FF5006C 0x3FF6E06C ᆺ‫؀‬ + ѯหੱሱ࡟ۚ‫׈‬௜ઝԊ + UART_LOWPULSE_REG ࠷թఖ + ѯหੱሱ࡟֮‫׈‬௜ઝԊ + UART_HIGHPULSE_REG ࠷թఖ + + UART_POSPULSE_REG + + UART_NEGPULSE_REG + +ুᶈྐ༏॓࠯ 319 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + +UART_RXD_CNT_REG ѯหੱሱ࡟ခэ߄࠹ඔ 0x3FF40030 0x3FF50030 0x3FF6E030 ᆺ‫؀‬ + ࠷թఖ + 0x3FF40048 0x3FF50048 +AT ሇၬ྽ਙ࡟ҩ࠷թఖ + 0x3FF4004C 0x3FF5004C + ሳ‫ژ‬྽ਙ‫ؿ‬ෂభ֥ൈ྽ 0x3FF40050 0x3FF50050 0x3FF6E048 ‫؀‬/ཿ +UART_AT_CMD_PRECNT_REG 0x3FF40054 0x3FF50054 + + ஥ᇂ 0x3FF40000 0x3FF50000 + 0x3FF40058 0x3FF50058 + ሳ‫ژ‬྽ਙ‫ؿ‬ෂު֥ൈ྽ 0x3FF40064 0x3FF50064 0x3FF6E04C ‫؀‬/ཿ +UART_AT_CMD_POSTCNT_REG + 0x3FF40004 0x3FF50004 0x3FF6E050 ‫؀‬/ཿ + ஥ᇂ 0x3FF40008 0x3FF50008 0x3FF6E054 ‫؀‬/ཿ + 0x3FF4000C 0x3FF5000C +UART_AT_CMD_GAPTOUT_REG ӑൈ஥ᇂ࠷թఖ 0x3FF40010 0x3FF50010 + +UART_AT_CMD_CHAR_REG AT ሇၬ྽ਙ࡟ҩ஥ᇂ +FIFO ஥ᇂ࠷թఖ + +UART_FIFO_REG FIFO ඔऌ࠷թఖ 0x3FF6E000 ‫؀‬/ཿ + 0x3FF6E058 ‫؀‬/ཿ +UART_MEM_CONF_REG UART ᚐᆴ‫ٳބ‬஥஥ᇂ 0x3FF6E064 ᆺ‫؀‬ + +UART_MEM_CNT_STATUS_REG ࢤ൳‫ؿބ‬ෂթԥఖ஥ᇂ +ᇏ؎࠷թఖ + +UART_INT_RAW_REG ჰ൓ᇏ؎ሑ෿ 0x3FF6E004 ᆺ‫؀‬ + 0x3FF6E008 ᆺ‫؀‬ +UART_INT_ST_REG ௠зᇏ؎ሑ෿ 0x3FF6E00C ‫؀‬/ཿ + 0x3FF6E010 ᆺཿ +UART_INT_ENA_REG ᇏ؎൐ି໊ + +UART_INT_CLR_REG ᇏ؎ౢԢ໊ + +13.4.2 UHCI ࠷թఖ + +଀ӫ ૭ඍ UDMA0 UDMA1 ٠໙ +஥ᇂ࠷թఖ + +UHCI_CONF0_REG UART ‫ބ‬ඔऌᆠ‫ٳ‬৖஥ᇂ 0x3FF54000 0x3FF4C000 ‫؀‬/ཿ + 0x3FF5402C 0x3FF4C02C ‫؀‬/ཿ +UHCI_CONF1_REG UHCI ஥ᇂ࠷թఖ 0x3FF54064 0x3FF4C064 ‫؀‬/ཿ + 0x3FF54068 0x3FF4C068 ‫؀‬/ཿ +UHCI_ESCAPE_CONF_REG ሇၬሳ‫ژ‬஥ᇂ 0x3FF540B0 0x3FF4C0B0 ‫؀‬/ཿ + 0x3FF540B4 0x3FF4C0B4 ‫؀‬/ཿ +UHCI_HUNG_CONF_REG ӑൈ஥ᇂ࠷թఖ 0x3FF540B8 0x3FF4C0B8 ‫؀‬/ཿ + 0x3FF540BC 0x3FF4C0BC ‫؀‬/ཿ +UHCI_ESC_CONF0_REG ሇၬ྽ਙ஥ᇂ࠷թఖ 0 + +UHCI_ESC_CONF1_REG ሇၬ྽ਙ஥ᇂ࠷թఖ 1 + +*UHCI_ESC_CONF2_REG ሇၬ྽ਙ஥ᇂ࠷թఖ 2 + +UHCI_ESC_CONF3_REG ሇၬ྽ਙ஥ᇂ࠷թఖ 3 +DMA ஥ᇂ࠷թఖ + +UHCI_DMA_OUT_LINK_REG ৽і૭ඍ‫ֹژ‬ᆶა॥ᇅ 0x3FF54024 0x3FF4C024 ‫؀‬/ཿ + 0x3FF54028 0x3FF4C028 ‫؀‬/ཿ +UHCI_DMA_IN_LINK_REG ৽і૭ඍ‫ֹژ‬ᆶა॥ᇅ 0x3FF54018 0x3FF4C018 ‫؀‬/ཿ + 0x3FF54020 0x3FF4C020 ᆺ‫؀‬ +UHCI_DMA_OUT_PUSH_REG FIFO ೆᅜඔऌ࠷թఖ + +UHCI_DMA_IN_POP_REG FIFO ԛᅜඔऌ࠷թఖ +DMA ሑ෿࠷թఖ + +UHCI_DMA_OUT_STATUS_REG DMA FIFO ሑ෿ 0x3FF54014 0x3FF4C014 ᆺ‫؀‬ + 0x3FF54038 0x3FF4C038 ᆺ‫؀‬ +UHCI_DMA_OUT_EOF_DES_ADDR_REG EOF Ⴕིൈ‫ؿ‬ෂ৽і૭ඍ + ‫ֹ֥ژ‬ᆶ + + EOF Бհൈ‫ؿ‬ෂ৽і૭ඍ 0x3FF54044 0x3FF4C044 ᆺ‫؀‬ +UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG + + ‫ֹ֥ژ‬ᆶ + +UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG EOF Ⴕིൈࢤ൬৽і૭ඍ 0x3FF5403C 0x3FF4C03C ᆺ‫؀‬ + ‫ֹ֥ژ‬ᆶ + +ুᶈྐ༏॓࠯ 320 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + +UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG EOF Бհൈࢤ൬৽і૭ඍ 0x3FF54040 0x3FF4C040 ᆺ‫؀‬ + ‫ֹ֥ژ‬ᆶ 0x3FF5404C 0x3FF4C04C ᆺ‫؀‬ +UHCI_DMA_IN_DSCR_REG ֒భࢤ൬৽і૭ඍ‫ֻ֥ژ‬ 0x3FF54050 0x3FF4C050 ᆺ‫؀‬ + ၂۱ሳ 0x3FF54054 0x3FF4C054 ᆺ‫؀‬ +UHCI_DMA_IN_DSCR_BF0_REG ֒భࢤ൬৽і૭ඍ‫ֻ֥ژ‬ 0x3FF54058 0x3FF4C058 ᆺ‫؀‬ + ‫ؽ‬۱ሳ 0x3FF5405C 0x3FF4C05C ᆺ‫؀‬ +UHCI_DMA_IN_DSCR_BF1_REG ֒భࢤ൬৽і૭ඍ‫ֻ֥ژ‬ 0x3FF54060 0x3FF4C060 ᆺ‫؀‬ + ೘۱ሳ +UHCI_DMA_OUT_DSCR_REG ֒భ‫ؿ‬ෂ৽і૭ඍ‫ֻ֥ژ‬ + ၂۱ሳ +UHCI_DMA_OUT_DSCR_BF0_REG ֒భ‫ؿ‬ෂ৽і૭ඍ‫ֻ֥ژ‬ + ‫ؽ‬۱ሳ +UHCI_DMA_OUT_DSCR_BF1_REG ֒భ‫ؿ‬ෂ৽і૭ඍ‫ֻ֥ژ‬ +ᇏ؎࠷թఖ ೘۱ሳ +UHCI_INT_RAW_REG +UHCI_INT_ST_REG ჰ൓ᇏ؎ሑ෿ 0x3FF54004 0x3FF4C004 ᆺ‫؀‬ +UHCI_INT_ENA_REG ௠зᇏ؎ሑ෿ 0x3FF54008 0x3FF4C008 ᆺ‫؀‬ +UHCI_INT_CLR_REG ᇏ؎൐ି໊ 0x3FF5400C 0x3FF4C00C ‫؀‬/ཿ + ᇏ؎ౢԢ໊ 0x3FF54010 0x3FF4C010 ᆺཿ + +ুᶈྐ༏॓࠯ 321 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + +13.5 ࠷թఖ + + Register 13.1. UART_FIFO_REG (0x0) + + (reserved) UART_RXFIFO_RD_BYTE + +31 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UART_RXFIFO_RD_BYTE ٠໙ FIFObč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 322 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.2. UART_INT_RAW_REG (0x4) + + (reserved) UARTU_AATR_TCU_MRASRD4T_U8C_5RAH_SRAC4TRLU8__A5RADS_SREFH4TTR_U8__MI5TANIN_X_RTPT_E_TAD_RUR_RRORTAAAIXN_TRWW_IYENTBU___TREITA_NRKXRRT_R_AT_BIU_D_RWRIGANLAKERLWT_I_T_TDDUR_COSOAAHWNRWN_TEED_U__X_ESIAIONNTWRF_TTTIF___NU__RXRTRIAOANA_XRWNRTWFT__AIU_FRIWNBAOATRR_W_KTTRUO__ACDAUWRTETSTT_U___INICDANTHSRT_RGT_RU_R__ARCAAIWNXRHWTFTG_IU_FR_FAOIANRR_WTMOT_U__VRPAEFAARR_WRIRTNUI__TTTAIYN_XR_RTFETA_IFR_RWORRAX__WEFINIMFTOP__TRFYAU_WILNLT__INRTA_WRAW + +31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UART_AT_CMD_CHAR_DET_INT_RAW UART_AT_CMD_CHAR_DET_INT ᇏ؎֥ ჰ൓ ᇏ؎ ሑ෿ + ໊bčᆺ‫؀‬Ď + + UART_RS485_CLASH_INT_RAW UART_RS485_CLASH_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_RS485_FRM_ERR_INT_RAW UART_RS485_FRM_ERR_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ + + ‫؀‬Ď + UART_RS485_PARITY_ERR_INT_RAW UART_RS485_PARITY_ERR_INT ᇏ ؎ ֥ ჰ ൓ ᇏ ؎ ሑ ෿ + + ໊bčᆺ‫؀‬Ď + UART_TX_DONE_INT_RAW UART_TX_DONE_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_TX_BRK_IDLE_DONE_INT_RAW UART_TX_BRK_IDLE_DONE_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿ + + ໊bčᆺ‫؀‬Ď + UART_TX_BRK_DONE_INT_RAW UART_TX_BRK_DONE_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_GLITCH_DET_INT_RAW UART_GLITCH_DET_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_SW_XOFF_INT_RAW UART_SW_XOFF_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_SW_XON_INT_RAW UART_SW_XON_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_RXFIFO_TOUT_INT_RAW UART_RXFIFO_TOUT_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_BRK_DET_INT_RAW UART_BRK_DET_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_CTS_CHG_INT_RAW UART_CTS_CHG_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_DSR_CHG_INT_RAW UART_DSR_CHG_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_RXFIFO_OVF_INT_RAW UART_RXFIFO_OVF_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_FRM_ERR_INT_RAW UART_FRM_ERR_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_PARITY_ERR_INT_RAW UART_PARITY_ERR_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_TXFIFO_EMPTY_INT_RAW UART_TXFIFO_EMPTY_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_RXFIFO_FULL_INT_RAW UART_RXFIFO_FULL_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 323 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.3. UART_INT_ST_REG (0x8) + + (reserved) UARTU_AATR_TCU_MRASRD4T_U8C_5RAH_SRAC4TRLU8__A5RADS_SREFH4TTR_U8__MI5TANIN_X_RTPT_E_TAD_RUS_SRORTTATIXN_TR_IYENTBU___TREITA_NRKXSRT_R_TT_BIU_D_SRIGANLTKERLT_I_T_TDDUS_COSOATHWNRN_TEED_U__X_ESIAIONNTWRF_TTTIF___NU__SXSTRIAOTNT_XRNSTFT_T_IU_FSINBAOTTRR__KTTSUO__TCDAURTETSTT_U___INICDANTHSRT_RGT_SU_S__TRCATINXRHTFTG_IU_FS_FAOITNRR_TMOT_U__VSPAEFTARR_RIRTNUI__TTTAIYN_XR_STFETT_IFR_SORRTX__EFINIMFTOP__TSFYTU_ILNLT__INSTT_ST + +31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UART_AT_CMD_CHAR_DET_INT_ST UART_AT_CMD_CHAR_DET_INT ᇏ ؎ ֥ ႅ з ᇏ ؎ ሑ ෿ + ໊bčᆺ‫؀‬Ď + + UART_RS485_CLASH_INT_ST UART_RS485_CLASH_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_RS485_FRM_ERR_INT_ST UART_RS485_FRM_ERR_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_RS485_PARITY_ERR_INT_ST UART_RS485_PARITY_ERR_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊čbᆺ + + ‫؀‬Ď + UART_TX_DONE_INT_ST UART_TX_DONE_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_TX_BRK_IDLE_DONE_INT_ST UART_TX_BRK_IDLE_DONE_INT ᇏ ؎ ֥ ႅ з ᇏ ؎ ሑ ෿ + + ໊bčᆺ‫؀‬Ď + UART_TX_BRK_DONE_INT_ST UART_TX_BRK_DONE_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_GLITCH_DET_INT_ST UART_GLITCH_DET_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_SW_XOFF_INT_ST UART_SW_XOFF_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_SW_XON_INT_ST UART_SW_XON_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_RXFIFO_TOUT_INT_ST UART_RXFIFO_TOUT_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_BRK_DET_INT_ST UART_BRK_DET_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_CTS_CHG_INT_ST UART_CTS_CHG_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_DSR_CHG_INT_ST UART_DSR_CHG_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_RXFIFO_OVF_INT_ST UART_RXFIFO_OVF_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_FRM_ERR_INT_ST UART_FRM_ERR_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_PARITY_ERR_INT_ST UART_PARITY_ERR_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_TXFIFO_EMPTY_INT_ST UART_TXFIFO_EMPTY_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UART_RXFIFO_FULL_INT_ST UART_RXFIFO_FULL_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 324 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.4. UART_INT_ENA_REG (0xC) + + (reserved) UARTU_AATR_TCU_MRASRD4T_U8C_5RAH_SRAC4TRLU8__A5RADS_SREFH4TTR_U8__MI5TANIN_X_RTPT_E_TAD_RUE_ERORTNANIXN_TRAA_IYENTBU___TREITA_NRKXERT_R_NT_BIU_D_EARIGANNLKERLAT_I_T_TDDUE_COSONAHWNRAN_TEED_U__X_ESIAIONNTWRF_TTTIF___NU__EXETRIAONNN_XRANETAFT_N_IU_FEIANBAONTRR_A_KTTEUO__NCDAUARTETSTT_U___INICDANTHSRT_RGT_EU_E_N_RCANIANXRHATFTG_IU_FE_FAOINNRR_ATMOT_U__VEPAEFNARR_ARIRTNUI__TTTAIYN_XR_ETFETN_IFR_EAORRNX__AEFINIMFTOP__TEFYNU_AILNLT__INETN_AENA + +31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UART_AT_CMD_CHAR_DET_INT_ENA UART_AT_CMD_CHAR_DET_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_RS485_CLASH_INT_ENA UART_RS485_CLASH_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_RS485_FRM_ERR_INT_ENA UART_RS485_FRM_ERR_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_RS485_PARITY_ERR_INT_ENA UART_RS485_PARITY_ERR_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_TX_DONE_INT_ENA T UART_TX_DONE_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_TX_BRK_IDLE_DONE_INT_ENA UART_TX_BRK_IDLE_DONE_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_TX_BRK_DONE_INT_ENA UART_TX_BRK_DONE_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_GLITCH_DET_INT_ENA UART_GLITCH_DET_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_SW_XOFF_INT_ENA UART_SW_XOFF_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_SW_XON_INT_ENA UART_SW_XON_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_RXFIFO_TOUT_INT_ENA UART_RXFIFO_TOUT_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_BRK_DET_INT_ENA UART_BRK_DET_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_CTS_CHG_INT_ENA UART_CTS_CHG_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_DSR_CHG_INT_ENA UART_DSR_CHG_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_RXFIFO_OVF_INT_ENA UART_RXFIFO_OVF_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_FRM_ERR_INT_ENA UART_FRM_ERR_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_PARITY_ERR_INT_ENA UART_PARITY_ERR_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_TXFIFO_EMPTY_INT_ENA UART_TXFIFO_EMPTY_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UART_RXFIFO_FULL_INT_ENA UART_RXFIFO_FULL_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 325 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.5. UART_INT_CLR_REG (0x10) + + (reserved) UARTU_AATR_TCU_MRASRD4T_U8C_5RAH_SRAC4TRLU8__A5RADS_SREFH4TTR_U8__MI5TANIN_X_RTPT_E_TAD_RUC_CRORTALLIXN_RTRR_IYENTBU___TREITA_NRKXCRT_R_TL_BIU_D_RCRIGANLLKERLRT_I_T_TDDUC_COSOALHWNRRN_TEED_U__X_ESIAIONNTWRF_TTTIF___NU__CXCTRIAONLL_XRRNRCTFT__LIU_FCIRNBAOLTRR_R_KTTCUO__LCDAURRTETSTT_U___INICDANTHSRT_RGT_CU_C__LRCAILRNXRRHTFTG_IU_FC_FAOILNRR_RTMOT_U__VCPAEFLARR_RRIRTNUI__TTTAIYN_XR_CTFETL_IFR_RCORRLX__REFINIMFTOP__TCFYLU_RILNLT__INCTL_RCLR + +31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UART_AT_CMD_CHAR_DET_INT_CLR ᇂ໊ౢԢ UART_AT_CMD_CHAR_DET_INT ᇏ؎bčᆺཿĎ + UART_RS485_CLASH_INT_CLR ᇂ໊ౢԢ UART_RS485_CLASH_INT ᇏ؎bčᆺཿĎ + UART_RS485_FRM_ERR_INT_CLR ᇂ໊ౢԢ UART_RS485_FRM_ERR_INT ᇏ؎bčᆺཿĎ + UART_RS485_PARITY_ERR_INT_CLR ᇂ໊ౢԢ UART_RS485_PARITY_ERR_INT ᇏ؎bčᆺཿĎ + UART_TX_DONE_INT_CLR ᇂ໊ౢԢ UART_TX_DONE_INT ᇏ؎bčᆺཿĎ + UART_TX_BRK_IDLE_DONE_INT_CLR ᇂ໊ౢԢ UART_TX_BRK_IDLE_DONE_INT ᇏ؎bčᆺཿĎ + UART_TX_BRK_DONE_INT_CLR ᇂ໊ౢԢ UART_TX_BRK_DONE_INT ᇏ؎bčᆺཿĎ + UART_GLITCH_DET_INT_CLR ᇂ໊ౢԢ UART_GLITCH_DET_INT ᇏ؎bčᆺཿĎ + UART_SW_XOFF_INT_CLR ᇂ໊ౢԢ UART_SW_XOFF_INT ᇏ؎bčᆺཿĎ + UART_SW_XON_INT_CLR ᇂ໊ౢԢ UART_SW_XON_INT ᇏ؎bčᆺཿĎ + UART_RXFIFO_TOUT_INT_CLR ᇂ໊ౢԢ UART_RXFIFO_TOUT_INT ᇏ؎b‫࠷ھ‬թఖᆺିᄝ rx- + + fifo_cnt ‫ ބ‬rx_mem_cnt ‫ ູ׻‬0 ֥౦ঃ༯Ҍॖၛᇂ໊bčᆺཿĎ + UART_BRK_DET_INT_CLR ᇂ໊ౢԢ UART_BRK_DET_INT ᇏ؎bčᆺཿĎ + UART_CTS_CHG_INT_CLR ᇂ໊ౢԢ UART_CTS_CHG_INT ᇏ؎bčᆺཿĎ + UART_DSR_CHG_INT_CLR ᇂ໊ౢԢ UART_DSR_CHG_INT ᇏ؎bčᆺཿĎ + UART_RXFIFO_OVF_INT_CLR ᇂ໊ౢԢ UART_RXFIFO_OVF_INT ᇏ؎bčᆺཿĎ + UART_FRM_ERR_INT_CLR ᇂ໊ౢԢ UART_FRM_ERR_INT ᇏ؎bčᆺཿĎ + UART_PARITY_ERR_INT_CLR ᇂ໊ౢԢ UART_PARITY_ERR_INT ᇏ؎bčᆺཿĎ + UART_TXFIFO_EMPTY_INT_CLR ᇂ໊ౢԢ UART_TXFIFO_EMPTY_INT ᇏ؎bčᆺཿĎ + UART_RXFIFO_FULL_INT_CLR ᇂ ໊ ౢ Ԣ UART_RXFIFO_FULL_INT ᇏ ؎b ‫ ࠷ ھ‬թ ఖ ᆺ Ⴕ ᄝ + + Rx_FIFO ᇏඔऌ۱ඔཬႿ UART_RXFIFO_FULL_THRHD ֥౦ঃ༯ᇂ໊ҌିളིbčᆺཿĎ + +ুᶈྐ༏॓࠯ 326 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.6. UART_CLKDIV_REG (0x14) + + (reserved) UART_CLKDIV_FRAG UART_CLKDIV + 0x0002B6 +31 24 23 20 19 0 + +00000000 0x00 Reset + + UART_CLKDIV_FRAG ‫ٳ‬௔༢ඔ֥ཬඔ҆‫ٳ‬bč‫؀‬/ཿĎ + UART_CLKDIV ‫ٳ‬௔༢ඔ֥ᆜඔ҆‫ٳ‬bč‫؀‬/ཿĎ + + Register 13.7. UART_AUTOBAUD_REG (0x18) + + (reserved) UART_GLITCH_FILT (reserved) UART_AUTOBAUD_EN + +31 16 15 87 10 + +0000000000000000 0x010 0 0 0 0 0 0 0 0 Reset + + UART_GLITCH_FILT ੲѯ૊ཋᆴđ֒ൻೆઝԊॺ؇ཬႿՎ࠷թఖ֥ᆴൈđઝԊФޭ੻bՎ࠷թఖႨ + Ⴟሱ‫׮‬ѯหੱ࡟ҩ֥‫ݖ‬ӱᇏbč‫؀‬/ཿĎ + + UART_AUTOBAUD_EN ሱ‫׮‬ѯหੱ࡟ҩ֥൐ି໊bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 327 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.8. UART_STATUS_REG (0x1C) + + UARTU_TAXRDTU_RATRST(N_reDsTeRrvNed) UART_ST_UTX_OUT UART_TXFIFO_CNT UARTU_RAXRDTU_CARTST(N_reDsSeRrvNed) UART_ST_URX_OUT UART_RXFIFO_CNT + +31 30 29 28 27 24 23 16 15 14 13 12 11 87 0 + +0x000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +UART_TXD Վ໊іૼଽ҆ UART RxD ྐ‫׈֥ݼ‬௜bčᆺ‫؀‬Ď + +UART_RTSN Վ໊ؓႋଽ҆ UART CTS ྐ‫׈֥ݼ‬௜bčᆺ‫؀‬Ď + +UART_DTRN Վ໊ؓႋଽ҆ UAR DSR ྐ‫׈֥ݼ‬௜bčᆺ‫؀‬Ď + +UART_ST_UTX_OUT Վ࠷թఖթԥ‫ؿ‬ෂఖႵཋሑ෿ࠏ֥ሑ෿b0: TX_IDLEĠ1: TX_STRTĠ2: + TX_DAT0Ġ3: TX_DAT1Ġ4: TX_DAT2Ġ5: TX_DAT3Ġ6: TX_DAT4Ġ7: TX_DAT5Ġ8: TX_DAT6Ġ + 9: TX_DAT7Ġ10: TX_PRTYĠ11: TX_STP1Ġ12: TX_STP2Ġ13: TX_DL0Ġ14: TX_DL1bčᆺ‫؀‬Ď + +UART_TXFIFO_CNT (tx_mem_cnt, txfifo_cnt) թԥ‫ؿ‬ෂ FIFO ᇏ֥Ⴕིඔऌሳࢫඔbtx_mem_cnt թ + ԥ 3 ۱ቋ໊ۚĠtxfifo_cnt թԥ 8 ۱ቋ໊֮bčᆺ‫؀‬Ď + +UART_RXD Վ໊ؓႋଽ҆ UART RxD ྐ‫׈֥ݼ‬௜bčᆺ‫؀‬Ď + +UART_CTSN Վ໊ؓႋଽ҆ UART CTS ྐ‫׈֥ݼ‬௜bčᆺ‫؀‬Ď + +UART_DSRN Վ໊ؓႋଽ҆ UAR DSR ྐ‫׈֥ݼ‬௜bčᆺ‫؀‬Ď + +UART_ST_URX_OUT Վ࠷թఖթԥࢤ൬ఖႵཋሑ෿ࠏ֥ሑ෿b0: RX_IDLEĠ1: RX_STRTĠ2: + RX_DAT0Ġ3: RX_DAT1Ġ4: RX_DAT2Ġ5: RX_DAT3Ġ6: RX_DAT4Ġ7: RX_DAT5Ġ8: RX_DAT6Ġ + 9: RX_DAT7Ġ10: RX_PRTYĠ11: RX_STP1Ġ12: RX_STP2Ġ13: RX_DL1bčᆺ‫؀‬Ď + +UART_RXFIFO_CNT (rx_mem_cnt, rxfifo_cnt) թԥࢤ൬ FIFO ᇏ֥Ⴕིඔऌሳࢫඔbrx_mem_cnt թ + ԥ 3 ۱ቋ໊ۚĠrxfifo_cnt թԥ 8 ۱ቋ໊֮bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 328 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.9. UART_CONF0_REG (0x20) + + (reserved) UART_TI(CreKs_eRrvEeFdU_) AALRWTU_ADAYTRSRT_U__OIRANNTRVSTU__ITANXRVDTU__IDANSRVRTU__CIANRTVSTU__IRANXRVDTU__ITANXRVFTIUF_ORAXR_RFTIUS_FIATORR_DRTAU_S_TATEXRN_TFU_LLAOORWOTU__PEIABRNRADTCAU__KIARRRDXT_AU_I_NIARTVRXDT_AUI_N_IARWVRDCTAUT__ILARTRXDT_AUE__TNADXRPDTLU__XBSARWRKT__DSTUWRA_RRTT_SSTOUPA_BRITT__BNUIUTA_MRNTUU_MPAARRTI_TPYA_REINTY + +31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 21 0 + +0 0 0 010 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 Reset + + UART_TICK_REF_ALWAYS_ON Վ࠷թఖႨႿ࿊ᄴൈᇒb1ğAPB ൈᇒĠ0: REF_TICKbč‫؀‬/ཿĎ + + UART_DTR_INV ᇂّ໊ሇ UART DTR ྐ‫׈֥ݼ‬௜bč‫؀‬/ཿĎ + + UART_RTS_INV ᇂّ໊ሇ UART RTS ྐ‫׈֥ݼ‬௜bč‫؀‬/ཿĎ + + UART_TXD_INV ᇂّ໊ሇ UART TxD ྐ‫׈֥ݼ‬௜bč‫؀‬/ཿĎ + + UART_DSR_INV ᇂّ໊ሇ UART DSR ྐ‫׈֥ݼ‬௜bč‫؀‬/ཿĎ + + UART_CTS_INV ᇂّ໊ሇ UART CTS ྐ‫׈֥ݼ‬௜bč‫؀‬/ཿĎ + + UART_RXD_INV ᇂّ໊ሇ UART Rxd ྐ‫׈֥ݼ‬௜bč‫؀‬/ཿĎ + + UART_TXFIFO_RST ᇂ໊đ‫ ໊گ‬UART ‫ؿ‬ෂ FIFObᇿၩđUART2 ીႵ‫࠷໊گھ‬թఖđ౏ UART1 ֥ + UART1_TXFIFO_RST ‫ ބ‬UART1_RXFIFO_RST ߶႕ཙ UART2 ֥‫۽‬ቔbၹՎđᆺႵᄝ UART2 ֥ + Tx_FIFO ‫ ބ‬Rx_FIFO ᇏીႵඔऌൈđҌॖၛᇂ໊ᆃਆ۱࠷թఖbč‫؀‬/ཿĎ + + UART_RXFIFO_RST ᇂ໊đ‫ ໊گ‬UART ࢤ൬ FIFObᇿၩđUART2 ીႵ‫࠷໊گھ‬թఖđ౏ UART1 ֥ + UART1_TXFIFO_RST ‫ ބ‬UART1_RXFIFO_RST ߶႕ཙ UART2 ֥‫۽‬ቔbၹՎđᆺႵᄝ UART2 ֥ + Tx_FIFO ‫ ބ‬Rx_FIFO ᇏીႵඔऌൈđҌॖၛᇂ໊ᆃਆ۱࠷թఖbč‫؀‬/ཿĎ + + UART_IRDA_EN ᇂ໊൐ି IrDA ླྀၰbč‫؀‬/ཿĎ + + UART_TX_FLOW_EN ᇂ໊൐ି‫ؿ‬ෂఖ֥ੀ॥‫ିۿ‬bč‫؀‬/ཿĎ + + UART_LOOPBACK ᇂ໊൐ି UART ߭ߌҩ൫‫ିۿ‬bč‫؀‬/ཿĎ + + UART_IRDA_RX_INV ᇂّ໊ሇ IrDA ࢤ൬ఖ֥‫׈‬௜bč‫؀‬/ཿĎ + + UART_IRDA_TX_INV ᇂّ໊ሇ IrDA ‫ؿ‬ෂఖ֥‫׈‬௜bč‫؀‬/ཿĎ + + UART_IRDA_WCTL 1ğIrDA ‫ؿ‬ෂఖֻ֥ 11 ໊აֻ 10 ໊ཌྷ๝b0: ഡᇂ IrDA ‫ؿ‬ෂఖֻ֥ 11 ູ໊ + 0bč‫؀‬/ཿĎ + + UART_IRDA_TX_EN IrDA ‫ؿ‬ෂఖ֥ఓ‫׮‬൐ି໊bč‫؀‬/ཿĎ + + UART_IRDA_DPLX ᇂ໊൐ି IrDA ߭ߌଆൔbč‫؀‬/ཿĎ + + UART_TXD_BRK ᇂ໊൐‫ؿ‬ෂఖᄝඔऌ‫ؿ‬ෂປӮު‫ؿ‬ෂ NULLbč‫؀‬/ཿĎ + + UART_SW_DTR ஥ᇂႨႿೈࡱੀ॥֥ೈࡱ DTR ྐ‫ݼ‬bč‫؀‬/ཿĎ + + UART_SW_RTS ႨႿ UART_RX_FLOW_EN ູ 0 ൈ֥႗ࡱੀ॥bᇂ໊ঘ֮ RTS (rtsn_out) ྐ‫ݼ‬đ‫گ‬ + ໊ঘۚྐ‫ݼ‬bč‫؀‬/ཿĎ + + ࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 329 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.9. UART_CONF0_REG (0x20) + + ࠿ഈ၂်࠷թఖ૭ඍb + UART_STOP_BIT_NUM ႨႿഡᇂ๔ᆸ໊֥Ӊ؇b1: 1 bitĠ2: 1.5 bitbč‫؀‬/ཿĎ + UART_BIT_NUM ႨႿഡᇂඔऌ֥Ӊ؇Ġ0: 5 bitĠ1: 6 bitĠ2: 7 bitĠ3: 8 bitbč‫؀‬/ཿĎ + UART_PARITY_EN ᇂ໊൐ି UART అ୽཮ဒbč‫؀‬/ཿĎ + UART_PARITY ஥ᇂఅ୽཮ဒٚൔb0: ୽཮ဒĠ1: అ཮ဒbč‫؀‬/ཿĎ + + Register 13.10. UART_CONF1_REG (0x24) + +UART_RX_TOUT_EN UART_RX_TOUT_THRUHADRT_RX_FLOW_EN UART_RX_FLOW _THRHD UART_TXFIFO_EMPTY(_reTsHeRrvHeDd) UART_RXFIFO_FULL_THRHD + + (reserved) 876 0 + +31 30 24 23 22 16 15 14 + +00 0 0 0 0 0 00 0x00 0 0x60 0 0x60 Reset + +UART_RX_TOUT_EN ᇂ໊൐ି UART ࢤ൬ఖ֥ӑൈ‫ିۿ‬bč‫؀‬/ཿĎ + +UART_RX_TOUT_THRHD ஥ᇂ UART ࢤ൬ఖ֩րࢤ൬֥ӑൈൈࡗbᄝ൐Ⴈ APB_CLK ൈᇒჷൈđ‫ھ‬ + ࠷թఖၛѯหੱᇛ௹֥ 8 Пູ࠹ൈֆ໊Ġᄝ൐Ⴈ REF_TICK ൈᇒჷൈđ‫࠷ھ‬թఖ֥࠹ൈֆູ໊ + UART ѯหੱᇛ௹ * 8 * (REF_TICK ௔ੱ)/(APB_CLK ௔ੱ)bč‫؀‬/ཿĎ + +UART_RX_FLOW_EN ᇂ໊൐ି UART ࢤ൬ఖ֥ੀ॥‫ିۿ‬b1: ஥ᇂ sw_rts ྐ‫ݼ‬࿊ᄴೈࡱੀ॥Ġ0ğ + ܱоೈࡱੀ॥bč‫؀‬/ཿĎ + +UART_RX_FLOW_THRHD ֒ UART_RX_FLOW_EN ູ 1aࢤ൬ FIFO ӑ‫ݖ‬ᚐᆴൈđࢤ൬ఖӁള + rtsn_out ྐ‫ؿුۡݼ‬ෂఖ๔ᆸ‫ؿ‬ෂඔऌbᚐᆴູ (rx_flow_thrhd_h3, rx_flow_thrhd)bč‫؀‬/ཿĎ + +UART_TXFIFO_EMPTY_THRHD ֒ ‫ ؿ‬ෂ FIFO ֥ ඔ ऌ ਈ ഒ Ⴟ ᚐ ᆴ ൈđ ߶ Ӂ ള TX- + FIFO_EMPTY_INT_RAW ᇏ؎bᚐᆴູ (tx_mem_empty_thrhd, txfifo_empty_thrhd)bč‫؀‬/ཿĎ + +UART_RXFIFO_FULL_THRHD ֒ ࢤ ൬ ఖ ࢤ ൬ ֞ б ᚐ ᆴ ‫ ֥ ؟‬ඔ ऌ ൈđ ࢤ ൬ ఖ Ӂ ള RX- + FIFO_FULL_INT_RAW ᇏ؎bᚐᆴູ (rx_flow_thrhd_h3, rxfifo_full_thrhd)bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 330 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.11. UART_LOWPULSE_REG (0x28) + + (reserved) UART_LOWPULSE_MIN_CNT + 0x0FFFFF +31 20 19 0 + +000000000000 Reset + + UART_LOWPULSE_MIN_CNT Վ࠷թఖթԥቋཬ֮‫׈‬௜ઝԊॺ؇đႨႿѯหੱሱ࡟‫ݖ‬ӱbčᆺ‫؀‬Ď + + Register 13.12. UART_HIGHPULSE_REG (0x2C) + + (reserved) UART_HIGHPULSE_MIN_CNT + 0x0FFFFF +31 20 19 0 + +000000000000 Reset + + UART_HIGHPULSE_MIN_CNT Վ࠷թఖթԥቋཬۚ‫׈‬௜ઝԊॺ؇ᆴđႨႿѯหੱሱ࡟‫ݖ‬ӱbčᆺ + ‫؀‬Ď + + Register 13.13. UART_RXD_CNT_REG (0x30) + + (reserved) UART_RXD_EDGE_CNT + +31 10 9 0 + +0000000000000000000000 0x000 Reset + + UART_RXD_EDGE_CNT Վ࠷թఖթԥ RxD ခэ߄֥ՑඔđႨႿѯหੱሱ࡟‫ݖ‬ӱbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 331 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.14. UART_FLOW_CONF_REG (0x34) + + (reserved) UARTU_SAERNTUD_SA_EXRNOTUD_FFAF_OXRORTU_CNFAEOR_RXTUO_CXAFEORF_XNTO_OSNFWF__DFLEOL W_CON_EN + +31 65 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UART_SEND_XOFF ႗ࡱሱౢ 0đᇂ໊‫ؿ‬ෂ Xoff ሳ‫ژ‬bč‫؀‬/ཿĎ + UART_SEND_XON ႗ࡱሱౢ 0đᇂ໊‫ؿ‬ෂ Xon ሳ‫ژ‬bč‫؀‬/ཿĎ + UART_FORCE_XOFF ᇂ໊ഡᇂ CTSn ቅᆸ‫ؿ‬ෂఖ‫ؿ‬ෂඔऌbč‫؀‬/ཿĎ + UART_FORCE_XON ᇂ໊ౢԢ CTSn ൐ି‫ؿ‬ෂఖ࠿࿃‫ؿ‬ෂඔऌbč‫؀‬/ཿĎ + UART_XONOFF_DEL ᇂ໊၍Ԣࢤ൬֥֞ඔऌᇏ֥ੀ॥ሳ‫ژ‬bč‫؀‬/ཿĎ + UART_SW_FLOW_CON_EN ᇂ໊൐ିೈࡱੀ॥đა sw_xon ࠇ sw_xoff ࠷թఖ၂ఏ൐Ⴈbč‫؀‬/ཿĎ + + Register 13.15. UART_SLEEP_CONF_REG (0x38) + + (reserved) UART_ACTIVE_THRESHOLD + +31 10 9 0 + +0000000000000000000000 0x0F0 Reset + + UART_ACTIVE_THRESHOLD ֒ ൻ ೆ RxD ခэ߄֥ՑඔնႿ֩Ⴟ + + (UART_ACTIVE_THRESHOLD+2) ൈđ༢๤Ֆ Light-sleep ᇏྜটbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 332 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.16. UART_SWFC_CONF_REG (0x3C) + + UART_XOFF_CHAR UART_XON_CHAR UART_XOFF_THRESHOLD UART_XON_THRESHOLD + +31 24 23 16 15 87 0 + + 0x013 0x011 0x0E0 0x000 Reset + + UART_XOFF_CHAR թԥ Xoff ੀ॥ሳ‫ژ‬bč‫؀‬/ཿĎ + + UART_XON_CHAR թԥ Xon ੀ॥ሳ‫ژ‬bč‫؀‬/ཿĎ + + UART_XOFF_THRESHOLD ֒ࢤ൬ FIFO ᇏ֥ඔऌਈ‫؟‬Ⴟ஥ᇂᆴൈđ߶‫ؿ‬ෂ၂۱ Xoff ሳ‫ژ‬đླေ + UART_SW_FLOW_CON_EN ᇂູ 1bč‫؀‬/ཿĎ + + UART_XON_THRESHOLD ֒ࢤ൬ FIFO ᇏ֥ඔऌਈഒႿ஥ᇂᆴൈđ߶‫ؿ‬ෂ၂۱ Xon ሳ‫ژ‬đླေ + UART_SW_FLOW_CON_EN ᇂູ 1bč‫؀‬/ཿĎ + + Register 13.17. UART_IDLE_CONF_REG (0x40) + + (reserved) UART_TX_BRK_NUM UART_TX_IDLE_NUM UART_RX_IDLE_THRHD + +31 28 27 20 19 10 9 0 + +0000 0x00A 0x100 0x100 Reset + + UART_TX_BRK_NUM ႨႿᄝ‫ؿ‬ෂඔऌࢲඏު஥ᇂ‫ؿ‬ෂ֥ 0 ֥ඔਈđ֒ txd_brk ᇂູ 1 ൈ‫۽‬ + ቔbč‫؀‬/ཿĎ + + UART_TX_IDLE_NUM ႨႿ஥ᇂඔऌԮൻ֥ࡗ‫ۯ‬bč‫؀‬/ཿĎ + UART_RX_IDLE_THRHD ֒ࢤ൬ఖ֩ր֥ൈࡗնႿ஥ᇂᆴൈđ߶Ӂളᆠࢲඏྐ‫ݼ‬bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 333 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.18. UART_RS485_CONF_REG (0x44) + + (reserved) UART_RS485_UTAXR_TDU_LRAYSR_N4TU8_U5RAM_SRR4TXU8__5RADRSRLX4TYBU8__5DYANT_LRUXT1TM_X_U_R_EDAEXNLRN_0TE__NERNS485_EN + +31 10 9 65 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UART_RS485_TX_DLY_NUM ႨႿ࿼Ӿ‫ؿ‬ෂఖଽ҆ඔऌྐ‫ݼ‬bč‫؀‬/ཿĎ + UART_RS485_RX_DLY_NUM ႨႿ࿼Ӿࢤ൬ఖଽ҆ඔऌྐ‫ݼ‬bč‫؀‬/ཿĎ + UART_RS485RXBY_TX_EN 1: ֒ RS-485 ࢤ൬ఖཌਫ਼َફൈ RS-485 ‫ؿ‬ෂఖି‫ؿܔ‬ෂඔऌb0: ֒ + + ࢤ൬ఖَફൈ RS-485 ‫ؿ‬ෂఖ҂‫ؿ‬ෂඔऌbč‫؀‬/ཿĎ + UART_RS485TX_RX_EN ᇂ໊൐ି‫ؿ‬ෂఖൻԛྐ‫ࢤ֞ߌ߭ݼ‬൬ఖൻೆྐ‫ݼ‬bč‫؀‬/ཿĎ + UART_DL1_EN ᇂ໊࿼Ӿ๔ᆸ໊ 1 bitbč‫؀‬/ཿĎ + UART_DL0_EN ᇂ໊ᆭުđᄝ DL1 ᆭު࿼Ӿ 1 bit ๔ᆸ໊bč‫؀‬/ཿĎ + UART_RS485_EN ᇂ໊࿊ᄴ RS-485 ଆൔbč‫؀‬/ཿĎ + + Register 13.19. UART_AT_CMD_PRECNT_REG (0x48) + + (reserved) UART_PRE_IDLE_NUM + 0x0186A00 +31 24 23 0 + +00000000 Reset + + UART_PRE_IDLE_NUM ႨႿ஥ᇂࢤ൬ఖࢤ൬ֻ֞၂۱ at_cmd భ֥ॢ༽ൈࡗb֒ॢ༽ൈࡗഒႿ஥ + ᇂᆴൈđࢤ൬ఖ҂߶ࡼࢤ൬֥֞༯၂۱ඔऌ֒ቔ at_cmd ሳ‫ژ‬bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 334 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.20. UART_AT_CMD_POSTCNT_REG (0x4c) + + (reserved) UART_POST_IDLE_NUM + 0x0186A00 +31 24 23 0 + +00000000 Reset + + UART_POST_IDLE_NUM ႨႿ஥ᇂቋު၂۱ at_cmd ‫ބ‬༯၂۱ඔऌᆭࡗ֥ࡗ‫ۯ‬ൈࡗb֒ࡗ‫ۯ‬ൈࡗ + ഒႿ஥ᇂᆴൈđ҂߶ࡼభ၂۱ඔऌ֒ቓ at_cmd ሳ‫ژ‬bč‫؀‬/ཿĎ + + Register 13.21. UART_AT_CMD_GAPTOUT_REG (0x50) + + (reserved) UART_RX_GAP_TOUT + 0x0001E00 +31 24 23 0 + +00000000 Reset + + UART_RX_GAP_TOUT ႨႿ஥ᇂ at_cmd ሳ‫ژ‬ᆭࡗ֥ࡗ‫ۯ‬ൈࡗb֒ࡗ‫ۯ‬ൈࡗնႿ஥ᇂᆴൈđ҂߶ࡼ + ඔऌ֒ቓ৵࿃֥ at_cmd ሳ‫ژ‬đ౏‫࠷ھ‬թఖ֥஥ᇂᆴᇀഒေնႿ‫ٳؽ‬ᆭ၂ѯหੱbč‫؀‬/ཿĎ + + Register 13.22. UART_AT_CMD_CHAR_REG (0x54) + + (reserved) UART_CHAR_NUM UART_AT_CMD_CHAR + +31 16 15 87 0 + +0000000000000000 0x003 0x02B Reset + + UART_CHAR_NUM ႨႿ஥ᇂࢤ൬ఖࢤ൬֥֞৵࿃ at_cmd ሳ‫֥ژ‬ඔਈbč‫؀‬/ཿĎ + UART_AT_CMD_CHAR ႨႿ஥ᇂ at_cmd ሳ‫֥ژ‬ଽಸbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 335 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.23. UART_MEM_CONF_REG (0x58) + +(reserved) UART_TX_MEM_UEAMRPTT_YR_XT_HMREHUMDA_RFTU_LXLO_TFHUF_RATRHHTDR_EXSOHNO_TLUHDAR_RHETS2_HROXL_DT_OHU2TU_TAHRRTH_RDX__HF3LOW_T(HreRsHerDv_eHd)3 UART_TX_SIZE UART_RX_SIZE (reservedU) ART_MEM_PD + +31 30 28 27 25 24 23 22 21 20 18 17 15 14 11 10 76 32 10 + +0 0x0 0x0 0x0 0x0 0x0 0x0 0 0 0 0 0x01 0x01 0 0 0 Reset + + UART_TX_MEM_EMPTY_THRHD ҕॉ TXFIFO_EMPTY_THRHD ֥૭ඍbč‫؀‬/ཿĎ + UART_RX_MEM_FULL_THRHD ҕॉ RXFIFO_FULL_THRHD ֥૭ඍbč‫؀‬/ཿĎ + UART_XOFF_THRESHOLD_H2 ҕॉ UART_XOFF_THRESHOLD ֥૭ඍbč‫؀‬/ཿĎ + UART_XON_THRESHOLD_H2 ҕॉ UART_XON_THRESHOLD ֥૭ඍbč‫؀‬/ཿĎ + UART_RX_TOUT_THRHD_H3 ҕॉ RX_TOUT_THRHD ֥૭ඍbč‫؀‬/ཿĎ + UART_RX_FLOW_THRHD_H3 ҕॉ RX_FLOW_THRHD ֥૭ඍbč‫؀‬/ཿĎ + UART_TX_SIZE ႨႿ஥ᇂ‫ٳ‬஥۳‫ؿ‬ෂ FIFO ֥ RAM ॢࡗđଏಪູ 128 bytebč‫؀‬/ཿĎ + UART_RX_SIZE ႨႿ஥ᇂ‫ٳ‬஥۳ࢤ൬ FIFO ֥ RAM ॢࡗđଏಪູ 128 bytebč‫؀‬/ཿĎ + UART_MEM_PD ᇂ໊ܱо RAMđ֒ 3 ۱ UART ॥ᇅఖ֥ reg_mem_pd ‫׻‬ᇂູ 1 ൈđRAM ࣉೆ֮ + + ‫ݻۿ‬ଆൔbč‫؀‬/ཿĎ + + Register 13.24. UART_MEM_CNT_STATUS_REG (0x64) + + (reserved) UART_TX_MEM_UCANRTT_RX_MEM_CNT + +31 65 32 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 Reset + + UART_TX_MEM_CNT ҕॉ TXFIFO_CNT ֥૭ඍbčᆺ‫؀‬Ď + UART_RX_MEM_CNT ҕॉ RXFIFO_CNT ֥૭ඍbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 336 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.25. UART_POSPULSE_REG (0x68) + + (reserved) UART_POSEDGE_MIN_CNT + 0x0FFFFF +31 20 19 0 + +000000000000 Reset + + UART_POSEDGE_MIN_CNT թԥ RxD ഈശခ֥ခэ߄ՑඔđႨႿѯหੱሱ࡟֥‫ݖ‬ӱbčᆺ‫؀‬Ď + + Register 13.26. UART_NEGPULSE_REG (0x6c) + + (reserved) UART_NEGEDGE_MIN_CNT + 0x0FFFFF +31 20 19 0 + +000000000000 Reset + + UART_NEGEDGE_MIN_CNT թԥ RxD ༯ࢆခ֥ခэ߄ՑඔđႨႿѯหੱሱ࡟֥‫ݖ‬ӱbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 337 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.27. UHCI_CONF0_REG (0x0) + + (reserved) UHCI_UEHNCCI_OULHDEECN_I__UCEUHROACCFRI___TUEEC_HNNIRDCCLI_UE_HR_HEEECAOCID_F_S_E_EEENPNNER_(rEeNserved) UHCI_UUHACRI_TUU2H_ACCRIE_TU1_ACRET0_CE (reserved) + +31 22 21 20 19 18 17 16 15 12 11 10 9 8 0 + +0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_ENCODE_CRC_EN Ќ਽b౨Ԛ൓߄ູ 0bč‫؀‬/ཿĎ + UHCI_LEN_EOF_EN Ќ਽b౨Ԛ൓߄ູ 0bč‫؀‬/ཿĎ + UHCI_UART_IDLE_EOF_EN Ќ਽b౨Ԛ൓߄ູ 0bč‫؀‬/ཿĎ + UHCI_CRC_REC_EN Ќ਽b౨Ԛ൓߄ູ 0bč‫؀‬/ཿĎ + UHCI_HEAD_EN Ќ਽b౨Ԛ൓߄ູ 0bč‫؀‬/ཿĎ + UHCI_SEPER_EN ᇂ໊൐Ⴈห൹ሳ‫ژ‬ট‫ٳ‬৖ඔऌᆠbč‫؀‬/ཿĎ + UHCI_UART2_CE ᇂ໊൐Ⴈ UART2 ‫ؿ‬ෂࠇࢤ൬ඔऌbč‫؀‬/ཿĎ + UHCI_UART1_CE ᇂ໊൐Ⴈ UART1 ‫ؿ‬ෂࠇࢤ൬ඔऌbč‫؀‬/ཿĎ + UHCI_UART0_CE ᇂ໊൐Ⴈ UART ‫ؿ‬ෂࠇࢤ൬ඔऌbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 338 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.28. UHCI_INT_RAW_REG (0x4) + + (reserved) UHCI_UOHUCTI__UOTHOUCTTIA_LUILINHN__CKED_OI_USEFOHCO_UCRIFNT__I_T_UEEID_NRHMRS_RCPACD_ITW_URISNYOH_C_TUECRI_NRTR_I_T_UREAOE_H_RWROUICRNAFT_ITW___UI_NIIDNNHRTOT_CA_E_NWIR_RRUEAIANRH_WWI__CNESIT_OUU_INHCFR__C_AIDENWI_UOOTTH_FNXR_CE_IAHNI__UWIUTRNH_NXTCR__GAIHR__UWTAUIHNXWNCT_G_SI_R_TRIAANXRWT_T_S_RTIAANRWT_TR_IANWT_RAW + +31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_OUT_TOTAL_EOF_INT_RAW UHCI_OUT_TOTAL_EOF_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_OUTLINK_EOF_ERR_INT_RAW UHCI_OUTLINK_EOF_ERR_INT ᇏ ؎ ֥ ჰ ൓ ᇏ ؎ ሑ ෿ + + ໊bčᆺ‫؀‬Ď + UHCI_IN_DSCR_EMPTY_INT_RAW UHCI_IN_DSCR_EMPTY_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_OUT_DSCR_ERR_INT_RAW UHCI_OUT_DSCR_ERR_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_IN_DSCR_ERR_INT_RAW UHCI_IN_DSCR_ERR_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_OUT_EOF_INT_RAW UHCI_OUT_EOF_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_OUT_DONE_INT_RAW UHCI_OUT_DONE_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_IN_ERR_EOF_INT_RAW UHCI_IN_ERR_EOF_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_IN_SUC_EOF_INT_RAW UHCI_IN_SUC_EOF_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_IN_DONE_INT_RAW UHCI_IN_DONE_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_TX_HUNG_INT_RAW UHCI_TX_HUNG_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_RX_HUNG_INT_RAW UHCI_RX_HUNG_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_TX_START_INT_RAW UHCI_TX_START_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_RX_START_INT_RAW UHCI_RX_START_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 339 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.29. UHCI_INT_ST_REG (0x8) + + (reserved) UHCI_UDHMCAI_U_SIHNECFNIIFD_USO_HEA_CNF_IURD_UOLE_HLGSUC___TWIRQ__UOETM_HOGIUN_CT_TITNIAQ_LU_TILI_NSHN__ITN_SCKEDTT_OI_USE_FOSHCO_UTCRIFNT__I_T_UEEID_NRHMSS_RCPTCD_IT_URISNYOH_C_TUECRI_NRTS_I_T_URETOE_H_RSOUICRNTFT_IT___UI_NIIDNNHSTOT_TC_E_NIS_SRUETITNRH_I__CNESIT_OUU_INHCFS__C_TIDENI_UOOTTH_FNXS_CE_ITHNI__UIUTRNH_NXTCS__GTIHS__UTTUIHNXNCT_G_SI_S_TRITANXRT_T_S_STITANRT_TS_ITNT_ST + +31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_SEND_A_REG_Q_INT_ST UHCI_SEND_A_REG_Q_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_SEND_S_REG_Q_INT_ST UHCI_SEND_S_REG_Q_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_OUT_TOTAL_EOF_INT_ST UHCI_OUT_TOTAL_EOF_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_OUTLINK_EOF_ERR_INT_ST UHCI_OUTLINK_EOF_ERR_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ + + ‫؀‬Ď + UHCI_IN_DSCR_EMPTY_INT_ST UHCI_IN_DSCR_EMPTY_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_OUT_DSCR_ERR_INT_ST UHCI_OUT_DSCR_ERR_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_IN_DSCR_ERR_INT_ST UHCI_IN_DSCR_ERR_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_OUT_EOF_INT_ST UHCI_OUT_EOF_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_OUT_DONE_INT_ST UHCI_OUT_DONE_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_IN_ERR_EOF_INT_ST UHCI_IN_ERR_EOF_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_IN_SUC_EOF_INT_ST UHCI_IN_SUC_EOF_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_IN_DONE_INT_ST UHCI_IN_DONE_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_TX_HUNG_INT_ST UHCI_TX_HUNG_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_RX_HUNG_INT_ST UHCI_RX_HUNG_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_TX_START_INT_ST UHCI_TX_START_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + UHCI_RX_START_INT_ST UHCI_RX_START_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 340 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.30. UHCI_INT_ENA_REG (0xC) + + (reserved) UHCI_UDHMCAI_U_SIHNECFNIIFD_USO_HEA_CNF_IURD_UOLE_HLGSUC___TWIRQ__UOETM_HOGIUN_CT_TITNIAQ_LU_TILI_NEHN__INN_ECKEDANT_OI_USE_AFOEHCO_UNCRIFNTA__I_T_UEEID_NRHMES_RCNPCD_ITA_URISNYOH_C_TUECRI_NRTE_I_T_URENOE_H_RAEOUICRNNFT_ITA___UI_NIIDNNHETOT_NC_E_NAIE_ERUENINNRH_AAI__CNESIT_OUU_INHCFE__NC_IDENAI_UOOTTH_FNXE_CE_INHNI__UAIUTRNH_NXTCE__GNIHE__UANTUIHNXANCT_G_SI_E_TRINANXRAT_T_S_ETINANRAT_TE_INNAT_ENA + +31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_SEND_A_REG_Q_INT_ENA UHCI_SEND_A_REG_Q_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_SEND_S_REG_Q_INT_ENA UHCI_SEND_S_REG_Q_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_OUT_TOTAL_EOF_INT_ENA UHCI_OUT_TOTAL_EOF_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_OUTLINK_EOF_ERR_INT_ENA UHCI_OUTLINK_EOF_ERR_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_IN_DSCR_EMPTY_INT_ENA UHCI_IN_DSCR_EMPTY_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_OUT_DSCR_ERR_INT_ENA UHCI_OUT_DSCR_ERR_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_IN_DSCR_ERR_INT_ENA UHCI_IN_DSCR_ERR_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_OUT_EOF_INT_ENA UHCI_OUT_EOF_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_OUT_DONE_INT_ENA UHCI_OUT_DONE_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_IN_ERR_EOF_INT_ENA UHCI_IN_ERR_EOF_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_IN_SUC_EOF_INT_ENA UHCI_IN_SUC_EOF_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_IN_DONE_INT_ENA UHCI_IN_DONE_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_TX_HUNG_INT_ENA UHCI_TX_HUNG_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_RX_HUNG_INT_ENA UHCI_RX_HUNG_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_TX_START_INT_ENA UHCI_TX_START_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + UHCI_RX_START_INT_ENA UHCI_RX_START_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 341 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.31. UHCI_INT_CLR_REG (0x10) + + (reserved) UHCI_UDHMCAI_U_SIHNECFNIIFD_USO_HEA_CNF_IURD_UOLE_HLGSUC___TWIRQ__UOETM_HOGIUN_CT_TITNIAQ_LU_TILI_NCHN__IN_LCCKEDRT_OLI_USE_RFOCHCO_ULCRIFNTR__I_T_UEEID_NRHMCS_RCPLCD_ITR_URISNYOH_C_TUECRI_NRTC_I_T_URELOE_H_RRCOUICRNLFT_ITR___UI_NIIDNNHCTOT_CL_E_NRIC_CRUEILNLRH_RRI__CNESIT_OUU_INHCFC__C_LIDENRI_UOOTTH_FNXC_CE_ILHNI__URIUTRNH_NXTCC__GILHC__URTULIHNXRNCT_G_SI_C_TRIALNXRRT_T_S_CTIANLRRT_TC_ILNRT_CLR + +31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_SEND_A_REG_Q_INT_CLR ᇂ໊ౢԢ UHCI_SEND_A_REG_Q_INT ᇏ؎bčᆺཿĎ + UHCI_SEND_S_REG_Q_INT_CLR ᇂ໊ౢԢ UHCI_SEND_S_REG_Q_INT ᇏ؎bčᆺཿĎ + UHCI_OUT_TOTAL_EOF_INT_CLR ᇂ໊ౢԢ UHCI_OUT_TOTAL_EOF_INT ᇏ؎bčᆺཿĎ + UHCI_OUTLINK_EOF_ERR_INT_CLR ᇂ໊ౢԢ UHCI_OUTLINK_EOF_ERR_INT ᇏ؎bčᆺཿĎ + UHCI_IN_DSCR_EMPTY_INT_CLR ᇂ໊ౢԢ UHCI_IN_DSCR_EMPTY_INT ᇏ؎bčᆺཿĎ + UHCI_OUT_DSCR_ERR_INT_CLR ᇂ໊ౢԢ UHCI_OUT_DSCR_ERR_INT ᇏ؎bčᆺཿĎ + UHCI_IN_DSCR_ERR_INT_CLR ᇂ໊ౢԢ UHCI_IN_DSCR_ERR_INT ᇏ؎bčᆺཿĎ + UHCI_OUT_EOF_INT_CLR ᇂ໊ౢԢ UHCI_OUT_EOF_INT ᇏ؎bčᆺཿĎ + UHCI_OUT_DONE_INT_CLR ᇂ໊ౢԢ UHCI_OUT_DONE_INT ᇏ؎bčᆺཿĎ + UHCI_IN_ERR_EOF_INT_CLR ᇂ໊ౢԢ UHCI_IN_ERR_EOF_INT ᇏ؎bčᆺཿĎ + UHCI_IN_SUC_EOF_INT_CLR ᇂ໊ౢԢ UHCI_IN_SUC_EOF_INT ᇏ؎bčᆺཿĎ + UHCI_IN_DONE_INT_CLR ᇂ໊ౢԢ UHCI_IN_DONE_INT ᇏ؎bčᆺཿĎ + UHCI_TX_HUNG_INT_CLR ᇂ໊ౢԢ UHCI_TX_HUNG_INT ᇏ؎bčᆺཿĎ + UHCI_RX_HUNG_INT_CLR ᇂ໊ౢԢ UHCI_RX_HUNG_INT ᇏ؎bčᆺཿĎ + UHCI_TX_START_INT_CLR ᇂ໊ౢԢ UHCI_TX_START_INT ᇏ؎bčᆺཿĎ + UHCI_RX_START_INT_CLR ᇂ໊ౢԢ UHCI_RX_START_INT ᇏ؎bčᆺཿĎ + +ুᶈྐ༏॓࠯ 342 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.32. UHCI_DMA_OUT_STATUS_REG (0x14) + + (reserved) UHCI_UOHUCTI__OEMUTP_TFYULL + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset + + UHCI_OUT_EMPTY 1: DMA ࢤ൬৽і૭ඍ‫ ֥ژ‬FIFO ູॢbčᆺ‫؀‬Ď + UHCI_OUT_FULL 1: DMA ‫ؿ‬ෂ৽і૭ඍ‫ ֥ژ‬FIFO ൞ડ֥bčᆺ‫؀‬Ď + + Register 13.33. UHCI_DMA_OUT_PUSH_REG (0x18) + + (reserved) UHCI_OUTFIFO_PUSH(reserved) UHCI_OUTFIFO_WDATA + +31 17 16 15 98 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0x000 Reset + + UHCI_OUTFIFO_PUSH ᇂ໊ࡼඔऌ๷ೆ DMA FIFObč‫؀‬/ཿĎ + UHCI_OUTFIFO_WDATA ླေФ๷ೆ DMA FIFO ֥ᆴbč‫؀‬/ཿĎ + + Register 13.34. UHCI_DMA_IN_POP_REG (0x20) + + (reserved) UHCI_INFIFO_(PreOsePrved) UHCI_INFIFO_RDATA + 0x0000 +31 17 16 15 12 11 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 Reset + + UHCI_INFIFO_POP ᇂ໊ࡼඔऌՖ DMA FIFO ᇏ֐ԛbč‫؀‬/ཿĎ + UHCI_INFIFO_RDATA թԥ DMA FIFO ᇏ֐ԛ֥ඔऌbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 343 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.35. UHCI_DMA_OUT_LINK_REG (0x24) + + UHCI_UOHUCTI_LUOIHNUCKT_I_LUPOIAHNURCKTK_I_LROINEUSKTT_LASINRTATKR_TSTOP (reserved) 20 19 UHCI_OUTLINK_ADDR 0 + 0x000000 +31 30 29 28 27 Reset + +0 0 0 00 0 0 0 0 0 0 0 + +UHCI_OUTLINK_PARK 1ğ‫ؿ‬ෂ৽і૭ඍ‫ ֥ژ‬FSM ԩႿॢ༽ሑ෿Ġ0: ‫ؿ‬ෂ৽і૭ඍ‫ ֥ژ‬FSM ԩ + Ⴟ‫۽‬ቔሑ෿bčᆺ‫؀‬Ď + +UHCI_OUTLINK_RESTART ᇂ໊ࡼ‫ؿ‬ෂ৽і૭ඍ‫ژ‬Ֆഈ၂Ց๔ᆸֹ֥ٚᇗྍఓ‫׮‬bč‫؀‬/ཿĎ +UHCI_OUTLINK_START ᇂ໊ఓ‫ؿ֥ྍ׮‬ෂ৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ +UHCI_OUTLINK_STOP ᇂ໊๔ᆸԩ৘‫ؿ‬ෂ৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ +UHCI_OUTLINK_ADDR թԥֻ၂۱‫ؿ‬ෂ৽і૭ඍ‫ ֥֮ژ‬20 ֹ໊ᆶbč‫؀‬/ཿĎ + + Register 13.36. UHCI_DMA_IN_LINK_REG (0x28) + + UHCI_UINHLCINI_UKINH_LCPIANI_URKINHK_LCRINIE_SKINT_LASINRTATKR_TSTOP (reserved) UHCI_INLINK_ADDR + 0x000000 +31 30 29 28 27 20 19 0 + +0 0 0 00 0 0 0 0 0 0 0 Reset + +UHCI_INLINK_PARK 1: ࢤ൬৽і૭ඍ‫ ֥ژ‬FSM ԩႿॢ༽ሑ෿Ġ0: ࢤ൬৽і૭ඍ‫ ֥ژ‬FSM ԩႿ‫۽‬ + ቔሑ෿bčᆺ‫؀‬Ď + +UHCI_INLINK_RESTART ᇂ໊ᇗఓྍ֥ࢤ൬৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ +UHCI_INLINK_START ᇂ໊ष൓ԩ৘ࢤ൬৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ +UHCI_INLINK_STOP ᇂ໊๔ᆸԩ৘ࢤ൬৽і૭ඍ‫ژ‬bč‫؀‬/ཿĎ +UHCI_INLINK_ADDR թԥֻ၂۱ࢤ൬৽і૭ඍ‫ ֥֮ژ‬20 ֹ໊ᆶbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 344 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.37. UHCI_CONF1_REG (0x2C) + + (reserved) UHCI_UTHXC_AI_CTKX(r__eCNsHeUrEMvCe_dKRU)_EHSCUI_MUCH_HRCEEI_CCKH_ESCEQK__SENUM_EN + +31 65 43 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 Reset + + UHCI_TX_ACK_NUM_RE Ќ਽b౨Ԛ൓߄ູ 0bč‫؀‬/ཿĎ + UHCI_TX_CHECK_SUM_RE Ќ਽b౨Ԛ൓߄ູ 0bč‫؀‬/ཿĎ + UHCI_CHECK_SEQ_EN Ќ਽b౨Ԛ൓߄ູ 0bč‫؀‬/ཿĎ + UHCI_CHECK_SUM_EN Ќ਽b౨Ԛ൓߄ູ 0bč‫؀‬/ཿĎ + + Register 13.38. UHCI_DMA_OUT_EOF_DES_ADDR_REG (0x38) + +31 0 + + 0x000000000 Reset + + UHCI_DMA_OUT_EOF_DES_ADDR_REG թԥ֒‫ؿ‬ෂ৽і૭ඍ‫ ֥ژ‬EOF ູ໊ 1 ൈֹ֥ᆶbčᆺ‫؀‬Ď + + Register 13.39. UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG (0x3C) + +31 0 + + 0x000000000 Reset + + UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG թԥ֒ࢤ൬৽і૭ඍ‫ ֥ژ‬EOF ູ໊ 1 ൈֹ֥ᆶbčᆺ + ‫؀‬Ď + + Register 13.40. UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG (0x40) + +31 0 + + 0x000000000 Reset + + UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG թԥ֒ࢤ൬৽і૭ඍ‫ژ‬ᇏႵհ༂ൈֹ֥ᆶbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 345 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.41. UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG (0x44) + +31 0 + + 0x000000000 Reset + + UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG թԥ֒‫ؿ‬ෂ৽і૭ඍ‫ژ‬ᇏႵհ༂ൈֹ֥ᆶbčᆺ‫؀‬Ď + + Register 13.42. UHCI_DMA_IN_DSCR_REG (0x4C) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_DMA_IN_DSCR_REG ֒భࢤ൬৽і૭ඍ‫ֹ֥ژ‬ᆶbčᆺ‫؀‬Ď + + Register 13.43. UHCI_DMA_IN_DSCR_BF0_REG (0x50) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_DMA_IN_DSCR_BF0_REG ֒భࢤ൬৽і૭ඍ‫֥ژ‬భ૫ֻ 1 ۱ֹ֥ᆶbčᆺ‫؀‬Ď + + Register 13.44. UHCI_DMA_IN_DSCR_BF1_REG (0x54) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_DMA_IN_DSCR_BF1_REG ֒భࢤ൬৽і૭ඍ‫֥ژ‬భ૫ֻ 2 ۱ֹ֥ᆶbčᆺ‫؀‬Ď + + Register 13.45. UHCI_DMA_OUT_DSCR_REG (0x58) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_DMA_OUT_DSCR_REG ֒భ‫ؿ‬ෂ৽і૭ඍ‫ֹ֥ژ‬ᆶbčᆺ‫؀‬Ď + + Register 13.46. UHCI_DMA_OUT_DSCR_BF0_REG (0x5C) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_DMA_OUT_DSCR_BF0_REG ֒భ‫ؿ‬ෂ৽і૭ඍ‫֥ژ‬భ૫ֻ 1 ۱ֹ֥ᆶbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 346 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.47. UHCI_DMA_OUT_DSCR_BF1_REG (0x60) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + UHCI_DMA_OUT_DSCR_BF1_REG ֒భ‫ؿ‬ෂ৽і૭ඍ‫֥ژ‬భ૫ֻ 2 ۱ֹ֥ᆶbčᆺ‫؀‬Ď + + Register 13.48. UHCI_ESCAPE_CONF_REG (0x64) + + (reserved) UHCI_URHXC_I1_U3RH_XEC_SI1_UC1RH__XEEC_NSID_UCBRH__XECE_NICS_UCT0HX__CE_E1SIN_U3CTH_X_ECE_S1NI_CU1TH__XEEC_NSDI_CBT__XEE_NCSC0__EESNC_EN + +31 87 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 Reset + + UHCI_RX_13_ESC_EN ᇂ໊൐ି DMA ‫ؿ‬ෂඔऌൈੀ॥ሳ‫ ژ‬0x13 ู֥ߐbč‫؀‬/ཿĎ + UHCI_RX_11_ESC_EN ᇂ໊൐ି DMA ‫ؿ‬ෂඔऌൈੀ॥ሳ‫ ژ‬0x11 ู֥ߐbč‫؀‬/ཿĎ + UHCI_RX_DB_ESC_EN ᇂ໊൐ି DMA ‫ؿ‬ෂඔऌൈੀ॥ሳ‫ ژ‬0xdb ู֥ߐbč‫؀‬/ཿĎ + UHCI_RX_C0_ESC_EN ᇂ໊൐ି DMA ‫ؿ‬ෂඔऌൈੀ॥ሳ‫ ژ‬0xc0 ู֥ߐbč‫؀‬/ཿĎ + UHCI_TX_13_ESC_EN ᇂ໊൐ି DMA ࢤ൬ඔऌൈੀ॥ሳ‫ ژ‬0x13 ֥ࢳ઒bč‫؀‬/ཿĎ + UHCI_TX_11_ESC_EN ᇂ໊൐ି DMA ࢤ൬ඔऌൈੀ॥ሳ‫ ژ‬0x11 ֥ࢳ઒bč‫؀‬/ཿĎ + UHCI_TX_DB_ESC_EN ᇂ໊൐ି DMA ࢤ൬ඔऌൈੀ॥ሳ‫ ژ‬0xdb ֥ࢳ઒bč‫؀‬/ཿĎ + UHCI_TX_C0_ESC_EN ᇂ໊൐ି DMA ࢤ൬ඔऌൈੀ॥ሳ‫ ژ‬0xc0 ֥ࢳ઒bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 347 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 13 UART ॥ᇅఖ (UART) + + Register 13.49. UHCI_HUNG_CONF_REG (0x68) + + (reserved) UHCI_RXFIFUOH_CTII_MREXOFIUFOT__ETNIMAEOUT_SHIFUTHCI_RXFIFO_TIMEOUT UHCI_TXFIFUOH_CTII_MTEXOFIUFOT__ETNIMAEOUT_SHIFTUHCI_TXFIFO_TIMEOUT + +31 24 23 22 20 19 12 11 10 87 0 + +0 0 0 0 0 0 0 010 0 0 0x010 10 0 0 0x010 Reset + + UHCI_RXFIFO_TIMEOUT_ENA DMA ‫ؿ‬ෂඔऌӑൈ֥൐ି໊bč‫؀‬/ཿĎ + + UHCI_RXFIFO_TIMEOUT_SHIFT ֒ ࠹ ඔ ᆴ >=(17’d8000»reg_rxfifo_timeout_shift) ൈ ࠹ ඔ ఖ ౢ + ਬbč‫؀‬/ཿĎ + + UHCI_RXFIFO_TIMEOUT թԥӑൈᆴb֒ DMA Ֆ RAM ᇏ‫؀‬౼ඔऌ֥ൈࡗӑ‫ݖ‬஥ᇂᆴൈđ߶Ӂള + UHCI_RX_HUNG_INT ᇏ؎bč‫؀‬/ཿĎ + + UHCI_TXFIFO_TIMEOUT_ENA ‫ؿ‬ෂ FIFO ࢤ൬ඔऌӑൈ֥൐ି໊bč‫؀‬/ཿĎ + + UHCI_TXFIFO_TIMEOUT_SHIFT ֒ ࠹ ඔ ᆴ >=(17’d8000»reg_txfifo_timeout_shift) ൈ ࠹ ඔ ఖ ౢ + ਬbč‫؀‬/ཿĎ + + UHCI_TXFIFO_TIMEOUT թԥӑൈᆴb֒ DMA Ֆ RAM ᇏ‫؀‬౼ඔऌ֥ൈࡗӑ‫ݖ‬஥ᇂᆴൈđ߶Ӂള + UHCI_TX_HUNG_INT ᇏ؎bč‫؀‬/ཿĎ + + Register 13.50. UHCI_ESC_CONFn_REG (n: 0­3) (0xB0+4*n) + + (reserved) UHCI_ESC_SEQ2_CHAR1 UHCI_ESC_SEQ2_CHAR0 UHCI_ESC_SEQ2 + +31 24 23 16 15 87 0 + +00000000 0x0DF 0x0DB 0x013 Reset + + UHCI_ESC_SEQ2_CHAR1 թԥႨႿูߐඔऌᇏ reg_esc_seq2 ֻ֥ 2 ۱ሳ‫ژ‬bč‫؀‬/ཿĎ + UHCI_ESC_SEQ2_CHAR0 թԥႨႿูߐඔऌᇏ reg_esc_seq2 ֻ֥ 1 ۱ሳ‫ژ‬bč‫؀‬/ཿĎ + UHCI_ESC_SEQ2 թԥ flow_control ሳ‫ژ‬Ⴈၛܱо flow_controlbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 348 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + +14 LED PWM ॥ᇅఖ (LEDC) + +14.1 ‫ۀ‬ඍ + +LED_PWM ᇶေႨႿ॥ᇅ LED ֥ਊ؇‫ބ‬࿾೤đ္ॖၛӁള PWM ྐ‫ݼ‬ႨႿః෰Ⴈ๯bLED_PWM Ⴕ 16 ਫ਼๙֡đ +ࠧ 8 ਫ਼ۚ෎๙֡‫ ބ‬8 ਫ਼֮෎๙֡bᆃ 16 ਫ਼๙֡ି‫ܔ‬Ӂള‫׿‬৫֥ඔሳѯྙট౺‫ ׮‬RGB LED ഡСbۚ෎ࠇ֮෎๙ +֡ॖၛႮඹ۱ۚ෎‫ק‬ൈఖᆭ၂ࠇඹ۱֮෎‫ק‬ൈఖᆭ၂ࣉྛ౺‫׮‬bPWM ॥ᇅఖߎି‫ܔ‬ሱ‫׮‬ᇯࡶᄹࡆࠇࡨഒᅝॢ +бđᄝ໭ྶԩ৘ఖ‫ۄ‬ყ֥౦ঃ༯ൌགྷਊ؇‫ބ‬࿾೤ࡶэbLED_PWM ߎᆦӻཬඔ‫ٳ‬௔b + +ᄝЧ໓ᇏđhschn ᆷۚ෎๙֡đlschn ᆷ֮෎๙֡bۚ෎‫ק‬ൈఖ‫֮ބ‬෎‫ק‬ൈఖ‫ٳ‬љଁ଀ູ h_timerx ‫ބ‬ +l_timerxb + +14.2 ‫ିۿ‬૭ඍ + +14.2.1 ࡏ‫ܒ‬ + +๭ 14-1 ູ LED_PWM ࠎЧࡏ‫ܒ‬๭bՖ๭ᇏॖᆩđLED_PWM ଽ҆Ⴕ 8 ۱ۚ෎๙֡ၛࠣ 8 ۱֮෎๙֡bۚ෎๙ +֡Ⴕ 4 ۱ۚ෎ൈᇒଆॶđॖၛՖᇏ಩࿊၂۱ h_timerxb֮෎๙֡Ⴕ 4 ۱֮෎ൈᇒଆॶđॖၛՖᇏ಩࿊၂۱ +l_timerxb + + ๭ 14­1. LED_PWM ࡏ‫ܒ‬ +๭ 14-2 іൕ၂۱ PWM ๙֡‫ބ‬෱࿊౼֥‫ٳ‬௔ఖĠᄝ‫ھ‬౦ঃ༯đ၂۱ۚ෎๙֡஥Ⴕ၂۱ۚ෎‫ٳ‬௔ఖb + + Fractional + divider (18 bit) + + ๭ 14­2. LED_PWM ۚ෎๙֡ॿ๭ + +ুᶈྐ༏॓࠯ 349 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + +14.2.2 ‫ٳ‬௔ఖ + +Divider input ... ... ... ... ... ... ... ... ... ... ... + +clock + + Clock pulses ... Clock pulses Clock pulses divided Clock pulses ... Clock pulses Clock pulses divided ... Clock pulses Clock pulses divided + divided by A divided by A by (A+1) divided by A divided by A by (A+1) divided by A by (A+1) + + B clock pulses divided + by (A+1) + + ... + +Divider output +clock + + 256 output clock pulses + + ๭ 14­3. LED_PWM ‫ٳ‬௔ఖ + +LED PWM ۚ෎‫ק‬ൈఖ֥ൈᇒ LEDC_CLKx Ⴕਆ۱ൈᇒჷğREF_TICK ‫ ބ‬APB_CLKčܱႿൈᇒჷ֥۷‫ྐ؟‬༏౨ +ҕॉᅣࢫ‫ބ໊گ‬ൈᇒĎbൻೆൈᇒ൮༵Ⴎ‫ٳ‬௔ఖࣉྛ‫ٳ‬௔đ‫ٳ‬௔༢ඔູ LEDC_CLK_DIV_NUM_HSTIMERxđ‫ھ‬༢ +ඔ֥‫ॺ໊קܥ‬൞ 18 ໊ğఃᇏۚ 10 ູ໊ᆜඔ҆‫ ٳ‬Ađ֮ 8 ູ໊ཬඔ҆‫ ٳ‬Bb‫ٳ‬௔༢ඔ LEDC_CLK_DIVx ֥‫܄‬ൔ +ູğ + + LE DC _C LK _DI V x = A + B + 256 + +‫ٳ‬௔༢ඔ֥ٓຶູ 1 ∼ 1023b + +ཬඔ҆‫ٳ‬҂ູ 0 ൈđ‫ٳ‬௔ఖ֥ൻೆൻԛൈᇒೂ๭ 14-3 ෮ൕb256 ۱ൻԛᇛ௹ᇏႵ B ۱ᇛ௹ၛ (A+1) ‫ٳ‬௔đႵ +(256-B) ۱ᇛ௹ၛ A ‫ٳ‬௔bၛ (A+1) ‫ٳ‬௔֥ B ۱ᇛ௹नᄋ‫҃ٳ‬ᄝ 256 ۱ᇛ௹ᇏb + +‫ٳ‬௔ఖ֥ൻԛൈᇒቔູ࠹ඔఖ֥ࠎሙൈᇒđ࠹ඔఖ֥࠹ඔٓຶႮ LEDC_HSTIMERx_DUTY_RES ࣉྛ஥ᇂđૄ +Ց࠹ඔղ֞ቋնᆴ 2LEDC_HST IMERx_DUT Y _RES − 1 ൈđӁളၮԛᇏ؎đѩ౏࠹ඔᆴ݂߭֞ 0bೈࡱॖၛ‫໊گ‬a +ᄠ๔ၛࠣ‫؀‬౼࠹ඔఖ֥࠹ඔᆴb + +‫ק‬ൈఖ֥ൻԛྐ‫ݼ‬Ⴎ࠹ඔఖӁളđ໊ॺູ 20 ໊bྐ‫֥ݼ‬࿖ߌᇛ௹थ‫ק‬ਔ಩‫ޅ‬৵ࢤ֞‫קھ‬ൈఖ֥ PWM ๙֥֡ྐ +‫ݼ‬௔ੱb + +PWM ളӮఖൻԛྐ‫ ݼ‬sig_outn ֥௔ੱ౼थႿ‫ٳ‬௔ఖ֥‫ٳ‬௔༢ඔၛࠣ࠹ඔఖ֥࠹ඔٓຶğ + + fsig_outn = fLEDC_CLKx + LEDC_CLK_DIVx · 2LEDC_HSTIMERx_DUTY_RES + +ӈႨ஥ᇂ௔ੱࠣࣚ؇ೂі 14-1 ෮ൕb + і 14­1. ӈႨ஥ᇂ௔ੱࠣࣚ؇ + + LEDC ൈᇒჷ LEDC ൻԛ (PWM) ௔ੱ ቋۚࣚ؇ + APB_CLK (80 MHz) 1 kHz 1/65536 (16 bit) + APB_CLK (80 MHz) 5 kHz 1/8192 (13 bit) + APB_CLK (80 MHz) 10 kHz 1/4096 (12 bit) + RTC8M_CLK (8 MHz) 1 kHz 1/4096 (12 bit) + RTC8M_CLK (8 MHz) 8 kHz 1/512 (9 bit) + REF_TICK (1 MHz) 1 kHz 1/512 (9 bit) + +֮෎๙֥֡‫ٳ‬௔ఖ l_timerx ཌྷؓႿۚ෎๙֥֡‫ٳ‬௔ఖ h_timerx টඪႵၛ༯ 2 ׄ౵љğ + +ুᶈྐ༏॓࠯ 350 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + + 1. ۚ෎‫໊ק‬ఖ֥ൈᇒჷҐႨਔ REF_TICK ࠇ APB_CLKđ֮෎‫໊ק‬ఖҐႨਔ REF_TICK ࠇ SLOW_CLOCKb + ᇂ໊ LEDC_APB_CLK_SEL ࠷թఖđSLOW_CLOCK ֥௔ੱູ 80 MHzđ‫ڎ‬ᄵູ 8 MHzb + + 2. ֒ೈࡱྩ‫ڿ‬ਔۚ෎๙֡࠹ඔఖ֥ቋնᆴࠇ‫ٳ‬௔༢ඔ֥߅đൻԛྐ‫֥ݼ‬۷ྍࡼ߶ᄝ༯၂Ցၮԛᇏ؎ᆭުള + ིb‫֮ط‬෎๙֡ᄝᇂ໊ LEDC_LSTIMERx_PARA_UP ᆭުđ৫ख़۷ྍ࠹ඔఖ֥࠹ඔٓຶҕඔ‫ٳބ‬௔ఖ֥‫ٳ‬ + ௔༢ඔb + +14.2.3 ๙֡ + +ૄ۱๙֡Ⴕਆ۱бࢠఖđࠧ๭ 14-2 ᇏ֥ high_level_comparator ၛࠣ low_level_comparatorb +high_level_comparator ֥бࢠᆴ൞ hpointđႮ LEDC_HPOINT_HSCHn ஥ᇂb֒࠹ඔఖ֥ᆴղ֞ hpoint ൈđൻ +ԛྐ‫يݼ‬ሇູۚ‫׈‬௜b +low_level_comparator ֥бࢠᆴ൞ lpointđႮ LEDC_DUTY_HSCHnđLEDC_DUTY_START_HSCHnđ +LEDC_DUTY_INC_HSCHnđLEDC_DUTY_NUM_HSCHn ၛࠣ LEDC_DUTY_SCALE_HSCHn ‫܋‬๝थ‫ק‬b֒࠹ඔ +ఖ֥ᆴ֩Ⴟ lpoint ൈđൻԛྐ‫يݼ‬ሇູ֮‫׈‬௜b๭ 14-4 ູ LED_PWM ൻԛྐ‫ݼ‬๭b + + ๭ 14­4. LED_PWM ൻԛྐ‫ݼ‬๭ + +LEDC_DUTY_HSCHn ൞၂۱ऎႵ 4 ໊ཬඔ֥‫࠷ׄڜ‬թఖđఃᇏۚ 20 ໊൞ᆜඔ҆‫ٳ‬đ֮ 4 ໊൞ཬඔ҆‫ٳ‬b֮֒ +4 ໊٤ 0 ൈđൻԛྐ‫֥ݼ‬ઝԊॺ؇Ⴕ LEDC_DUTY_HSCHnŀ3ğ0]/16 ֥‫؟ੱۀ‬၂۱࠹ඔᇛ௹b֮ 4 ໊ཬඔႵ০ +Ⴟิۚൻԛྐ‫ݼ‬ᅝॢб֥ࣚ؇bᇂ໊ LEDC_DUTY_START_HSCHnđ๙֡۷ྍު֥ LEDC_DUTY_HSCHn ࠷թ +ఖᆴҌ߶ఏቔႨđࠧ๙֡ॖၛൌགྷ၂ᇕᅝॢб֞ਸ਼၂ᇕᅝॢб֥ሇߐb +LEDC_DUTY_INC_HSCHn थ‫ק‬ਔᅝॢб֥э߄ٚཟbࡶэᅝॢб֥‫ק‬ၬೂ༯ğ +ૄ LEDC_DUTY_CYCLE_HSCHn ۱ઝԊđLEDC_DUTY_HSCHn֥ۚ 20 ໊ࣼ߶‫־‬ᄹࠇ‫ࡨ־‬ +LEDC_DUTY_SCALE_HSCHnđࡶэӉ؇Ⴎ LEDC_DUTY_NUM_HSCHn ॥ᇅđ֒ࡶэປӮުđ߶ӁളࡶэປӮ +ᇏ؎đ౏ᆭު֥ൻԛྐ‫ࡼݼ‬࿼࿃ቋު၂ՑઝԊb๭ 14-5 ູ LEDC_DUTY_INC_HSCHn ູ 1 ൈ֥ࡶэ๭đࠧૄ‫ۯ‬ +LEDC_DUTY_CYCLE_HSCHn ۱ઝԊđൻԛྐ‫ݼ‬ઝॺ‫־‬ᄹ LEDC_DUTY_SCALE_HSCHnb + + ๭ 14­5. ࡶэᅝॢбൻԛྐ‫ݼ‬๭ + +ᇿၩ + + • ֒஥ᇂ LEDC ູࡶэଆൔൈđсྶᄝ LEDC_DUTY_CHNG_END_HSCHn ࠇᆀ + LEDC_DUTY_CHNG_END_LSCHn ᇏ؎ᆭުҌॖၛࣉྛֻ‫ؽ‬Ցࡶэ஥ᇂb + +ুᶈྐ༏॓࠯ 351 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + + • ֒஥ᇂ LEDC ູ‫ࡶࡨ־‬э౏ LEDC_DUTY_HSCHn ູ 2LEDC_HST IMERx_DUT Y _RES ൈđ҂ᄍྸ஥ᇂ + LEDC_DUTY_SCALE_HSCHn ູ 1Ġ֒஥ᇂ LEDC ູ‫ࡶࡨ־‬э౏ LEDC_DUTY_LSCHn ູ + 2LEDC_LST IMERx_DUT Y _RES ൈđ҂ᄍྸ஥ᇂ LEDC_DUTY_SCALE_LSCHn ູ 1b + +14.2.4 ᇏ؎ + + • LEDC_DUTY_CHNG_END_LSCHn_INT ֮෎๙֡ഈ֥ᅝॢбࡶэࢲඏԨ‫ؿ‬ᇏ؎b + + • LEDC_DUTY_CHNG_END_HSCHn_INT ۚ෎๙֡ഈ֥ᅝॢбࡶэࢲඏԨ‫ؿ‬ᇏ؎b + + • LEDC_HS_TIMERn_OVF_INT ۚ෎ൈᇒ࠹ඔఖղ֞ቋն࠹ඔᆴԨ‫ؿ‬ᇏ؎b + + • LEDC_LS_TIMERn_OVF_INT ֮෎ൈᇒ࠹ඔఖղ֞ቋն࠹ඔᆴԨ‫ؿ‬ᇏ؎b + +14.3 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + + ଀ӫ LEDC ಆअ஥ᇂ࠷թఖ 0x3FF59190 ‫؀‬Ĕཿ + ஥ᇂ࠷թఖ ۚ෎๙֡ 0 ֥஥ᇂ࠷թఖ 0 0x3FF59000 ‫؀‬Ĕཿ + LEDC_CONF_REG ۚ෎๙֡ 1 ֥஥ᇂ࠷թఖ 0 0x3FF59014 ‫؀‬Ĕཿ + LEDC_HSCH0_CONF0_REG ۚ෎๙֡ 2 ֥஥ᇂ࠷թఖ 0 0x3FF59028 ‫؀‬Ĕཿ + LEDC_HSCH1_CONF0_REG ۚ෎๙֡ 3 ֥஥ᇂ࠷թఖ 0 0x3FF5903C ‫؀‬Ĕཿ + LEDC_HSCH2_CONF0_REG ۚ෎๙֡ 4 ֥஥ᇂ࠷թఖ 0 0x3FF59050 ‫؀‬Ĕཿ + LEDC_HSCH3_CONF0_REG ۚ෎๙֡ 5 ֥஥ᇂ࠷թఖ 0 0x3FF59064 ‫؀‬Ĕཿ + LEDC_HSCH4_CONF0_REG ۚ෎๙֡ 6 ֥஥ᇂ࠷թఖ 0 0x3FF59078 ‫؀‬Ĕཿ + LEDC_HSCH5_CONF0_REG ۚ෎๙֡ 7 ֥஥ᇂ࠷թఖ 0 0x3FF5908C ‫؀‬Ĕཿ + LEDC_HSCH6_CONF0_REG ۚ෎๙֡ 0 ֥஥ᇂ࠷թఖ 1 0x3FF5900C ‫؀‬Ĕཿ + LEDC_HSCH7_CONF0_REG ۚ෎๙֡ 1 ֥஥ᇂ࠷թఖ 1 0x3FF59020 ‫؀‬Ĕཿ + LEDC_HSCH0_CONF1_REG ۚ෎๙֡ 2 ֥஥ᇂ࠷թఖ 1 0x3FF59034 ‫؀‬Ĕཿ + LEDC_HSCH1_CONF1_REG ۚ෎๙֡ 3 ֥஥ᇂ࠷թఖ 1 0x3FF59048 ‫؀‬Ĕཿ + LEDC_HSCH2_CONF1_REG ۚ෎๙֡ 4 ֥஥ᇂ࠷թఖ 1 0x3FF5905C ‫؀‬Ĕཿ + LEDC_HSCH3_CONF1_REG ۚ෎๙֡ 5 ֥஥ᇂ࠷թఖ 1 0x3FF59070 ‫؀‬Ĕཿ + LEDC_HSCH4_CONF1_REG ۚ෎๙֡ 6 ֥஥ᇂ࠷թఖ 1 0x3FF59084 ‫؀‬Ĕཿ + LEDC_HSCH5_CONF1_REG ۚ෎๙֡ 7 ֥஥ᇂ࠷թఖ 1 0x3FF59098 ‫؀‬Ĕཿ + LEDC_HSCH6_CONF1_REG ֮෎๙֡ 0 ֥஥ᇂ࠷թఖ 0 0x3FF590A0 ‫؀‬Ĕཿ + LEDC_HSCH7_CONF1_REG ֮෎๙֡ 1 ֥஥ᇂ࠷թఖ 0 0x3FF590B4 ‫؀‬Ĕཿ + LEDC_LSCH0_CONF0_REG ֮෎๙֡ 2 ֥஥ᇂ࠷թఖ 0 0x3FF590C8 ‫؀‬Ĕཿ + LEDC_LSCH1_CONF0_REG ֮෎๙֡ 3 ֥஥ᇂ࠷թఖ 0 0x3FF590DC ‫؀‬Ĕཿ + LEDC_LSCH2_CONF0_REG ֮෎๙֡ 4 ֥஥ᇂ࠷թఖ 0 0x3FF590F0 ‫؀‬Ĕཿ + LEDC_LSCH3_CONF0_REG ֮෎๙֡ 5 ֥஥ᇂ࠷թఖ 0 0x3FF59104 ‫؀‬Ĕཿ + LEDC_LSCH4_CONF0_REG ֮෎๙֡ 6 ֥஥ᇂ࠷թఖ 0 0x3FF59118 ‫؀‬Ĕཿ + LEDC_LSCH5_CONF0_REG ֮෎๙֡ 7 ֥஥ᇂ࠷թఖ 0 0x3FF5912C ‫؀‬Ĕཿ + LEDC_LSCH6_CONF0_REG ֮෎๙֡ 0 ֥஥ᇂ࠷թఖ 1 0x3FF590AC ‫؀‬Ĕཿ + LEDC_LSCH7_CONF0_REG ֮෎๙֡ 1 ֥஥ᇂ࠷թఖ 1 0x3FF590C0 ‫؀‬Ĕཿ + LEDC_LSCH0_CONF1_REG ֮෎๙֡ 2 ֥஥ᇂ࠷թఖ 1 0x3FF590D4 ‫؀‬Ĕཿ + LEDC_LSCH1_CONF1_REG ֮෎๙֡ 3 ֥஥ᇂ࠷թఖ 1 0x3FF590E8 ‫؀‬Ĕཿ + LEDC_LSCH2_CONF1_REG ֮෎๙֡ 4 ֥஥ᇂ࠷թఖ 1 0x3FF590FC ‫؀‬Ĕཿ + LEDC_LSCH3_CONF1_REG + LEDC_LSCH4_CONF1_REG + +ুᶈྐ༏॓࠯ 352 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + +଀ӫ ૭ඍ ֹᆶ ٠໙ +LEDC_LSCH5_CONF1_REG ֮෎๙֡ 5 ֥஥ᇂ࠷թఖ 1 0x3FF59110 ‫؀‬Ĕཿ +LEDC_LSCH6_CONF1_REG ֮෎๙֡ 6 ֥஥ᇂ࠷թఖ 1 0x3FF59124 ‫؀‬Ĕཿ +LEDC_LSCH7_CONF1_REG ֮෎๙֡ 7 ֥஥ᇂ࠷թఖ 1 0x3FF59138 ‫؀‬Ĕཿ +ᅝॢб࠷թఖ +LEDC_HSCH0_DUTY_REG ۚ෎๙֡ 0 ֥Ԛ൓ᅝॢб 0x3FF59008 ‫؀‬Ĕཿ +LEDC_HSCH1_DUTY_REG ۚ෎๙֡ 1 ֥Ԛ൓ᅝॢб 0x3FF5901C ‫؀‬Ĕཿ +LEDC_HSCH2_DUTY_REG ۚ෎๙֡ 2 ֥Ԛ൓ᅝॢб 0x3FF59030 ‫؀‬Ĕཿ +LEDC_HSCH3_DUTY_REG ۚ෎๙֡ 3 ֥Ԛ൓ᅝॢб 0x3FF59044 ‫؀‬Ĕཿ +LEDC_HSCH4_DUTY_REG ۚ෎๙֡ 4 ֥Ԛ൓ᅝॢб 0x3FF59058 ‫؀‬Ĕཿ +LEDC_HSCH5_DUTY_REG ۚ෎๙֡ 5 ֥Ԛ൓ᅝॢб 0x3FF5906C ‫؀‬Ĕཿ +LEDC_HSCH6_DUTY_REG ۚ෎๙֡ 6 ֥Ԛ൓ᅝॢб 0x3FF59080 ‫؀‬Ĕཿ +LEDC_HSCH7_DUTY_REG ۚ෎๙֡ 7 ֥Ԛ൓ᅝॢб 0x3FF59094 ‫؀‬Ĕཿ +LEDC_HSCH0_DUTY_R_REG ۚ෎๙֡ 0 ֥֒భᅝॢб 0x3FF59010 ᆺ‫؀‬ +LEDC_HSCH1_DUTY_R_REG ۚ෎๙֡ 1 ֥֒భᅝॢб 0x3FF59024 ᆺ‫؀‬ +LEDC_HSCH2_DUTY_R_REG ۚ෎๙֡ 2 ֥֒భᅝॢб 0x3FF59038 ᆺ‫؀‬ +LEDC_HSCH3_DUTY_R_REG ۚ෎๙֡ 3 ֥֒భᅝॢб 0x3FF5904C ᆺ‫؀‬ +LEDC_HSCH4_DUTY_R_REG ۚ෎๙֡ 4 ֥֒భᅝॢб 0x3FF59060 ᆺ‫؀‬ +LEDC_HSCH5_DUTY_R_REG ۚ෎๙֡ 5 ֥֒భᅝॢб 0x3FF59074 ᆺ‫؀‬ +LEDC_HSCH6_DUTY_R_REG ۚ෎๙֡ 6 ֥֒భᅝॢб 0x3FF59088 ᆺ‫؀‬ +LEDC_HSCH7_DUTY_R_REG ۚ෎๙֡ 7 ֥֒భᅝॢб 0x3FF5909C ᆺ‫؀‬ +LEDC_LSCH0_DUTY_REG ֮෎๙֡ 0 ֥Ԛ൓ᅝॢб 0x3FF590A8 ‫؀‬Ĕཿ +LEDC_LSCH1_DUTY_REG ֮෎๙֡ 1 ֥Ԛ൓ᅝॢб 0x3FF590BC ‫؀‬Ĕཿ +LEDC_LSCH2_DUTY_REG ֮෎๙֡ 2 ֥Ԛ൓ᅝॢб 0x3FF590D0 ‫؀‬Ĕཿ +LEDC_LSCH3_DUTY_REG ֮෎๙֡ 3 ֥Ԛ൓ᅝॢб 0x3FF590E4 ‫؀‬Ĕཿ +LEDC_LSCH4_DUTY_REG ֮෎๙֡ 4 ֥Ԛ൓ᅝॢб 0x3FF590F8 ‫؀‬Ĕཿ +LEDC_LSCH5_DUTY_REG ֮෎๙֡ 5 ֥Ԛ൓ᅝॢб 0x3FF5910C ‫؀‬Ĕཿ +LEDC_LSCH6_DUTY_REG ֮෎๙֡ 6 ֥Ԛ൓ᅝॢб 0x3FF59120 ‫؀‬Ĕཿ +LEDC_LSCH7_DUTY_REG ֮෎๙֡ 7 ֥Ԛ൓ᅝॢб 0x3FF59134 ‫؀‬Ĕཿ +LEDC_LSCH0_DUTY_R_REG ֮෎๙֡ 0 ֥֒భᅝॢб 0x3FF590B0 ᆺ‫؀‬ +LEDC_LSCH1_DUTY_R_REG ֮෎๙֡ 1 ֥֒భᅝॢб 0x3FF590C4 ᆺ‫؀‬ +LEDC_LSCH2_DUTY_R_REG ֮෎๙֡ 2 ֥֒భᅝॢб 0x3FF590D8 ᆺ‫؀‬ +LEDC_LSCH3_DUTY_R_REG ֮෎๙֡ 3 ֥֒భᅝॢб 0x3FF590EC ᆺ‫؀‬ +LEDC_LSCH4_DUTY_R_REG ֮෎๙֡ 4 ֥֒భᅝॢб 0x3FF59100 ᆺ‫؀‬ +LEDC_LSCH5_DUTY_R_REG ֮෎๙֡ 5 ֥֒భᅝॢб 0x3FF59114 ᆺ‫؀‬ +LEDC_LSCH6_DUTY_R_REG ֮෎๙֡ 6 ֥֒భᅝॢб 0x3FF59128 ᆺ‫؀‬ +LEDC_LSCH7_DUTY_R_REG ֮෎๙֡ 7 ֥֒భᅝॢб 0x3FF5913C ᆺ‫؀‬ +‫ٳ‬௔ఖ࠷թఖ +LEDC_HSTIMER0_CONF_REG ஥ᇂۚ෎ൈᇒ࠹ඔఖ 0 0x3FF59140 ‫؀‬Ĕཿ +LEDC_HSTIMER1_CONF_REG ஥ᇂۚ෎ൈᇒ࠹ඔఖ 1 0x3FF59148 ‫؀‬Ĕཿ +LEDC_HSTIMER2_CONF_REG ஥ᇂۚ෎ൈᇒ࠹ඔఖ 2 0x3FF59150 ‫؀‬Ĕཿ +LEDC_HSTIMER3_CONF_REG ஥ᇂۚ෎ൈᇒ࠹ඔఖ 3 0x3FF59158 ‫؀‬Ĕཿ +LEDC_HSTIMER0_VALUE_REG ۚ෎ൈᇒ࠹ඔఖ 0 ֥֒భ࠹ඔᆴ 0x3FF59144 ᆺ‫؀‬ +LEDC_HSTIMER1_VALUE_REG ۚ෎ൈᇒ࠹ඔఖ 1 ֥֒భ࠹ඔᆴ 0x3FF5914C ᆺ‫؀‬ + +ুᶈྐ༏॓࠯ 353 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + +଀ӫ ૭ඍ ֹᆶ ٠໙ +LEDC_HSTIMER2_VALUE_REG ۚ෎ൈᇒ࠹ඔఖ 2 ֥֒భ࠹ඔᆴ 0x3FF59154 ᆺ‫؀‬ +LEDC_HSTIMER3_VALUE_REG ۚ෎ൈᇒ࠹ඔఖ 3 ֥֒భ࠹ඔᆴ 0x3FF5915C ᆺ‫؀‬ +LEDC_LSTIMER0_CONF_REG ஥ᇂ֮෎ൈᇒ࠹ඔఖ 0 0x3FF59160 ‫؀‬Ĕཿ +LEDC_LSTIMER1_CONF_REG ஥ᇂ֮෎ൈᇒ࠹ඔఖ 1 0x3FF59168 ‫؀‬Ĕཿ +LEDC_LSTIMER2_CONF_REG ஥ᇂ֮෎ൈᇒ࠹ඔఖ 2 0x3FF59170 ‫؀‬Ĕཿ +LEDC_LSTIMER3_CONF_REG ஥ᇂ֮෎ൈᇒ࠹ඔఖ 3 0x3FF59178 ‫؀‬Ĕཿ +LEDC_LSTIMER0_VALUE_REG ֮෎ൈᇒ࠹ඔఖ 0 ֥֒భ࠹ඔᆴ 0x3FF59164 ᆺ‫؀‬ +LEDC_LSTIMER1_VALUE_REG ֮෎ൈᇒ࠹ඔఖ 1 ֥֒భ࠹ඔᆴ 0x3FF5916C ᆺ‫؀‬ +LEDC_LSTIMER2_VALUE_REG ֮෎ൈᇒ࠹ඔఖ 2 ֥֒భ࠹ඔᆴ 0x3FF59174 ᆺ‫؀‬ +LEDC_LSTIMER3_VALUE_REG ֮෎ൈᇒ࠹ඔఖ 3 ֥֒భ࠹ඔᆴ 0x3FF5917C ᆺ‫؀‬ +ᇏ؎࠷թఖ +LEDC_INT_RAW_REG ჰ൓ᇏ؎ሑ෿ 0x3FF59180 ᆺ‫؀‬ +LEDC_INT_ST_REG ௠зᇏ؎ሑ෿ 0x3FF59184 ᆺ‫؀‬ +LEDC_INT_ENA_REG ᇏ؎൐ି໊ 0x3FF59188 ‫؀‬Ĕཿ +LEDC_INT_CLR_REG ᇏ؎ౢԢ໊ 0x3FF5918C ᆺཿ + +ুᶈྐ༏॓࠯ 354 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + +14.4 ࠷թఖ + + Register 14.1. LEDC_HSCHn_CONF0_REG (n: 0­7) (0x1C+0x10*n) + + (reserved) LEDCL_EIDDLCE__SLVLIG_E_HDOSCUC_TTH_InMENER_H_SSECLH_nHSCHn + +31 43 21 0 + + 0x00000000 0 0 0 Reset + + LEDC_IDLE_LV_HSCHn ۚ෎๙֡ n ҂‫۽‬ቔൈđႨႿ॥ᇅൻԛᆴbč‫؀‬ĔཿĎ + + LEDC_SIG_OUT_EN_HSCHn ۚ෎๙֡ n ൻԛ൐ି॥ᇅ໊bč‫؀‬ĔཿĎ + + LEDC_TIMER_SEL_HSCHn ႨႿՖ 4 ᇕۚ෎ൈᇒ࠹ඔఖᇏູۚ෎๙֡ n ࿊ᄴ၂۱ൈᇒ࠹ඔఖbč‫؀‬ + ĔཿĎ + 0: ࿊ᄴ hstimer0Ġ + 1: ࿊ᄴ hstimer1Ġ + 2: ࿊ᄴ hstimer2Ġ + 3: ࿊ᄴ hstimer3b + + Register 14.2. LEDC_HSCHn_HPOINT_REG (n: 0­7) (0x20+0x10*n) + + (reserved) LEDC_HPOINT_HSCHn + 0x000000 +31 20 19 0 + + 0x0000 Reset + + LEDC_HPOINT_HSCHn ֒ۚ෎๙֡ n ֥ htimerx(x=[0,3]) ղ֞ LEDC_HPOINT_HSCHn[19:0]đൻԛ + ྐ‫يݼ‬ሇູۚ‫׈‬௜bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 355 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + + Register 14.3. LEDC_HSCHn_DUTY_REG (n: 0­7) (0x24+0x10*n) + + (reserved) LEDC_DUTY_HSCHn + 0x0000000 +31 25 24 0 + + 0x00 Reset + + LEDC_DUTY_HSCHn Ⴈ Ⴟ ॥ ᇅ ൻ ԛ ᅝ ॢ бb ֒ ๙ ֡ n ֥ hstimerx(x=[0,3]) ղ ֞ + LEDC_LPOINT_HSCHn ൈđൻԛྐ‫يݼ‬ሇູ֮‫׈‬௜b + LEDC_LPOINT_HSCHn=LEDC_LPOINT_HSCHn[19:0]+LEDC_DUTY_HSCHn[24:4]) (1) + LEDC_LPOINT_HSCHn=LEDC_LPOINT_HSCHn[19:0]+LEDC_DUTY_HSCHn[24:4] +1) (2) + ֒࠷թఖ࿊ᄴ 1đ2 ൈđ౨Ֆ‫ିۿ‬૭ඍᇏࠆ౼۷‫ྐ؟‬༏b + + Register 14.4. LEDC_HSCHn_CONF1_REG (n: 0­7) (0x28+0x10*n) + + LEDCL_EDDUCTY_D_SUTTAYR_TIN_CH_SHCSHCnHn LEDC_DUTY_NUM_HSCHn LEDC_DUTY_CYCLE_HSCHn LEDC_DUTY_SCALE_HSCHn + +31 30 29 20 19 10 9 0 + +01 0x000 0x000 0x000 Reset + + LEDC_DUTY_START_HSCHn ֒ ஥ ᇂ ਔ LEDC_DUTY_NUM_HSCHn, + + LEDC_DUTY_CYCLE_HSCHn ၛ ࠣ LEDC_DUTY_SCALE_HSCHn ൈđ ླ ေ ᇂ ໊ + + LEDC_DUTY_START_HSCHnđᆃུ࠷թఖҌ߶ളིb႗ࡱሱ‫׮‬ౢਬՎ໊bč‫؀‬ĔཿĎ + + LEDC_DUTY_INC_HSCHn ႨႿ‫־‬ᄹࠇ‫ۚࡨ־‬෎๙֡ n ֥ൻԛྐ‫֥ݼ‬ᅝॢбbč‫؀‬ĔཿĎ + + LEDC_DUTY_NUM_HSCHn ႨႿ॥ᇅۚ෎๙֡ n ᅝॢбэ߄֥Ցඔbč‫؀‬ĔཿĎ + + LEDC_DUTY_CYCLE_HSCHn ૄ LEDC_DUTY_CYCLE_HSCHn ۱ൈᇒᇛ௹‫־‬ᄹࠇ‫ۚࡨ־‬෎๙֡ n + ֥ᅝॢбb + + LEDC_DUTY_SCALE_HSCHn ႨႿ‫־‬ᄹࠇ‫ۚࡨ־‬෎๙֡ n ֥҄Ӊbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 356 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + + Register 14.5. LEDC_HSCHn_DUTY_R_REG (n: 0­7) (0x2C+0x10*n) + + (reserved) LEDC_DUTY_LSCHn_R + 0x0000000 +31 25 24 0 + + 0x00 Reset + + LEDC_DUTY_HSCHn_R ֒༯ۚ෎๙֡ n ֥ൻԛྐ‫֥ݼ‬ᅝॢбbčᆺ‫؀‬Ď + + Register 14.6. LEDC_LSCHn_CONF0_REG (n: 0­7) (0xBC+0x10*n) + + (reserved) LEDCL_EPDARCLA_EI_DDULCPE___LSLSVLIGC_E_LDHOSCnCU_HTT_InMENER_L_SSCELH_nLSCHn + +31 54 3 21 0 + + 0x0000000 0 0 0 0 Reset + + LEDC_PARA_UP_LSCHn ႨႿ۷ྍ֮෎๙֡ n ֥ LEDC_LSCHn_HPOINT ‫ ބ‬LEDC_LSCHn_DUTY + ࠷թఖbč‫؀‬ĔཿĎ + + LEDC_IDLE_LV_LSCHn ֮֒෎๙֡ n ҂‫۽‬ቔൈđႨႿ॥ᇅൻԛᆴbč‫؀‬ĔཿĎ + + LEDC_SIG_OUT_EN_LSCHn ֮෎๙֡ n ֥ൻԛ॥ᇅ໊bč‫؀‬ĔཿĎ + + LEDC_TIMER_SEL_LSCHn ႨႿՖ 4 ᇕ֮෎‫ٳ‬௔ఖᇏູ֮෎๙֡ n ࿊ᄴ၂۱ൈᇒ࠹ඔఖbč‫؀‬Ĕ + ཿĎ + 0: ࿊ᄴ lstimer0Ġ + 1: ࿊ᄴ lstimer1Ġ + 2: ࿊ᄴ lstimer2Ġ + 3: ࿊ᄴ lstimer3b + + Register 14.7. LEDC_LSCHn_HPOINT_REG (n: 0­7) (0xC0+0x10*n) + + (reserved) LEDC_HPOINT_LSCHn + 0x000000 +31 20 19 0 + + 0x0000 Reset + + LEDC_HPOINT_LSCHn ֮֒෎๙֡ n ֥ lstimerx(x=[0,3]) ղ֞ LEDC_HPOINT_LSCHn[19:0] ൈđൻ + ԛྐ‫يݼ‬ሇູۚ‫׈‬௜bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 357 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + + Register 14.8. LEDC_LSCHn_DUTY_REG (n: 0­7) (0xC4+0x10*n) + + (reserved) LEDC_DUTY_LSCHn + 0x0000000 +31 25 24 0 + + 0x00 Reset + + LEDC_DUTY_LSCHn Ⴈ Ⴟ ॥ ᇅ ൻ ԛ ᅝ ॢ бb ֒ ֮ ෎ ๙ ֡ n ֥ lstimerx(x=[0,3]) ղ ֞ + LEDC_LPOINT_LSCHnൈđൻԛྐ‫يݼ‬ሇູ֮‫׈‬௜bč‫؀‬ĔཿĎ + LEDC_LPOINT_LSCHn=(LEDC_HPOINT_LSCHn[19:0]+LEDC_DUTY_LSCHn[24:4]) (1) + LEDC_LPOINT_LSCHn=(LEDC_HPOINT_LSCHn[19:0]+LEDC_DUTY_LSCHn[24:4] +1) (2) + ֒࠷թఖ࿊ᄴ 1đ2 ൈđ౨Ֆ‫ିۿ‬૭ඍᇏࠆ౼۷‫ྐ؟‬༏b + + Register 14.9. LEDC_LSCHn_CONF1_REG (n: 0­7) (0xC8+0x10*n) + + LEDCL_EDDUCTY_D_SUTTAYR_TIN_CLS_LCSHCnHn LEDC_DUTY_NUM_LSCHn LEDC_DUTY_CYCLE_LSCHn LEDC_DUTY_SCALE_LSCHn + +31 30 29 20 19 10 9 0 + +01 0x000 0x000 0x000 Reset + + LEDC_DUTY_START_LSCHn ֒ ஥ ᇂ ਔ LEDC_DUTY_NUM_HSCHna + + LEDC_DUTY_CYCLE_HSCHn ၛ ࠣ LEDC_DUTY_SCALE_HSCHn ൈđ ླ ေ ᇂ ໊ + + LEDC_DUTY_START_HSCHnđᆃུ࠷թఖҌିളིb႗ࡱሱ‫׮‬ౢਬՎ໊bč‫؀‬ĔཿĎ + + LEDC_DUTY_INC_LSCHn ႨႿ‫־‬ᄹࠇ‫֮ࡨ־‬෎๙֡ n ֥ൻԛྐ‫֥ݼ‬ᅝॢбbč‫؀‬ĔཿĎ + + LEDC_DUTY_NUM_LSCHn ႨႿ॥ᇅ֮෎๙֡ n ֥ᅝॢбэ߄֥Ցඔbč‫؀‬ĔཿĎ + + LEDC_DUTY_CYCLE_LSCHn ႨႿૄ LEDC_DUTY_CYCLE_LSCHn ۱ൈᇒᇛ௹‫־‬ᄹࠇ‫ࡨ־‬ᅝॢ + бbč‫؀‬ĔཿĎ + + LEDC_DUTY_SCALE_LSCHn Ⴈ‫־‬ᄹࠇ‫֮ࡨ־‬෎๙֡ n ֥҄Ӊbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 358 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + + Register 14.10. LEDC_LSCHn_DUTY_R_REG (n: 0­7) (0xCC+0x10*n) + + (reserved) LEDC_DUTY_LSCHn_R + 0x0000000 +31 25 24 0 + + 0x00 Reset + + LEDC_DUTY_R_LSCHn_R ֮෎๙֡ n ֥ൻԛྐ‫֥֒ݼ‬భᅝॢбbčᆺ‫؀‬Ď + + Register 14.11. LEDC_HSTIMERx_CONF_REG (x: 0­3) (0x140+8*x) + + (reserved) LEDCL_ETDICCKL__EHSDSECTLI__MHHESSRTTxIIMM_REESRRTxx_PAUSE LEDC_CLK_DIV_NUM_HSTIMERx LEDC_HSTIMERx_DUTY_RES + 0x00000 +31 26 25 24 23 22 54 0 + + 0x00 010 0x00 Reset + + LEDC_TICK_SEL_HSTIMERx ႨႿ࿊ᄴ APB_CLK ࠇ REF_TICK ቔູۚ෎ൈᇒ࠹ඔఖbč‫؀‬ĔཿĎ + 1ğAPB_CLKĠ + 0ğREF_TICKb + + LEDC_HSTIMERx_RST ႨႿ‫໊ۚگ‬෎ൈᇒ࠹ඔఖ xđ‫࠹ު໊گ‬ඔఖູ 0bč‫؀‬ĔཿĎ + + LEDC_HSTIMERx_PAUSE ႨႿᄠ๔ۚ෎ൈᇒ࠹ඔఖ xbč‫؀‬ĔཿĎ + + LEDC_CLK_DIV_NUM_HSTIMERx ႨႿ஥ᇂۚ෎ൈᇒ࠹ඔఖ xđ֮ 8 ູ໊ཬඔ҆‫ٳ‬bč‫؀‬ĔཿĎ + + LEDC_HSTIMERx_DUTY_RES Ⴈ Ⴟ ॥ ᇅ ۚ ෎ ൈ ᇒ ࠹ ඔ ఖ x ֥ ࠹ ඔ ٓ ຶb ࠹ ඔ ٓ ຶ ູ + [0,2**LEDC_HSTIMERx_DUTY_RES]đቋն໊ॺູ 20 ໊bč‫؀‬ĔཿĎ + + Register 14.12. LEDC_HSTIMERx_VALUE_REG (x: 0­3) (0x144+8*x) + + (reserved) LEDC_HSTIMERx_CNT + +31 20 19 0 + + 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + LEDC_HSTIMERx_CNT ೈࡱॖၛ‫؀‬౼ۚ෎ൈᇒ࠹ඔఖ x ֥֒భ࠹ඔᆴbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 359 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + + Register 14.13. LEDC_LSTIMERx_CONF_REG (x: 0­3) (0x160+8*x) + + (reserved) LEDCL_ELSDTCIL_METEDICRCKxL___ELPSSDAETCRLI_MA_LL_ESSURTTPxIIMM_REESRRTxx_PAUSE LEDC_CLK_DIV_NUM_LSTIMERx LEDC_LSTIMERx_DUTY_RES + 0x00000 +31 27 26 25 24 23 22 54 0 + + 0x00 0010 0x00 Reset + + LEDC_LSTIMERx_PARA_UP Ⴈ Ⴟ ۷ ྍ LEDC_CLK_DIV_NUM_LSTIMERx ‫ބ‬ + + LEDC_LSTIMERx_DUTY_RESb + + LEDC_TICK_SEL_LSTIMERx ႨႿູ֮෎ൈᇒ࠹ඔఖ x ࿊ᄴ SLOW_CLK ࠇ REF_TICK ൈᇒbč‫؀‬ + ĔཿĎ + 1ğSLOW_CLKĠ + 0ğREF_TICKb + + LEDC_LSTIMERx_RST ႨႿ‫໊֮گ‬෎ൈᇒ࠹ඔఖ xđ‫࠹ު໊گ‬ඔఖູ 0bč‫؀‬ĔཿĎ + + LEDC_LSTIMERx_PAUSE ႨႿᄠ๔֮෎ൈᇒ࠹ඔఖ xbč‫؀‬ĔཿĎ + + LEDC_CLK_DIV_NUM_LSTIMERx ႨႿ஥ᇂ֮෎ൈᇒ࠹ඔఖ xđ֮ 8 ູ໊ཬඔ҆‫ٳ‬bč‫؀‬ĔཿĎ + + LEDC_LSTIMERx_DUTY_RES Ⴈ Ⴟ ॥ ᇅ ֮ ෎ ൈ ᇒ ࠹ ඔ ఖ x ֥ ࠹ ඔ ٓ ຶb ࠹ ඔ ٓ ຶ ູ + [0,2**LEDC_LSTIMERx_DUTY_RES]đቋն໊ॺູ 20 ໊bč‫؀‬ĔཿĎ + + Register 14.14. LEDC_LSTIMERx_VALUE_REG (x: 0­3) (0x164+8*x) + + (reserved) LEDC_LSTIMERx_CNT + +31 20 19 0 + + 0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + LEDC_LSTIMERx_CNT թԥ֮෎๙֡ൈᇒ࠹ඔఖ x ֥֒భ࠹ඔᆴbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 360 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + + Register 14.15. LEDC_INT_RAW_REG (0x0180) + + (reserved) LEDCL_EDDUCTLY_ED_DCUCHTLY_NED_GDCU_CHTELY_NNED_GDDCU__CHTELLY_NSNED_GCDDCUH__CHTEL7LY_NSN_ED_GCIDDNCUH__CTHTEL6L_Y_NSN_RED_GCIDDANCUH__WCTHTEL5L_Y_NSN_RED_GCIDDANCUH__WCTHTEL4L_Y_NSN_RED_GCIDDANCUH__WCTHTEL3L_Y_NSN_RED_GCIDDANCUH__WCTHTEL2L_Y_NSN_RED_GCIDDANCUH__WCTHTEL1L_Y_NSN_RED_GCIDDANCUH__WCTHTEH0L_Y_NN_SRED_GIDCDANCU__HWCTHTEHL_7Y_NNSRED__GDCIDACUN__HWCHTTEHL6Y__NNSED_R_GDCIDCUAN__HCHTWTEHL5Y__NNSED_R_GDCIDCUAN__HCHTWTEHL4Y__NNSEL_R_GDCISDCAN__THCHWTEHIL3_M_NNSEL_RGEDCISDANR__THCWTEH3IL2_M_N_SEL_ROEDCISDANRV_THCWTFH2IL1_M___SEL_RIOENCISDANRVTTHCWTF1_IL0_M__R_EH_RIOEANIDSANRVWTCTWTF0_LI___MR_EHRIOANEDSAVWTRCTWF_3LI__MR_EHIANOEDSWTRVCT_F2I_MR__HIAOENSWRVTTF1_IM_R_IOEANRVWTF0__R_IOANVWTF__RIANWT_RAW + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + LEDC_DUTY_CHNG_END_LSCHn_INT_RAW LEDC_DUTY_CHNG_END_LSCHn_INT ᇏ؎֥ჰ൓ + ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + + LEDC_DUTY_CHNG_END_HSCHn_INT_RAW LEDC_DUTY_CHNG_END_HSCHn_INT ᇏ ؎ ֥ ჰ + ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + + LEDC_LSTIMERx_OVF_INT_RAW LEDC_LSTIMERx_OVF_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + + LEDC_HSTIMERx_OVF_INT_RAW LEDC_HSTIMERx_OVF_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + + Register 14.16. LEDC_INT_ST_REG (0x0184) + + (reserved) LEDCL_EDDUCTLY_ED_DCUCHTLY_NED_GDCU_CHTELY_NNED_GDDCU__CHTELLY_NSNED_GCDDCUH__CHTEL7LY_NSN_ED_GCIDDNCUH__CTHTEL6L_Y_NSN_SED_GCIDDTNCUH__CTHTEL5L_Y_NSN_SED_GCIDDTNCUH__CTHTEL4L_Y_NSN_SED_GCIDDTNCUH__CTHTEL3L_Y_NSN_SED_GCIDDTNCUH__CTHTEL2L_Y_NSN_SED_GCIDDTNCUH__CTHTEL1L_Y_NSN_SED_GCIDDTNCUH__CTHTEH0L_Y_NN_SSED_GIDCDTNCU__HCTHTEHL_7Y_NNSSED__GDCIDTCUN__HCHTTEHL6Y__NNSED_S_GDCIDCUTN__HCHTTEHL5Y__NNSED_S_GDCIDCUTN__HCHTTEHL4Y__NNSEL_S_GDCISDCTN__THCHTEHIL3_M_NNSEL_SGEDCISDTNR__THCTEH3IL2_M_N_SEL_SOEDCISDTNRV_THCTFH2IL1_M___SEL_SIOENCISDTNRVTTHCTF1_IL0_M__S_EH_SIOETNIDSTNRVTCTTF0_LI___MS_EHSIOTNEDSTVTRCTF_3LI__MS_EHITNOEDSTRVCT_F2I_MS__HITOENSRVTTF1_IM_S_IOETNRVTF0__S_IOTNVTF__SITNT_ST + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + LEDC_DUTY_CHNG_END_LSCHn_INT_ST LEDC_DUTY_CHNG_END_LSCHn_INT ᇏ؎֥ႅзᇏ + ؎ሑ෿໊bčᆺ‫؀‬Ď + + LEDC_DUTY_CHNG_END_HSCHn_INT_ST LEDC_DUTY_CHNG_END_HSCHn_INT ᇏ؎֥ႅз + ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + + LEDC_LSTIMERx_OVF_INT_ST LEDC_LSTIMERx_OVF_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + + LEDC_HSTIMERx_OVF_INT_ST LEDC_HSTIMERx_OVF_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 361 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + + Register 14.17. LEDC_INT_ENA_REG (0x0188) + + (reserved) LEDCL_EDDUCTLY_ED_DCUCHTLY_NED_GDCU_CHTELY_NNED_GDDCU__CHTELLY_NSNED_GCDDCUH__CHTEL7LY_NSN_ED_GCIDDNCUH__CTHTEL6L_Y_NSN_EED_GCIDNDNCUH__ACTHTEL5L_Y_NSN_EED_GCIDNDNCUH__ACTHTEL4L_Y_NSN_EED_GCIDNDNCUH__ACTHTEL3L_Y_NSN_EED_GCIDNDNCUH__ACTHTEL2L_Y_NSN_EED_GCIDNDNCUH__ACTHTEL1L_Y_NSN_EED_GCIDNDNCUH__ACTHTEH0L_Y_NN_SEED_GIDCNDNCU__HACTHTEHL_7Y_NNSEED__GDCNIDCUN__HACHTTEHL6Y__NNSED_E_GDCIDCNUN__HCHTATEHL5Y__NNSED_E_GDCIDCNUN__HCHTATEHL4Y__NNSEL_E_GDCISDCNN__THCHATEHIL3_M_NNSEL_EGEDCISDNNR__THCATEH3IL2_M_N_SEL_EOEDCISDNNRV_THCATFH2IL1_M___SEL_EIOENCISDNNRVTTHCATF1_IL0_M__E_EH_EIONENIDNSNRVATCTATF0_LI___ME_EHEIONNEDNSVATRCTAF_3LI__ME_EHINNOEDSATRVCT_F2I_ME__HNIOENSARVTTF1_IM_E_IONENRVATF0__E_IONNVATF__EINNAT_ENA + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + LEDC_DUTY_CHNG_END_LSCHn_INT_ENA LEDC_DUTY_CHNG_END_LSCHn_INT ᇏ؎֥൐ି + ໊bč‫؀‬ĔཿĎ + + LEDC_DUTY_CHNG_END_HSCHn_INT_ENA LEDC_DUTY_CHNG_END_HSCHn_INT ᇏ؎֥൐ି + ໊bč‫؀‬ĔཿĎ + + LEDC_LSTIMERx_OVF_INT_ENA LEDC_LSTIMERx_OVF_INT ᇏ؎֥൐ି໊bč‫؀‬ĔཿĎ + + LEDC_HSTIMERx_OVF_INT_ENA LEDC_HSTIMERx_OVF_INT ᇏ؎֥൐ି໊bč‫؀‬ĔཿĎ + + Register 14.18. LEDC_INT_CLR_REG (0x018C) + + (reserved) LEDCL_EDDUCTLY_ED_DCUCHTLY_NED_GDCU_CHTELY_NNED_GDDCU__CHTELLY_NSNED_GCDDCUH__CHTEL7LY_NSN_ED_GCIDDNCUH__CTHTEL6L_Y_NSN_CED_GCIDDNCLUH__RCTHTEL5L_Y_NSN_CED_GCIDDNCLUH__RCTHTEL4L_Y_NSN_CED_GCIDDNCLUH__RCTHTEL3L_Y_NSN_CED_GCIDDNCLUH__RCTHTEL2L_Y_NSN_CED_GCIDDNCLUH__RCTHTEL1L_Y_NSN_CED_GCIDDNCLUH__RCTHTEH0L_Y_NN_SCED_GIDCDNCLU__RHCTHTEHL_7Y_NNSCED__GDCIDCLUN__RHCHTTEHL6Y__NNSED_C_GDCIDCUNL__HCHRTTEHL5Y__NNSED_C_GDCIDCUNL__HCHRTTEHL4Y__NNSEL_C_GDCISDCNL__THCHRTEHIL3_M_NNSEL_CGEDCISDNLR__THCRTEH3IL2_M_N_SEL_COEDCISDNLRV_THCRTFH2IL1_M___SEL_CIOENCISDNLRVTTHCRTF1_IL0_M__C_EH_CIOENLIDSNLRRVTCRTTF0_LI___MC_EHCIONLEDSLRVTRCRTF_3LI__MC_EHINOLEDSRTRVCT_F2I_MC__HIOLENSRRVTTF1_IM_C_IOENLRRVTF0__C_IONLRVTF__CINLRT_CLR + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + LEDC_DUTY_CHNG_END_LSCHn_INT_CLR ႨႿౢԢ LEDC_DUTY_CHNG_END_LSCHn_INT ᇏ + ؎bčᆺཿĎ + + LEDC_DUTY_CHNG_END_HSCHn_INT_CLR Ⴈ Ⴟ ౢ Ԣ LEDC_DUTY_CHNG_END_HSCHn_INT + ᇏ؎bčᆺཿĎ + + LEDC_LSTIMERx_OVF_INT_CLR ႨႿౢԢ LEDC_LSTIMERx_OVF_INT ᇏ؎bčᆺཿĎ + + LEDC_HSTIMERx_OVF_INT_CLR ႨႿౢԢ LEDC_HSTIMERx_OVF_INT ᇏ؎bčᆺཿĎ + +ুᶈྐ༏॓࠯ 362 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 14 LED PWM ॥ᇅఖ (LEDC) + + Register 14.19. LEDC_CONF_REG (0x0190) + + (reserved) LEDC_APB_CLK_SEL + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + LEDC_APB_CLK_SEL ႨႿഡᇂ SLOW_CLK ֥௔ੱbč‫؀‬ĔཿĎ + 0ğ8 MHzĠ + 1ğ80 MHzb + +ুᶈྐ༏॓࠯ 363 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 15 ‫ޣ‬ຓဪ॥ (RMT) + +15 ‫ޣ‬ຓဪ॥ (RMT) + +15.1 ‫ۀ‬ඍ + +RMTč‫ޣ‬ຓဪ॥ఖĎ൞၂۱‫ޣ‬ຓ‫ؿ‬ෂĔࢤ൬॥ᇅఖ, ఃห൹ഡ࠹ᆦӻളӮ۲োྐ‫ݼ‬b‫ޣ‬ຓဪ॥‫ؿ‬ഝఖՖଽᇂ֥ +RAMčෛࠏթ౼թԥఖĎ౵ᇏ‫؀‬౼৵࿃֥ઝԊ઒, ѩؓൻԛྐ‫ྛࣉݼ‬ᄛѯ‫ט‬ᇅbࢤ൬ఖ࡟ҩൻೆྐ‫ݼ‬, ѩࣉྛੲ +ѯ, ಖުࡼྐ‫׈֮ۚݼ‬௜ၛࠣӉ؇ᆴթೆ RAM ᇏb +RMT Ⴕ 8 ۱๙֡đщ઒ູ 0 ~ 7đૄ۱๙֡Ⴕ၂ቆ‫ିۿ‬ཌྷ๝֥࠷թఖbູਔٚьྻඍđၛ n іൕ۲۱๙ +֡b + +15.2 ‫ିۿ‬૭ඍ + +15.2.1 RMT ࡏ‫ܒ‬ + + ๭ 15­1. RMT ࡏ‫ܒ‬ + +RMT Ⴕ 8 ۱‫׿‬৫๙֡, ૄ۱๙֡ଽ҆Ⴕ၂۱‫ؿ‬ෂఖ‫ބ‬၂۱ࢤ൬ఖ, ‫ؿ‬ෂ‫ࢤބ‬൬҂ॖ๝ൈ‫۽‬ቔb8 ۱๙֡‫܋‬ཚ၂ॶ +512x32 bit ֥ RAMbRAM ॖႮԩ৘ఖଽ‫ނ‬๙‫ ݖ‬APB ሹཌࣉྛ‫؀‬ཿb‫ؿ‬ഝఖॖၛؓྐ‫ྛࣉݼ‬ᄛѯ‫ט‬ᇅbೈࡱॖ +ၛ๙‫ݖ‬஥ᇂ RMT_REF_ALWAYS_ON_CHn ࿊ᄴૄ۱๙֥֡‫۽‬ቔൈᇒğ80 MHz APBčຓຶሹཌĎൈᇒࠇᆀ +REF_TICKb + +ুᶈྐ༏॓࠯ 364 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 15 ‫ޣ‬ຓဪ॥ (RMT) + +15.2.2 RMT RAM + + ๭ 15­2. ඔऌࢲ‫ܒ‬ + +RAM ᇏඔऌࢲ‫ܒ‬ೂ๭ 15-2 ෮ൕđႮ֮ 16 ໊‫ ۚބ‬16 ໊ቆӮbਆ۱ሳ‫؍‬ᇏ level іൕ‫׈‬௜֮ۚᆴđperiod іൕ +level ӻ࿃֥‫ٳ‬௔ൈᇒč๭ 15-1 ᇏ clk_divĎᇛ௹ඔbperiod ູ 0 іൕࢲඏѓᆽđ‫ؿ‬ഝఖ๔ᆸ‫ؿ‬ෂඔऌđࢤ൬ఖ +ᄝ࡟ҩ֞ࢤ൬֥ྐ‫ݼ‬эӮॢ༽ሑ෿ު߶ཿՎᆴb + +RAM ॖၛ๙‫ ݖ‬APB ሹཌࣉྛ٠໙đఃఏ൓ֹᆶູ 0x3FF56800bૄ۱๙֡ॖ൐Ⴈ֥ RAM ٓຶοᅶ 64x32 bit +‫ٳ‬Ӯ 8 ۱ blockbଏಪ౦ঃ༯ૄ۱๙֡ॖ൐Ⴈ֥ block ඔਈູ 1č๙֡ 0 ൐Ⴈ block0đ๙֡ 1 ൐Ⴈ block1đၛ +Վো๷Ďb֒๙֡ n ‫ؿ‬ෂ֥ඔऌਈնႿॖ൐Ⴈ֥ block ൈđԢਔॖၛ๙‫ݖ‬஥ᇂ RMT_MEM_SIZE_CHn ࠷թఖঔ +ᅚ block ߎॖၛࣉྛ௘ஓҠቔbࡼ RMT_MEM_SIZE_CHn ࠷թఖ஥ᇂູ >1, ၩ໅ሢՎ๙֡߶ᅝႨ༯၂۱๙֥֡ +blockb๙֡ n ൐Ⴈ֥ RAM ֹᆶٓຶູ: + +start_addr_chn = 0x3FF56800 + 64 ∗ 4 ∗ n, and +end_addr_chn = 0x3FF56800 + (64 ∗ 4 ∗ n + 64 ∗ 4 ∗ RMT_MEM_SIZE_CHn)mod(512 ∗ 4) − 4 + +ູਔٝᆸඔऌ‫ۂڭ‬đॖၛ๙‫ݖ‬஥ᇂ RMT_MEM_OWNER_CHn টіൕ‫ؿ‬ഝఖࠇᆀࢤ൬ఖؓႿྐ֡ n ֥ RAM ൐ +Ⴈಃb֒஥ᇂ҂ᆞಒൈđᄵ߶Ӂള RMT_CHn_ERR ᇏ؎b + +ᇿၩğ֒षఓ৵࿃‫ؿ‬ෂଆൔčࠧᇂ໊ RMT_REG_TX_CONTI_MODEĎൈđ‫ؿ‬ෂఖ߶৵࿃‫ؿ‬ෂ๙֡ᇏ֥ඔऌčࠧ +Ֆֻ၂۱ඔऌ‫ؿ‬ෂ֞ቋު၂۱ඔऌđᄜՖֻ၂۱‫ؿ‬ෂ֞ቋު၂۱đ၇Վো๷Ďbᄝ৵࿃‫ؿ‬ෂଆൔ༯đֻ N Ց‫ֻބ‬ +N+1 Ցᆭࡗ߶Ⴕ၂۱ clk_div ᇛ௹֥ IDLE ‫׈‬௜b + +15.2.3 ൈᇒ + +ೈࡱॖၛ๙‫ݖ‬஥ᇂ RMT_REF_ALWAYS_ON_CHn ࿊ᄴૄ۱๙֥֡‫۽‬ቔൈᇒğ80 MHz APB ൈᇒࠇᆀ REF_TICKđ +౨ҕॉᅣࢫ‫ބ໊گ‬ൈᇒbࣜ‫ ݖ‬8 ໊ॺ‫ٳ‬௔ఖ‫ٳ‬௔ᆭު֥ൈᇒ‫܂‬ᄛѯ‫ؿ‬ളఖၛࠣ࠹ඔఖ൐Ⴈb‫ٳ‬௔ఖॖၛ๙‫ݖ‬஥ +ᇂ RMT_REF_CNT_RST_CHn ࣉྛ‫໊گ‬bః‫ٳ‬௔༢ඔႮ RMT_DIV_CNT_CHn ॥ᇅb + +15.2.4 ‫ؿ‬ഝఖ + +֒ RMT_TX_START_CHn ᇂູ 1 ൈđ๙֡ n ֥‫ؿ‬ഝఖष൓Ֆ RAM ᇏ‫؀‬౼ඔऌb‫ؿ‬ഝఖૄ‫؀‬౼၂Ց RAMđॖၛ +ࠆ֤ 32 ໊֥ඔऌ, ֮ 16 ໊൮༵‫ؿ‬ෂđۚ 16 ໊ఃՑ‫ؿ‬ෂb + +֒‫ؿ‬ෂ֥ඔऌਈնႿॖ൐Ⴈ֥ block ൈ, ॖၛࣉྛ௘ஓҠቔbᄝࣉྛ௘ஓҠቔభ஥ᇂ RMT_TX_LIM_CHnđ֒‫ؿ‬ +ෂ֥ඔऌਈնႿ֩Ⴟ RMT_TX_LIM_CHn ൈđ߶Ӂള RMT_CHn_TX_THR_EVENT_INT ᇏ؎đೈࡱॖၛᄝ࡟ҩ֞ +‫ھ‬ᇏ؎ᆭު۷ྍၘ‫ؿ‬ෂ֥ඔऌb֒‫ؿ‬ഝఖ‫ؿ‬ෂ֥ඔऌਈղ֞ block ֥ഈཋൈ, ‫ؿ‬ഝఖ߶ْ߭֞ start_addr_chn ࠿ +࿃࿖ߌ‫ؿ‬ෂb + +ᆺႵ֒ඔऌᇏ period ֩Ⴟ 0 ൈđ‫ؿ‬ഝఖࡼࢲඏ‫۽‬ቔѩӁള RMT_CHn_TX_END_INT ᇏ؎đಖުْ߭ॢ༽ሑ෿b +ॢ༽ሑ෿ଏಪ‫ؿ‬ෂ֥‫׈‬௜ູࢲඏѓᆽ 0 ؓႋ֥‫׈‬௜đՎൈ္ॖၛ๙‫ݖ‬஥ᇂ RMT_IDLE_OUT_EN_CHn ‫ބ‬ +RMT_IDLE_OUT_LV_CHn ট॥ᇅ‫ؿ‬ഝఖ֥ൻԛ‫׈‬௜b + +ൻԛྐ‫ݼ‬ॖၛ๙‫ݖ‬஥ᇂ RMT_CARRIER_EN_CHn ࣉྛᄛѯ‫ט‬ᇅbᄛѯ֥௔ੱॖၛ๙‫ݖ‬ + +ুᶈྐ༏॓࠯ 365 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 15 ‫ޣ‬ຓဪ॥ (RMT) + +RMT_CARRIER_HIGH_CHn ‫ ބ‬RMT_CARRIER_LOW_CHn ࣉྛഡᇂb + +15.2.5 ࢤ൬ఖ + +֒ RMT_RX_EN_CHn ᇂູ 1 ൈđ࠹ඔఖष൓ҩਈྐ‫֥ݼ‬Ӊ؇ѩᄝ༯၂Ցྐ‫ݼ‬ခэ߄ൈࡼഈՑ֥ྐ‫׈֮ۚݼ‬௜ +ၛࠣӉ؇ᆴթೆ RAMb֒‫ؿ‬ഝఖӉൈࡗ࡟ҩ҂֞ྐ‫ݼ‬ခэ߄ࠧ࠹ඔఖ֥ᆴնႿ֩Ⴟ RMT_IDLE_THRES_CHn +ൈđࢤ൬ఖࢲඏࢤ൬‫ݖ‬ӱđӁള RMT_CHn_RX_END_INT ᇏ؎ѩْ߭ॢ༽ሑ෿b + +ൻೆྐ‫ݼ‬ॖၛ๙‫ݖ‬ᇂ໊ RMT_RX_FILTER_EN_CHn টࣉྛੲѯbੲѯఖॖၛੲԢྐ‫ॺݼ‬؇ཬႿ +RMT_RX_FILTER_THRES_CHn ۱ APB ൈᇒᇛ௹֥ઝԊb + +֒ RMT ଆॶ҂‫۽‬ቔൈđॖၛ๙‫ݖ‬஥ᇂ RMT_MEM_PD ࠷թఖ൐ RAM ‫۽‬ቔႿ֮‫ݻۿ‬ଆൔb + +15.2.6 ᇏ؎ + + • RMT_CHn_TX_THR_EVENT_INTğ‫ؿ‬ഝఖૄ‫ؿ‬ෂ RMT_CHn_TX_LIM_REG ֥ඔऌđࠧԨ‫ؿ‬၂ՑՎᇏ؎b + + • RMT_CHn_TX_END_INTğ֒‫ؿ‬ഝఖ๔ᆸ‫ؿ‬ෂྐ‫ݼ‬ൈ, ࠧԨ‫ؿ‬Վᇏ؎b + + • RMT_CHn_RX_END_INTğ֒ࢤ൬ఖ๔ᆸࢤ൬ྐ‫ݼ‬ൈ, ࠧԨ‫ؿ‬Վᇏ؎b + +15.3 ࠷թఖਙі + +଀ӫ ૭ඍ ֹᆶ ٠໙ +஥ᇂ࠷թఖ +RMT_CH0CONF0_REG ๙֡ 0 ֥஥ᇂ࠷թఖ 0 0x3FF56020 ‫؀‬/ཿ +RMT_CH0CONF1_REG ๙֡ 0 ֥஥ᇂ࠷թఖ 1 0x3FF56024 ‫؀‬/ཿ +RMT_CH1CONF0_REG ๙֡ 1 ֥஥ᇂ࠷թఖ 0 0x3FF56028 ‫؀‬/ཿ +RMT_CH1CONF1_REG ๙֡ 1 ֥஥ᇂ࠷թఖ 1 0x3FF5602C ‫؀‬/ཿ +RMT_CH2CONF0_REG ๙֡ 2 ֥஥ᇂ࠷թఖ 0 0x3FF56030 ‫؀‬/ཿ +RMT_CH2CONF1_REG ๙֡ 2 ֥஥ᇂ࠷թఖ 1 0x3FF56034 ‫؀‬/ཿ +RMT_CH3CONF0_REG ๙֡ 3 ֥஥ᇂ࠷թఖ 0 0x3FF56038 ‫؀‬/ཿ +RMT_CH3CONF1_REG ๙֡ 3 ֥஥ᇂ࠷թఖ 1 0x3FF5603C ‫؀‬/ཿ +RMT_CH4CONF0_REG ๙֡ 4 ֥஥ᇂ࠷թఖ 0 0x3FF56040 ‫؀‬/ཿ +RMT_CH4CONF1_REG ๙֡ 4 ֥஥ᇂ࠷թఖ 1 0x3FF56044 ‫؀‬/ཿ +RMT_CH5CONF0_REG ๙֡ 5 ֥஥ᇂ࠷թఖ 0 0x3FF56048 ‫؀‬/ཿ +RMT_CH5CONF1_REG ๙֡ 5 ֥஥ᇂ࠷թఖ 1 0x3FF5604C ‫؀‬/ཿ +RMT_CH6CONF0_REG ๙֡ 6 ֥஥ᇂ࠷թఖ 0 0x3FF56050 ‫؀‬/ཿ +RMT_CH6CONF1_REG ๙֡ 6 ֥஥ᇂ࠷թఖ 1 0x3FF56054 ‫؀‬/ཿ +RMT_CH7CONF0_REG ๙֡ 7 ֥஥ᇂ࠷թఖ 0 0x3FF56058 ‫؀‬/ཿ +RMT_CH7CONF1_REG ๙֡ 7 ֥஥ᇂ࠷թఖ 1 0x3FF5605C ‫؀‬/ཿ +ᇏ؎࠷թఖ +RMT_INT_RAW_REG ჰ൓ᇏ؎ሑ෿ 0x3FF560A0 ᆺ‫؀‬ +RMT_INT_ST_REG ႅзᇏ؎ሑ෿ 0x3FF560A4 ᆺ‫؀‬ +RMT_INT_ENA_REG ᇏ؎൐ି໊ 0x3FF560A8 ‫؀‬/ཿ +RMT_INT_CLR_REG ᇏ؎ౢԢ໊ 0x3FF560AC ᆺཿ +ᄛѯᅝॢб࠷թఖ +RMT_CH0CARRIER_DUTY_REG ๙֡ 0 ֥ᅝॢб஥ᇂ࠷թఖ 0x3FF560B0 ‫؀‬/ཿ +RMT_CH1CARRIER_DUTY_REG ๙֡ 1 ֥ᅝॢб஥ᇂ࠷թఖ 0x3FF560B4 ‫؀‬/ཿ + +ুᶈྐ༏॓࠯ 366 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 15 ‫ޣ‬ຓဪ॥ (RMT) + +଀ӫ ૭ඍ ֹᆶ ٠໙ +RMT_CH2CARRIER_DUTY_REG ๙֡ 2 ֥ᅝॢб஥ᇂ࠷թఖ 0x3FF560B8 ‫؀‬/ཿ +RMT_CH3CARRIER_DUTY_REG ๙֡ 3 ֥ᅝॢб஥ᇂ࠷թఖ 0x3FF560BC ‫؀‬/ཿ +RMT_CH4CARRIER_DUTY_REG ๙֡ 4 ֥ᅝॢб஥ᇂ࠷թఖ 0x3FF560C0 ‫؀‬/ཿ +RMT_CH5CARRIER_DUTY_REG ๙֡ 5 ֥ᅝॢб஥ᇂ࠷թఖ 0x3FF560C4 ‫؀‬/ཿ +RMT_CH6CARRIER_DUTY_REG ๙֡ 6 ֥ᅝॢб஥ᇂ࠷թఖ 0x3FF560C8 ‫؀‬/ཿ +RMT_CH7CARRIER_DUTY_REG ๙֡ 7 ֥ᅝॢб஥ᇂ࠷թఖ 0x3FF560CC ‫؀‬/ཿ +‫ؿ‬ෂ൙ࡱ஥ᇂ࠷թఖ +RMT_CH0_TX_LIM_REG ๙֡ 0 ֥ Tx ൙ࡱ஥ᇂ࠷թఖ 0x3FF560D0 ‫؀‬/ཿ +RMT_CH1_TX_LIM_REG ๙֡ 1 ֥ Tx ൙ࡱ஥ᇂ࠷թఖ 0x3FF560D4 ‫؀‬/ཿ +RMT_CH2_TX_LIM_REG ๙֡ 2 ֥ Tx ൙ࡱ஥ᇂ࠷թఖ 0x3FF560D8 ‫؀‬/ཿ +RMT_CH3_TX_LIM_REG ๙֡ 3 ֥ Tx ൙ࡱ஥ᇂ࠷թఖ 0x3FF560DC ‫؀‬/ཿ +RMT_CH4_TX_LIM_REG ๙֡ 4 ֥ Tx ൙ࡱ஥ᇂ࠷թఖ 0x3FF560E0 ‫؀‬/ཿ +RMT_CH5_TX_LIM_REG ๙֡ 5 ֥ Tx ൙ࡱ஥ᇂ࠷թఖ 0x3FF560E4 ‫؀‬/ཿ +RMT_CH6_TX_LIM_REG ๙֡ 6 ֥ Tx ൙ࡱ஥ᇂ࠷թఖ 0x3FF560E8 ‫؀‬/ཿ +RMT_CH7_TX_LIM_REG ๙֡ 7 ֥ Tx ൙ࡱ஥ᇂ࠷թఖ 0x3FF560EC ‫؀‬/ཿ +ః෰࠷թఖ +RMT_APB_CONF_REG RMT ๙Ⴈ஥ᇂ࠷թఖ 0x3FF560F0 ‫؀‬/ཿ + +15.4 ࠷թఖ + +Чཬࢫও‫ݼ‬ᇏֹ֥ᆶनູཌྷؓႿ RMT ࠎֹᆶֹ֥ᆶொ၍ਈčཌྷֹؓᆶĎđऎุࠎֹᆶ࡮ᅣࢫ 1 ༢๤‫ބ‬թԥఖ ᇏ +֥і 1-6 ຓഡֹᆶ႘ഝb࠷թఖधֹؓᆶ࡮ᅣࢫ 15.3 ࠷թఖਙіb + + Register 15.1. RMT_CHnCONF0_REG (n: 0­7) (0x0020+8*n) + +(reservReMd)T_RMMETM__RCPMADRT_RCIEARR_ROIEURRT_M_ELTVN___MCCEHHMnn_SIZE_CHn RMT_IDLE_THRES_CHn RMT_DIV_CNT_CHn + 0x01000 +31 30 29 28 27 24 23 87 0 + +0x0 0 1 1 0x01 0x002 Reset + +RMT_MEM_PD ႨႿࢆ֮ RMT RAM ֥‫ݻۿ‬čࣇթᄝႿ RMT_CH0CONF0 ࠷թఖĎb1ğRAM ԩႿ + ֮‫ݻۿ‬ሑ෿Ġ0ğRAM ԩႿᆞӈ‫۽‬ቔሑ෿bč‫؀‬/ཿĎ + +RMT_CARRIER_OUT_LV_CHn ႨႿ஥ᇂᄛѯ‫ט‬ᇅٚൔb0ğᄛѯࡆᄛᄝ֮‫׈‬௜ൻԛྐ‫ݼ‬ഈĠ1ğᄛ + ѯࡆᄛᄝۚ‫׈‬௜ൻԛྐ‫ݼ‬ഈbč‫؀‬/ཿĎ + +RMT_CARRIER_EN_CHn ๙֡ n ֥ᄛѯ‫ט‬ᇅ൐ି໊b1ğ൐ିᄛѯ‫ט‬ᇅĠ0: ܱоᄛѯ‫ט‬ᇅbč‫؀‬/ཿĎ + +RMT_MEM_SIZE_CHn ஥ᇂ๙֡ n ֥ block նཬbč‫؀‬/ཿĎ + +RMT_IDLE_THRES_CHn ֒ ࢤ ൬ ఖ Ӊ ൈ ࡗ ࡟ ҩ ҂ ֞ ྐ ‫ ݼ‬ခ э ߄ ࠧ ࠹ ඔ ఖ ֥ ᆴ ն Ⴟ ֩ Ⴟ + RMT_IDLE_THRES_CHn ൈđࢤ൬ఖࢲඏࢤ൬‫ݖ‬ӱbč‫؀‬/ཿĎ + +RMT_DIV_CNT_CHn ႨႿഡᇂ๙֡ n ֥‫ٳ‬௔ఖ֥‫ٳ‬௔༢ඔbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 367 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 15 ‫ޣ‬ຓဪ॥ (RMT) + + Register 15.2. RMT_CHnCONF1_REG (n: 0­7) (0x0024+8*n) + + (reserved) RMT_RIDMLTE__RIODMULTET___RROEMENUFT_T__C_ARLHLVEnW_FC_ACHYNSn_TO_RNS_TC_HCnHRnMT_RX_FILTER_THRESR_CMHTn_RRMX_TF_IRTLTMXE_TCR_(_OMrEeNEsNTeM_Ir_Cv_RMeOHMdOWnT) D_NRMEEM_ERCTM_H_C_RMnHRMEnDTM__R_RRWSMXTR_T_E__CNRTHX_SnC_TSH_TCnAHRnT_CHn + +31 20 19 18 17 16 15 87 6 5 4 3 2 1 0 + + 0x0000 0000 0x00F 0 0 1 0 0 0 0 0 Reset + + RMT_IDLE_OUT_EN_CHn ๙֡ n ໊Ⴟॢ༽ሑ෿༯֥ൻԛ൐ି॥ᇅ໊bč‫؀‬/ཿĎ + + RMT_IDLE_OUT_LV_CHn ஥ᇂ๙֡ n ໊Ⴟॢ༽ሑ෿༯֥ൻԛྐ‫׈ݼ‬௜bč‫؀‬/ཿĎ + + RMT_REF_ALWAYS_ON_CHn ႨႿ࿊ᄴ๙֥֡ࠎԤൈᇒb1ğclk_apbĠ0ğclk_refbč‫؀‬/ཿĎ + + RMT_REF_CNT_RST_CHn ‫໊گ‬๙֡ n ֥ൈᇒ‫ٳ‬௔ఖbč‫؀‬/ཿĎ + + RMT_RX_FILTER_THRES_CHn ࢤ ൬ ଆ ൔ ༯đ ๙ ֡ n ޭ੻ପུॺ؇ཬႿ + + RMT_RX_FILTER_THRES_CHn ۱ APB ൈᇒᇛ௹֥ઝԊbč‫؀‬/ཿĎ + + RMT_RX_FILTER_EN_CHn ๙֡ n ֥ࢤ൬ੲѯ൐ି໊bč‫؀‬/ཿĎ + + RMT_TX_CONTI_MODE_CHn ‫ؿ‬ෂࢲඏൈđ‫ؿ‬ഝఖᇗఓ‫ؿ‬ෂđ҂ࣉೆॢ༽ሑ෿đ֝ᇁᇗ‫گ‬ൻԛྐ + ‫ݼ‬bč‫؀‬/ཿĎ + + RMT_MEM_OWNER_CHn ѓᆽ๙֡ n ֥ RAM ൐Ⴈಃb1: ࢤ൬ఖĠ0: ‫ؿ‬ഝఖbč‫؀‬/ཿĎ + + RMT_MEM_RD_RST_CHn ႨႿ‫໊گ‬๙֡ n ֥‫ؿ‬ഝఖ֥ RAM ‫؀‬౼ֹᆶbč‫؀‬/ཿĎ + + RMT_MEM_WR_RST_CHn ႨႿ‫໊گ‬๙֡ n ֥ࢤ൬ఖ֥ RAM ཿֹᆶbč‫؀‬/ཿĎ + + RMT_RX_EN_CHn ႨႿ൐ି๙֡ n ֥ࢤ൬ఖbč‫؀‬/ཿĎ + + RMT_TX_START_CHn ႨႿ൐ି๙֡ n ֥‫ؿ‬ഝఖbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 368 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 15 ‫ޣ‬ຓဪ॥ (RMT) + + Register 15.3. RMT_INT_RAW_REG (0x00A0) + + RMT_RCMHT7__RCTMXH_T6T__HRCTRMXH__T5ET__HVRCTERMXHN__T4ETT__HV_RCTIERMNXHN__TT3ETT___HV_RRCTIERMANXHN__WTT2ETT___HV_RRCTIERMANXHN__WTT1ETT___HV_RRCTIERMANXHN__WTT0ETT___HV_RRCTIERMANXHN__WTT7ETT___HV_RRCEIERMANRHN_WTRT7ET____V_RRCIRNIEMANXHTNWT_T7_TE___R_RRNCTAIMANXDHW_WT_T6E_I__NNRRCETDMARH_W_RTR6I_N__ARCIRTWNMXH_TR_T6_E_A_RRNCTWAMXDHW__T5EI__NNRCETDMRH__RTR5I_N__ARCIRTWNMXH_TR_T5_E_A_RRNCTWAMXDHW__T4EI__NNRCETDMRH__RTR4I_N__ARCIRTWNMXH_TR_T4_E_A_RRNCTWAMXDHW__T3EI__NNRCETDMRH__RTR3I_N__ARCIRTWNMXH_TR_T3_E_A_RRNCTWAMXDHW__T2EI__NNRCETDMRH__RTR2I_N__ARCIRTWNMXH_TR_T2_E_A_RRNCTWAMXDHW__T1EI__NNRCETDMRH__RTR1I_N__ARCIRTWNMXH_TR_T1_E_A_RRNCTWAMXDHW__T0EI__NNRCETDMRH__RTR0I_N__ACIRTWNXH_TR_0_EA_RNTWAXDW__EINNTD__RINATW_RAW + + 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RMT_CHn_TX_THR_EVENT_INT_RAW RMT_CHn_TX_THR_EVENT_INT ᇏ ؎ ֥ ჰ ൓ ᇏ ؎ ሑ ෿ + ໊bčᆺ‫؀‬Ď + + RMT_CHn_ERR_INT_RAW RMT_CHn_ERR_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RMT_CHn_RX_END_INT_RAW RMT_CHn_RX_END_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RMT_CHn_TX_END_INT_RAW RMT_CHn_TX_END_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + + Register 15.4. RMT_INT_ST_REG (0x00A4) + + RMT_RCMHT7__RCTMXH_T6T__HRCTRMXH__T5ET__HVRCTERMXHN__T4ETT__HV_RCTIERMNXHN__TT3ETT___HV_RSCTIERTMNXHN__TT2ETT___HV_RSCTIERTMNXHN__TT1ETT___HV_RSCTIERTMNXHN__TT0ETT___HV_RSCTIERTMNXHN__TT7ETT___HV_RSCEIERTMNRHN_TRT7ET____V_RSCIRNIETMNXHTNT_T7_TE___S_RSNCTTITMNXDH_T_T6E_I__NNRSCETTDMRH__RTS6I_N__TRCIRTNMXH_TS_T6_ET__SRNCTTMXDH__T5EI__NNRCETDMRH__RTS5I_N__TRCIRTNMXH_TS_T5_ET__SRNCTTMXDH__T4EI__NNRCETDMRH__RTS4I_N__TRCIRTNMXH_TS_T4_ET__SRNCTTMXDH__T3EI__NNRCETDMRH__RTS3I_N__TRCIRTNMXH_TS_T3_ET__SRNCTTMXDH__T2EI__NNRCETDMRH__RTS2I_N__TRCIRTNMXH_TS_T2_ET__SRNCTTMXDH__T1EI__NNRCETDMRH__RTS1I_N__TRCIRTNMXH_TS_T1_ET__SRNCTTMXDH__T0EI__NNRCETDMRH__RTS0I_N__TCIRTNXH_TS_0_ET_SNTTXD__EINNTD__SINTT_ST + + 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RMT_CHn_TX_THR_EVENT_INT_ST RMT_CHn_TX_THR_EVENT_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ + ‫؀‬Ď + + RMT_CHn_ERR_INT_ST RMT_CHn_ERR_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RMT_CHn_RX_END_INT_ST RMT_CHn_RX_END_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RMT_CHn_TX_END_INT_ST RMT_CHn_TX_END_INT ᇏ؎֥ႅзᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 369 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 15 ‫ޣ‬ຓဪ॥ (RMT) + + Register 15.5. RMT_INT_ENA_REG (0x00A8) + + RMT_RCMHT7__RCTMXH_T6T__HRCTRMXH__T5ET__HVRCTERMXHN__T4ETT__HV_RCTIERMNXHN__TT3ETT___HV_RECTIENRMNXHN__ATT2ETT___HV_RECTIENRMNXHN__ATT1ETT___HV_RECTIENRMNXHN__ATT0ETT___HV_RECTIENRMNXHN__ATT7ETT___HV_RECEIENRMNRHN_ATRT7ET____V_RECIRNIENMNXHTNAT_T7_TE___E_RENCTNINMNXDHA_AT_T6E_I__NNRECETNDMRH_A_RTE6I_N__NRCIRTANMXH_TE_T6_EN__ERNCTANMXDHA__T5EI__NNRCETDMRH__RTE5I_N__NRCIRTANMXH_TE_T5_EN__ERNCTANMXDHA__T4EI__NNRCETDMRH__RTE4I_N__NRCIRTANMXH_TE_T4_EN__ERNCTANMXDHA__T3EI__NNRCETDMRH__RTE3I_N__NRCIRTANMXH_TE_T3_EN__ERNCTANMXDHA__T2EI__NNRCETDMRH__RTE2I_N__NRCIRTANMXH_TE_T2_EN__ERNCTANMXDHA__T1EI__NNRCETDMRH__RTE1I_N__NRCIRTANMXH_TE_T1_EN__ERNCTANMXDHA__T0EI__NNRCETDMRH__RTE0I_N__NCIRTANXH_TE_0_EN_ENTANXDA__EINNTD__EINNTA_ENA + + 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RMT_CHn_TX_THR_EVENT_INT_ENA RMT_CHn_TX_THR_EVENT_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + RMT_CHn_ERR_INT_ENA RMT_CHn_ERROR_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + RMT_CHn_RX_END_INT_ENA RMT_CHn_RX_END_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + RMT_CHn_TX_END_INT_ENA RMT_CHn_TX_END_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + + Register 15.6. RMT_INT_CLR_REG (0x00AC) + + RMT_RCMHT7__RCTMXH_T6T__HRCTRMXH__T5ET__HVRCTERMXHN__T4ETT__HV_RCTIERMNXHN__TT3ETT___HV_RCCTIERMNXLHNR__TT2ETT___HV_RCCTIERMNXLHNR__TT1ETT___HV_RCCTIERMNXLHNR__TT0ETT___HV_RCCTIERMNXLHNR__TT7ETT___HV_RCCEIERMNLRHNR_TRT7ET____V_RCCIRNIEMNLXHTNRT_T7_TE___C_RCNCTLIMNXLDHRR_T_T6E_I__NNRCCETDMLRH_R_RTC6I_N__LRCIRRTNMXH_TC_T6_E__LCRNCTRLMXDHR__T5EI__NNRCETDMRH__RTC5I_N__LRCIRRTNMXH_TC_T5_E__LCRNCTRLMXDHR__T4EI__NNRCETDMRH__RTC4I_N__LRCIRRTNMXH_TC_T4_E__LCRNCTRLMXDHR__T3EI__NNRCETDMRH__RTC3I_N__LRCIRRTNMXH_TC_T3_E__LCRNCTRLMXDHR__T2EI__NNRCETDMRH__RTC2I_N__LRCIRRTNMXH_TC_T2_E__LCRNCTRLMXDHR__T1EI__NNRCETDMRH__RTC1I_N__LRCIRRTNMXH_TC_T1_E__LCRNCTRLMXDHR__T0EI__NNRCETDMRH__RTC0I_N__LCIRRTNXH_TC_0_E_LCNTRLXDR__EINNTD__CINLRT_CLR + + 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RMT_CHn_TX_THR_EVENT_INT_CLR ႨႿౢԢ RMT_CHn_TX_THR_EVENT_INT ᇏ؎bčᆺཿĎ + RMT_CHn_ERR_INT_CLR ႨႿౢԢ RMT_CHn_ERRINT ᇏ؎bčᆺཿĎ + RMT_CHn_RX_END_INT_CLR ႨႿౢԢ RMT_CHn_RX_END_INT ᇏ؎bčᆺཿĎ + RMT_CHn_TX_END_INT_CLR ႨႿౢԢ RMT_CHn_TX_END_INT ᇏ؎bčᆺཿĎ + +ুᶈྐ༏॓࠯ 370 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 15 ‫ޣ‬ຓဪ॥ (RMT) + + Register 15.7. RMT_CHnCARRIER_DUTY_REG (n: 0­7) (0x00B0+4*n) + + RMT_CARRIER_HIGH_CHn RMT_CARRIER_LOW_CHn + +31 16 15 0 + + 0x00040 0x00040 Reset + + RMT_CARRIER_HIGH_CHn ႨႿ஥ᇂ๙֡ n ֥ᄛѯ֥ۚ‫׈‬௜ൈᇒᇛ௹bൈᇒჷॖၛ൞ REF_TICK + ࠇ APB_CLKbč‫؀‬/ཿĎ + + RMT_CARRIER_LOW_CHn ႨႿ஥ᇂ๙֡ n ֥ᄛѯ֥֮‫׈‬௜ൈᇒᇛ௹bൈᇒჷॖၛ൞ REF_TICK + ࠇ APB_CLKbč‫؀‬/ཿĎ + + Register 15.8. RMT_CHn_TX_LIM_REG (n: 0­7) (0x00D0+4*n) + + (reserved) RMT_TX_LIM_CHn + +31 98 0 + + 0x000000 0x080 Reset + + RMT_TX_LIM_CHn ֒๙֡‫ؿ‬ෂ֥ඔऌਈնႿᆷ‫ ֥ק‬block նཬđᄵӁള TX_THR_EVENT ᇏ + ؎bč‫؀‬/ཿĎ + + Register 15.9. RMT_APB_CONF_REG (0x00F0) + + (reserved) RMT_RMMETM__MTEXM_W_ARCACP_EESNS_EN + +31 21 0 + + 0x00000000 0 0 Reset + + RMT_MEM_TX_WRAP_EN ௘ஓҠቔ൐ି໊b֒‫ؿ‬ഝఖ‫ؿ‬ෂ֥ඔऌਈնႿ block նཬđ‫ؿ‬ഝఖࡼ࠿ + ࿃Ֆֻ၂ሳࢫष൓‫ؿ‬ෂඔऌbč‫؀‬/ཿĎ + + RMT_MEM_ACCESS_EN сྶᇂ 1đ‫ڎ‬ᄵ໭‫م‬٠໙ RMT թԥఖb + +ুᶈྐ༏॓࠯ 371 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +16.1 ‫ۀ‬ඍ + +‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (MCPWM) ຓഡႨႿ‫׈ބࠏ׈‬ჷ॥ᇅb෱ิ‫܂‬ਔੂ۱ PWM ൻԛđॖᄝࠫᇕຉ௪ࢲ‫ܒ‬ᇏᄎ +ྛbӈ࡮֥ຉ௪ࢲ‫ܒ‬ᆭ၂൞Ⴈ၂ؓ PWM ൻԛট౺‫ ׮‬H ూၛ॥ᇅ‫ࠏ׈‬࿈ሇ෎؇‫ބ‬࿈ሇٚཟb + +MCPWM ֥ൈ྽‫ބ‬॥ᇅሧჷ‫ູٳ‬ਆᇕᇶေো྘֥ଆॶğPWM ‫ק‬ൈఖ‫ ބ‬PWM Ҡቔఖbૄ۱ PWM ‫ק‬ൈఖิ‫܂‬ +‫ק‬ൈҕॉđॖၛሱႮᄎྛđࠇ๝҄֞ః෰‫ק‬ൈఖࠇຓ҆ჷbૄ۱ PWM ҠቔఖऎႵႨႿູ၂۱ PWM ๙֡ളӮ +ѯྙ֥ؓ෮Ⴕ॥ᇅሧჷbMCPWM ຓഡߎЇ‫ݣ‬ህႨѽࠆଆॶđႨႿླေࣚಒ‫ק‬ൈຓ҆൙ࡱ֥༢๤b + +ESP32 Ⴕਆ۱ MCPWM ຓഡđ‫ٳ‬љ൞ MCPWM0 ‫ ބ‬MCPWM1b෱ૌ֥॥ᇅ࠷թఖ‫ٳ‬љ໊ႿՖֹᆶ +0x3FF5E000 ‫ ބ‬0x3FF6C000 ष൓֥ 4 KB ଽթᇏbབྷ࡮ᅣࢫ 16.4 ࠷թఖਙіb + +16.2 ᇶေหྟ + +ૄ۱ MCPWM ຓഡ‫׻‬Ⴕ၂۱ൈᇒ‫ٳ‬௔ఖčყ‫ٳ‬௔ఖĎđ೘۱ PWM ‫ק‬ൈఖđ೘۱ PWM Ҡቔఖ‫ބ‬၂۱ѽࠆଆॶb +๭ 16-1 ᅚൕਔ MCPWM ֥ଆॶ‫ࢤބ‬१ഈ֥ྐ‫ݼ‬bPWM ‫ק‬ൈఖႨႿളӮ‫ק‬ൈҕॉbPWM Ҡቔఖࡼ۴ऌ‫ק‬ൈҕ +ॉളӮ෮ླ֥ѯྙb๙‫ݖ‬஥ᇂđ಩၂ PWM Ҡቔఖॖၛ൐Ⴈ಩၂ PWM ‫ק‬ൈఖ֥‫ק‬ൈҕॉb҂๝֥ PWM Ҡቔ +ఖॖၛ൐Ⴈཌྷ๝֥ PWM ‫ק‬ൈఖ֥‫ק‬ൈҕॉটӁള PWM ྐ‫ݼ‬bՎຓđ҂๝֥ PWM Ҡቔఖ္ॖၛ൐Ⴈ҂๝֥ +PWM ‫ק‬ൈఖ֥ᆴটളӮֆ‫ ֥׿‬PWM ྐ‫ݼ‬b҂๝֥ PWM ‫ק‬ൈఖ္ॖࣉྛ๝҄b + + ๭ 16­1. MCPWM ຓഡ‫ۀ‬ফ + +ၛ༯൞๭ 16-1 ᇏଆॶ֥‫ۀିۿ‬ඍğ + • PWM ‫ק‬ൈఖ 0đ1 ‫ ބ‬2 + – ૄ۱ PWM ‫ק‬ൈఖ‫׻‬Ⴕ၂۱ህႨ֥ 8 ໊ൈᇒყ‫ٳ‬௔ఖb + – PWM ‫ק‬ൈఖᇏ֥ 16 ໊࠹ඔ֥‫۽‬ቔଆൔЇওğ‫־‬ᄹ࠹ඔଆൔđ‫࠹ࡨ־‬ඔଆൔđ‫־‬ᄹ‫ࡨ־‬࿖ߌ࠹ඔଆ + +ুᶈྐ༏॓࠯ 372 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + ൔb + – ႗ࡱ๝҄ॖၛԨ‫ ؿ‬PWM ‫ק‬ൈఖᇗᄛ, ᇗᄛᆴ໊Ⴟཌྷ໊࠷թఖᇏĠ๝ൈԨ‫ؿ‬ყ‫ٳ‬௔֥ᇗఓđՖ‫ط‬๝҄ + + ‫ק‬ൈఖ֥ൈᇒb๝҄ჷॖၛটሱ಩‫ ޅ‬GPIO ࠇ಩‫ޅ‬ః෰ PWM ‫ק‬ൈఖ֥ sync_outb + • PWM Ҡቔఖ 0đ1 ‫ ބ‬2 + + – ૄ۱ PWM ҠቔఖႵਆ۱ PWM ൻԛčPWMxA ‫ ބ‬PWMxBĎđॖၛᄝؓӫ‫ބ‬٤ؓӫ஥ᇂᇏ‫׿‬৫‫۽‬ቔb + – ೈࡱၳ҄Ⴊ༵॥ᇅ PWM ྐ‫ݼ‬b + – ඵ౵ᄝഈശခ‫ބ‬༯ࢆခॖ஥ᇂđѩॖ‫ٳ‬љഡᇂb + – ෮Ⴕ൙ࡱ‫׻‬ॖԨ‫ ؿ‬CPU ᇏ؎b + – ๙‫ۚݖ‬௔ᄛѯྐ‫טݼ‬ᇅ PWM ൻԛđᄝ൐Ⴈэ࿢ఖ‫ۯ‬৖ᅅࠞ౺‫׮‬ఖൈ٤ӈႵႨb + – ᇛ௹đൈࡗՄ࠷թఖ‫ބ‬ః෰ᇶေ֥॥ᇅ࠷թఖႵ႕ሰ࠷թఖđ۷ྍٚ‫م‬ਲࠃb + • ‫ܣ‬ᅰ࡟ҩଆॶ + – ԛགྷ‫ܣ‬ᅰൈđॖ࿊ᄴᄝᇯᇛ௹ଆൔࠇ၂Ցྟଆൔ༯ԩ৘b + – ‫ܣ‬ᅰ่ࡱॖ఼ᇅ PWM ൻԛۚࠇ֮‫׈‬௜b + • ѽࠆଆॶ + – ࿈ሇ‫֥ࠏ׈‬෎؇ҩਈč২ೂđႨࠉ‫غ‬Ԯ‫ۋ‬ఖ࡟ҩ֥Ԃྙ৽੽Ďb + – ໊ᇂԮ‫ۋ‬ఖઝԊᆭࡗ֥ࡗ‫ۯ‬ൈࡗҩਈb + – ઝԊ྽ਙྐ‫֥ݼ‬ᇛ௹‫ބ‬ᅝॢбҩਈb + – Ֆᅝॢбщ઒֥‫׈‬ੀ/‫׈‬࿢Ԯ‫ۋ‬ఖ֝ԛ֥ࢳ઒‫׈‬ੀࠇ‫׈‬࿢ᆒ‫ږ‬b + – 3 ۱‫׿‬৫֥ѽࠆ๙֡đ۲ऎС၂۱ 32 ໊֥ൈࡗՄ࠷թఖb + – ൻೆѽࠆྐ‫ݼ‬ॖၛყ‫ٳ‬௔đшခࠞྟॖ࿊b + – ѽࠆ‫ק‬ൈఖॖၛა PWM ‫ק‬ൈఖࠇຓ҆ྐ‫ݼ‬๝҄b + – 3 ۱ѽࠆ๙֡ഈ‫׻‬ॖၛӁളᇏ؎b + +ুᶈྐ༏॓࠯ 373 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +16.3 ଆॶ + +16.3.1 ଆॶ‫ۀ‬ඍ + +ၛ༯ิ‫ ܂‬MCPWM ܱ࡯ଆॶ֥ᇶေ஥ᇂҕඔb‫ט‬ᆜห‫ק‬ҕඔđ২ೂ PWM ‫ק‬ൈఖ֥๝҄ჷđ౨ҕॉֻ 16.3.2 +ᅣb + +16.3.1.1 ყ‫ٳ‬௔ఖଆॶ + + ๭ 16­2. ყ‫ٳ‬௔ఖଆॶ +஥ᇂҕඔğ + + • ۴ऌ CLK_160M ؓ PWM ൈᇒࣉྛ‫ٳ‬௔b + +16.3.1.2 ‫ק‬ൈఖଆॶ + + ๭ 16­3. ‫ק‬ൈఖଆॶ + +஥ᇂҕඔğ + • ഡᇂ PWM ‫ק‬ൈఖ֥௔ੱࠇᇛ௹b + • ஥ᇂ‫ק‬ൈఖ֥‫۽‬ቔଆൔğ + – ‫־‬ᄹ࠹ඔଆൔğႨႿ٤ؓӫ PWM ൻԛ + – ‫࠹ࡨ־‬ඔଆൔğႨႿ٤ؓӫ PWM ൻԛ + – ‫־‬ᄹ‫ࡨ־‬࿖ߌ࠹ඔଆൔğႨႿႿؓӫ PWM ൻԛ + • ஥ᇂೈࡱࠇ႗ࡱ๝҄‫ؿ‬ളൈ֥ᇗᄛཌྷ໊đЇওᆴ‫ބ‬ٚཟb + +ুᶈྐ༏॓࠯ 374 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + • ๙‫ݖ‬႗ࡱࠇೈࡱ๝҄൐ PWM ‫ק‬ൈఖдՎ๝҄b + • ഡᇂ PWM ‫ק‬ൈఖ֥๝҄ൻೆჷđ7 ࿊ 1ğ + + – 3 ۱ PWM ‫ק‬ൈఖ֥๝҄ൻԛ + – টሱ GPIO इᆔ֥ 3 ۱๝҄ྐ‫ݼ‬čSYNC0đSYNC1đSYNC2Ď + – ໃ࿊ᄴ๝҄ൻೆྐ‫ݼ‬ + • ஥ᇂ PWM ‫ק‬ൈఖ֥๝҄ൻԛჷࠇൻԛൈख़đ4 ࿊ 1ğ + – ๝҄ൻೆྐ‫ݼ‬ + – PWM ‫ק‬ൈఖ֥ᆴູ 0 ൈ + – PMW ‫ק‬ൈఖ֥ᆴ֩Ⴟൈᇒᇛ௹֥ᆴ + – ીႵളӮ๝҄ൻԛ + • ஥ᇂᇛ௹۷ྍٚൔb + +16.3.1.3 Ҡቔఖଆॶ + + ๭ 16­4. Ҡቔఖଆॶ +і 16-1 ਙईҠቔఖଆॶ֥ᇶေ஥ᇂҕඔb + +ুᶈྐ༏॓࠯ 375 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +ሰଆॶ і 16­1. Ҡቔఖଆॶ֥஥ᇂҕඔ +PWM ളӮఖ +ඵ౵ളӮఖ ஥ᇂҕඔĔ࿊ཛ +PWM ᄛѯ + • ഡᇂ PWMxA ‫ބ‬Ĕࠇ PWMxB ൻԛ֥ PWM ᅝॢб +‫ܣ‬ᅰԩ৘ఖ • ഡᇂ‫ק‬ൈ൙ࡱ‫ؿ‬ള֥ൈࡗ + • ഡᇂ‫ؿ‬ള‫ק‬ൈ൙ࡱൈҐ౼֥ྛ‫׮‬ğ + + – ‫ڿ‬э PWMxA ‫ބ‬Ĕࠇ PWMxB ൻԛູۚࠇ֮ + – ࡼ PWMxA ‫ބ‬Ĕࠇ PWMxB ౼ّ + – ҂ؓൻԛᆳྛ಩‫ޅ‬Ҡቔ + • ๙‫ݖ‬ᆰࢤ S/W ॥ᇅ఼ᇅ PWM ൻԛ֥ሑ෿ + • ᄝ PWM ൻԛ֥ഈശ‫ބ‬Ĕࠇ༯ࢆшခഈᄹࡆඵ౵ + • ஥ᇂՎሰଆॶ֥۷ྍٚൔ + + • ॥ᇅۚҧ‫֮ބ‬ҧषܱᆭࡗ֥޺Ҁඵ౵ܱ༢ + • ᆷ‫ק‬ഈശခඵ౵ + • ᆷ‫ק‬༯ࢆခඵ౵ + • ಡ‫ݖ‬ඵ౵‫ؿ‬ളఖଆॶđPWM ѯྙ҂Ҭೆඵ౵ + • ॖ۴ऌ PWMxA ൻԛࣉྛ PWMxB ཌྷ၍ + • ஥ᇂՎሰଆॶ֥۷ྍٚൔ + + • ൐ିᄛѯđഡᇂᄛѯ௔ੱ + • ഡᇂᄛѯѯྙᇏֻ၂۱ઝԊ֥ӻ࿃ൈࡗ + • ഡᇂֻ‫ؽ‬۱ၛࠣᆭު֥ઝԊ֥ᅝॢб + • ಡ‫ ݖ‬PWM ᄛѯଆॶđPWM ѯྙ໭э‫׮‬ + + • ஥ᇂ PWM ଆॶ൞‫ڎ‬ၛࠣೂ‫ޅ‬ཙႋ‫ܣ‬ᅰ൙ࡱྐ‫ݼ‬ + • ᆷ‫ؿק‬ള‫ܣ‬ᅰ൙ࡱൈҐ౼֥Ҡቔğ + + – ఼ᇅ PWMxA ‫ބ‬Ĕࠇ PWMxB ູۚ‫׈‬௜ + – ఼ᇅ PWMxA ‫ބ‬Ĕࠇ PWMxB ູ֮‫׈‬௜ + – ஥ᇂ PWMxA ‫ބ‬Ĕࠇ PWMxB ޭ੻಩‫ܣޅ‬ᅰ൙ࡱ + • ஥ᇂ PWM ႋؓ‫ܣ‬ᅰ൙ࡱ֥ଆൔğ + – ၂Ցྟଆൔ + – ᇯᇛ௹ଆൔ + • ളӮᇏ؎ + • ಡ‫ܣݖ‬ᅰԩ৘ఖଆॶ + • ഡᇂᇯᇛ௹ҠቔౢԢ֥ٚൔ + • ֒ൈࠎ࠹ඔఖҐ౼֚࠹ൈ‫ބ‬ᆞ࠹ൈ࠹ඔൈđॖҐ౼҂๝Ҡቔ + +ুᶈྐ༏॓࠯ 376 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +16.3.1.4 ‫ܣ‬ᅰ࡟ҩଆॶ + + ๭ 16­5. ‫ܣ‬ᅰ࡟ҩଆॶ + +஥ᇂҕඔğ + • षఓ‫ܣ‬ᅰ൙ࡱ֥ളӮđѩູૄ۱‫ܣ‬ᅰྐ‫ݼ‬஥ᇂ‫ܣ‬ᅰ൙ࡱളӮ֥ࠞྟ + • ളӮ‫ܣ‬ᅰ൙ࡱᇏ؎ + +16.3.1.5 ѽࠆଆॶ + + ๭ 16­6. ѽࠆଆॶ + +஥ᇂҕඔğ + • ࿊ᄴѽࠆଆॶൻೆ֥шခࠞྟ‫ބ‬ყ‫ٳ‬௔ + • ഡᇂೈࡱԨ‫ؿ‬ѽࠆ + • ஥ᇂѽࠆ‫ק‬ൈఖ๝҄Ԩ‫ބؿ‬๝҄ཌྷ໊ + • ೈࡱ๝҄ѽࠆ‫ק‬ൈఖ + +16.3.2 PWM ‫ק‬ൈఖଆॶ + +ૄ۱ MCPWM ຓഡ‫׻‬Ⴕ೘۱ PWM ‫ק‬ൈఖଆॶb෱ૌᇏ֥಩‫ޅ‬၂۱‫׻‬ॖၛथ‫ק‬೘۱ PWM Ҡቔఖଆॶᇏ಩ၩ၂ +۱֥сေ൙ࡱൈ྽b๙‫ݖ‬൐Ⴈ GPIO इᆔ֥๝҄ྐ‫ݼ‬đଽᇂ๝҄આࠠᄍྸ၂۱ࠇ‫؟‬۱ MCPWM ຓഡᇏ֥‫؟‬۱ +PWM ‫ק‬ൈఖଆॶቔູ၂۱༢๤ླྀ๝‫۽‬ቔb + +16.3.2.1 PWM ‫ק‬ൈఖଆॶ֥஥ᇂ + +Ⴈ޼ॖ஥ᇂ PWM ‫ק‬ൈఖଆॶ֥ၛ༯‫ିۿ‬ğ + • ๙‫ݖ‬ᆷ‫ ק‬PWM ‫ק‬ൈఖ௔ੱࠇᇛ௹ট॥ᇅ൙ࡱ‫ؿ‬ള֥௔ੱb + • ஥ᇂห‫ ק‬PWM ‫ק‬ൈఖაః෰ PWM ‫ק‬ൈఖࠇଆॶ๝҄b + +ুᶈྐ༏॓࠯ 377 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + • ൐ PWM ‫ק‬ൈఖაః෰ PWM ‫ק‬ൈఖࠇଆॶ๝ཌྷb + + • ഡᇂ‫ק‬ൈఖ࠹ඔଆൔğ‫־‬ᄹđ‫ࡨ־‬đࠇ‫־‬ᄹ‫ࡨ־‬࿖ߌ࠹ඔଆൔb + + • ൐Ⴈყ‫ٳ‬௔ఖ۷‫ ڿ‬PWM ‫ק‬ൈఖൈᇒčPT_clkĎ֥෎ੱbૄ۱‫ק‬ൈఖ‫׻‬Ⴕሱ֥࠭ყ‫ٳ‬௔ఖđ๙‫࠷ݖ‬թఖ + PWM_TIMER0_CFG0_REG ֥ PWM_TIMERx_PRESCALE ஥ᇂbPWM ‫ק‬ൈఖ۴ऌ‫࠷ھ‬թఖ֥ഡᇂၛࢠત + ֥෎؇‫־‬ᄹࠇ‫ࡨ־‬b + +16.3.2.2 PWM ‫ק‬ൈఖ‫۽‬ቔଆൔ‫קބ‬ൈ൙ࡱളӮ + +PWM ‫ק‬ൈఖႵ೘ᇕ‫۽‬ቔଆൔđႮ PWMx ‫ק‬ൈఖଆൔ࠷թఖ஥ᇂğ + • ‫־‬ᄹ࠹ඔଆൔğ + ‫ק‬ൈఖՖਬᄹࡆ֞ᇛ௹࠷թఖᇏ஥ᇂ֥ᆴb၂֊֞ղᇛ௹ᆴđPWM ‫ק‬ൈఖౢਬđѩᄜՑष൓‫־‬ᄹbPWM + ᇛ௹֩Ⴟᇛ௹࠷թఖᇏ֥ᇛ௹ᆴ + 1b + ඪૼğᇛ௹࠷թఖູ PWM_TIMERx_PERIODđx = 0, 1, 2đؓႋ PWM_TIMER0_PERIODđ + PWM_TIMER1_PERIODđPWM_TIMER2_PERIODb + + • ‫࠹ࡨ־‬ඔଆൔğ + PWM ‫ק‬ൈఖՖᇛ௹࠷թఖᇏ֥ᆴष൓‫֞ࡨ־‬ਬbղ֞ਬުđࡼ߫‫ູگ‬ᇛ௹ᆴđᄜՑष൓‫ࡨ־‬bᄝᆃᇕ౦ + ঃ༯đPWM ᇛ௹֩Ⴟᇛ௹࠷թఖᇏ֥ᇛ௹ᆴ + 1b + + • ‫־‬ᄹ-‫ࡨ־‬࿖ߌଆൔğ + Վଆൔࢲ‫ކ‬ਔഈඍਆᇕଆൔbPWM ‫ק‬ൈఖՖਬष൓‫־‬ᄹđᆰ֞ղ֞ᇛ௹ᆴđᄜՑ‫ູࡨ־‬ਬbPWM ‫ק‬ൈ + ఖοᅶՎଆൔ࿖ߌ‫־‬ᄹ‫ࡨ־‬bPWM ᇛ௹ູᇛ௹࠷թఖ֥ᇛ௹ᆴ × 2 + 1b + +๭ 16-7 ᇀ 16-10 ཁൕ҂๝֥ଆൔ༯ PWM ‫ק‬ൈఖѯྙđЇও๝҄൙ࡱ௹ࡗ֥‫ק‬ൈఖྛູb + + ๭ 16­7. ‫־‬ᄹ࠹ඔଆൔѯྙ + +ুᶈྐ༏॓࠯ 378 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + ๭ 16­8. ‫࠹ࡨ־‬ඔଆൔѯྙ + + ๭ 16­9. ‫־‬ᄹ‫ࡨ־‬࿖ߌଆൔѯྙđ๝҄൙ࡱު‫ࡨ־‬ + + ๭ 16­10. ‫־‬ᄹ‫ࡨ־‬࿖ߌଆൔѯྙđ๝҄൙ࡱު‫־‬ᄹ + +ুᶈྐ༏॓࠯ 379 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +֒ PWM ‫ק‬ൈఖᄎྛൈđ‫ק‬௹ሱ‫ֹ׮‬ളӮၛ༯‫ק‬ൈ൙ࡱğ + • UTEP + ֒ PWM ‫ק‬ൈఖ֩Ⴟᇛ௹࠷թఖᆴčPWM_TIMERx_PERODĎ౏ PWM ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈളӮ֥‫ק‬ൈ൙ࡱb + • UTEZ + ֒ PWM ‫ק‬ൈఖ֩Ⴟਬ౏ PWM ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈളӮ֥‫ק‬ൈ൙ࡱb + • DTEP + ֒ PWM ‫ק‬ൈఖ֩Ⴟᇛ௹࠷թఖᆴčPWM_TIMERx_PERODĎ౏ PWM ‫ק‬ൈఖ‫ࡨ־‬ൈളӮ֥‫ק‬ൈ൙ࡱb + • DTEZ + ֒ PWM ‫ק‬ൈఖ֩Ⴟਬ౏ PWM ‫ק‬ൈఖ‫ࡨ־‬ൈളӮ֥‫ק‬ൈ൙ࡱb + +๭ 16-11 ᇀ 16-13 ູ U/DTEP ‫ ބ‬U/DTEZ ‫ק‬ൈ൙ࡱ֥ൈ྽ѯྙb + + ๭ 16­11. ‫־‬ᄹଆൔᇏളӮ֥ UTEP ‫ ބ‬UTEZ + +ুᶈྐ༏॓࠯ 380 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + ๭ 16­12. ‫ࡨ־‬ଆൔᇏളӮ֥ UTEP ‫ ބ‬UTEZ + +ুᶈྐ༏॓࠯ 381 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + ๭ 16­13. ‫־‬ᄹ‫ࡨ־‬ଆൔᇏളӮ֥ UTEP ‫ ބ‬UTEZ + +16.3.2.3 PWM ‫ק‬ൈఖ႕ሰ࠷թఖ + +PWM ‫ק‬ൈఖᇛ௹࠷թఖ‫ ބ‬PWM ‫ק‬ൈఖൈᇒყ‫ٳ‬௔ఖ࠷թఖऎႵ႕ሰ࠷թఖb႕ሰ࠷թఖ֥ቔႨ൞Ќթଖ۱ +ᆴđᄝა႗ࡱ๝֥҄ห‫ק‬ൈख़ཿೆႵི࠷թఖbਆᇕ࠷թఖো྘‫ק‬ၬೂ༯ğ + + • Ⴕི࠷թఖ + Ⴕི࠷թఖᆰࢤ॥ᇅ႗ࡱᆳྛ֥෮ႵҠቔb + + • ႕ሰ࠷թఖ + ႕ሰ࠷թఖቔູေཿೆႵི࠷թఖ֥ᆴ֥ਢൈߏթbᄝႨ޼஥ᇂ֥ଖ۱ൈࡗׄđ႕ሰ࠷թఖᇏ֥ᆴФཿೆ + Ⴕི࠷թఖbᄝՎᆭభđ႕ሰ࠷թఖ֥ଽಸؓ൳॥႗ࡱીႵ಩‫ޅ‬ᆰࢤ႕ཙbᆃႵᇹႿٝᆸ࠷թఖႮೈࡱၳ + ҄ྩ‫ڿ‬ൈॖି‫ؿ‬ള֥հ༂႗ࡱҠቔb႕ሰ࠷թఖ‫ބ‬Ⴕི࠷թఖऎႵཌྷ๝֥թԥఖֹᆶbೈࡱሹ൞ཿೆࠇ‫؀‬ + ౼႕ሰ࠷թఖbႵི࠷թఖ֥۷ྍൈࡗׄႮఃห‫֥ק‬۷ྍٚൔ࠷թఖथ‫ק‬b۷ྍൈࡗׄॖၛ൞ PWM ‫ק‬ൈ + ఖ֩ႿਬൈđPWM ‫ק‬ൈఖ֩Ⴟᇛ௹ൈđ๝҄ൈࡗׄࠇ৫ࠧbೈࡱॖၛԨ‫఼ؿ‬ᇅಆअ۷ྍđ۴ऌ႕ሰ࠷թ + ఖ۷ྍଆॶᇏ֥෮ႵႵི࠷թఖb + +16.3.2.4 PWM ‫ק‬ൈఖ๝҄‫ބ‬෭ཌྷ + +PWM ଆॶҐႨਲࠃ֥๝҄ٚ‫م‬bૄ۱ PWM ‫ק‬ൈఖ‫׻‬Ⴕ၂۱๝҄ൻೆ‫ބ‬၂۱๝҄ൻԛb๝҄ൻೆॖၛՖ GPIO +इᆔ֥೘۱๝҄ൻԛ‫ބ‬೘۱๝҄ྐ‫ݼ‬ᇏ࿊ᄴb๝҄ൻԛॖၛ൐Ⴈ๝҄ൻೆྐ‫ݼ‬đࠇᄝ PWM ‫ק‬ൈఖ֩Ⴟᇛ௹ࠇ +PWM ‫ק‬ൈఖ֩ႿਬൈӁളbၹՎđPWM ‫ק‬ൈఖॖၛ๙‫ݖ‬๝҄൐෱ૌᆭࡗ֥ཌྷ໊෭‫ק‬bᄝ๝҄௹ࡗđPWM ‫ק‬ +ൈఖൈᇒყ‫ٳ‬௔ఖࡼ‫໊گ‬ః࠹ඔఖđၛ๝҄ PWM ‫ק‬ൈఖൈᇒb + +16.3.3 PWM Ҡቔఖଆॶ + +PWM ҠቔఖଆॶऎСၛ༯‫ିۿ‬ğ + +ুᶈྐ༏॓࠯ 382 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + • ۴ऌཌྷႋ PWM ‫ק‬ൈఖ֥‫ק‬ൈҕॉളӮ PWM ྐ‫ؓݼ‬b + • PWM ྐ‫ૄ֥ؓݼ‬۱ྐ‫׻ݼ‬ॖၛ‫׿‬৫ഡᇂห‫֥ק‬ඵ౵b + • ॖ๙‫ݖ‬஥ᇂࡼᄛѯ‫ ֞ࡆן‬PWM ྐ‫ݼ‬ഈb + • ‫ܣ‬ᅰ่ࡱ༯ԩ৘ཙႋb +๭ 16-14 ູ PWM Ҡቔఖ֥ॿ๭b + + ๭ 16­14. PWM Ҡቔఖ֥ሰଆॶ + +16.3.3.1 PWM ളӮఖଆॶ + +PWM ളӮఖଆॶ֥ቔႨ +ՎଆॶᇏളӮࠇ֝ೆᇗေ֥ൈ྽൙ࡱđѩሇ߄ູห‫ק‬Ҡቔđᄝ PWMxA ‫ ބ‬PWMxB ൻԛԩളӮ෮ླ֥ѯ +ྙb +PWM ളӮఖଆॶᆳྛၛ༯Ҡቔğ + + • ࠎႿ൐Ⴈ࠷թఖ A ‫ ބ‬B ஥ᇂ֥ൈࡗՄളӮ‫ק‬ൈ൙ࡱbડቀၛ༯่ࡱൈ‫ؿ‬ള‫ק‬ൈ൙ࡱğ + – UTEAğPWM ‫ק‬ൈఖ‫־‬ᄹ࠹ඔѩ౏ఃᆴ֩Ⴟ࠷թఖ Ab + – UTEBğPWM ‫ק‬ൈఖ‫־‬ᄹ࠹ඔѩ౏ఃᆴ֩Ⴟ࠷թఖ Bb + – DTEAğPWM ‫ק‬ൈఖ‫࠹ࡨ־‬ඔѩ౏ఃᆴ֩Ⴟ࠷թఖ Ab + – DTEBğPWM ‫ק‬ൈఖ‫࠹ࡨ־‬ඔѩ౏ఃᆴ֩Ⴟ࠷թఖ Bb + + • ࠎႿ‫ܣ‬ᅰࠇ๝҄൙ࡱളӮ U/DT1đU/DT2 ‫ק‬ൈ൙ࡱb + • ֒ᆃུ‫ק‬ൈ൙ࡱ๝ൈ‫ؿ‬ളൈܵ৘Ⴊ༵ࠩb + • ࠎႿ‫ק‬ൈ൙ࡱӁളᇂ 1đᇂ 0 ‫ބ‬౼ّҠቔb + • ۴ऌ PWM ളӮఖଆॶ֥஥ᇂট॥ᇅ PWM ᅝॢбb + +ুᶈྐ༏॓࠯ 383 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +• ൐Ⴈ႕ሰ࠷թఖԩ৘ྍ֥ൈࡗՄᆴđၛٝᆸ PWM ѯྙᇏ֥ઝԊ‫ۄ‬ಠb + +PWM Ҡቔఖ႕ሰ࠷թఖ + +ൈࡗՄ࠷թఖ A ‫ ބ‬BđၛࠣҠቔ஥ᇂ࠷թఖ PWM_GENx_A_REG ‫ ބ‬PWM_GENx_B_REG ‫׻‬Ⴕ႕ሰ࠷թఖb႕ +ሰ࠷թఖิ‫܂‬ਔ၂ᇕა႗ࡱ๝҄۷ྍ࠷թఖ֥ٚ‫م‬b႕ሰ࠷թఖ૭ඍ౨Ұुֻ 16.3.2.3 ᅣb + +‫ק‬ൈ൙ࡱ + +і 16-2 ‫ۀ‬ওਔ෮Ⴕ‫ק‬ൈྐ‫ބݼ‬൙ࡱb + і 16­2. PWM ളӮఖᇏ֥෮Ⴕ‫ק‬ൈ൙ࡱ + +ྐ‫ݼ‬ ൙ࡱ૭ඍ PWM ‫ק‬ൈఖҠቔ +DTEP PWM ‫ק‬ൈఖ֥ᆴ֩Ⴟᇛ௹࠷թఖ֥ᆴ PWM ‫ק‬ൈఖ‫࠹ࡨ־‬ඔ +DTEZ PWM ‫ק‬ൈఖ֥ᆴ֩Ⴟ 0 +DTEA PWM ‫ק‬ൈఖ֥ᆴ֩Ⴟ࠷թఖ A PWM ‫ק‬ൈఖ‫־‬ᄹ࠹ඔ +DTEB PWM ‫ק‬ൈఖ֥ᆴ֩Ⴟ࠷թఖ B - +DT0 ൙ࡱ ࠎႿ‫ܣ‬ᅰࠇ๝҄൙ࡱ +DT1 ൙ࡱ ࠎႿ‫ܣ‬ᅰࠇ๝҄൙ࡱ +UTEP PWM ‫ק‬ൈఖ֥ᆴ֩Ⴟᇛ௹࠷թఖ֥ᆴ +UTEZ ‫ק‬ൈఖ֥ᆴ֩Ⴟ 0 +UTEA PWM ‫ק‬ൈఖ֥ᆴ֩Ⴟ࠷թఖ A +UTEB PWM ‫ק‬ൈఖ֥ᆴ֩Ⴟ࠷թఖ B +UT0 ൙ࡱ ࠎႿ‫ܣ‬ᅰࠇ๝҄൙ࡱ +UT1 ൙ࡱ ࠎႿ‫ܣ‬ᅰࠇ๝҄൙ࡱ +ೈࡱ఼ᇅ൙ࡱ ೈࡱԨ‫֥ؿ‬ၳ҄൙ࡱ + +ೈࡱ఼ᇅ൙ࡱႨႿᄝ PWMxA ‫ ބ‬PWMxB ൻԛഈീࡆ٤৵࿃ࠇ৵࿃఼֥ᇅ‫׈‬௜bՎ۷‫ڿ‬൞ၳ҄ປӮ֥bೈࡱ఼ +ᇅႮ࠷թఖ PWM_PWM_GENx_FORCE_REG ॥ᇅb + +PWM ളӮఖଆॶᇏ T0/T1 ֥࿊ᄴ‫ބ‬஥ᇂ‫׿‬৫Ⴟ‫ܣ‬ᅰԩ৘ଆॶᇏ֥‫ܣ‬ᅰ൙ࡱ֥஥ᇂb‫ܣ‬ᅰ൙ࡱॖၛ҂Ф஥ᇂູ +ᄝ‫ܣ‬ᅰԩ৘ఖଆॶᇏႄఏ๋ᅃ‫׮‬ቔđ֌ཌྷ๝֥൙ࡱॖၛႮ PWM ളӮఖႨႿԨ‫ ؿ‬T0/T1 ၛ॥ᇅ PWM ѯ +ྙb + +ླေᇿၩ֥൞đ֒ PWM ‫ק‬ൈఖԩႿ‫־‬ᄹ‫ࡨ־‬࿖ߌ࠹ඔଆൔൈđ෱ࡼᄝ TEP ൙ࡱު‫ࡨ־‬đᄝ TEZ ൙ࡱު‫־‬ᄹb +ၹՎđ֒ PWM ‫ק‬ൈఖԩႿՎଆൔൈđࡼԛགྷ DTEP ‫ ބ‬UTEZđ֌ UTEP ‫ ބ‬DTEZ ҂߶ԛགྷb + +PWM ളӮఖॖၛ๝ൈԩ৘‫؟‬۱൙ࡱb൙ࡱႪ༵ࠩႮ႗ࡱथ‫ק‬đབྷ࡮і 16-3 ‫ބ‬і 16-4bႪ༵ࠩՖ 1čቋۚĎ֞ +7čቋ֮Ďஆਙbླေᇿၩ֥൞đTEP ‫ ބ‬TEZ ൙ࡱ֥Ⴊ༵ࠩ౼थႿ PWM ‫ק‬ൈఖ֥࠹ඔଆൔb + +ೂ‫ ݔ‬A ࠇ B ֥ᆴഡᇂູնႿᇛ௹đᄵ U/DTEA ‫ ބ‬U/DTEB ࡼႥჹ҂߶‫ؿ‬ളb + + і 16­3. PWM ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđ‫ק‬ൈ൙ࡱ֥Ⴊ༵ࠩ + + Ⴊ༵ࠩ ൙ࡱ + 1čቋۚĎ ೈࡱ఼ᇅ൙ࡱ + 2 UTEP + 3 UT0 + +ুᶈྐ༏॓࠯ 384 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Ⴊ༵ࠩ ൙ࡱ + 4 UT1 + 5 UTEB + 6 UTEA + 7čቋ֮Ď UTEZ + + і 16­4. PWM ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđ‫ק‬ൈ൙ࡱ֥Ⴊ༵ࠩ + + Ⴊ༵ࠩ ൙ࡱ + 1čቋۚĎ ೈࡱ఼ᇅ൙ࡱ + 2 DTEZ + 3 DT0 + 4 DT1 + 5 DTEB + 6 DTEA + 7čቋ֮Ď DTEP + +ඪૼğ + + 1. UTEP ‫ ބ‬UTEZ ҂๝ൈ‫ؿ‬ളb֒ PWM ‫ק‬ൈఖԩႿ‫־‬ᄹ࠹ඔଆൔ, UTEP ࡼ൓ᇔб UTEZ ิభ၂۱ᇛ௹‫ؿ‬ + ളđೂ๭ 16-11 ෮ൕđၹՎ෱ૌؓ PWM ྐ‫֥ݼ‬ቔႨ҂߶дՎ‫ۄ‬ಠb֒ PWM ‫ק‬ൈఖԩႿ‫־‬ᄹ‫ࡨ־‬࿖ߌଆ + ൔൈđUTEP ҂߶‫ؿ‬ളb + + 2. DTEP ‫ ބ‬DTEZ ҂๝ൈ‫ؿ‬ളb֒ PWM ‫ק‬ൈఖԩႿ‫࠹ࡨ־‬ඔଆൔൈđDTEZ ൓ᇔб DTEP ᄪ၂۱ᇛ௹‫ؿ‬ളđ + ೂ๭ 16-12 ෮ൕđၹՎ෱ૌؓ PWM ྐ‫֥ݼ‬ቔႨ҂߶дՎ‫ۄ‬ಠb֒ PWM ‫ק‬ൈఖԩႿ‫־‬ᄹ‫ࡨ־‬࿖ߌଆൔ + ൈđDTEZ ҂߶‫ؿ‬ളb + +PWM ྐ‫ݼ‬ളӮ + +֒ଖ۱‫ק‬ൈ൙ࡱ‫ؿ‬ളൈđPWM ളӮఖ॥ᇅൻԛ PWMxA ‫ ބ‬PWMxB ֥‫׈‬௜b‫ק‬ൈ൙ࡱ๙‫ ݖ‬PWM ‫ק‬ൈఖ࠹ඔٚ +ཟč‫־‬ᄹࠇ‫ࡨ־‬Ďࣉ၂҄ཋ‫ק‬b۴ऌ‫ק‬ൈఖ࠹ඔٚཟđଆॶॖၛؓ PWM ‫ק‬ൈఖ‫־‬ᄹࠇ‫࠹ࡨ־‬ඔ֥ࢨ‫؍‬ᆳྛ҂ +๝֥Ҡቔb + +ॖၛᄝ PWMxA ‫ ބ‬PWMxB ൻԛഈ஥ᇂၛ༯Ҡቔğ + + • ᇂູۚ‫׈‬௜ğ + ࡼ PWMxA ࠇ PWMxB ֥ൻԛഡᇂູۚ‫׈‬௜b + + • ᇂູ֮‫׈‬௜ğ + ๙‫ ࡼݖ‬PWMxA ࠇ PWMxB ֥ൻԛഡᇂູ֮‫׈‬௜টౢԢ PWMxA ࠇ PWMxB ֥ൻԛb + + • ౼ّğ + ࡼ PWMxA ࠇ PWMxB ֥֒భൻԛ‫׈‬௜۷‫ູڿ‬ཌྷّ֥ᆴbೂ‫ݔ‬෱֒భФঘۚđᄵঘ֮đࠇّᆭb + + • ҂ࣉྛҠቔğ + Ќӻ PWMxA ‫ ބ‬PWMxB ൻԛ‫׈‬௜҂эbᄝᆃᇕሑ෿༯đಯಖॖၛԨ‫ؿ‬ᇏ؎b + +ൻԛഈ֥Ҡቔ๙‫࠷ݖ‬թఖ PWN_GENx_A_REG ‫ ބ‬PWN_GENx_B_REG ஥ᇂbૄ၂Ցൻԛ֥Ҡቔ‫׿׻‬৫஥ᇂb +ՎຓđࠎႿ൙ࡱᄝଖ۱ൻԛഈਲࠃֹᆳྛ҂๝֥Ҡቔbі 16-2 ᇏਙई֥಩‫ޅ‬൙ࡱ‫׻‬ॖၛቔႨႿ PWMxA ࠇ + +ুᶈྐ༏॓࠯ 385 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +PWMxB ൻԛഈbܱႿളӮఖ 0đ1 ࠇ 2 ֥࠷թఖྐ༏đ౨ҕॉֻ 16.4 ᅣb + +ӈ࡮஥ᇂ֥ѯྙ +๭ 16-15 ູ PWM ‫ק‬ൈఖᄝ‫־‬ᄹ‫ࡨ־‬࿖ߌ࠹ඔൈളӮ֥ؓӫ PWM ѯྙb‫ھ‬ଆൔ༯֥ᆰੀ 0%-100% ‫ט‬ᇅॖႮ +ၛ༯‫܄‬ൔࠆ֤ğ + + Duty = (P eriod − A) ÷ P eriod +ೂ‫ ݔ‬A ֥ᆴ֩Ⴟ PWM ‫ק‬ൈఖ֥ᆴđѩ౏ PWM ‫ק‬ൈఖ‫־‬ᄹđᄵ PWM ൻԛФഈঘbೂ‫ ݔ‬A ֥ᆴᄝ PWM ‫ק‬ൈ +ఖ‫ࡨ־‬ൈ֩Ⴟ PWM ‫ק‬ൈఖ֥ᆴđᄵ PWM ൻԛФঘ֮b + + ๭ 16­15. ‫־‬ᄹ‫ࡨ־‬ଆൔ༯֥ؓӫѯྙ + +ুᶈྐ༏॓࠯ 386 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +๭ 16-16 ᇀ๭ 16-19 ֥ PWM ѯྙ૭ඍਔӈ࡮֥ PWM Ҡቔఖ஥ᇂb๭ᇏඔऌඪૼೂ༯ğ + • PeriodđA ‫ ބ‬B ‫ٳ‬љіൕཿೆᇛ௹࠷թఖđ࠷թఖ A ‫ ބ‬B ֥ᆴb + • PWMxA ‫ ބ‬PWMxB ൞ PWM Ҡቔఖ x ֥ൻԛྐ‫ݼ‬b + + ๭ 16­16. ‫־‬ᄹ࠹ඔଆൔđֆш҂ؓӫѯྙđPWMxA ‫ ބ‬PWMxB ‫׿‬৫‫ט‬ᇅ⚶ۚ‫׈‬௜ + +PWMxA ֥ᅝॢб‫ט‬ᇅႮ B ഡᇂđۚ‫׈‬௜Ⴕིđა B Ӯᆞбb +PWMxB ֥ᅝॢб‫ט‬ᇅႮ A ഡᇂđۚ‫׈‬௜Ⴕིđა A Ӯᆞбb + + P eriod = (P W M _T IM ERx_P ERIOD + 1) × TP T _clk + +ুᶈྐ༏॓࠯ 387 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + ๭ 16­17. ‫־‬ᄹ࠹ඔଆൔđઝԊ໊ᇂ҂ؓӫѯྙđPWMxA ‫׿‬৫‫ט‬ᇅ + +ઝԊॖၛᄝ PWM ѯྙଽčਬᇀᇛ௹ᆴᆭࡗĎ֥಩‫ֹޅ‬ٚളӮb +PWMxA ۚ‫׈‬௜ᅝॢбა (B ⚶A) Ӯᆞбb + + P eriod = (P W M _T IM ERx_P ERIOD + 1) × TP T _clk + +ুᶈྐ༏॓࠯ 388 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + ๭ 16­18. ‫־‬ᄹ‫ࡨ־‬࿖ߌ࠹ඔଆൔđචခؓӫѯྙđᄝ PWMxA ‫ ބ‬PWMxB ഈ‫׿‬৫‫ט‬ᇅ⚶ۚ‫׈‬௜Ⴕི + +PWMxA ֥ᅝॢб‫ט‬ᇅႮ A ഡᇂđۚ‫׈‬௜Ⴕིđა A Ӯᆞбb +PWMxB ֥ᅝॢб‫ט‬ᇅႮ B ഡᇂđۚ‫׈‬௜Ⴕིđა B Ӯᆞбb +ൻԛ PWMxA ‫ ބ‬PWMxB ॖ౺‫׮‬҂๝षܱb + + P eriod = (2 × P W M _T IM ERx_P ERIOD + 1) × TP T _clk + +ুᶈྐ༏॓࠯ 389 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + ๭ 16­19. ‫־‬ᄹ‫ࡨ־‬࿖ߌ࠹ඔଆൔđචခؓӫѯྙđᄝ PWMxA ‫ ބ‬PWMxB ഈ‫׿‬৫‫ט‬ᇅ⚶޺Ҁ + +PWMxA ֥ᅝॢб‫ט‬ᇅႮ A ഡᇂđۚ‫׈‬௜Ⴕིđა A Ӯᆞбb +PWMxB ֥ᅝॢб‫ט‬ᇅႮ B ഡᇂđۚ‫׈‬௜Ⴕིđა B Ӯᆞбb +PWMxA/B ൻԛॖ౺‫׮‬ഈ/༯č޺ҀĎषܱb +ඵ౵ = B ⚶Ađшခ໊ᇂປಆॖႮೈࡱ஥ᇂbсေൈđॖ൐Ⴈඵ౵ളӮఖଆॶഡᇂః෰шခ࿼Ӿٚൔb + + P eriod = (2 × P W M _T IM ERx_P ERIOD + 1) × TP T _clk + +ুᶈྐ༏॓࠯ 390 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +ೈࡱ఼ᇅ൙ࡱ + +ᄝ PWM ളӮఖଽႵ 2 ᇕೈࡱ఼ᇅ൙ࡱğ + • ٤৵࿃ࠧൈ (NCI) ೈࡱ఼ᇅ൙ࡱ + ֒ႮೈࡱԨ‫ؿ‬ൈđᆃུো྘֥൙ࡱᄝ PWM ൻԛഈ৫ࠧളིbѩ౏఼ᇅ൞҂৵࿃֥đᆃၩ໅ሢ༯၂۱ࠗࠃ + ֥‫ק‬ൈ൙ࡱି‫ڿܔ‬э PWM ൻԛb + • ৵࿃ (CNTU) ೈࡱ఼ᇅ൙ࡱ + ᆃ၂ো྘൙ࡱ൞৵࿃֥bᆰ֞๙‫ݖ‬ೈࡱ൤٢đ఼ᇅ PWM ӻ࿃ൻԛb൙ࡱԨ‫ؿ‬ఖॖ஥ᇂbᆃ၂ো൙ࡱॖ஥ + ᇂູ‫ק‬ൈࠇࠧൈ‫ؿ‬ളb + +๭ 16-20 ູ NCI ೈࡱ఼ᇅ൙ࡱ֥၂ᇕѯྙbNCI ႨႿֆ‫఼׿‬ᇅ PWMxA ൻԛູ֮‫׈‬௜đPWMxB ҂൳఼ +ᇅb + + ๭ 16­20. NCI ᄝ PWMxA ൻԛഈೈࡱ఼ᇅ൙ࡱൕ২ + +ুᶈྐ༏॓࠯ 391 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +๭ 16-21 ູ CNTU ೈࡱ఼ᇅ൙ࡱ֥ѯྙbUTEZ ൙ࡱФ࿊ູ CNTU ೈࡱ఼ᇅ൙ࡱ֥Ԩ‫ؿ‬ఖbCNTU ႨႿֆ‫఼׿‬ +ᇅ PWMxB ൻԛູ֮‫׈‬௜đ֌ PWMxA ҂൳఼ᇅb + + ๭ 16­21. CNTU ᄝ PWMxB ൻԛഈೈࡱ఼ᇅ൙ࡱൕ২ + +ুᶈྐ༏॓࠯ 392 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +16.3.3.2 ඵ౵ളӮఖଆॶ + +ඵ౵ളӮఖଆॶቔႨ +ᅣࢫ PWM ളӮఖଆॶࢃඍਔᄝ PWMxA ‫ ބ‬PWMxB ഈൻԛห‫ק‬шခ໊ᇂ֥ྐ‫֥ࠫݼ‬۱஥ᇂ࿊ཛb๙‫ڿݖ‬эྐ +‫ݼ‬ᆭࡗ֥шခ໊ᇂၛࠣഡᇂྐ‫֥ݼ‬ᅝॢбđॖࠆ֤෮ླ֥ඵ౵bਸ਼၂ᇕٚൔ൞൐Ⴈህ૊֥ඵ౵ളӮఖଆॶ॥ᇅ +ඵ౵b +ඵ౵ളӮఖଆॶ֥ᇶေ‫ିۿ‬ೂ༯ğ + + • ۴ऌֆ۱ PWMxA ൻೆ֥ඵ౵ളӮྐ‫ؓݼ‬čPWMxA ‫ ބ‬PWMxBĎ + • ๙‫ݖ‬ᄝྐ‫ݼ‬шခᄹࡆ࿼ӾটളӮඵ౵ğ + + – ഈശခ࿼Ӿ (RED) + – ༯ࢆခ࿼Ӿ (FED) + • ஥ᇂྐ‫ؓݼ‬ğ + – ۚ‫׈‬௜Ⴕི޺Ҁ (AHC) + – ֮‫׈‬௜Ⴕི޺Ҁ (ALC) + – ۚ‫׈‬௜Ⴕི (AH) + – ֮‫׈‬௜Ⴕི (AL) + • ೂ‫ݔ‬ඵ౵ᆰࢤᄝളӮఖଆॶᇏ஥ᇂđᄵඵ౵‫ؿ‬ളఖ҂ളིb + +ඵ౵ଆॶളӮఖ႕ሰ࠷թఖ +࿼Ӿ࠷թఖ RED ‫ ބ‬FED ֥႕ሰ࠷թఖູ PWM_DTx_RED_CFG_REG ‫ ބ‬PWM_DTx_FED_CFG_REGb࠷թఖ૭ +ඍབྷ࡮ 16.3.2.3b + +ুᶈྐ༏॓࠯ 393 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +ඵ౵ളӮఖଆॶ֥Ҡቔေׄ +๭ 16-22 ૭ඍਔԷࡹඵ౵ଆॶ֥षܱຉ௪b + + ๭ 16­22. ඵ౵ଆॶ֥षܱຉ௪ + +ഈ๭ᇏ֥ S0 - S8 ൞Ⴎі 16-5 ᇏ֥ PWM_DTx_CFG_REG ࠷թఖ॥ᇅ֥षܱb + і 16­5. ॥ᇅඵ౵ൈࡗളӮఖषܱ֥࠷թఖ + +षܱ ࠷թఖ +S0 PWM_DTx_B_OUTBYPASS +S1 PWM_DTx_A_OUTBYPASS +S2 PWM_DTx_RED_OUTINVERT +S3 PWM_DTx_FED_OUTINVERT +S4 PWM_DTx_RED_INSEL +S5 PWM_DTx_FED_INSEL +S6 PWM_DTx_A_OUTSWAP +S7 PWM_DTx_B_OUTSWAP +S8 PWM_DTx_DEB_MODE + +ᆦӻ෮Ⴕषܱቆ‫ކ‬đ֌҂൞෮Ⴕ֥षܱଆൔ‫׻‬൞‫֥྘ׅ‬൐Ⴈଆൔbі 16-6 ਙईਔ၂ུ‫֥྘ׅ‬ඵ౵஥ᇂbᄝᆃུ +஥ᇂᇏđS4 ‫ ބ‬S5 ֥ष໊ܱᇂࡼ PWMxA ഡᇂູ༯ࢆခ‫ބ‬ഈശခ࿼Ӿ֥‫܋܄‬ჷbі 16-6 ᇏ֥ଆൔॖ‫ູٳ‬ၛ༯ +ࠫোğ + + • ଆൔ 1ğಡ‫ݖ‬༯ࢆခ (FED) ‫ބ‬ഈശခ (RED) ֥࿼Ӿ + ᄝ‫ھ‬ଆൔ༯đඵ౵ଆॶФܱоbPWMxA ‫ ބ‬PWMxB ྐ‫֥ݼ‬ѯྙ໭э߄b + + • ଆൔ 2­5ğࣜ‫ׅ‬ඵ౵ࠞྟഡᇂ + ᆃུଆൔູ‫ྟࠞ྘ׅ‬஥ᇂđ‫۽ۂݤ‬ြ‫׈‬ჷᅅࠞ౺‫׮‬ఖᇏ֥ۚĔ֮‫׈‬௜Ⴕིଆൔb๭ 16-23 ᇀ 16-26ູ‫྘ׅ‬ + ѯྙb + + • ଆൔ 6 ‫ ބ‬7ğಡ‫ݖ‬༯ࢆခ (FED) ࠇഈശခ (RED) ֥࿼Ӿ + Վଆൔ༯đಡ‫ݖ‬ഈശခ࿼Ӿ (RED) ࠇ༯ࢆခ࿼Ӿ (FED) bၹՎđ҂൐Ⴈؓႋ࿼Ӿb + +ুᶈྐ༏॓࠯ 394 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + і 16­6. ඵ౵ളӮఖ֥‫྘ׅ‬Ҡቔଆൔ + +ଆൔ ૭ඍ S0 S1 S2 S3 + +1 PWMxA ‫ ބ‬PWMxB ѯྙ໭э߄ 1 1 X X + +2 ۚ‫׈‬௜Ⴕི޺Ҁ (AHC)đҕ࡮๭ 16-23 0 0 0 1 + +3 ֮‫׈‬௜Ⴕི޺Ҁ (ALC)đҕ࡮๭ 16-24 0 0 1 0 + +4 ۚ‫׈‬௜Ⴕི (AH)đҕ࡮๭ 16-25 0 0 0 0 + +5 ֮‫׈‬௜Ⴕི (AL)đҕ࡮๭ 16-26 0 0 1 1 + +6 PWMxA ൻԛ = PWMxA ൻೆč໭࿼ӾĎ 0 1 0ࠇ1 0ࠇ1 + + PWMxB ൻԛ = PWMxA ൻೆđ༯ࢆခ࿼Ӿ + +7 PWMxA ൻԛ = PWMxA ൻೆđഈശခ࿼Ӿ 1 0 0ࠇ1 0ࠇ1 + + PWMxB ൻԛ = PWMxB ൻೆč໭࿼ӾĎ + +ඪૼğၛഈ෮ႵଆൔᇏđS4 - S8 ֥ष໊ܱᇂ‫׻‬ᇂ 0b + + ๭ 16­23. ۚ‫׈‬௜Ⴕི޺Ҁ (AHC) ඵ౵ѯྙ + + ๭ 16­24. ֮‫׈‬௜Ⴕི޺Ҁ (ALC) ඵ౵ѯྙ + +ুᶈྐ༏॓࠯ 395 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + ๭ 16­25. ۚ‫׈‬௜Ⴕི (AH) ඵ౵ѯྙ + ๭ 16­26. ֮‫׈‬௜Ⴕི (AL) ඵ౵ѯྙ + +ুᶈྐ༏॓࠯ 396 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +ഈശခ࿼Ӿ (RED) ‫ބ‬༯ࢆခ࿼Ӿ (FED) ॖ‫ٳ‬љഡᇂb࿼Ӿ֥ᆴ๙‫ ݖ‬16 ໊࠷թఖ PWM_DTx_RED ‫ބ‬ +PWM_DTx_FED ஥ᇂb࠷թఖᆴіൕ၂۱ྐ‫ݼ‬шခॖၛ࿼Ӿ֥ DT_clk ൈᇒᇛ௹ᆴbDT_clk ॖ๙‫࠷ݖ‬թఖ +PWM_DTx_CLK_SEL Ֆ PWM_clk ࠇ PT_clk ᇏ࿊ᄴb +๙‫ݖ‬ၛ༯‫܄‬ൔ࠹ෘ༯ࢆခ࿼Ӿ (FED) ‫ބ‬ഈശခ࿼Ӿ (RED) ֥ᆴ: + + F ED = P W M _DT x_F ED × TDT _clk + RED = P W M _DT x_RED × TDT _clk + +16.3.3.3 PWM ᄛѯଆॶ + +ࡼ PWM ൻԛᯒ‫ࠏ׈֞ކ‬౺‫׮‬ఖॖିླေ൐Ⴈэ࿢ఖ‫ۯ‬৖bэ࿢ఖᆺิ‫ࢌ܂‬ੀྐ‫ݼ‬đ‫ ط‬PWM ྐ‫֥ݼ‬ᅝॢбॖ +ିᄝ 0% ֞ 100% ᆭࡗэ߄bPWM ᄛѯଆॶॖၛ๙‫ݖ‬൐Ⴈۚ௔ᄛѯؓఃࣉྛ‫ט‬ᇅđࡼ‫ݼྐھ‬Ԯ‫־‬۳э࿢ +ఖb + +‫ۀିۿ‬ඍ +Վଆॶ֥ၛ༯ܱ࡯‫ିۿ‬ॖ஥ᇂğ + + • ᄛѯ௔ੱ + • ֻ၂۱ઝԊ֥ઝॺ + • ֻ‫ؽ‬۱ၛࠣᆭު֥ઝԊ֥ᅝॢб + • षఓ/ܱоᄛѯ + +Ҡቔေׄ +PWM ᄛѯൈᇒ (PC_clk) টሱႿ PWM_clkb๙‫࠷ݖ‬թఖ PWM_CARRIERx_CFG_REG ֥ +PWM_CARRIERx_PRESCALE ‫ ބ‬PWM_CARRIERx_DUTY ໊஥ᇂ௔ੱ‫ބ‬ᅝॢбb၂ՑྟઝԊ֥‫ିۿ‬ᄝႿิ‫ۚ܂‬ +ିਈઝԊၛࢤ๙‫׈‬ჷषܱbෛު֥ઝԊႨႿЌӻഈ‫֥׈‬ሑ෿b၂ՑྟઝԊॺ؇ॖ๙‫ݖ‬ +PWM_CARRIERx_OSHTWTH ໊ࣉྛ஥ᇂb๙‫ ݖ‬PWM_CARRIERx_EN ໊ট൐ିĔ࣌ᆸᄛѯଆॶb + +ᄛѯൕ২ +๭ 16-27 ૭ඍਔᄛѯ‫ࡆן‬ᄝჰ൓ PWM ઝԊഈ֥ൕ২ѯྙb‫ھ‬๭҂ཁൕֻ၂۱ઝԊ‫ބ‬ᅝॢб॥ᇅđཌྷܱབྷ༥ྐ +༏ࡼᄝުਆࢫᇏࢺകb + +ুᶈྐ༏॓࠯ 397 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + ๭ 16­27. PWM ᄛѯҠቔ֥ѯྙൕ২ + +ֻ၂۱ઝԊ +ֻ၂۱ઝԊ֥ॺ؇ॖ஥ᇂđఃᆴႵ 16 ᇕॖିđॖ๙‫ݖ‬༯‫܄‬ൔ࠹ෘğ +T1stpulse = TP W M_clk × 8 × (P W M _CARRIERx_P RESCALE + 1) × (P W M _CARRIERx_OSHT W T H + 1) +ఃᇏğ + + • TP MW _clk ູ PWM ൈᇒᇛ௹ (PWM_clk) + • (P W M _CARRIERx_OSHT W T H + 1) ູ၂ՑྟઝԊॺ؇ᆴč౼ᆴٓຶğ1-16Ď + • (P W M _CARRIERx_P RESCALE + 1) PWM ᄛѯൈᇒ (PC_clk) ყ‫ٳ‬௔ᆴ +๭ 16-28 ᅚൕਔֻ၂۱ઝԊ‫ބ‬ᆭުӻ࿃֥ઝԊb + +ুᶈྐ༏॓࠯ 398 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + ๭ 16­28. ᄛѯଆॶֻ֥၂۱ઝԊ‫ބ‬ᆭުӻ࿃֥ઝԊൕ২ + +ᅝॢб॥ᇅ +ᄝ‫ؿ‬ԛֻ၂۱၂ՑྟઝԊᆭުđ۴ऌᄛѯ௔ੱ‫ט‬ᇅഺჅ֥ PWM ྐ‫ݼ‬bႨ޼ॖ஥ᇂ‫֥ݼྐھ‬ᅝॢбbᄝ၂‫ק‬౦ +ঃ༯đ‫ט‬ᆜᅝॢбॖ൐ྐ‫ݼ‬๙‫ۯݖ‬৖э࿢ఖުಯಖॖၛषఓࠇܱо‫ࠏ׮׈‬౺‫׮‬ఖđ‫ڿ‬э‫ࠏ׈‬࿈ሇ෎؇‫ބ‬ٚ +ཟb +ᅝॢб๙‫࠷ݖ‬թఖ PWM_CARRIERx_CFG_REG ֥ PWM_CARRIERx_DUTY ֻ 5 ֞ 7 ໊ഡᇂđఃᆴႵ 7 ᇕॖି +ྟb +ᅝॢб֥ᆴॖ๙‫ݖ‬ၛ༯ٚൔ࠹ෘğ + + Duty = P W M _CARRIERx_DU T Y ÷ 8 +๭ 16-29 ູ෮Ⴕ 7 ᇕᅝॢбഡᇂb + +ুᶈྐ༏॓࠯ 399 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + ๭ 16­29. PWM ᄛѯଆॶᇏӻ࿃ઝԊ֥ 7 ᇕᅝॢбഡᇂ + +16.3.3.4 ‫ܣ‬ᅰԩ৘ఖଆॶ + +ૄ۱ MCPWM ຓഡ‫׻‬৵ࢤটሱ GPIO इᆔ֥ 3 ۱‫ܣ‬ᅰྐ‫ݼ‬čFAULT0đFAULT1 ‫ ބ‬FAULT2Ďbᆃུྐ‫ݼ‬ႨႿᆷൕ +ຓ҆‫ܣ‬ᅰሑঃđѩ౏ॖႮ‫ܣ‬ᅰ࡟ҩଆॶყԩ৘ުളӮ‫ܣ‬ᅰ൙ࡱb‫ܣ‬ᅰ൙ࡱ๙‫ݖ‬ᆳྛႨ޼ս઒đᆌؓห‫ܣק‬ᅰ‫ט‬ +ᆜ MCPWM ൻԛb + +‫ܣ‬ᅰԩ৘ଆॶ‫ିۿ‬ +‫ܣ‬ᅰԩ৘ଆॶ֥ᇶေ‫ູିۿ‬ğ + + • ᄝ࡟ҩ֞‫ܣ‬ᅰൈ఼ᇅ PWMxA ‫ ބ‬PWMxB ൻԛྐ‫ࣉݼ‬ೆၛ༯ሑ෿ᆭ၂ğ + –ۚ + –֮ + – ౼ّ + –໭ + + • ᄝ࡟ҩ֞‫׈ݖ‬ੀ‫ݖ‬ᄛĔ؋ਫ਼ൈᆳྛ၂Ցྟ๋ᅃčOSTĎb + • ᇯᇛ௹๋ᅃčCBCĎၛิ‫܂‬ཋੀҠቔb + • ૄ۱‫ܣ‬ᅰྐ‫ݼ‬ֆ‫ٳ׿‬஥၂Ցྟࠇᇯᇛ௹Ҡቔb + • ૄ۱‫ܣ‬ᅰൻೆ‫׻‬ളӮᇏ؎b + • ᆦӻೈࡱ఼ᇅ๋ᅃb + • ۴ऌླေषఓࠇܱоଆॶ‫ିۿ‬b + +ুᶈྐ༏॓࠯ 400 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +Ҡቔა஥ᇂေׄ + +Чࢫิ‫ܣ܂‬ᅰԩ৘ଆॶ֥Ҡቔေׄ‫ބ‬஥ᇂ࿊ཛb + +টሱܵ࢖֥‫ܣ‬ᅰྐ‫ݼ‬ᄝ GPIO इᆔᇏҐဢ‫ބ‬๝҄bູਔЌᆣ‫ܣ‬ᅰઝԊҐဢ֥Ӯ‫ۿ‬đૄ۱ઝԊӻ࿃ൈࡗсྶᇀഒ +ູ 2 ۱ APB ൈᇒᇛ௹b‫ܣ‬ᅰ࡟ҩଆॶ൐Ⴈ PWM_clk ؓ‫ܣ‬ᅰྐ‫ྛࣉݼ‬ҐဢđၹՎটሱ GPIO इᆔ֥‫ܣ‬ᅰઝԊӻ +࿃ൈࡗсྶᇀഒູ 1 ۱ PWM_clk ᇛ௹bၹՎđ໭ં APB ൈᇒᇛ௹‫ ބ‬PWM_clk ᇛ௹֥նཬܱ༢ೂ‫ޅ‬đܵ࢖ഈ +֥‫ܣ‬ᅰྐ‫ݼ‬ઝԊ֥ॺ؇сྶᇀഒ֩Ⴟਆ۱ APB ൈᇒᇛ௹ა၂۱ PWM_clk ᇛ௹֥‫ބ‬b + +‫ܣ‬ᅰԩ৘ఖଆॶॖၛ൐Ⴈ‫ܣ‬ᅰྐ‫ ݼ‬FAULT0 ᇀ FAULT2 ᇏ֥ۚ‫׈‬௜ࠇ֮‫׈‬௜টളӮ‫ܣ‬ᅰ൙ࡱ fault_event0 ᇀ +fault_event2bૄ۱‫ܣ‬ᅰ൙ࡱॖၛֆ‫׿‬஥ᇂູࣉྛ CBC ҠቔđOST Ҡቔࠇ໭Ҡቔb + + • ᇯᇛ௹ (CBC) Ҡቔğ + ֒ CBC ҠቔФԨ‫ؿ‬đPWMxA ‫ ބ‬PWMxB ֥ሑ෿৫ࠧ۴ऌ࠷թఖ PWM_FHx_A_CBC_U/D ‫ބ‬ + PWM_FHx_B_CBC_U/D ֥ഡᇂ‫ڿ‬эbPWM ‫ק‬ൈఖ‫־‬ᄹࠇ‫࠹ࡨ־‬ඔൈđॖᆷ‫ק‬҂๝֥Ҡቔb҂๝֥‫ܣ‬ᅰ + ൙ࡱॖԨ‫ؿ‬҂๝֥ᇯᇛ௹Ҡቔᇏ؎b๙‫ݖ‬ሑ෿࠷թఖ PWM_FHx_CBC_ON षఓࠇܱо CBC Ҡቔbᄝી + Ⴕ‫ܣ‬ᅰ൙ࡱൈđࡼᄝᆷ‫ק‬ൈࡗׄđࠧ‫ؿ‬ള D/UTEP ࠇ D/UTEZ ൙ࡱൈౢԢ PWMxA/B ഈ֥ CBC Ҡቔb࠷ + թఖ PWM_FHx_CBCPULSE ॥ᇅथ‫ ק‬PWMxA ‫ ބ‬PWMxB ߫‫گ‬ᆞӈ֥൙ࡱbၹՎđᄝՎଆൔ༯đCBC Ҡ + ቔᄝૄ۱ PWM ࿖ߌުౢԢࠇ඗ྍb + + • ၂ՑྟčOSTĎҠቔğ + ֒ OST ҠቔФԨ‫ؿ‬ൈđPWMxA ‫ ބ‬PWMxB ֥ሑ෿৫ࠧ۴ऌ࠷թఖ PWM_FHx_A_OST_U/D ‫ބ‬ + PWM_FHx_B_OST_U/D ‫ڿ‬эbPWM ‫ק‬ൈఖ‫־‬ᄹࠇ‫࠹ࡨ־‬ඔൈđॖ஥ᇂ҂๝֥Ҡቔb҂๝֥‫ܣ‬ᅰ൙ࡱॖ + Ԩ‫ؿ‬҂๝֥ OST Ҡቔᇏ؎b๙‫ݖ‬ሑ෿࠷թఖ PWM_FHx_OST_ON षఓࠇܱо OST ҠቔbPWMxA/B ഈ֥ + OST ҠቔࡼᄝીႵ‫ܣ‬ᅰ൙ࡱൈ҂ିሱ‫׮‬ౢԢb၂ՑྟҠቔсླದູ๙‫࠷ࡼݖ‬թఖ PWM_FHx_CLR_OST + ֥ᆴ౼ّটౢԢb + +16.3.4 ѽࠆଆॶ +16.3.4.1 ࢺക + +ѽࠆଆॶЇ‫ ݣ‬3 ۱ປᆜ֥ѽࠆ๙֡b๙֡ൻೆྐ‫ ݼ‬CAP0đCAP1 ‫ ބ‬CAP2 টሱႿ GPIO इᆔbႮႿ GPIO इᆔ +֥ਲࠃྟđCAP0đCAP1 ‫ ބ‬CAP2 ॖၛ๙‫ݖ‬಩၂ܵ࢖ൻೆ஥ᇂb‫؟‬۱ѽࠆ๙֡ॖၛটሱ๝၂ܵ࢖ൻೆđ‫ૄط‬۱ +๙֥֡ყ‫ٳ‬௔ॖၛ‫ٳ‬љഡᇂbՎຓđૄ۱ѽࠆ๙֡ߎॖၛটሱ҂๝֥ܵ࢖ൻೆbၹՎđॖၛ๙‫ުݖ‬෻႗ࡱႨ‫؟‬ +ᇕٚൔԩ৘ѽࠆྐ‫ݼ‬đ‫ط‬҂ᆰࢤႮ CPU ԩ৘b + +ૄ۱ଆॶ‫׻‬Ⴕၛ༯‫׿‬৫ሧჷğ + + • ၂۱ 32 ໊‫ק‬ൈఖč࠹ඔఖĎđॖა PWM ‫ק‬ൈఖđਸ਼၂۱ଆॶࠇೈࡱ๝҄b + + • 3 ۱ѽࠆ๙֡đૄ۱๙֡஥Ⴕ၂۱ 32 ໊ൈࡗՄ‫ބ‬၂۱ѽࠆყ‫ٳ‬௔ఖb + + • ಩‫ޅ‬ѽࠆ๙֥֡шခࠞྟčഈശ/༯ࢆခĎॖ‫׿‬৫࿊ᄴb + + • ൻೆѽࠆྐ‫ݼ‬ყ‫ٳ‬௔č‫ٳ‬௔౼ᆴٓຶğ1 ⚶256Ďb + + • ೘۱ѽࠆ൙ࡱ‫׻‬Ⴕᇏ؎‫ିۿ‬b + +16.3.4.2 ѽࠆ‫ק‬ൈఖ + +ѽࠆ‫ק‬ൈఖ൞၂۱ 32 ໊࠹ඔఖđ൐ିൈ҂؎‫־‬ᄹ࠹ඔbൻೆ؊֥ APB ൈᇒ௔ੱ๙ӈູ 80 MHzb‫ؿ‬ള๝҄൙ +ࡱൈđࡆᄛ࠹ඔఖđఃཌྷ໊թԥᄝ࠷թఖ PWM_CAP_TIMER_PHASE_REG ᇏb๝҄൙ࡱॖটሱ PWM ‫ק‬ൈఖ +๝҄ൻԛđPWM ଆॶ๝҄ൻೆđࠇೈࡱb‫ھ‬ѽࠆ‫ק‬ൈఖູ෮Ⴕ 3 ۱ѽࠆ๙֡ิ‫ק܂‬ൈҕॉb + +ুᶈྐ༏॓࠯ 401 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +16.3.4.3 ѽࠆ๙֡ + +сေൈđ֞ղѽࠆ๙֥֡ѽࠆྐ‫ݼ‬ॖ༵Фّཌྷđಖުყ‫ٳ‬௔bቋުđყԩ৘ު֥ѽࠆྐ‫֥ݼ‬ᆷ‫ק‬шခࡼԨ‫ؿ‬ѽ +ࠆ൙ࡱbᄝѽࠆ൙ࡱ‫ؿ‬ളൈđѽࠆ‫ק‬ൈఖ֥ᆴթԥᄝൈࡗՄ࠷թఖ PWM_CAP_CHx_REG ᇏbѽࠆ൙ࡱᇏ֥҂ +๝ѽࠆ๙֡ॖളӮ҂๝֥ᇏ؎bԨ‫ؿ‬ѽࠆ൙ࡱ֥шခԥթᄝ࠷թఖ PWM_CAPx_EDGE ᇏbѽࠆ൙ࡱॖႮೈࡱ +఼ᇅ‫ؿ‬ളb + +16.4 ࠷թఖਙі + +࠷թఖਙі ૭ඍ PWM0 PWM1 ٠໙ +ყ‫ٳ‬௔ఖ஥ᇂ + 0x3FF5E000 0x3FF6C000 ‫؀‬/ཿ +PWM_CLK_CFG_REG ஥ᇂყ‫ٳ‬௔ఖ +PWM ‫ק‬ൈఖ 0 ஥ᇂაሑ෿ 0x3FF5E004 0x3FF6C004 ‫؀‬/ཿ + 0x3FF5E008 0x3FF6C008 ‫؀‬/ཿ +PWM_TIMER0_CFG0_REG ‫ק‬ൈఖᇛ௹ა۷ྍٚ‫م‬ 0x3FF5E00C 0x3FF6C00C ‫؀‬/ཿ + 0x3FF5E010 0x3FF6C010 ᆺ‫؀‬ +PWM_TIMER0_CFG1_REG ‫۽‬ቔଆൔაष൓Ĕ๔ᆸ॥ᇅ + 0x3FF5E014 0x3FF6C014 ‫؀‬/ཿ +PWM_TIMER0_SYNC_REG ๝҄ഡᇂ 0x3FF5E018 0x3FF6C018 ‫؀‬/ཿ + 0x3FF5E01C 0x3FF6C01C ‫؀‬/ཿ +PWM_TIMER0_STATUS_REG ‫ק‬ൈఖሑ෿ 0x3FF5E020 0x3FF6C020 ᆺ‫؀‬ +PWM ‫ק‬ൈఖ 1 ஥ᇂაሑ෿ + 0x3FF5E024 0x3FF6C024 ‫؀‬/ཿ +PWM_TIMER1_CFG0_REG ‫ק‬ൈఖ۷ྍٚൔაᇛ௹ 0x3FF5E028 0x3FF6C028 ‫؀‬/ཿ + 0x3FF5E02C 0x3FF6C02C ‫؀‬/ཿ +PWM_TIMER1_CFG1_REG ‫۽‬ቔଆൔაष൓Ĕ๔ᆸ॥ᇅ 0x3FF5E030 0x3FF6C030 ᆺ‫؀‬ + +PWM_TIMER1_SYNC_REG ๝҄ഡᇂ 0x3FF5E034 0x3FF6C034 ‫؀‬/ཿ + 0x3FF5E038 0x3FF6C038 ‫؀‬/ཿ +PWM_TIMER1_STATUS_REG ‫ק‬ൈఖሑ෿ +PWM ‫ק‬ൈఖ 2 ஥ᇂაሑ෿ 0x3FF5E03C 0x3FF6C03C ‫؀‬/ཿ + 0x3FF5E040 0x3FF6C040 +PWM_TIMER2_CFG0_REG ‫ק‬ൈఖ۷ྍაሑ෿ 0x3FF5E044 0x3FF6C044 ‫؀‬/ཿ + 0x3FF5E048 0x3FF6C048 ‫؀‬/ཿ +PWM_TIMER2_CFG1_REG ‫۽‬ቔଆൔაष൓Ĕ๔ᆸ॥ᇅ 0x3FF5E04C 0x3FF6C04C ‫؀‬/ཿ + 0x3FF5E050 0x3FF6C050 +PWM_TIMER2_SYNC_REG ๝҄ഡᇂ 0x3FF5E054 0x3FF6C054 ‫؀‬/ཿ + 0x3FF5E058 0x3FF6C058 +PWM_TIMER2_STATUS_REG ‫ק‬ൈఖሑ෿ 0x3FF5E05C 0x3FF6C05C ‫؀‬/ཿ +PWM ‫ק‬ൈఖӈ࡮஥ᇂ 0x3FF5E060 0x3FF6C060 ‫؀‬/ཿ + 0x3FF5E064 0x3FF6C064 ‫؀‬/ཿ +PWM_TIMER_SYNCI_CFG_REG ‫ק‬ൈఖ๝҄ൻೆ࿊ᄴ 0x3FF5E068 0x3FF6C068 ‫؀‬/ཿ + ‫؀‬/ཿ +PWM_OPERATOR_TIMERSEL_REG ູ PWM Ҡቔఖ࿊ᄴห‫࠹֥ק‬ൈఖ ‫؀‬/ཿ +PWM Ҡቔఖ 0 ஥ᇂაሑ෿ + ‫؀‬/ཿ +PWM_GEN0_STMP_CFG_REG ൈࡗՄ࠷թఖ A ‫ ބ‬B ֥Ԯൻሑ෿ + ‫ބ‬۷ྍٚൔ + +PWM_GEN0_TSTMP_A_REG ࠷թఖ A ֥႕ሰ࠷թఖ + +PWM_GEN0_TSTMP_B_REG ࠷թఖ B ֥႕ሰ࠷թఖ + +PWM_GEN0_CFG0_REG ‫ܣ‬ᅰൈࡗ T0 ‫ ބ‬T1 ԩ৘ + +PWM_GEN0_FORCE_REG ೈࡱ఼ᇅ PWM0A ‫ ބ‬PWM0B ൻ + ԛ + +PWM_GEN0_A_REG PWM0A ൻԛഈ൙ࡱԨ‫֥ؿ‬Ҡቔ + +PWM_GEN0_B_REG PWM0B ൻԛഈ൙ࡱԨ‫֥ؿ‬Ҡቔ + +PWM_DT0_CFG_REG ඵ౵აো྘֥࿊ᄴა஥ᇂ + +PWM_DT0_FED_CFG_REG FED ֥႕ሰ࠷թఖ + +PWM_DT0_RED_CFG_REG RED ֥႕ሰ࠷թఖ + +PWM_CARRIER0_CFG_REG ᄛѯ൐ିა஥ᇂ + +PWM_FH0_CFG0_REG ‫ܣ‬ᅰ൙ࡱᇏ PWM0A ‫ ބ‬PWM0B + ഈ֥Ҡቔ + +ুᶈྐ༏॓࠯ 402 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +࠷թఖਙі ૭ඍ PWM0 PWM1 ٠໙ +PWM_FH0_CFG1_REG ‫ܣ‬ᅰԩ৘֥ೈࡱԨ‫ؿ‬ 0x3FF5E06C 0x3FF6C06C ‫؀‬/ཿ +PWM_FH0_STATUS_REG ‫ܣ‬ᅰ൙ࡱሑ෿ 0x3FF5E070 0x3FF6C070 ᆺ‫؀‬ +PWM Ҡቔఖ 1 ஥ᇂაሑ෿ + ൈࡗՄ࠷թఖ A ‫ ބ‬B ֥Ԯൻሑ෿ 0x3FF5E074 0x3FF6C074 ‫؀‬/ཿ +PWM_GEN1_STMP_CFG_REG ‫ބ‬۷ྍٚൔ + ࠷թఖ A ֥႕ሰ࠷թఖ 0x3FF5E078 0x3FF6C078 ‫؀‬/ཿ +PWM_GEN1_TSTMP_A_REG ࠷թఖ B ֥႕ሰ࠷թఖ 0x3FF5E07C 0x3FF6C07C ‫؀‬/ཿ +PWM_GEN1_TSTMP_B_REG ‫ܣ‬ᅰ൙ࡱ T0 ‫ ބ‬T1 ԩ৘ 0x3FF5E080 0x3FF6C080 ‫؀‬/ཿ +PWM_GEN1_CFG0_REG ೈࡱ఼ᇅ PWM1A ‫ ބ‬PWM1B ൻ + ԛ 0x3FF5E084 0x3FF6C084 ‫؀‬/ཿ +PWM_GEN1_FORCE_REG PWM1A ൻԛഈ֥൙ࡱԨ‫֥ؿ‬Ҡቔ + PWM1B ൻԛഈ֥൙ࡱԨ‫֥ؿ‬Ҡቔ 0x3FF5E088 0x3FF6C088 ‫؀‬/ཿ +PWM_GEN1_A_REG ඵ౵ো྘֥࿊ᄴა஥ᇂ 0x3FF5E08C 0x3FF6C08C ‫؀‬/ཿ +PWM_GEN1_B_REG FED ֥႕ሰ࠷թఖ 0x3FF5E090 0x3FF6C090 ‫؀‬/ཿ +PWM_DT1_CFG_REG RED ֥႕ሰ࠷թఖ 0x3FF5E094 0x3FF6C094 ‫؀‬/ཿ +PWM_DT1_FED_CFG_REG ൐ିა஥ᇂᄛѯ 0x3FF5E098 0x3FF6C098 ‫؀‬/ཿ +PWM_DT1_RED_CFG_REG ‫ܣ‬ᅰ൙ࡱᇏ PWM1A ‫ ބ‬PWM1B 0x3FF5E09C 0x3FF6C09C ‫؀‬/ཿ +PWM_CARRIER1_CFG_REG ൻԛഈ֥Ҡቔ + ‫ܣ‬ᅰԩ৘֥ೈࡱԨ‫ؿ‬ 0x3FF5E0A0 0x3FF6C0A0 ‫؀‬/ཿ +PWM_FH1_CFG0_REG ‫ܣ‬ᅰ൙ࡱሑ෿ + 0x3FF5E0A4 0x3FF6C0A4 ‫؀‬/ཿ +PWM_FH1_CFG1_REG 0x3FF5E0A8 0x3FF6C0A8 ᆺ‫؀‬ +PWM_FH1_STATUS_REG +PWM Ҡቔఖ 2 ֥஥ᇂაሑ෿ ൈࡗՄ࠷թఖ A ‫ ބ‬B ֥Ԯൻሑ෿ 0x3FF5E0AC 0x3FF6C0AC ‫؀‬/ཿ + ‫ބ‬۷ྍٚൔ +PWM_GEN2_STMP_CFG_REG ࠷թఖ A ֥႕ሰ࠷թఖ 0x3FF5E0B0 0x3FF6C0B0 ‫؀‬/ཿ + ࠷թఖ B ֥႕ሰ࠷թఖ 0x3FF5E0B4 0x3FF6C0B4 ‫؀‬/ཿ +PWM_GEN2_TSTMP_A_REG ‫ܣ‬ᅰ൙ࡱ T0 ‫ ބ‬T1 ԩ৘ 0x3FF5E080 0x3FF6C080 ‫؀‬/ཿ +PWM_GEN2_TSTMP_B_REG ೈࡱ఼ᇅ PWM2A ‫ ބ‬PWM2B ൻ +PWM_GEN2_CFG0_REG ԛ 0x3FF5E0BC 0x3FF6C0BC ‫؀‬/ཿ + PWM2A ൻԛഈ֥൙ࡱԨ‫֥ؿ‬Ҡቔ +PWM_GEN2_FORCE_REG PWM2B ൻԛഈ֥൙ࡱԨ‫֥ؿ‬Ҡቔ 0x3FF5E0C0 0x3FF6C0C0 ‫؀‬/ཿ + ඵ౵ো྘֥࿊ᄴა஥ᇂ 0x3FF5E0C4 0x3FF6C0C4 ‫؀‬/ཿ +PWM_GEN2_A_REG FED ႕ሰ࠷թఖ 0x3FF5E0C8 0x3FF6C0C8 ‫؀‬/ཿ +PWM_GEN2_B_REG RED ႕ሰ࠷թఖ 0x3FF5E0CC 0x3FF6C0CC ‫؀‬/ཿ +PWM_DT2_CFG_REG ൐ିა஥ᇂᄛѯ 0x3FF5E0D0 0x3FF6C0D0 ‫؀‬/ཿ +PWM_DT2_FED_CFG_REG ‫ܣ‬ᅰ൙ࡱᇏ PWM2A ‫ ބ‬PWM2B 0x3FF5E0D4 0x3FF6C0D4 ‫؀‬/ཿ +PWM_DT2_RED_CFG_REG ൻԛഈ֥Ҡቔ +PWM_CARRIER2_CFG_REG ‫ܣ‬ᅰԩ৘֥ೈࡱԨ‫ؿ‬ 0x3FF5E0D8 0x3FF6C0D8 ‫؀‬/ཿ + ‫ܣ‬ᅰ൙ࡱሑ෿ +PWM_FH2_CFG0_REG 0x3FF5E0DC 0x3FF6C0DC ‫؀‬/ཿ + 0x3FF5E0E0 0x3FF6C0E0 ᆺ‫؀‬ +PWM_FH2_CFG1_REG +PWM_FH2_STATUS_REG ‫ܣ‬ᅰ࡟ҩა஥ᇂ 0x3FF5E0E4 0x3FF6C0E4 ‫؀‬/ཿ +‫ܣ‬ᅰ࡟ҩა஥ᇂ +PWM_FAULT_DETECT_REG ஥ᇂѽࠆ‫ק‬ൈఖ 0x3FF5E0E8 0x3FF6C0E8 ‫؀‬/ཿ +ѽࠆ஥ᇂაሑ෿ ѽࠆ‫ק‬ൈఖ๝҄ཌྷ໊ 0x3FF5E0EC 0x3FF6C0EC ‫؀‬/ཿ +PWM_CAP_TIMER_CFG_REG +PWM_CAP_TIMER_PHASE_REG + +ুᶈྐ༏॓࠯ 403 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + +࠷թఖਙі ૭ඍ PWM0 PWM1 ٠໙ +PWM_CAP_CH0_CFG_REG ѽࠆ๙֡ 0 ֥஥ᇂა൐ି 0x3FF5E0F0 0x3FF6C0F0 ‫؀‬/ཿ +PWM_CAP_CH1_CFG_REG ѽࠆ๙֡ 1 ֥஥ᇂა൐ି 0x3FF5E0F4 0x3FF6C0F4 ‫؀‬/ཿ +PWM_CAP_CH2_CFG_REG ѽࠆ๙֡ 2 ֥஥ᇂა൐ି 0x3FF5E0F8 0x3FF6C0F8 ‫؀‬/ཿ +PWM_CAP_CH0_REG ѽࠆ๙֡ 0 ഈ၂Ցѽࠆ֥ᆴ 0x3FF5E0FC 0x3FF6C0FC ᆺ‫؀‬ +PWM_CAP_CH1_REG ѽࠆ๙֡ 1 ഈ၂Ցѽࠆ֥ᆴ 0x3FF5E100 0x3FF6C100 ᆺ‫؀‬ +PWM_CAP_CH2_REG ѽࠆ๙֡ 2 ഈ၂Ցѽࠆ֥ᆴ 0x3FF5E104 0x3FF6C104 ᆺ‫؀‬ +PWM_CAP_STATUS_REG ഈ၂ՑѽࠆԨ‫ؿ‬ఖ֥шခ 0x3FF5E108 0x3FF6C108 ᆺ‫؀‬ +൐ିႵི࠷թఖ֥۷ྍ +PWM_UPDATE_CFG_REG ൐ି۷ྍ 0x3FF5E10C 0x3FF6C10C ‫؀‬/ཿ +ܵ৘ᇏ؎ +INT_ENA_PWM_REG ᇏ؎൐ି໊ 0x3FF5E110 0x3FF6C110 ‫؀‬/ཿ +INT_RAW_PWM_REG ჰ൓ᇏ؎ሑ෿ 0x3FF5E114 0x3FF6C114 ᆺ‫؀‬ +INT_ST_PWM_REG ௠зᇏ؎ሑ෿ 0x3FF5E118 0x3FF6C118 ᆺ‫؀‬ +INT_CLR_PWM_REG ᇏ؎ౢԢ໊ 0x3FF5E11C 0x3FF6C11C WO + +16.5 ࠷թఖ + + Register 16.1. PWM_CLK_CFG_REG (0x0000) + + (reserved) PWM_CLK_PRESCALE + +31 87 0 + +000000000000000000000000 0x000 Reset + + PWM_CLK_PRESCALE PWM_clk ֥ᇛ௹ = 6.25 ns * (PWM_CLK_PRESCALE + 1)bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 404 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.2. PWM_TIMER0_CFG0_REG (0x0004) + + (reserved) PWM_TIMER0_PERIOD_UPMETHOD PWM_TIMER0_PERIOD PWM_TIMER0_PRESCALE + +31 26 25 24 23 87 0 + +000000 0 0x000FF 0x000 Reset + + PWM_TIMER0_PERIOD_UPMETHOD PWM ‫ק‬ൈఖ 0 ᇛ௹Ⴕི࠷թఖ֥۷ྍٚൔb0ğ৫ࠧ۷ྍĠ + 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠ2ğ๝҄ൈ۷ྍĠ3ğ‫ؿ‬ള TEZ ൙ࡱࠇ๝҄ൈ۷ྍbЧ໓֖ᇏđTEZ ᆷ + ‫ק‬ൈఖູ 0 ൈ֥൙ࡱbč‫؀‬ĔཿĎ + + PWM_TIMER0_PERIOD ࠹ൈఖ 0 ֥႕ሰᇛ௹࠷թఖbč‫؀‬ĔཿĎ + + PWM_TIMER0_PRESCALE PT0_clk ᇛ௹ = PWM_clk ᇛ௹ * (PWM_TIMER0_PRESCALE + 1)bč‫؀‬ + ĔཿĎ + + Register 16.3. PWM_TIMER0_CFG1_REG (0x0008) + + (reserved) PWM_TIMER0P_WMMOD_TIMER0_START + +31 54 32 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Reset + + PWM_TIMER0_MOD PWM ‫ק‬ൈఖ 0 ‫۽‬ቔଆൔb0ğᄠ๔Ġ1ğ‫־‬ᄹଆൔĠ2ğ‫ࡨ־‬ଆൔĠ3ğ‫־‬ᄹ‫־‬ + ࡨ࿖ߌଆൔbč‫؀‬ĔཿĎ + + PWM_TIMER0_START ॥ᇅ PWM ‫ק‬ൈఖ֥षఓაܱоb0ğೂ‫ݔ‬षఓđᄝ TEZ ൙ࡱ‫ؿ‬ളൈ๔ᆸĠ + 1ğೂ‫ݔ‬षఓđᄝ TEP ൙ࡱ‫ؿ‬ളൈ๔ᆸĠ2ğषఓĠ3ğषఓđѩᄝ༯၂۱ TEZ ൙ࡱ‫ؿ‬ളൈ๔ᆸĠ4ğ + षఓđѩᄝ༯၂۱ TEP ൙ࡱ‫ؿ‬ളൈ๔ᆸbЧ໓֖ᇏđTEP ᆷ‫ק‬ൈఖູᇛ௹ᆴൈ‫ؿ‬ള֥൙ࡱbč‫؀‬ + ĔཿĎ + +ুᶈྐ༏॓࠯ 405 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.4. PWM_TIMER0_SYNC_REG (0x000c) + + (reserved) PWM_TIMER0_PHASE_DIRECTION PWM_TIMER0_PHASE PWM_TIPMWERM0_P_TWSIMYMNE_RCT0OIM__SESYREN0L_CS_YSNWCI_EN + 0 +31 21 20 19 43 21 0 + +0 0 0 0 0 0 0 0 0 0 00 0 0 0 Reset + + PWM_TIMER0_PHASE_DIRECTION 0ğ‫־‬ᄹĠ1ğ‫ࡨ־‬bč‫؀‬/ཿĎ + PWM_TIMER0_PHASE ๝҄൙ࡱᇏ‫ק‬ൈఖᇗᄛ֥ཌྷ໊bč‫؀‬ĔཿĎ + PWM_TIMER0_SYNCO_SEL ࿊ᄴ PWM ‫ק‬ൈఖ 0 ֥๝҄ൻԛটჷb0ğ๝҄Ġ1ğTEZĠ2ğTEPĠ + + ః෰ᆴğ๝҄ൻԛ၂ᆰൻԛ 0bč‫؀‬ĔཿĎ + PWM_TIMER0_SYNC_SW Վ໊౼ّđԨ‫ؿ‬ೈࡱ๝҄bč‫؀‬ĔཿĎ + PWM_TIMER0_SYNCI_EN ᇂ 1 ൈđ൐ିᄝ๝҄ൻೆ൙ࡱ‫ؿ‬ളൈ֥‫ק‬ൈఖཌྷ໊ᇗᄛbč‫؀‬ĔཿĎ + + Register 16.5. PWM_TIMER0_STATUS_REG (0x0010) + + (reserved) PWM_TIMER0_DIRECTION PWM_TIMER0_VALUE + 0 +31 17 16 15 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 Reset + + PWM_TIMER0_DIRECTION ֒భ PWM ‫ק‬ൈఖ 0 ֥࠹ඔఖଆൔb0ğ‫־‬ᄹଆൔĠ1ğ‫ࡨ־‬ଆൔbčᆺ + ‫؀‬Ď + + PWM_TIMER0_VALUE ֒భ PWM ‫ק‬ൈఖ 0 ࠹ඔఖ֥ᆴbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 406 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.6. PWM_TIMER1_CFG0_REG (0x0014) + + (reserved) PWM_TIMER1_PERIOD_UPMETHOD PWM_TIMER1_PERIOD PWM_TIMER1_PRESCALE + +31 26 25 24 23 87 0 + +000000 0 0x000FF 0x000 Reset + + PWM_TIMER1_PERIOD_UPMETHOD PWM ‫ק‬ൈఖ 1 ᇛ௹Ⴕི࠷թఖ֥۷ྍٚൔb0ğ৫ࠧ۷ྍĠ + 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠ2ğ๝҄ൈ۷ྍĠ3ğ‫ؿ‬ള TEZ ൙ࡱࠇ๝҄ൈ۷ྍbč‫؀‬ĔཿĎ + + PWM_TIMER1_PERIOD ‫ק‬ൈఖ 1 ֥႕ሰᇛ௹࠷թఖbč‫؀‬ĔཿĎ + + PWM_TIMER1_PRESCALE PT1_clk ᇛ௹ = PWM_clk ᇛ௹ * (PWM_TIMER1_PRESCALE + 1)bč‫؀‬ + ĔཿĎ + + Register 16.7. PWM_TIMER1_CFG1_REG (0x0018) + + (reserved) PWM_TIMER1P_WMMOD_TIMER1_START + +31 54 32 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Reset + + PWM_TIMER1_MOD PWM ࠹ൈఖ 1 ֥‫۽‬ቔଆൔb0ğᄠ๔Ġ1ğ‫־‬ᄹଆൔĠ2ğ‫ࡨ־‬ଆൔĠ3ğ‫־‬ᄹ + ‫ࡨ־‬࿖ߌଆൔbč‫؀‬ĔཿĎ + + PWM_TIMER1_START PWM ॥ᇅ‫ק‬ൈఖ 1 ֥षఓა๔ᆸb0ğೂ‫ݔ‬षఓđᄝ‫ؿ‬ള TEZ ൙ࡱൈ๔ᆸĠ + 1ğೂ‫ݔ‬षఓđᄝ‫ؿ‬ള TEP ൙ࡱൈ๔ᆸĠ2ğषఓĠ3ğषఓѩᄝ༯၂Ց TEZ ൙ࡱᇏ๔ᆸĠ4ğष + ఓѩᄝ༯၂Ց TEP ൙ࡱᇏ๔ᆸbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 407 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.8. PWM_TIMER1_SYNC_REG (0x001c) + + (reserved) PWM_TIMER1_PHASE_DIRECTION PWM_TIMER1_PHASE PWM_TIPMWERM1_P_TWSIMYMNE_RCT1OIM__SESYREN1L_CS_YSNWCI_EN + 0 +31 21 20 19 43 21 0 + +0 0 0 0 0 0 0 0 0 0 00 0 0 0 Reset + + PWM_TIMER1_PHASE_DIRECTION 0ğ‫־‬ᄹĠ1ğ‫ࡨ־‬bč‫؀‬/ཿĎ + PWM_TIMER1_PHASE ๝҄ൈࡗᇏ࠹ൈఖᇗᄛ֥ཌྷ໊bč‫؀‬ĔཿĎ + PWM_TIMER1_SYNCO_SEL ࿊ᄴ PWM ࠹ൈఖ 1 ๝҄ൻԛটჷb0ğ๝҄ൻೆĠ1ğTEZĠ2ğTEPĠ + + ః෰ᆴğ๝҄ൻԛ၂ᆰൻԛ 0bč‫؀‬ĔཿĎ + PWM_TIMER1_SYNC_SW Վ໊౼ّđԨ‫ؿ‬ೈࡱ๝҄൙ࡱbč‫؀‬ĔཿĎ + PWM_TIMER1_SYNCI_EN ᇂ 1 ൈđ൐ିᄝ๝҄ൻೆ൙ࡱൈ֥‫ק‬ൈఖཌྷ໊ᇗᄛbč‫؀‬ĔཿĎ + + Register 16.9. PWM_TIMER1_STATUS_REG (0x0020) + + (reserved) PWM_TIMER1_DIRECTION PWM_TIMER1_VALUE + 0 +31 17 16 15 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 Reset + + PWM_TIMER1_DIRECTION ֒భ PWM ࠹ൈఖ 1 ֥࠹ඔఖଆൔb0ğ‫־‬ᄹĠ1ğ‫ࡨ־‬bčᆺ‫؀‬Ď + PWM_TIMER1_VALUE ֒భ PWM ࠹ൈఖ 1 ֥࠹ඔఖᆴbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 408 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.10. PWM_TIMER2_CFG0_REG (0x0024) + + (reserved) PWM_TIMER2_PERIOD_UPMETHOD PWM_TIMER2_PERIOD PWM_TIMER2_PRESCALE + +31 26 25 24 23 87 0 + +000000 0 0x000FF 0x000 Reset + + PWM_TIMER2_PERIOD_UPMETHOD PWM ‫ק‬ൈఖ 2 ᇛ௹Ⴕི࠷թఖ֥۷ྍٚൔb0ğ৫ࠧ۷ྍĠ + 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠ2ğ‫ؿ‬ള๝҄ൈࡗൈ۷ྍĠ3ğ‫ؿ‬ള TEZ ࠇ๝҄൙ࡱൈ۷ྍbč‫؀‬ĔཿĎ + + PWM_TIMER2_PERIOD PWM ‫ק‬ൈఖ 2 ֥႕ሰᇛ௹࠷թఖbč‫؀‬ĔཿĎ + + PWM_TIMER2_PRESCALE PT2_clk ᇛ௹ = PWM_clk ᇛ௹ * (PWM_TIMER2_PRESCALE + 1)bč‫؀‬ + ĔཿĎ + + Register 16.11. PWM_TIMER2_CFG1_REG (0x0028) + + (reserved) PWM_TIMER2P_WMMOD_TIMER2_START + +31 54 32 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Reset + + PWM_TIMER2_MOD PWM ‫ק‬ൈఖ 2 ֥‫۽‬ቔଆൔb0ğᄠ๔Ġ1ğ‫־‬ᄹଆൔĠ2ğ‫ࡨ־‬ଆൔĠ3ğ‫־‬ᄹ + ‫ࡨ־‬࿖ߌଆൔbč‫؀‬ĔཿĎ + + PWM_TIMER2_START ॥ᇅ PWM ‫ק‬ൈఖ 2 ֥षఓა๔ᆸb0ğೂ‫ݔ‬षఓđᄝ‫ؿ‬ള TEZ ൙ࡱൈ๔ᆸĠ + 1ğೂ‫ݔ‬षఓđᄝ‫ؿ‬ള TEP ൙ࡱൈ๔ᆸĠ2ğषఓĠ3ğषఓѩᄝ༯၂۱ TEZ ൙ࡱൈ๔ᆸĠ4ğष + ఓѩᄝ༯၂۱ TEZ ൙ࡱൈ๔ᆸbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 409 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.12. PWM_TIMER2_SYNC_REG (0x002c) + + (reserved) PWM_TIMER2_PHASE_DIRECTION PWM_TIMER2_PHASE PWM_TIPMWERM2_P_TWSIMYMNE_RCT2OIM__SESYREN2L_CS_YSNWCI_EN + 0 +31 21 20 19 43 21 0 + +0 0 0 0 0 0 0 0 0 0 00 0 0 0 Reset + + PWM_TIMER2_PHASE_DIRECTION 0ğ‫־‬ᄹĠ1ğ‫ࡨ־‬bč‫؀‬/ཿĎ + PWM_TIMER2_PHASE ๝҄൙ࡱᇏ‫ק‬ൈఖᇗᄛཌྷ໊bč‫؀‬ĔཿĎ + PWM_TIMER2_SYNCO_SEL ࿊ᄴ PWM ‫ק‬ൈఖ 2 ๝҄ൻԛটჷb0ğ๝҄ൻೆĠ1ğTEZĠ2ğTEPĠ + + ః෰ᆴğ๝҄ൻԛ၂ᆰൻԛ 0bč‫؀‬ĔཿĎ + PWM_TIMER2_SYNC_SW Վ໊౼ّđԨ‫ؿ‬ೈࡱ๝҄൙ࡱbč‫؀‬ĔཿĎ + PWM_TIMER2_SYNCI_EN ᇂ 1 ൈ൐ିᄝ๝҄ൻೆ൙ࡱൈ֥‫ק‬ൈఖཌྷ໊ᇗᄛbč‫؀‬ĔཿĎ + + Register 16.13. PWM_TIMER2_STATUS_REG (0x0030) + + (reserved) PWM_TIMER2_DIRECTION PWM_TIMER2_VALUE + 0 +31 17 16 15 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 Reset + + PWM_TIMER2_DIRECTION ֒భ PWM ‫ק‬ൈఖ 2 ֥࠹ඔఖଆൔb0ğ‫־‬ᄹଆൔĠ1ğ‫ࡨ־‬ଆൔbčᆺ + ‫؀‬Ď + + PWM_TIMER2_VALUE ֒భ PWM ‫ק‬ൈఖ 2 ࠹ඔఖ֥ᆴbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 410 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.14. PWM_TIMER_SYNCI_CFG_REG (0x0034) + + (reserved) PWM_PEWXMTE_PREWNXMTAEL_R_ESNXYTAENLPR_CWSNI2MYA_NL_IN_TCVSIIM1EY_ERNIRNTC2VI0_E_SRPIYNTWNVCEMRI_STTEILMER1_SPYWNCMI_STEILMER0_SYNCISEL + +31 12 11 10 9 8 65 32 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 Reset + + PWM_EXTERNAL_SYNCI2_INVERT ࡼটሱ GPIO इᆔ֥ SYNC2 ّཌྷbč‫؀‬ĔཿĎ + + PWM_EXTERNAL_SYNCI1_INVERT ࡼটሱ GPIO इᆔ֥ SYNC1 ّཌྷbč‫؀‬ĔཿĎ + + PWM_EXTERNAL_SYNCI0_INVERT ࡼটሱ GPIO इᆔ֥ SYNC0 ّཌྷbč‫؀‬ĔཿĎ + + PWM_TIMER2_SYNCISEL ࿊ᄴ PWM ‫ק‬ൈఖ 2 ֥๝҄ൻೆটჷb1ğPWM ‫ק‬ൈఖ 0 ๝҄ൻԛĠ2ğ + PWM ‫ק‬ൈఖ 1 ๝҄ൻԛĠ3ğPWM ‫ק‬ൈఖ 2 ๝҄ൻԛĠ4ğটሱ GPIO इᆔ֥ SYNC0Ġ5ğটሱ + GPIO इᆔ֥ SYNC1Ġ6ğটሱ GPIO इᆔ֥ SYNC2Ġః෰ᆴğໃ࿊ᄴ಩‫ޅ‬๝҄ൻೆbč‫؀‬ĔཿĎ + + PWM_TIMER1_SYNCISEL ࿊ᄴ PWM ‫ק‬ൈఖ 1 ֥๝҄ൻೆটჷb1ğPWM ‫ק‬ൈఖ 0 ๝҄ൻԛĠ2ğ + PWM ‫ק‬ൈఖ 1 ๝҄ൻԛĠ3ğPWM ‫ק‬ൈఖ 2 ๝҄ൻԛĠ4ğটሱ GPIO इᆔ֥ SYNC0Ġ5ğটሱ + GPIO इᆔ֥ SYNC1Ġ6ğটሱ GPIO इᆔ֥ SYNC2Ġః෰ᆴğໃ࿊ᄴ಩‫ޅ‬๝҄ൻೆbč‫؀‬ĔཿĎ + + PWM_TIMER0_SYNCISEL ࿊ᄴ PWM ‫ק‬ൈఖ 0 ֥๝҄ൻೆটჷb1ğPWM ‫ק‬ൈఖ 0 ๝҄ൻԛĠ2ğ + PWM ‫ק‬ൈఖ 1 ๝҄ൻԛĠ3ğPWM ‫ק‬ൈఖ 2 ๝҄ൻԛĠ4ğটሱ GPIO इᆔ֥ SYNC0Ġ5ğটሱ + GPIO इᆔ֥ SYNC1Ġ6ğটሱ GPIO इᆔ֥ SYNC2Ġః෰ᆴğໃ࿊ᄴ಩‫ޅ‬๝҄ൻೆbč‫؀‬ĔཿĎ + + Register 16.15. PWM_OPERATOR_TIMERSEL_REG (0x0038) + + (reserved) PWM_OPERPWATMO_RO2P_TEIRPMWAETMROS_REO1LP_TEIRMAETROSRE0L_TIMERSEL + +31 65 43 21 0 + +00000000000000000000000000 0 0 0 Reset + + PWM_OPERATOR2_TIMERSEL ࿊ᄴ PWM Ҡቔఖ 2 ֥‫ק‬ൈҕॉটჷb0ğ‫ק‬ൈఖ 0Ġ1ğ‫ק‬ൈఖ 1Ġ + 2ğ‫ק‬ൈఖ 2bč‫؀‬ĔཿĎ + + PWM_OPERATOR1_TIMERSEL ࿊ᄴ PWM Ҡቔఖ 1 ֥‫ק‬ൈҕॉটჷb0ğ‫ק‬ൈఖ 0Ġ1ğ‫ק‬ൈఖ 1Ġ + 2ğ‫ק‬ൈఖ 2bč‫؀‬ĔཿĎ + + PWM_OPERATOR0_TIMERSEL ࿊ᄴ PWM Ҡቔఖ 0 ֥‫ק‬ൈҕॉটჷb0ğ‫ק‬ൈఖ 0Ġ1ğ‫ק‬ൈఖ 1Ġ + 2ğ‫ק‬ൈఖ 2bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 411 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.16. PWM_GEN0_STMP_CFG_REG (0x003c) + + (reserved) PWM_PGWEMN_0G_BE_NS0H_ADP_WWSM_HFD_UGWLEL_NF0U_LBL_UPMEPTWHOMD_GEN0_A_UPMETHOD + +31 10 9 8 7 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 Reset + + PWM_GEN0_B_SHDW_FULL Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđPWM ളӮఖ 0 ൈࡗՄ࠷թఖ B ֥႕ + ሰ࠷թఖФཿೆđཿೆ֥ᆴࡼԮൻ۳Ⴕི࠷թఖ BbౢਬൈđႵི࠷թఖ B ᇏཿೆః႕ሰ࠷թఖ + ቋྍ֥ᆴbčᆺ‫؀‬Ď + + PWM_GEN0_A_SHDW_FULL ႗ࡱᇂ 1 ࠇ‫໊گ‬bᇂ 1 ൈđPWM ളӮఖ 0 ൈࡗՄ࠷թఖ A ֥႕ሰ + ࠷թఖФཿೆđཿೆ֥ᆴࡼԮൻ۳Ⴕི࠷թఖ AbౢਬൈđႵི࠷թఖ A ᇏཿೆః႕ሰ࠷թఖቋ + ྍ֥ᆴbčᆺ‫؀‬Ď + + PWM_GEN0_B_UPMETHOD PWM ളӮఖ 0 ൈࡗՄ࠷թఖ B Ⴕི࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴ + ູ 0ğ৫ࠧ۷ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ + ‫ؿ‬ള๝҄ൈࡗൈ۷ྍĠbit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + + PWM_GEN0_A_UPMETHOD PWM ളӮఖ 0 ൈࡗՄ࠷թఖ A Ⴕི࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴ + ູ 0ğ৫ࠧ۷ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ + ‫ؿ‬ള๝҄ൈࡗൈ۷ྍĠbit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + + Register 16.17. PWM_GEN0_TSTMP_A_REG (0x0040) + + (reserved) PWM_GEN0_A + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_GEN0_A PWM ളӮఖ 0 ൈࡗՄ࠷թఖ A ֥႕ሰ࠷թఖbč‫؀‬ĔཿĎ + + Register 16.18. PWM_GEN0_TSTMP_B_REG (0x0044) + + (reserved) PWM_GEN0_B + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_GEN0_B PWM ളӮఖ 0 ൈࡗՄ࠷թఖ B ֥႕ሰ࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 412 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.19. PWM_GEN0_CFG0_REG (0x0048) + + (reserved) PWM_GEN0_T1_PSWELM_GEN0_T0_SEPLWM_GEN0_CFG_UPMETHOD + +31 10 9 76 43 0 + +0000000000000000000000 0 0 0 Reset + + PWM_GEN0_T1_SEL ࿊ᄴ PWM ളӮఖ 0 event_t1 ֥ྐ‫ݼ‬ჷđ৫ࠧളིb0ğfault_event0Ġ1ğ + fault_event1Ġ2ğfault_event2Ġ3ğsync_takenĠ4ğ໭bč‫؀‬ĔཿĎ + + PWM_GEN0_T0_SEL ࿊ᄴ PWM ളӮఖ 0 event_t0 ֥ྐ‫ݼ‬ჷđ৫ࠧളིb0ğfault_event0Ġ1ğ + fault_event1Ġ2ğfault_event2Ġ3ğsync_takenĠ4ğ໭bč‫؀‬ĔཿĎ + + PWM_GEN0_CFG_UPMETHOD PWM ളӮఖ 0 Ⴕི஥ᇂ࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴູ 0ğ৫ + ࠧ۷ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള๝ + ҄ൈࡗൈ۷ྍĠbit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 413 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.20. PWM_GEN0_FORCE_REG (0x004c) + + (reserved) PWM_GEPNW0M_B_G_NEPCNWI0FM_OB_RG_CNEPECNW_I0FMM_OA_ORG_DCNEPEECNWI0FM_OA_RG_CNEECN_PI0FM_WOBORM_DCC_EGENETNU0FO_AR_CCEN_TMUOPFDOWERMC_EG_EMNO0D_CENTUFORCE_UPMETHOD + +31 16 15 14 13 12 11 10 9 87 65 0 + +0000000000000000 0 0 0 0 0 0 0x20 Reset + + PWM_GEN0_B_NCIFORCE_MODE ഡᇂ PWM0B ഈ֥٤৵࿃ࠧൈೈࡱ఼ᇅଆൔb0ğܱоĠ1ğ֮ + ‫׈‬௜Ġ2ğۚ‫׈‬௜Ġ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN0_B_NCIFORCE ‫໊֥ھ‬ᆴ౼ّൈࡼԨ‫ ؿ‬PWM0B ഈ֥٤৵࿃ࠧൈೈࡱ఼ᇅ൙ࡱbč‫؀‬ + ĔཿĎ + + PWM_GEN0_A_NCIFORCE_MODE ഡᇂႨႿ PWM0A ֥٤৵࿃ࠧൈೈࡱ఼ᇅଆൔb0ğܱоĠ1ğ + ֮‫׈‬௜Ġ2ğۚ‫׈‬௜Ġ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN0_A_NCIFORCE ‫໊֥ھ‬ᆴ౼ّൈࡼԨ‫ ؿ‬PWM0A ഈ֥٤৵࿃ࠧൈೈࡱ఼ᇅ൙ࡱbč‫؀‬Ĕ + ཿĎ + + PWM_GEN0_B_CNTUFORCE_MODE PWM0B ֥৵࿃ೈࡱ఼ᇅଆൔb0ğܱоĠ1ğ֮‫׈‬௜Ġ2ğۚ + ‫׈‬௜Ġ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN0_A_CNTUFORCE_MODE ഡᇂ PWM0A ֥৵࿃ೈࡱ఼ᇅଆൔb0ğܱоĠ1ğ֮‫׈‬௜Ġ + 2ğۚ‫׈‬௜Ġ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN0_CNTUFORCE_UPMETHOD ളӮఖ 0 ֥৵࿃ೈࡱ఼ᇅ൙ࡱ۷ྍٚൔb෮Ⴕ bit ູ 0 + ൈğ৫ࠧ۷ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ + ‫ؿ‬ള TEA ൙ࡱൈ۷ྍĠbit3 ູ 1ğ‫ؿ‬ള TEB ൙ࡱൈ۷ྍĠbit4ğ‫ؿ‬ള๝҄൙ࡱൈ۷ྍĠbit5 ູ 1ğ + ܱо۷ྍbčЧ໓֖ᇏđTEA/B ᆷ‫ק‬ൈఖᆴູ࠷թఖ A/B ֥ᆴൈളӮ֥൙ࡱbĎč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 414 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.21. PWM_GEN0_A_REG (0x0050) + + (reserved) PWM_GENP0_WAM_D_GT1ENP0_WAM_D_GT0ENP0_WAM_D_GTEEBNP0_WAM_D_GTEEANP0_WAM_D_GTEEPNP0_WAM_D_GTEEZNP0_WAM_U_GT1ENP0_WAM_U_GT0ENP0_WAM_U_GTEEBNP0_WAM_U_GTEEANP0_WAM_U_GTEEPN0_A_UTEZ + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 65 43 21 0 + +00000000 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_GEN0_A_DT1 ‫ק‬ൈఖ‫ࡨ־‬ൈđevent_t1 ᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔb0ğѯྙ໭‫ڿ‬эĠ1ğঘ֮Ġ + 2ğঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_GEN0_A_DT0 ‫ק‬ൈఖ‫ࡨ־‬ൈđevent_t0 ᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_A_DTEB ‫ק‬ൈఖ‫ࡨ־‬ൈđTEB ൙ࡱᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_A_DTEA ‫ק‬ൈఖ‫ࡨ־‬ൈđTEA ൙ࡱᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_A_DTEP ‫ק‬ൈఖ‫ࡨ־‬ൈđTEP ൙ࡱᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_A_DTEZ ‫ק‬ൈఖ‫ࡨ־‬ൈđTEZ ൙ࡱᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_A_UT1 ‫ק‬ൈఖ‫־‬ᄹൈđevent_t1 ᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_A_UT0 ‫ק‬ൈఖ‫־‬ᄹൈđevent_t0 ᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_A_UTEB ‫ק‬ൈఖ‫־‬ᄹൈđTEB ൙ࡱᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_A_UTEA ‫ק‬ൈఖ‫־‬ᄹൈđTEA ൙ࡱᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_A_UTEP ‫ק‬ൈఖ‫־‬ᄹൈđTEP ൙ࡱᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_A_UTEZ ‫ק‬ൈఖ‫־‬ᄹൈđTEZ ൙ࡱᄝ PWM0A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 415 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.22. PWM_GEN0_B_REG (0x0054) + + (reserved) PWM_GENP0_WBM_D_GT1ENP0_WBM_D_GT0ENP0_WBM_D_GTEEBNP0_WBM_D_GTEEANP0_WBM_D_GTEEPNP0_WBM_D_GTEEZNP0_WBM_U_GT1ENP0_WBM_U_GT0ENP0_WBM_U_GTEEBNP0_WBM_U_GTEEANP0_WBM_U_GTEEPN0_B_UTEZ + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 65 43 21 0 + +00000000 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_GEN0_B_DT1 ‫ק‬ൈఖ‫ࡨ־‬ൈđevent_t1 ᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔb0ğѯྙ໭‫ڿ‬эĠ1ğঘ + ֮Ġ2ğঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_GEN0_B_DT0 ‫ק‬ൈఖ‫ࡨ־‬ൈđevent_t0 ൙ࡱᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_B_DTEB ‫ק‬ൈఖ‫ࡨ־‬ൈđTEB ൙ࡱᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_B_DTEA ‫ק‬ൈఖ‫ࡨ־‬ൈđTEA ൙ࡱᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_B_DTEP ‫ק‬ൈఖ‫ࡨ־‬ൈđTEP ൙ࡱᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_B_DTEZ ‫ק‬ൈఖ‫ࡨ־‬ൈđTEZ ൙ࡱᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_B_UT1 ‫ק‬ൈఖ‫־‬ᄹൈđevent_t1 ᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_B_UT0 ‫ק‬ൈఖ‫־‬ᄹൈđevent_t0 ᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_B_UTEB ‫ק‬ൈఖ‫־‬ᄹൈđTEB ᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_B_UTEA ‫ק‬ൈఖ‫־‬ᄹൈđTEA ᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_B_UTEP ‫ק‬ൈఖ‫־‬ᄹൈđTEP ᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN0_B_UTEZ ‫ק‬ൈఖ‫־‬ᄹൈđTEZ ᄝ PWM0B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 416 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.23. PWM_DT0_CFG_REG (0x0058) + + (reserved) PWM_PDWTM0__PCDWLTMK0___PSBDWE_TOLM0U__PADTW_BTOM0YU_P_PFATDWEBSTDMY0S__P_PORADWUESTMDTS0I___NPFODWVEUTEDM0TR__I_PNTIRNDWVESTEMD0ER__L_PTBIDNW_TSOM0EU__LADT_STOW0U_ADTPSEPBWW_AMMP_ODDTE0_RED_UPMPEWTHMO_DDT0_FED_UPMETHOD + +31 18 17 16 15 14 13 12 11 10 9 8 7 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 00 1 1 0 0 0 0 0 0 0 0 0 Reset + + PWM_DT0_CLK_SEL ࿊ᄴඵ౵ൈࡗളӮఖ 0 ֥ൈᇒb0ğPWM_clkĠ1ğPT_clkbč‫؀‬ĔཿĎ + + PWM_DT0_B_OUTBYPASS і 16-5 ᇏ֥ S0bč‫؀‬ĔཿĎ + + PWM_DT0_A_OUTBYPASS і 16-5 ᇏ֥ S1bč‫؀‬ĔཿĎ + + PWM_DT0_FED_OUTINVERT і 16-5 ᇏ֥ S3bč‫؀‬ĔཿĎ + + PWM_DT0_RED_OUTINVERT і 16-5 ᇏ֥ S2bč‫؀‬ĔཿĎ + + PWM_DT0_FED_INSEL і 16-5 ᇏ֥ S5bč‫؀‬ĔཿĎ + + PWM_DT0_RED_INSEL і 16-5 ᇏ֥ S4bč‫؀‬ĔཿĎ + + PWM_DT0_B_OUTSWAP і 16-5 ᇏ֥ S7bč‫؀‬ĔཿĎ + + PWM_DT0_A_OUTSWAP S6 і 16-5 ᇏ֥ S6bč‫؀‬ĔཿĎ + + PWM_DT0_DEB_MODE S8 і 16-5 ᇏ֥ S8, B ਫ਼චшခଆൔb0ğ༯ࢆခ࿼ӾĔ༯ࢆခ࿼Ӿ‫ٳ‬љ + ᄝ҂๝֥ਫ਼ࣥᇏളིĠ1ğ༯ࢆခ࿼ӾĔ༯ࢆခ࿼Ӿᄝਫ਼ࣥ B ഈളིĠPWMxA ᆞӈൻԛbč‫؀‬Ĕ + ཿĎ + + PWM_DT0_RED_UPMETHOD ഈശခ࿼ӾႵི࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴູ 0ğ৫ࠧ۷ྍĠbit0 + ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള๝҄ൈࡗൈ۷ྍĠ + bit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + + PWM_DT0_FED_UPMETHOD ༯ࢆခ࿼ӾႵི࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴູ 0ğ৫ࠧ۷ྍĠbit0 + ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള๝҄ൈࡗൈ۷ྍĠ + bit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + + Register 16.24. PWM_DT0_FED_CFG_REG (0x005c) + + (reserved) PWM_DT0_FED + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_DT0_FED FED ֥႕ሰ࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 417 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.25. PWM_DT0_RED_CFG_REG (0x0060) + + (reserved) PWM_DT0_RED + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_DT0_RED RED ֥႕ሰ࠷թఖbč‫؀‬ĔཿĎ + + Register 16.26. PWM_CARRIER0_CFG_REG (0x0064) + + (reserved) PWM_PCWAMR_RCIEARR0R_IIENPR_W0IN_MVO_EUCRTAT_RINRVIEERR0T_OPSWHMW_TCHARRIER0_DPUWTYM_CARRIEPRW0_MP_RCEASRCRAIELRE0_EN + +31 14 13 12 11 87 54 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 Reset + + PWM_CARRIER0_IN_INVERT ᇂ 1 ൈđࡼՎଆॶ֥ PWM0A ‫ ބ‬PWM0B ൻೆّཌྷbč‫؀‬ĔཿĎ + PWM_CARRIER0_OUT_INVERT ᇂ 1 ൈđࡼՎଆॶ֥ PWM0A ‫ ބ‬PWM0B ൻԛّཌྷbč‫؀‬ĔཿĎ + PWM_CARRIER0_OSHWTH ᄛѯֻ၂۱ઝԊ֥ॺ؇đֆູ໊ᄛѯᇛ௹bč‫؀‬ĔཿĎ + PWM_CARRIER0_DUTY ࿊ᄴᄛѯᅝॢбbᅝॢб = PWM_CARRIER0_DUTY / 8bč‫؀‬ĔཿĎ + PWM_CARRIER0_PRESCALE PWM ᄛѯ 0 ൈᇒ (PC_clk) ֥ყ‫ٳ‬௔ᆴbPC_clk ᇛ௹ = PWM_clk ᇛ + + ௹ * (PWM_CARRIER0_PRESCALE + 1)bč‫؀‬ĔཿĎ + PWM_CARRIER0_EN ᇂ 1 ൈđ൐ିᄛѯ 0 ֥‫ିۿ‬bౢਬൈđᄛѯ 0 Фಡ‫ݖ‬bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 418 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.27. PWM_FH0_CFG0_REG (0x0068) + + (reserved) M_FH0_B_OMS_TF_HU0_B_OMS_TF_HD0_B_CMB_CFH_U0_B_CMB_CFH_D0_A_OMS_TF_HU0_A_OMS_TF_HD0_A_CMB_CFH_U0_AM__CFBHMC0___FDF0H_M0O__SFFT1H_M0O__SFFT2H_M0O__SSFTWHM0__O_FFS0HT_M0C__BFFC1H_M0C__BFFC2H_0C_BSCW_CBC + PW PW PW PW PW PW PW PW PW PW PW PW PW PW PW PW + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 6 5 4 3 2 1 0 + +00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_FH0_B_OST_U ‫ק‬ൈఖ‫־‬ᄹ࠹ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM0B ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH0_B_OST_D ‫ק‬ൈఖ‫࠹ࡨ־‬ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM0B ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH0_B_CBC_U ‫ק‬ൈఖ‫־‬ᄹ࠹ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM0B ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH0_B_CBC_D ‫ק‬ൈఖ‫࠹ࡨ־‬ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM0B ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH0_A_OST_U ‫ק‬ൈఖ‫־‬ᄹ࠹ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM0A ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH0_A_OST_D ‫ק‬ൈఖ‫࠹ࡨ־‬ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM0A ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH0_A_CBC_U ‫ק‬ൈఖ‫־‬ᄹ࠹ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM0A ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH0_A_CBC_D ‫ק‬ൈఖ‫࠹ࡨ־‬ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM0A ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH0_F0_OST ഡᇂ event_f0 ൞‫ڎ‬Ԩ‫ؿ‬၂ՑྟଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH0_F1_OST ഡᇂ event_f1 ൞‫ڎ‬Ԩ‫ؿ‬၂ՑྟଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH0_F2_OST ഡᇂ event_f2 ൞‫ڎ‬Ԩ‫ؿ‬၂ՑྟଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH0_SW_OST ೈࡱ఼ᇅ၂ՑྟଆൔҠቔ֥൐ି࠷թఖb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH0_F0_CBC ഡᇂ event_f0 ൞‫ڎ‬Ԩ‫ؿ‬ᇯᇛ௹ଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH0_F1_CBC ഡᇂ event_f1 ൞‫ڎ‬Ԩ‫ؿ‬ᇯᇛ௹ଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH0_F2_CBC ഡᇂ event_f2 ൞‫ڎ‬Ԩ‫ؿ‬ᇯᇛ௹ଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH0_SW_CBC ൐ିೈࡱ఼ᇅᇯᇛ௹ଆൔҠb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 419 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.28. PWM_FH0_CFG1_REG (0x006c) + + (reserved) PWM_PFWHM0__FFOHPR0W_CFMEO__ROFHCSP0ETW__CMCBB_FCCHP0U_LCSLER_OST + +31 54 32 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_FH0_FORCE_OST ๙‫ݖ‬ೈࡱࡼՎ໊֥ᆴ౼ّđॖԨ‫ؿ‬၂Ցྟଆൔ֥Ҡቔbč‫؀‬ĔཿĎ + PWM_FH0_FORCE_CBC ๙‫ݖ‬ೈࡱࡼՎ໊֥ᆴ౼ّđॖԨ‫ؿ‬ᇯᇛ௹ଆൔ֥Ҡቔbč‫؀‬ĔཿĎ + PWM_FH0_CBCPULSE ഡᇂᇯᇛ௹ଆൔҠቔ۷ྍ֥ൈࡗׄbbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈĠbit1 ູ + + 1ğ‫ؿ‬ള TEP ൙ࡱൈbč‫؀‬ĔཿĎ + PWM_FH0_CLR_OST ๙‫ݖ‬ೈࡱࡼՎ໊֥ᆴ౼ّđౢԢӻ࿃၂ՑྟଆൔҠቔbč‫؀‬ĔཿĎ + + Register 16.29. PWM_FH0_STATUS_REG (0x0070) + + (reserved) PWM_PFWHM0__OFHST0__OCBNC_ON + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_FH0_OST_ON Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđ၂Ցྟଆൔ֥Ҡቔᆞᄝࣉྛࣉྛbčᆺ‫؀‬Ď + PWM_FH0_CBC_ON Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđᇯᇛ௹ଆൔ֥Ҡቔᆞᄝࣉྛࣉྛbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 420 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.30. PWM_GEN1_STMP_CFG_REG (0x0074) + + (reserved) PWM_PGWEMN_1G_BE_NS1H_ADP_WWSM_HFD_UGWLEL_NF1U_LBL_UPMEPTWHOMD_GEN1_A_UPMETHOD + +31 10 9 8 7 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 Reset + + PWM_GEN1_B_SHDW_FULL Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđPWM ളӮఖ 1 ൈࡗՄ࠷թఖ B ֥႕ + ሰ࠷թఖФཿೆđཿೆ֥ᆴࡼԮൻ۳Ⴕི࠷թఖ BbౢਬൈđႵི࠷թఖ B ᇏཿೆః႕ሰ࠷թఖ + ቋྍ֥ᆴbčᆺ‫؀‬Ď + + PWM_GEN1_A_SHDW_FULL Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđPWM ളӮఖ 1 ൈࡗՄ࠷թఖ A ֥႕ + ሰ࠷թఖФཿೆđཿೆ֥ᆴࡼԮൻ۳Ⴕི࠷թఖ AbౢਬൈđႵི࠷թఖ A ᇏཿೆః႕ሰ࠷թఖ + ቋྍ֥ᆴbčᆺ‫؀‬Ď + + PWM_GEN1_B_UPMETHOD PWM ളӮఖ 1 ൈࡗՄ࠷թఖ B Ⴕི࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴ + ູ 0ğ৫ࠧ۷ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ + ‫ؿ‬ള๝҄ൈ۷ྍĠbit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + + PWM_GEN1_A_UPMETHOD PWM ളӮఖ 1 ൈࡗՄ࠷թఖ A Ⴕི࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴ + ູ 0ğ৫ࠧ۷ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ + ‫ؿ‬ള๝҄ൈࡗൈ۷ྍĠbit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + + Register 16.31. PWM_GEN1_TSTMP_A_REG (0x0078) + + (reserved) PWM_GEN1_A + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_GEN1_A PWM ളӮఖ 1 ൈࡗՄ࠷թఖ A ֥႕ሰ࠷թఖbč‫؀‬ĔཿĎ + + Register 16.32. PWM_GEN1_TSTMP_B_REG (0x007c) + + (reserved) PWM_GEN1_B + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_GEN1_B PWM ളӮఖ 1 ൈࡗՄ࠷թఖ B ֥႕ሰ࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 421 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.33. PWM_GEN1_CFG0_REG (0x0080) + + (reserved) PWM_GEN1_T1_PSWELM_GEN1_T0_SEPLWM_GEN1_CFG_UPMETHOD + +31 10 9 76 43 0 + +0000000000000000000000 0 0 0 Reset + + PWM_GEN1_T1_SEL ࿊ᄴ PWM ളӮఖ 1 event_t1 ֥ྐ‫ݼ‬ჷđ৫ࠧളིb0ğfault_event0Ġ1ğ + fault_event1Ġ2ğfault_event2Ġ3ğsync_takenĠ4ğ໭bč‫؀‬ĔཿĎ + + PWM_GEN1_T0_SEL ࿊ᄴ PWM ളӮఖ 1 event_t0 ֥ྐ‫ݼ‬ჷđ৫ࠧളིb0ğfault_event0Ġ1ğ + fault_event1Ġ2ğfault_event2Ġ3ğsync_takenĠ4ğ໭bč‫؀‬ĔཿĎ + + PWM_GEN1_CFG_UPMETHOD PWM ളӮఖ 1 Ⴕི࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴູ 0ğ৫ࠧ۷ + ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള๝҄ൈ + ࡗൈ۷ྍĠbit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 422 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.34. PWM_GEN1_FORCE_REG (0x0084) + + (reserved) PWM_GEPNW1M_B_G_NEPCNWI1FM_OB_RG_CNEPECNW_I1FMM_OA_ORG_DCNEPEECNWI1FM_OA_RG_CNEECN_PI1FM_WOBORM_DCC_EGENETNU1FO_AR_CCEN_TMUOPFDOWERMC_EG_EMNO1D_CENTUFORCE_UPMETHOD + +31 16 15 14 13 12 11 10 9 87 65 0 + +0000000000000000 0 0 0 0 0 0 0x20 Reset + + PWM_GEN1_B_NCIFORCE_MODE ႨႿ PWM1B ֥٤ӻ࿃ྟࠧൈೈࡱ఼ᇅ൙ࡱb0ğܱоĠ1ğঘ + ֮Ġ2ğঘۚĠ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN1_B_NCIFORCE ‫໊֥ھ‬ᆴ౼ّൈࡼԨ‫ ؿ‬PWM1B ഈ֥٤৵࿃ࠧൈೈࡱ఼ᇅ൙ࡱbč‫؀‬ + ĔཿĎ + + PWM_GEN1_A_NCIFORCE_MODE ႨႿ PWM1B ֥٤ӻ࿃ྟࠧൈೈࡱ఼ᇅ൙ࡱb0ğܱоĠ1ğঘ + ֮Ġ2ğঘۚĠ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN1_A_NCIFORCE ‫໊֥ھ‬ᆴ౼ّൈࡼԨ‫ ؿ‬PWM1A ഈ֥٤৵࿃ࠧൈೈࡱ఼ᇅ൙ࡱbč‫؀‬Ĕ + ཿĎ + + PWM_GEN1_B_CNTUFORCE_MODE ႨႿ PWM1B ֥৵࿃ೈࡱ఼ᇅ൙ࡱb0ğܱоĠ1ğঘ֮Ġ2ğ + ঘۚĠ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN1_A_CNTUFORCE_MODE ႨႿ PWM1A ֥৵࿃ೈࡱ఼ᇅ൙ࡱb0ğܱоĠ1ğঘ֮Ġ2ğ + ঘۚĠ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN1_CNTUFORCE_UPMETHOD PWM ളӮఖ 1 ӻ࿃ೈࡱ఼ᇅ֥۷ྍٚൔb0ğ৫ࠧ۷ྍĠ + bit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള TEA ൙ࡱ + ൈ۷ྍĠbit3 ູ 1ğ‫ؿ‬ള TEB ൙ࡱൈ۷ྍĠbit4 ູ 1ğ‫ؿ‬ള๝҄ൈࡗൈ۷ྍĠbit5 ູ 1ğܱо۷ + ྍbčЧ໓֖ᇏ֥ TEA/B іൕ࠹ൈఖᆴ֩Ⴟ࠷թఖ A/B ളӮ֥൙ࡱbĎč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 423 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.35. PWM_GEN1_A_REG (0x0088) + + (reserved) PWM_GENP1_WAM_D_GT1ENP1_WAM_D_GT0ENP1_WAM_D_GTEEBNP1_WAM_D_GTEEANP1_WAM_D_GTEEPNP1_WAM_D_GTEEZNP1_WAM_U_GT1ENP1_WAM_U_GT0ENP1_WAM_U_GTEEBNP1_WAM_U_GTEEANP1_WAM_U_GTEEPN1_A_UTEZ + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 65 43 21 0 + +00000000 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_GEN1_A_DT1 ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđevent_t1 ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔb0ğ໭Ġ1ğঘ֮Ġ2ğ + ঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_GEN1_A_DT0 ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđevent_t0 ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_A_DTEB ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđTEB ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_A_DTEA ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđTEA ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_A_DTEP ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđTEP ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_A_DTEZ ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđTEZ ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_A_UT1 ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđevent_t1 ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_A_UT0 ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđevent_t0 ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_A_UTEB ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđTEB ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_A_UTEA ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđTEA ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_A_UTEP ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđTEP ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_A_UTEZ ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđTEZ ᄝ PWM1A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 424 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.36. PWM_GEN1_B_REG (0x008c) + + (reserved) PWM_GENP1_WBM_D_GT1ENP1_WBM_D_GT0ENP1_WBM_D_GTEEBNP1_WBM_D_GTEEANP1_WBM_D_GTEEPNP1_WBM_D_GTEEZNP1_WBM_U_GT1ENP1_WBM_U_GT0ENP1_WBM_U_GTEEBNP1_WBM_U_GTEEANP1_WBM_U_GTEEPN1_B_UTEZ + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 65 43 21 0 + +00000000 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_GEN1_B_DT1 ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđevent_t1 ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔb0ğ໭Ġ1ğঘ֮Ġ2ğ + ঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_GEN1_B_DT0 ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđevent_t0 ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_B_DTEB ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđTEB ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_B_DTEA ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđTEA ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_B_DTEP ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđTEP ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_B_DTEZ ‫ק‬ൈఖ‫࠹ࡨ־‬ඔൈđTEZ ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_B_UT1 ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđevent_t1 ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_B_UT0 ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđevent_t0 ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_B_UTEB ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđTEB ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_B_UTEA ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđTEA ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_B_UTEP ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđTEP ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN1_B_UTEZ ‫ק‬ൈఖ‫־‬ᄹ࠹ඔൈđTEZ ᄝ PWM1B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 425 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.37. PWM_DT1_CFG_REG (0x0090) + + (reserved) PWM_PDWTM1__PCDWLTMK1___PSBDWE_TOLM1U__PADTW_BTOM1YU_P_PFATDWEBSTDMY1S__P_PORADWUESTMDTS1I___NPFODWVEUTEDM1TR__I_PNTIRNDWVESTEMD1ER__L_PTBIDNW_TSOM1EU__LADT_STOW1U_ADTPSEPBWW_AMMP_ODDTE1_RED_UPMPEWTHMO_DDT1_FED_UPMETHOD + +31 18 17 16 15 14 13 12 11 10 9 8 7 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 00 1 1 0 0 0 0 0 0 0 0 0 Reset + + PWM_DT1_CLK_SEL ഡᇂඵ౵ൈࡗളӮఖൈᇒb0ğPWM_clkĠ1ğPT_clkbč‫؀‬ĔཿĎ + PWM_DT1_B_OUTBYPASS і 16-5 ᇏ֥ S0bč‫؀‬ĔཿĎ + PWM_DT1_A_OUTBYPASS і 16-5 ᇏ֥ S1bč‫؀‬ĔཿĎ + PWM_DT1_FED_OUTINVERT і 16-5 ᇏ֥ S3bč‫؀‬ĔཿĎ + PWM_DT1_RED_OUTINVERT і 16-5 ᇏ֥ S2bč‫؀‬ĔཿĎ + PWM_DT1_FED_INSEL і 16-5 ᇏ֥ S5bč‫؀‬ĔཿĎ + PWM_DT1_RED_INSEL і 16-5 ᇏ֥ S4bč‫؀‬ĔཿĎ + PWM_DT1_B_OUTSWAP і 16-5 ᇏ֥ S7bč‫؀‬ĔཿĎ + PWM_DT1_A_OUTSWAP і 16-5 ᇏ֥ S6bč‫؀‬ĔཿĎ + PWM_DT1_DEB_MODE і 16-5 ᇏ֥ S8, B ਫ਼චခଆൔb0ğ༯ࢆခ࿼ӾĔ༯ࢆခ࿼Ӿ‫ٳ‬љᄝ҂๝ + + ֥ਫ਼ࣥᇏളིĠ1ğ༯ࢆခ࿼ӾĔ༯ࢆခ࿼Ӿᄝਫ਼ࣥ B ഈളིĠPWMxA ᆞӈൻԛbč‫؀‬ĔཿĎ + PWM_DT1_RED_UPMETHOD REDčഈശခ࿼ӾĎႵི࠷թఖ֥۷ྍٚൔb0ğ৫ࠧ۷ྍĠbit0 ູ + + 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള๝҄൙ࡱൈ۷ྍĠbit3 + ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + PWM_DT1_FED_UPMETHOD FEDč༯ࢆခ࿼ӾĎႵི࠷թఖ֥۷ྍٚൔb0ğ৫ࠧ۷ྍĠbit0 ູ + 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള๝҄൙ࡱൈ۷ྍĠbit3 + ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + + Register 16.38. PWM_DT1_FED_CFG_REG (0x0094) + + (reserved) PWM_DT1_FED + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_DT1_FED FED ႕ሰ࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 426 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.39. PWM_DT1_RED_CFG_REG (0x0098) + + (reserved) PWM_DT1_RED + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_DT1_RED RED ႕ሰ࠷թఖbč‫؀‬ĔཿĎ + + Register 16.40. PWM_CARRIER1_CFG_REG (0x009c) + + (reserved) PWM_PCWAMR_RCIEARR1R_IIENPR_W1IN_MVO_EUCRTAT_RINRVIEERR1T_OPSWHMW_TCHARRIER1_DPUWTYM_CARRIEPRW1_MP_RCEASRCRAIELRE1_EN + +31 14 13 12 11 87 54 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 Reset + + PWM_CARRIER1_IN_INVERT ᇂ 1 ൈđࡼՎଆॶ֥ PWM1A ‫ ބ‬PWM1B ൻೆّཌྷbč‫؀‬ĔཿĎ + PWM_CARRIER1_OUT_INVERT ᇂ 1 ൈđࡼՎଆॶ֥ PWM1A ‫ ބ‬PWM1B ൻԛّཌྷbč‫؀‬ĔཿĎ + PWM_CARRIER1_OSHWTH ᄛѯֻ၂۱ઝԊ֥ॺ؇đֆູ໊ᄛѯᇛ௹bč‫؀‬ĔཿĎ + PWM_CARRIER1_DUTY ഡᇂᄛѯᅝॢбbᅝॢб = PWM_CARRIER1_DUTY/8bč‫؀‬ĔཿĎ + PWM_CARRIER1_PRESCALE PWM ᄛѯ 1 ൈᇒ (PC_clk) ყ‫ٳ‬௔ᆴbPC_clk ᇛ௹ = PWM_clk ᇛ + + ௹ * (PWM_CARRIER1_PRESCALE + 1)bč‫؀‬ĔཿĎ + PWM_CARRIER1_EN ᇂ 1 ൈđ൐ିᄛѯ 1 ‫ିۿ‬bՎ໊ౢਬൈđಡ‫ݖ‬ᄛѯ 1bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 427 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.41. PWM_FH1_CFG0_REG (0x00a0) + + (reserved) M_FH1_B_OMS_TF_HU1_B_OMS_TF_HD1_B_CMB_CFH_U1_B_CMB_CFH_D1_A_OMS_TF_HU1_A_OMS_TF_HD1_A_CMB_CFH_U1_AM__CFBHMC1___FDF0H_M1O__SFFT1H_M1O__SFFT2H_M1O__SSFTWHM1__O_FFS0HT_M1C__BFFC1H_M1C__BFFC2H_1C_BSCW_CBC + PW PW PW PW PW PW PW PW PW PW PW PW PW PW PW PW + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 6 5 4 3 2 1 0 + +00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_FH1_B_OST_U ‫ק‬ൈఖ‫־‬ᄹ࠹ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM1B ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH1_B_OST_D ‫ק‬ൈఖ‫࠹ࡨ־‬ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM1B ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH1_B_CBC_U ‫ק‬ൈఖ‫־‬ᄹ࠹ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM1B ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH1_B_CBC_D ‫ק‬ൈఖ‫࠹ࡨ־‬ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM1B ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH1_A_OST_U ‫ק‬ൈఖ‫־‬ᄹ࠹ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM1A ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH1_A_OST_D ‫ק‬ൈఖ‫࠹ࡨ־‬ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM1A ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH1_A_CBC_U ‫ק‬ൈఖ‫־‬ᄹ࠹ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM1A ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH1_A_CBC_D ‫ק‬ൈఖ‫࠹ࡨ־‬ඔѩ౏‫ؿ‬ള‫ܣ‬ᅰ൙ࡱൈđPWM1A ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ + 1ğ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH1_F0_OST ഡᇂ event_f0 Ԩ‫ؿ‬၂ՑྟଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH1_F1_OST ഡᇂ event_f1 Ԩ‫ؿ‬၂ՑྟଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH1_F2_OST ഡᇂ event_f2 Ԩ‫ؿ‬၂ՑྟଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH1_SW_OST ೈࡱ఼ᇅ၂ՑྟଆൔҠቔ֥൐ି࠷թఖb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH1_F0_CBC ഡᇂ event_f0 Ԩ‫ؿ‬ᇯᇛ௹ଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH1_F1_CBC ഡᇂ event_f1 Ԩ‫ؿ‬ᇯᇛ௹ଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH1_F2_CBC ഡᇂ event_f2 Ԩ‫ؿ‬ᇯᇛ௹ଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH1_SW_CBC ೈࡱ఼ᇅᇯᇛ௹ଆൔҠቔ֥൐ି࠷թఖb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 428 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.42. PWM_FH1_CFG1_REG (0x00a4) + + (reserved) PWM_PFWHM1__FFOHPR1W_CFMEO__ROFHCSP1ETW__CMCBB_FCCHP1U_LCSLER_OST + +31 54 32 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_FH1_FORCE_OST ๙‫ݖ‬ೈࡱࡼ‫໊ھ‬౼ّൈđԨ‫ؿ‬၂ՑྟଆൔҠቔbč‫؀‬ĔཿĎ + PWM_FH1_FORCE_CBC ๙‫ݖ‬ೈࡱࡼ‫໊ھ‬౼ّൈđԨ‫ؿ‬ᇯᇛ௹ଆൔҠቔbč‫؀‬ĔཿĎ + PWM_FH1_CBCPULSE ഡᇂᇯᇛ௹ଆൔҠቔ֥۷ྍٚൔbbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 + + ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍbč‫؀‬ĔཿĎ + PWM_FH1_CLR_OST ᇂ 1 ౢԢᆞᄝࣉྛ֥၂ՑྟଆൔҠቔbč‫؀‬ĔཿĎ + + Register 16.43. PWM_FH1_STATUS_REG (0x00a8) + + (reserved) PWM_PFWHM1__OFHST1__OCBNC_ON + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_FH1_OST_ON ๙‫ݖ‬႗ࡱࡼᇂ 1 ൈࠇౢਬbᇂ 1 ൈđ၂ՑྟଆൔҠቔᆞᄝࣉྛbčᆺ‫؀‬Ď + PWM_FH1_CBC_ON ๙‫ݖ‬႗ࡱࡼᇂ 1 ൈࠇౢਬbᇂ 1 ൈđᇯᇛ௹ଆൔҠቔᆞᄝࣉྛbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 429 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.44. PWM_GEN2_STMP_CFG_REG (0x00ac) + + (reserved) PWM_PGWEMN_2G_BE_NS2H_ADP_WWSM_HFD_UGWLEL_NF2U_LBL_UPMEPTWHOMD_GEN2_A_UPMETHOD + +31 10 9 8 7 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 Reset + + PWM_GEN2_B_SHDW_FULL Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđPWM ളӮఖ 2 ൈࡗՄ࠷թఖ B ֥႕ + ሰ࠷թఖФཿೆđཿೆ֥ᆴࡼԮൻ۳Ⴕི࠷թఖ BbౢਬൈđႵི࠷թఖ B ᇏཿೆః႕ሰ࠷թఖ + ቋྍ֥ᆴbčᆺ‫؀‬Ď + + PWM_GEN2_A_SHDW_FULL Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđPWM ളӮఖ 2 ൈࡗՄ࠷թఖ A ֥႕ + ሰ࠷թఖФཿೆđཿೆ֥ᆴࡼԮൻ۳Ⴕི࠷թఖ AbౢਬൈđႵི࠷թఖ A ᇏཿೆః႕ሰ࠷թఖ + ቋྍ֥ᆴbčᆺ‫؀‬Ď + + PWM_GEN2_B_UPMETHOD ളӮఖ 2 ൈࡗՄ࠷թఖ B Ⴕི࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴູ 0ğ + ৫ࠧ۷ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള + ๝҄൙ࡱൈ۷ྍĠbit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + + PWM_GEN2_A_UPMETHOD ളӮఖ 2 ൈࡗՄ࠷թఖ A Ⴕི࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴູ 0ğ + ৫ࠧ۷ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള + ๝҄൙ࡱൈ۷ྍĠbit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + + Register 16.45. PWM_GEN2_TSTMP_A_REG (0x00b0) + + (reserved) PWM_GEN2_A + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_GEN2_A PWM ളӮఖ 2 ൈࡗՄ A ֥႕ሰ࠷թఖbč‫؀‬ĔཿĎ + + Register 16.46. PWM_GEN2_TSTMP_B_REG (0x00b4) + + (reserved) PWM_GEN2_B + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_GEN2_B PWM ളӮఖ 2 ൈࡗՄ B ֥႕ሰ࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 430 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.47. PWM_GEN2_CFG0_REG (0x00b8) + + (reserved) PWM_GEN2_T1_PSWELM_GEN2_T0_SEPLWM_GEN2_CFG_UPMETHOD + +31 10 9 76 43 0 + +0000000000000000000000 0 0 0 Reset + + PWM_GEN2_T1_SEL ഡᇂ PWM Ҡቔఖ 2 event_t1 ྐ‫ݼ‬ჷđ৫ࠧളིb0ğfault_event0Ġ1ğ + fault_event1Ġ2ğfault_event2Ġ3ğsync_taken, 4ğ໭bč‫؀‬ĔཿĎ + + PWM_GEN2_T0_SEL ഡᇂ PWM Ҡቔఖ 2 event_t0 ྐ‫ݼ‬ჷđ৫ࠧളིb0ğfault_event0Ġ1ğ + fault_event1Ġ2ğfault_event2Ġ3ğsync_taken, 4ğ໭bč‫؀‬ĔཿĎ + + PWM_GEN2_CFG_UPMETHOD PWM ളӮఖ 2 Ⴕི஥ᇂ࠷թఖ֥۷ྍٚൔb෮Ⴕ bit ᆴູ 0ğ৫ + ࠧ۷ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള๝ + ҄ൈࡗൈ۷ྍĠbit3 ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 431 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.48. PWM_GEN2_FORCE_REG (0x00bc) + + (reserved) PWM_GEPNW2M_B_G_NEPCNWI2FM_OB_RG_CNEPECNW_I2FMM_OA_ORG_DCNEPEECNWI2FM_OA_RG_CNEECN_PI2FM_WOBORM_DCC_EGENETNU2FO_AR_CCEN_TMUOPFDOWERMC_EG_EMNO2D_CENTUFORCE_UPMETHOD + +31 16 15 14 13 12 11 10 9 87 65 0 + +0000000000000000 0 0 0 0 0 0 0x20 Reset + + PWM_GEN2_B_NCIFORCE_MODE ႨႿഡᇂ PWM2B ֥٤ӻ࿃ྟࠧൈೈࡱ఼ᇅଆൔb0ğܱоĠ1ğ + ঘ֮Ġ2ğঘۚĠ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN2_B_NCIFORCE ‫໊֥ھ‬ᆴ౼ّൈࡼԨ‫ ؿ‬PWM2B ഈ֥٤৵࿃ࠧൈೈࡱ఼ᇅ൙ࡱbč‫؀‬ + ĔཿĎ + + PWM_GEN2_A_NCIFORCE_MODE ႨႿ PWM2A ֥٤ӻ࿃ྟࠧൈೈࡱ఼ᇅ൙ࡱb0ğܱоĠ1ğঘ + ֮Ġ2ğঘۚĠ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN2_A_NCIFORCE ‫໊֥ھ‬ᆴ౼ّൈࡼԨ‫ ؿ‬PWM2A ഈ֥٤৵࿃ࠧൈೈࡱ఼ᇅ൙ࡱbč‫؀‬Ĕ + ཿĎ + + PWM_GEN2_B_CNTUFORCE_MODE ႨႿ PWM2B ֥ӻ࿃ྟࠧൈೈࡱ఼ᇅ൙ࡱb0ğܱоĠ1ğঘ + ֮Ġ2ğঘۚĠ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN2_A_CNTUFORCE_MODE ႨႿ PWM2A ֥ӻ࿃ྟࠧൈೈࡱ఼ᇅ൙ࡱb0ğܱоĠ1ğঘ + ֮Ġ2ğঘۚĠ3ğܱоbč‫؀‬ĔཿĎ + + PWM_GEN2_CNTUFORCE_UPMETHOD PWM ളӮఖ 2 ֥ӻ࿃ྟೈࡱ఼ᇅ൙ࡱ֥۷ྍٚൔb0ğ + ৫ࠧ۷ྍĠbit0 ູ 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള + TEA ൙ࡱൈ۷ྍĠbit3 ູ 1ğ‫ؿ‬ള TEB ൙ࡱൈ۷ྍĠbit4 ູ 1ğ‫ؿ‬ള๝҄൙ࡱൈ۷ྍĠbit5 ູ 1ğ + ܱо۷ྍbčᆃ৚ၛࠣၛ༯֥ TEA/B іൕ‫ק‬ൈఖ֥ᆴູ࠷թఖ A/B ֥ᆴൈളӮ֥൙ࡱbĎč‫؀‬Ĕ + ཿĎ + +ুᶈྐ༏॓࠯ 432 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.49. PWM_GEN2_A_REG (0x00c0) + + (reserved) PWM_GENP2_WAM_D_GT1ENP2_WAM_D_GT0ENP2_WAM_D_GTEEBNP2_WAM_D_GTEEANP2_WAM_D_GTEEPNP2_WAM_D_GTEEZNP2_WAM_U_GT1ENP2_WAM_U_GT0ENP2_WAM_U_GTEEBNP2_WAM_U_GTEEANP2_WAM_U_GTEEPN2_A_UTEZ + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 65 43 21 0 + +00000000 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_GEN2_A_DT1 ‫ק‬ൈఖ‫ࡨ־‬ൈđevent_t1 ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔb0ğѯྙ໭‫ڿ‬эĠ1ğঘ֮Ġ + 2ğঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_GEN2_A_DT0 ‫ק‬ൈఖ‫ࡨ־‬ൈđevent_t0 ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_A_DTEB ‫ק‬ൈఖ‫ࡨ־‬ൈđTEB ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_A_DTEA ‫ק‬ൈఖ‫ࡨ־‬ൈđTEA ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_A_DTEP ‫ק‬ൈఖ‫ࡨ־‬ൈđTEP ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_A_DTEZ ‫ק‬ൈఖ‫ࡨ־‬ൈđTEZ ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_A_UT1 ‫ק‬ൈఖ‫־‬ᄹൈđevent_t1 ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_A_UT0 ‫ק‬ൈఖ‫־‬ᄹൈđevent_t0 ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_A_UTEB ‫ק‬ൈఖ‫־‬ᄹൈđTEB ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_A_UTEA ‫ק‬ൈఖ‫־‬ᄹൈđTEA ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_A_UTEP ‫ק‬ൈఖ‫־‬ᄹൈđTEP ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_A_UTEZ ‫ק‬ൈఖ‫־‬ᄹൈđTEZ ᄝ PWM2A ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 433 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.50. PWM_GEN2_B_REG (0x00c4) + + (reserved) PWM_GENP2_WBM_D_GT1ENP2_WBM_D_GT0ENP2_WBM_D_GTEEBNP2_WBM_D_GTEEANP2_WBM_D_GTEEPNP2_WBM_D_GTEEZNP2_WBM_U_GT1ENP2_WBM_U_GT0ENP2_WBM_U_GTEEBNP2_WBM_U_GTEEANP2_WBM_U_GTEEPN2_B_UTEZ + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 65 43 21 0 + +00000000 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_GEN2_B_DT1 ‫ק‬ൈఖ‫ࡨ־‬ൈđevent_t1 ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔb0ğѯྙ໭‫ڿ‬эĠ1ğঘ + ֮Ġ2ğঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_GEN2_B_DT0 ‫ק‬ൈఖ‫ࡨ־‬ൈđevent_t0 ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_B_DTEB ‫ק‬ൈఖ‫ࡨ־‬ൈđTEB ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_B_DTEA ‫ק‬ൈఖ‫ࡨ־‬ൈđTEA ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_B_DTEP ‫ק‬ൈఖ‫ࡨ־‬ൈđTEP ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_B_DTEZ ‫ק‬ൈఖ‫ࡨ־‬ൈđTEZ ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_B_UT1 ‫ק‬ൈఖ‫־‬ᄹൈđevent_t1 ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_B_UT0 ‫ק‬ൈఖ‫־‬ᄹൈđevent_t0 ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_B_UTEB ‫ק‬ൈఖ‫־‬ᄹൈđTEB ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_B_UTEA ‫ק‬ൈఖ‫־‬ᄹൈđTEA ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_B_UTEP ‫ק‬ൈఖ‫־‬ᄹൈđTEP ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + PWM_GEN2_B_UTEZ ‫ק‬ൈఖ‫־‬ᄹൈđTEZ ᄝ PWM2B ഈԨ‫֥ؿ‬Ҡቔbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 434 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.51. PWM_DT2_CFG_REG (0x00c8) + + (reserved) PWM_PDWTM2__PCDWLTMK2___PSBDWE_TOLM2U__PADTW_BTOM2YU_P_PFATDWEBSTDMY2S__P_PORADWUESTMDTS2I___NPFODWVEUTEDM2TR__I_PNTIRNDWVESTEMD2ER__L_PTBIDNW_TSOM2EU__LADT_STOW2U_ADTPSEPBWW_AMMP_ODDTE2_RED_UPMPEWTHMO_DDT2_FED_UPMETHOD + +31 18 17 16 15 14 13 12 11 10 9 8 7 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 00 1 1 0 0 0 0 0 0 0 0 0 Reset + + PWM_DT2_CLK_SEL ഡᇂඵ౵ൈࡗളӮఖ 1 ֥ൈᇒb0ğPWM_clkĠ1ğPT_clkbč‫؀‬ĔཿĎ + PWM_DT2_B_OUTBYPASS і 16-5 ᇏ֥ S0bč‫؀‬ĔཿĎ + PWM_DT2_A_OUTBYPASS і 16-5 ᇏ֥ S1bč‫؀‬ĔཿĎ + PWM_DT2_FED_OUTINVERT і 16-5 ᇏ֥ S3bč‫؀‬ĔཿĎ + PWM_DT2_RED_OUTINVERT і 16-5 ᇏ֥ S2bč‫؀‬ĔཿĎ + PWM_DT2_FED_INSEL і 16-5 ᇏ֥ S5bč‫؀‬ĔཿĎ + PWM_DT2_RED_INSEL і 16-5 ᇏ֥ S4bč‫؀‬ĔཿĎ + PWM_DT2_B_OUTSWAP і 16-5 ᇏ֥ S7bč‫؀‬ĔཿĎ + PWM_DT2_A_OUTSWAP і 16-5 ᇏ֥ S6bč‫؀‬ĔཿĎ + PWM_DT2_DEB_MODE і 16-5 ᇏ֥ S8, B ਫ਼චခଆൔb0ğ༯ࢆခ࿼ӾĔ༯ࢆခ࿼Ӿ‫ٳ‬љᄝ҂๝ + + ֥ਫ਼ࣥᇏളིĠ1ğ༯ࢆခ࿼ӾĔ༯ࢆခ࿼Ӿᄝਫ਼ࣥ B ഈളིĠPWMxA ᆞӈൻԛbč‫؀‬ĔཿĎ + PWM_DT2_RED_UPMETHOD REDčഈശခ࿼ӾĎႵི࠷թఖ֥۷ྍٚൔb0ğ৫ࠧ۷ྍĠbit0 ູ + + 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള๝҄൙ࡱൈ۷ྍĠbit3 + ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + PWM_DT2_FED_UPMETHOD FEDč༯ࢆခ࿼ӾĎႵི࠷թఖ֥۷ྍٚൔb0ğ৫ࠧ۷ྍĠbit0 ູ + 1ğ‫ؿ‬ള TEZ ൙ࡱൈ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ࡱൈ۷ྍĠbit2 ູ 1ğ‫ؿ‬ള๝҄൙ࡱൈ۷ྍĠbit3 + ູ 1ğܱо۷ྍbč‫؀‬ĔཿĎ + + Register 16.52. PWM_DT2_FED_CFG_REG (0x00cc) + + (reserved) PWM_DT2_FED + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_DT2_FED FED ႕ሰ࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 435 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.53. PWM_DT2_RED_CFG_REG (0x00d0) + + (reserved) PWM_DT2_RED + 0 +31 16 15 0 + +0000000000000000 Reset + + PWM_DT2_RED RED ႕ሰ࠷թఖbč‫؀‬ĔཿĎ + + Register 16.54. PWM_CARRIER2_CFG_REG (0x00d4) + + (reserved) PWM_PCWAMR_RCIEARR2R_IIENPR_W2IN_MVO_EUCRTAT_RINRVIEERR2T_OPSWHMW_TCHARRIER2_DPUWTYM_CARRIEPRW2_MP_RCEASRCRAIELRE2_EN + +31 14 13 12 11 87 54 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 Reset + + PWM_CARRIER2_IN_INVERT ᇂ 1 ൈđࡼՎଆॶ֥ PWM2A ‫ ބ‬PWM2B ൻೆّཌྷbč‫؀‬ĔཿĎ + PWM_CARRIER2_OUT_INVERT ᇂ 1 ൈđࡼՎଆॶ֥ PWM2A ‫ ބ‬PWM2B ൻԛّཌྷbč‫؀‬ĔཿĎ + PWM_CARRIER2_OSHWTH ᄛѯֻ၂۱ઝԊ֥ॺ؇đֆູ໊ᄛѯᇛ௹bč‫؀‬ĔཿĎ + PWM_CARRIER2_DUTY ഡᇂᄛѯᅝॢбbᅝॢб = PWM_CARRIER2_DUTY / 8bč‫؀‬ĔཿĎ + PWM_CARRIER2_PRESCALE PWM ᄛѯ 2 ൈᇒ (PC_clk) ֥ყ‫ٳ‬௔ᆴbPC_clk ᇛ௹ = PWM_clk ᇛ + + ௹ * (PWM_CARRIER0_PRESCALE + 1)bč‫؀‬ĔཿĎ + PWM_CARRIER2_EN ᇂ 1 ൈđ൐ିᄛѯ 2 ‫ିۿ‬bౢਬൈđᄛѯ 2 Фಡ‫ݖ‬bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 436 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.55. PWM_FH2_CFG0_REG (0x00d8) + + (reserved) M_FH2_B_OMS_TF_HU2_B_OMS_TF_HD2_B_CMB_CFH_U2_B_CMB_CFH_D2_A_OMS_TF_HU2_A_OMS_TF_HD2_A_CMB_CFH_U2_AM__CFBHMC2___FDF0H_M2O__SFFT1H_M2O__SFFT2H_M2O__SSFTWHM2__O_FFS0HT_M2C__BFFC1H_M2C__BFFC2H_2C_BSCW_CBC + PW PW PW PW PW PW PW PW PW PW PW PW PW PW PW PW + +31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 6 5 4 3 2 1 0 + +00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_FH2_B_OST_U ‫ؿ‬ള‫ܣ‬ᅰ൙ࡱѩ౏‫ק‬ൈఖ‫־‬ᄹൈđPWM2B ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ1ğ + ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH2_B_OST_D ‫ؿ‬ള‫ܣ‬ᅰ൙ࡱѩ౏‫ק‬ൈఖ‫ࡨ־‬ൈđPWM2B ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ1ğ + ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH2_B_CBC_U ‫ؿ‬ള‫ܣ‬ᅰ൙ࡱѩ౏‫ק‬ൈఖ‫־‬ᄹൈđPWM2B ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ1ğ + ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH2_B_CBC_D ‫ؿ‬ള‫ܣ‬ᅰ൙ࡱѩ౏‫ק‬ൈఖ‫ࡨ־‬ൈđPWM2B ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ1ğ + ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH2_A_OST_U ‫ؿ‬ള‫ܣ‬ᅰ൙ࡱѩ౏‫ק‬ൈఖ‫־‬ᄹൈđPWM2A ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ1ğ + ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH2_A_OST_D ‫ؿ‬ള‫ܣ‬ᅰ൙ࡱѩ౏‫ק‬ൈఖ‫ࡨ־‬ൈđPWM2A ഈ֥၂ՑྟଆൔҠቔb0ğ໭Ġ1ğ + ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH2_A_CBC_U ‫ؿ‬ള‫ܣ‬ᅰ൙ࡱѩ౏‫ק‬ൈఖ‫־‬ᄹൈđPWM2A ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ1ğ + ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH2_A_CBC_D ‫ؿ‬ള‫ܣ‬ᅰ൙ࡱѩ౏‫ק‬ൈఖ‫ࡨ־‬ൈđPWM2A ഈ֥ᇯᇛ௹ଆൔҠቔb0ğ໭Ġ1ğ + ఼ᇅঘ֮Ġ2ğ఼ᇅঘۚĠ3ğ౼ّbč‫؀‬ĔཿĎ + + PWM_FH2_F0_OST ഡᇂ event_f0 Ԩ‫ؿ‬၂ՑྟଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH2_F1_OST ഡᇂ event_f1 Ԩ‫ؿ‬၂ՑྟଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH2_F2_OST ഡᇂ event_f2 Ԩ‫ؿ‬၂ՑྟଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH2_SW_OST ೈࡱ఼ᇅ၂ՑྟଆൔҠቔ֥൐ି࠷թఖb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH2_F0_CBC ഡᇂ event_f0 Ԩ‫ؿ‬ᇯᇛ௹ଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH2_F1_CBC ഡᇂ event_f1 Ԩ‫ؿ‬ᇯᇛ௹ଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH2_F2_CBC ഡᇂ event_f2 Ԩ‫ؿ‬ᇯᇛ௹ଆൔҠቔb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + + PWM_FH2_SW_CBC ೈࡱ఼ᇅᇯᇛ௹ଆൔҠቔ֥൐ି࠷թఖb0ğܱоĠ1ğ൐ିbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 437 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.56. PWM_FH2_CFG1_REG (0x00dc) + + (reserved) PWM_PFWHM2__FFOHPR2W_CFMEO__ROFHCSP2ETW__CMCBB_FCCHP2U_LCSLER_OST + +31 54 32 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_FH2_FORCE_OST ๙‫ݖ‬ೈࡱ౼ّՎ໊֥ᆴԨ‫ؿ‬၂ՑྟଆൔҠቔbč‫؀‬ĔཿĎ + PWM_FH2_FORCE_CBC ๙‫ݖ‬ೈࡱ౼ّՎ໊֥ᆴԨ‫ؿ‬ᇯᇛ௹ଆൔҠቔbč‫؀‬ĔཿĎ + PWM_FH2_CBCPULSE ഡᇂᇯᇛ௹ଆൔ֥۷ྍٚൔbbit0 ູ 1ğ৫ࠧ۷ྍĠbit1 ູ 1ğ‫ؿ‬ള TEP ൙ + + ࡱൈ۷ྍbč‫؀‬ĔཿĎ + PWM_FH2_CLR_OST ౼ّՎ໊֥ᆴౢԢᆞᄝࣉྛ֥၂Ցྟଆൔ֥Ҡቔbč‫؀‬ĔཿĎ + + Register 16.57. PWM_FH2_STATUS_REG (0x00e0) + + (reserved) PWM_PFWHM2__OFHST2__OCBNC_ON + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_FH2_OST_ON Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđ၂ՑྟଆൔҠቔᆞᄝࣉྛbčᆺ‫؀‬Ď + PWM_FH2_CBC_ON Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđᇯᇛ௹ଆൔҠቔᆞᄝࣉྛbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 438 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.58. PWM_FAULT_DETECT_REG (0x00e4) + + (reserved) PWM_PEWVMEN_PETWV_MFE2N_PETWV_MFE1N_PFTW2__MFP0_POFWL1E_MP_POFWL0E_MP_POFWL2E_ME_PNFW1_ME_NF0_EN + +31 98 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_EVENT_F2 Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđevent_f2 ൙ࡱӻ࿃bčᆺ‫؀‬Ď + PWM_EVENT_F1 Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđevent_f1 ൙ࡱӻ࿃bčᆺ‫؀‬Ď + PWM_EVENT_F0 Ⴎ႗ࡱᇂ 1 ‫ބ‬ౢਬbᇂ 1 ൈđevent_f0 ൙ࡱӻ࿃bčᆺ‫؀‬Ď + PWM_F2_POLE ഡᇂটሱ GPIO इᆔ֥ FAULT2 ྐ‫ݼ‬ჷԨ‫ ؿ‬event_f2 ൈࠞྟb0ğ֮‫׈‬௜Ԩ‫ؿ‬Ġ1ğ + + ۚ‫׈‬௜Ԩ‫ؿ‬bč‫؀‬ĔཿĎ + PWM_F1_POLE ഡᇂটሱ GPIO इᆔ֥ FAULT2 ྐ‫ݼ‬ჷԨ‫ ؿ‬event_f1 ൈࠞྟb0ğ֮‫׈‬௜Ԩ‫ؿ‬Ġ1ğ + + ۚ‫׈‬௜Ԩ‫ؿ‬bč‫؀‬ĔཿĎ + PWM_F0_POLE ഡᇂটሱ GPIO इᆔ֥ FAULT2 ྐ‫ݼ‬ჷԨ‫ ؿ‬event_f0 ൈࠞྟb0ğ֮‫׈‬௜Ԩ‫ؿ‬Ġ1ğ + + ۚ‫׈‬௜Ԩ‫ؿ‬bč‫؀‬ĔཿĎ + PWM_F2_EN ᇂ 1 ൐ି event_f2 ֥ളӮbč‫؀‬ĔཿĎ + PWM_F1_EN ᇂ 1 ൐ି event_f1 ֥ളӮbč‫؀‬ĔཿĎ + PWM_F0_EN ᇂ 1 ൐ି event_f0 ֥ളӮbč‫؀‬ĔཿĎ + + Register 16.59. PWM_CAP_TIMER_CFG_REG (0x00e8) + + (reserved) PWM_CAP_PSWYMN_CC_ASPW_PSWYMN_CPCWI_ASMPE__LCSYANP_CTI_IMENER_EN + +31 654 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 Reset + + PWM_CAP_SYNC_SW ᇂ 1 ൈđ఼ᇅ๝҄ѽࠆ‫ק‬ൈఖđѽࠆ‫ק‬ൈఖᇏཿೆཌྷ໊࠷թఖ֥ᆴbčᆺཿĎ + + PWM_CAP_SYNCI_SEL ࿊ᄴѽࠆଆॶ֥๝҄ൻೆb0ğ໭Ġ1ğ‫ק‬ൈఖ 0 ֥๝҄ൻԛĠ2ğ‫ק‬ൈఖ + 1 ֥๝҄ൻԛĠ3ğ‫ק‬ൈఖ 2 ֥๝҄ൻԛĠ4ğটሱ GPIO इᆔ֥ SYNC0 Ġ5ğটሱ GPIO इᆔ֥ + SYNC1Ġ6ğটሱ GPIO इᆔ֥ SYNC2bč‫؀‬ĔཿĎ + + PWM_CAP_SYNCI_EN ᇂ 1 ൈđ൐ିѽࠆ‫ק‬ൈఖ๝҄bč‫؀‬ĔཿĎ + + PWM_CAP_TIMER_EN ᇂ 1 ൈđ൐ିѽࠆ‫ק‬ൈఖᄝ APB_clk ༯֥‫־‬ᄹbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 439 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) 0 + + Register 16.60. PWM_CAP_TIMER_PHASE_REG (0x00ec) Reset + + 31 + + 0 + + PWM_CAP_TIMER_PHASE_REG ѽࠆ‫ק‬ൈఖ๝҄Ҡቔ֥ཌྷ໊ᆴbč‫؀‬ĔཿĎ + + Register 16.61. PWM_CAP_CH0_CFG_REG (0x00f0) + + (reserved) PWM_PCWAMP_0C_SAWP0_IN_INVERT PWM_CAP0_PRESCALE PWM_CAPPW0M_M_COADPE0_EN + +31 13 12 11 10 32 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 Reset + + PWM_CAP0_SW ᇂ 1 Ԩ‫ ֡ྐؿ‬0 ഈ֥ೈࡱ఼ᇅѽࠆbčᆺཿĎ + PWM_CAP0_IN_INVERT ᇂ 1 ൈđটሱ GPIO इᆔ֥ CAP0 ᄝყ‫ٳ‬௔ᆭభّཌྷbč‫؀‬ĔཿĎ + PWM_CAP0_PRESCALE CAP0 ഈശခ֥ყ‫ٳ‬௔ᆴbყ‫ٳ‬௔ᆴ = PWM_CAP0_PRESCALE + 1bč‫؀‬ + + ĔཿĎ + + PWM_CAP0_MODE ყ‫ٳ‬௔ުྐ֡ 0 ഈ֥ѽࠆшჸbbit0 ູ 1ğ൐ି༯ࢆခѽࠆĠbit1 ູ 1ğ൐ି + ഈശခѽࠆbč‫؀‬ĔཿĎ + + PWM_CAP0_EN ᇂ 1 ൈđ൐ିྐ֡ 0 ഈ֥ѽࠆbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 440 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.62. PWM_CAP_CH1_CFG_REG (0x00f4) + + (reserved) PWM_PCWAMP_1C_SAWP1_IN_INVERT PWM_CAP1_PRESCALE PWM_CAPPW1M_M_COADPE1_EN + +31 13 12 11 10 32 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 Reset + + PWM_CAP1_SW ᇂ 1 ൈđԨ‫ ֡ྐؿ‬1 ഈ֥ೈࡱ఼ᇅѽࠆ൙ࡱbčᆺཿĎ + PWM_CAP1_IN_INVERT ᇂ 1 ൈđটሱႿ GPIO इᆔ֥ CAP1 ᄝყ‫ٳ‬௔భФّཌྷbč‫؀‬ĔཿĎ + PWM_CAP1_PRESCALE CAP1 ഈശခ֥ყ‫ٳ‬௔ᆴbყ‫ٳ‬௔ᆴ = PWM_CAP1_PRESCALE + 1bč‫؀‬ + + ĔཿĎ + + PWM_CAP1_MODE ყ‫ٳ‬௔ުྐ֡ 1 ഈ֥ѽࠆခbbit0 ູ 1ğ൐ି༯ࢆခѽࠆ, bit1 ູ 1ğ൐ିഈശ + ခѽࠆbč‫؀‬ĔཿĎ + + PWM_CAP1_EN ᇂ 1 ൈđ൐ିྐ֡ 1 ഈ֥ѽࠆ൙ࡱbč‫؀‬ĔཿĎ + + Register 16.63. PWM_CAP_CH2_CFG_REG (0x00f8) + + (reserved) PWM_PCWAMP_2C_SAWP2_IN_INVERT PWM_CAP2_PRESCALE PWM_CAPPW2M_M_COADPE2_EN + +31 13 12 11 10 32 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 Reset + + PWM_CAP2_SW ᇂ 1 Ԩ‫ ֡ྐؿ‬2 ഈ֥ೈࡱ఼ᇅѽࠆ൙ࡱbčᆺཿĎ + PWM_CAP2_IN_INVERT ᇂ 1 ൈđটሱ GPIO इᆔ֥ CAP2 ᄝყ‫ٳ‬௔భФّཌྷbč‫؀‬ĔཿĎ + PWM_CAP2_PRESCALE CAP2 ഈശခ֥ყ‫ٳ‬௔ᆴb‫ھ‬ყ‫ٳ‬௔ᆴ = PWM_CAP2_PRESCALE + + + 1bč‫؀‬ĔཿĎ + + PWM_CAP2_MODE ყ‫ٳ‬௔ުྐ֡ 2 ഈ֥ѽࠆခbbit0ğ൐ି༯ࢆခѽࠆĠbit1 ູ 1ğ൐ିഈശခ + ѽࠆbč‫؀‬ĔཿĎ + + PWM_CAP2_EN ᇂ 1 ൈđ൐ିྐ֡ 2 ഈ֥ѽࠆbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 441 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) 0 + + Register 16.64. PWM_CAP_CH0_REG (0x00fc) Reset + + 31 + + 0 + + PWM_CAP_CH0_REG ྐ֡ 0 ഈ၂Ցѽࠆ֥ᆴbčᆺ‫؀‬Ď + + Register 16.65. PWM_CAP_CH1_REG (0x0100) 0 + +31 Reset + + 0 + + PWM_CAP_CH1_REG ྐ֡ 1 ഈ၂Ցѽࠆ֥ᆴbčᆺ‫؀‬Ď + + Register 16.66. PWM_CAP_CH2_REG (0x0104) 0 + +31 Reset + + 0 + + PWM_CAP_CH2_REG ྐ֡ 2 ഈ၂Ցѽࠆ֥ᆴbčᆺ‫؀‬Ď + + Register 16.67. PWM_CAP_STATUS_REG (0x0108) + + (reserved) PWM_PCWAMP_2PC_WEAMDPG_1C_EEADPG0_EEDGE + +31 32 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PWM_CAP2_EDGE ྐ֡ 2 ഈ၂ՑѽࠆԨ‫ؿ‬൙ࡱ֥шခb0ğഈശခĠ1ğ༯ࢆခbčᆺ‫؀‬Ď + PWM_CAP1_EDGE ྐ֡ 1 ഈ၂ՑѽࠆԨ‫ؿ‬൙ࡱ֥шခb0ğഈശခĠ1ğ༯ࢆခbčᆺ‫؀‬Ď + PWM_CAP0_EDGE ྐ֡ 0 ഈ၂ՑѽࠆԨ‫ؿ‬൙ࡱ֥шခb0ğഈശခĠ1ğ༯ࢆခbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 442 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.68. PWM_UPDATE_CFG_REG (0x010c) + + (reserved) M_OPM2__FOOPMR2__CUOEPP_MU_1E__PNFOOPMR1__CUOEPP_MU_0E__PNFOOPMR0__CUGEPL_MOU_E_PBNGALLO_FBOARL_CUEP_U_EPN + PW PW PW PW PW PW PW PW + +31 87 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 Reset + + PWM_OP2_FORCE_UP ๙‫ݖ‬ೈࡱ౼ّՎ໊֥ᆴࡼԨ‫ ؿ‬PWM Ҡቔఖ 2 Ⴕི࠷թఖ఼ᇅ۷ྍbč‫؀‬ + ĔཿĎ + + PWM_OP2_UP_EN Վ໊ၛࠣ PWM_GLOBAL_UP_EN ᇂ 1 ൈ, ൐ି PWM Ҡቔఖ 2 Ⴕི࠷թఖ֥ + ۷ྍbč‫؀‬ĔཿĎ + + PWM_OP1_FORCE_UP ๙‫ݖ‬ೈࡱ౼ّՎ໊֥ᆴࡼԨ‫ ؿ‬PWM Ҡቔఖ 1 Ⴕི࠷թఖ఼ᇅ۷ྍbč‫؀‬ + ĔཿĎ + + PWM_OP1_UP_EN Վ໊ၛࠣ PWM_GLOBAL_UP_EN ᇂ 1 ൈ, ൐ି PWM Ҡቔఖ 1 Ⴕི࠷թఖ֥ + ۷ྍbč‫؀‬ĔཿĎ + + PWM_OP0_FORCE_UP ๙‫ݖ‬ೈࡱ౼ّՎ໊֥ᆴࡼԨ‫ ؿ‬PWM Ҡቔఖ 0 Ⴕི࠷թఖ఼ᇅ۷ྍbč‫؀‬ + ĔཿĎ + + PWM_OP0_UP_EN Վ໊ၛࠣ PWM_GLOBAL_UP_EN ᇂ 1 ൈ, ൐ି PWM Ҡቔఖ 0 Ⴕི࠷թఖ֥ + ۷ྍbč‫؀‬ĔཿĎ + + PWM_GLOBAL_FORCE_UP ๙‫ݖ‬ೈࡱ౼ّՎ໊֥ᆴࡼԨ‫ ؿ‬MCPWM ଆॶ෮ႵႵི࠷թఖ఼֥ᇅ + ۷ྍbč‫؀‬ĔཿĎ + + PWM_GLOBAL_UP_EN MCPWM ଆॶ෮ႵႵི࠷թఖ֥۷ྍ൐ି໊bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 443 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.69. INT_ENA_PWM_REG (0x0110) + + (reservedIN) T_CINAPT_2C_IINANPTT_1_C_EIINANNPTAT_0_F_EIHINNN2TAT___OFEIHSNNT1TA___IOFNIHSNTT0_T__E_IOFNNIHSNATT2_T__E_ICFNNIHBNATC1_T_E__CFNINIHBNATC0T____ECOINNIBNPATC2T____ETOINNIENPATB1T____EITONNIENPTAB_0T_E__ITONNIENAPTB_2T_E__ITONNIENAPTA_1T_E__ITONNIENAPTA_0T_E__INTFNIAENATUA_T_LE_TINFN2IANAT_U_TCLE_LTNFR1IANA__UTICNL_LTTFR0I_AN__EUTICNNL_LTATFR2I_AN__EUTIINNNL_TATTF1I__AN_EEUTINNNL_TAATT0I_INM_ETINEN_RATT2I_INME_TTNE_ERATP1IINM__ITTNE_ERTTP_0IINM_E_ITNTNE_EARTTP_2IINM_E_ITNTNE_EARTTZ_1IINM_E_ITNTNE_EARTTZ_0IINM_E_ITNTNE_EARTTZ_2IINM_E_ITNSNE_TARTTO_1IMEP_NSE_ITARNO0TP__S_EITNNOATP__EINNAT_ENA + +31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +INT_CAP2_INT_ENA ‫໊ھ‬ႨႿ൐ିႮྐ֡ 2 ഈ֥ѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_CAP1_INT_ENA ‫໊ھ‬ႨႿ൐ିႮྐ֡ 1 ഈ֥ѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_CAP0_INT_ENA ‫໊ھ‬ႨႿ൐ିႮྐ֡ 0 ഈ֥ѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FH2_OST_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM2 ഈ֥၂ՑྟଆൔҠቔԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FH1_OST_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM1 ഈ֥၂ՑྟଆൔҠቔԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FH0_OST_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM0 ഈ֥၂ՑྟଆൔҠቔԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FH2_CBC_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM2 ഈ֥ᇯᇛ௹ଆൔҠቔԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FH1_CBC_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM1 ഈ֥ᇯᇛ௹ଆൔҠቔԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FH0_CBC_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM0 ഈ֥ᇯᇛ௹ଆൔҠቔԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_OP2_TEB_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM Ҡቔఖ 2 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_OP1_TEB_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM Ҡቔఖ 2 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_OP0_TEB_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM Ҡቔఖ 0 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_OP2_TEA_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM Ҡቔఖ 2 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_OP1_TEA_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM Ҡቔఖ 1 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_OP0_TEA_INT_ENA ‫໊ھ‬ႨႿ൐ିႮ PWM Ҡቔఖ 0 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FAULT2_CLR_INT_ENA ‫໊ھ‬ႨႿ൐ି event_f2 ࢲඏުԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FAULT1_CLR_INT_ENA ‫໊ھ‬ႨႿ൐ି event_f1 ࢲඏުԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FAULT0_CLR_INT_ENA ‫໊ھ‬ႨႿ൐ି event_f0 ࢲඏުԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FAULT2_INT_ENA ‫໊ھ‬ႨႿ൐ି event_f2 ष൓ൈԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FAULT1_INT_ENA ‫໊ھ‬ႨႿ൐ି event_f1 ष൓ൈԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_FAULT0_INT_ENA ‫໊ھ‬ႨႿ൐ି event_f0 ष൓ൈԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_TIMER2_TEP_INT_ENA ‫໊ھ‬ႨႿ൐ି PWM ‫ק‬ൈఖ 2 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_TIMER1_TEP_INT_ENA ‫໊ھ‬ႨႿ൐ି PWM ‫ק‬ൈఖ 1 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_TIMER0_TEP_INT_ENA ‫໊ھ‬ႨႿ൐ି PWM ‫ק‬ൈఖ 0 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_TIMER2_TEZ_INT_ENA ‫໊ھ‬ႨႿ൐ି PWM ‫ק‬ൈఖ 2 TEZ ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_TIMER1_TEZ_INT_ENA ‫໊ھ‬ႨႿ൐ି PWM ‫ק‬ൈఖ 1 TEZ ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_TIMER0_TEZ_INT_ENA ‫໊ھ‬ႨႿ൐ି PWM ‫ק‬ൈఖ 0 TEZ ൙ࡱԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_TIMER2_STOP_INT_ENA ‫໊ھ‬ႨႿ൐ି‫ק‬ൈఖ 2 ๔ᆸൈԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_TIMER1_STOP_INT_ENA ‫໊ھ‬ႨႿ൐ି‫ק‬ൈఖ 1 ๔ᆸൈԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ +INT_TIMER0_STOP_INT_ENA ‫໊ھ‬ႨႿ൐ି‫ק‬ൈఖ 0 ๔ᆸൈԨ‫֥ؿ‬ᇏ؎bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 444 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.70. INT_RAW_PWM_REG (0x0114) + + (reservedIN) T_CINAPT_2C_IINANPTT_1_C_RIINAANPTWT_0_F_RIHINAN2TWT___OFRIHSNAT1TW___IOFNIHSNTT0_T__R_IOFANIHSNWTT2_T__R_ICFANIHBNWTC1_T_R__CFIANIHBNWTC0T____RCOIANIBNPWTC2T____RTOIANIENPWTB1T____RITONAIENPTWB_0T_R__ITOANIENWPTB_2T_R__ITOANIENWPTA_1T_R__ITONAIENWPTA_0T_R__ITFANIAENWTUA_T_LR_TIFAN2IANWT_U_TCLR_LTFAR1IANW__UTICNL_LTTFR0I_AN__RUTICANL_LTWTFR2I_AN__RUTIIANNL_TWTTF1I__AN_RRUTIAANL_TWWTT0I_INM_RTIEAN_RWTT2I_INMR_TTEA_ERWTP1IINM__ITTNE_ERTTP_0IINM_R_ITTANE_EWRTTP_2IINM_R_ITTANE_EWRTTZ_1IINM_R_ITTNAE_EWRTTZ_0IINM_R_ITTANE_EWRTTZ_2IINM_R_ITSANE_TWRTTO_1IMRP_SAE_ITWRNO0TP__S_RITANOWTP__RIANWT_RAW + +31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + INT_CAP2_INT_RAW Ⴎྐ֡ 2 ഈѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_CAP1_INT_RAW Ⴎྐ֡ 1 ഈѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_CAP0_INT_RAW Ⴎྐ֡ 0 ഈѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FH2_OST_INT_RAW Ⴎ PWM2 ၂ՑྟҠቔԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FH1_OST_INT_RAW Ⴎ PWM1 ၂ՑྟҠቔԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FH0_OST_INT_RAW Ⴎ PWM0 ၂ՑྟҠቔԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FH2_CBC_INT_RAW Ⴎ PWM2 ᇯᇛ௹ҠቔԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FH1_CBC_INT_RAW Ⴎ PWM1 ᇯᇛ௹ҠቔԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FH0_CBC_INT_RAW Ⴎ PWM0 ᇯᇛ௹ҠቔԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_OP2_TEB_INT_RAW Ⴎ PWM Ҡቔఖ 2 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_OP1_TEB_INT_RAW Ⴎ PWM Ҡቔఖ 1 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_OP0_TEB_INT_RAW Ⴎ PWM Ҡቔఖ 0 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_OP2_TEA_INT_RAW Ⴎ PWM Ҡቔఖ 2 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_OP1_TEA_INT_RAW Ⴎ PWM Ҡቔఖ 1 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_OP0_TEA_INT_RAW Ⴎ PWM Ҡቔఖ 0 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT2_CLR_INT_RAW event_f2 ࢲඏൈԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT1_CLR_INT_RAW event_f1 ࢲඏൈԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT0_CLR_INT_RAW event_f0 ࢲඏൈԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT2_INT_RAW event_f2 ष൓ުԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT1_INT_RAW event_f1 ष൓ުԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT0_INT_RAW event_f0 ष൓ުԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER2_TEP_INT_RAW PWM ‫ק‬ൈఖ 2 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER1_TEP_INT_RAW PWM ‫ק‬ൈఖ 1 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER0_TEP_INT_RAW PWM ‫ק‬ൈఖ 0 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER2_TEZ_INT_RAW PWM ‫ק‬ൈఖ 2 TEZ ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER1_TEZ_INT_RAW PWM ‫ק‬ൈఖ 1 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER0_TEZ_INT_RAW PWM ‫ק‬ൈఖ 0 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER2_STOP_INT_RAW ‫ק‬ൈఖ 2 ๔ᆸުԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER1_STOP_INT_RAW ‫ק‬ൈఖ 1 ๔ᆸުԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER0_STOP_INT_RAW ‫ק‬ൈఖ 0 ๔ᆸުԨ‫֥ؿ‬ᇏ؎֥ჰ൓ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 445 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.71. INT_ST_PWM_REG (0x0118) + + (reservedIN) T_CINAPT_2C_IINANPTT_1_C_SIINATNPTT_0_F_SIHINTN2TT___OFSIHSNTT1T___IOFNIHSNTT0_T__S_IOFTNIHSNTT2_T__S_ICFTNIHBNTC1_T_S__CFITNIHBNTC0T____SCOITNIBNPTC2T____STOITNIENPTB1T____SITONTIENPTB_0T_S__ITOTNIENPTB_2T_S__ITOTNIENPTA_1T_S__ITOTNIENPTA_0T_S__ITFTNIAENTUA_T_LS_TIFTN2IANT_U_TCLS_LTFTR1IAN__UTICNL_LTTFR0I_AN__SUTICTNL_LTTFR2I_AN__SUTIITNNL_TTTF1I__AN_SSUTITTNL_TTT0I_INM_STITEN_RTT2I_INMS_TTTE_ERTP1IINM__ITTNE_ERTTP_0IINM_S_ITTTNE_ERTTP_2IINM_S_ITTTNE_ERTTZ_1IINM_S_ITTNTE_ERTTZ_0IINM_S_ITTTNE_ERTTZ_2IINM_S_ITTSNE_TRTTO_1IMSP_TSE_ITRNO0TP__S_SITTNOTP__SITNT_ST + + 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + INT_CAP2_INT_ST ྐ֡ 2 ഈѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_CAP1_INT_ST ྐ֡ 1 ഈѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_CAP0_INT_ST ྐ֡ 0 ഈѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FH2_OST_INT_ST PWM2 ၂ՑྟҠቔԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FH1_OST_INT_ST PWM1 ၂ՑྟҠቔԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FH0_OST_INT_ST PWM0 ၂ՑྟҠቔԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FH2_CBC_INT_ST PWM2 ᇯᇛ௹ҠቔԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FH1_CBC_INT_ST PWM1 ᇯᇛ௹ҠቔԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FH0_CBC_INT_ST PWM0 ᇯᇛ௹ҠቔԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_OP2_TEB_INT_ST PWM Ҡቔఖ 2 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_OP1_TEB_INT_ST PWM Ҡቔఖ 1 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_OP0_TEB_INT_ST PWM Ҡቔఖ 0 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_OP2_TEA_INT_ST PWM Ҡቔఖ 2 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_OP1_TEA_INT_ST PWM Ҡቔఖ 1 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_OP0_TEA_INT_ST PWM Ҡቔఖ 0 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT2_CLR_INT_ST event_f2 ࢲඏൈԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT1_CLR_INT_ST event_f1 ࢲඏൈԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT0_CLR_INT_ST event_f0 ࢲඏൈԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT2_INT_ST event_f2 ष൓ൈԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT1_INT_ST event_f1 ष൓ൈԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_FAULT0_INT_ST event_f0 ष൓ൈԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER2_TEP_INT_ST PWM ‫ק‬ൈఖ 2 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER1_TEP_INT_ST PWM ‫ק‬ൈఖ 1 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER0_TEP_INT_ST PWM ‫ק‬ൈఖ 0 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER2_TEZ_INT_ST PWM ‫ק‬ൈఖ 2 TEZ ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER1_TEZ_INT_ST PWM ‫ק‬ൈఖ 1 TEZ ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER0_TEZ_INT_ST PWM ‫ק‬ൈఖ 0 TEZ ൙ࡱԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER2_STOP_INT_ST ‫ק‬ൈఖ 2 ๔ᆸުԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER1_STOP_INT_ST ‫ק‬ൈఖ 1 ๔ᆸުԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + INT_TIMER0_STOP_INT_ST ‫ק‬ൈఖ 0 ๔ᆸުԨ‫֥ؿ‬ᇏ؎֥௠зሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 446 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 16 ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) + + Register 16.72. INT_CLR_PWM_REG (0x011c) + + (reservedIN) T_CINAPT_2C_IINANPTT_1_C_CIINANLPTRT_0_F_CIHINNL2TRT___OFCIHSNLT1TR___IOFNIHSNTT0_T__C_IOFNLIHSRNTT2_T__C_ICFNLIHBRNTC1_T_C__CFILNIHBRNTC0T____CCOINLIBNPRTC2T____CTOINLIENPRTB1T____CITONLIENPRTB_0T_C__ITONLIENRPTB_2T_C__ITONLIENRPTA_1T_C__ITONLIENRPTA_0T_C__ITFNLIAERNTUA_T_LC_TIFNL2IARNT_U_TCLC_LTFLR1IARN__UTICNL_LTTFR0I_AN__CUTICNLL_LRTTFR2I_AN__CUTIINNLL_RTTTF1I__AN_CCUTINLLL_RRTTT0I_INM_CTIENL_RRTT2I_INMC_TTEL_ERRTP1IINM__ITTNE_ERTTP_0IINM_C_ITTNLE_ERRTTP_2IINM_C_ITTNLE_ERRTTZ_1IINM_C_ITTNLE_ERRTTZ_0IINM_C_ITTNLE_ERRTTZ_2IINM_C_ITSNLE_RTRTTO_1IMCP_SLE_RITRNO0TP__S_CITNLORTP__CINLRT_CLR + + 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + INT_CAP2_INT_CLR ᇂ 1 ൈౢԢྐ֡ 2 ഈѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_CAP1_INT_CLR ᇂ 1 ൈౢԢྐ֡ 1 ഈѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_CAP0_INT_CLR ᇂ 1 ൈౢԢྐ֡ 0 ഈѽࠆ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FH2_OST_INT_CLR ᇂ 1 ൈౢԢ PWM2 ၂ՑྟҠቔԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FH1_OST_INT_CLR ᇂ 1 ൈౢԢ PWM1 ၂ՑྟҠቔԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FH0_OST_INT_CLR ᇂ 1 ൈౢԢ PWM0 ၂ՑྟҠቔԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FH2_CBC_INT_CLR ᇂ 1 ൈౢԢ PWM2 ᇯᇛ௹ҠቔԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FH1_CBC_INT_CLR ᇂ 1 ൈౢԢ PWM1 ᇯᇛ௹ҠቔԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FH0_CBC_INT_CLR ᇂ 1 ൈౢԢ PWM0 ᇯᇛ௹ҠቔԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_OP2_TEB_INT_CLR ᇂ 1 ൈౢԢ PWM Ҡቔఖ 2 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_OP1_TEB_INT_CLR ᇂ 1 ൈౢԢ PWM Ҡቔఖ 1 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_OP0_TEB_INT_CLR ᇂ 1 ൈౢԢ PWM Ҡቔఖ 0 TEB ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_OP2_TEA_INT_CLR ᇂ 1 ൈౢԢ PWM Ҡቔఖ 2 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_OP1_TEA_INT_CLR ᇂ 1 ൈౢԢ PWM Ҡቔఖ 1 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_OP0_TEA_INT_CLR ᇂ 1 ൈౢԢ PWM Ҡቔఖ 0 TEA ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FAULT2_CLR_INT_CLR ᇂ 1 ൈౢԢ event_f2 ࢲඏൈԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FAULT1_CLR_INT_CLR ᇂ 1 ൈౢԢ event_f1 ࢲඏൈԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FAULT0_CLR_INT_CLR ᇂ 1 ൈౢԢ event_f0 ࢲඏൈԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FAULT2_INT_CLR ᇂ 1 ൈౢԢ event_f2 ष൓ൈԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FAULT1_INT_CLR ᇂ 1 ൈౢԢ event_f1 ष൓ൈԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_FAULT0_INT_CLR ᇂ 1 ൈౢԢ event_f0 ष൓ൈԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_TIMER2_TEP_INT_CLR ᇂ 1 ൈౢԢ PWM ‫ק‬ൈఖ 2 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_TIMER1_TEP_INT_CLR ᇂ 1 ൈౢԢ PWM ‫ק‬ൈఖ 1 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_TIMER0_TEP_INT_CLR ᇂ 1 ൈౢԢ PWM ‫ק‬ൈఖ 0 TEP ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_TIMER2_TEZ_INT_CLR ᇂ 1 ൈౢԢ PWM ‫ק‬ൈఖ 2 TEZ ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_TIMER1_TEZ_INT_CLR ᇂ 1 ൈౢԢ PWM ‫ק‬ൈఖ 1 TEZ ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_TIMER0_TEZ_INT_CLR ᇂ 1 ൈౢԢ PWM ‫ק‬ൈఖ 0 TEZ ൙ࡱԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_TIMER2_STOP_INT_CLR ᇂ 1 ൈౢԢ‫ק‬ൈఖ 2 ๔ᆸުԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_TIMER1_STOP_INT_CLR ᇂ 1 ൈౢԢ‫ק‬ൈఖ 1 ๔ᆸުԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + INT_TIMER0_STOP_INT_CLR ᇂ 1 ൈౢԢ‫ק‬ൈఖ 0 ๔ᆸުԨ‫֥ؿ‬ᇏ؎bčᆺཿĎ + +ুᶈྐ༏॓࠯ 447 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 17 ઝԊ࠹ඔఖ (PCNT) + +17 ઝԊ࠹ඔఖ (PCNT) + +17.1 ‫ۀ‬ඍ + +ઝԊ࠹ඔఖଆॶႨႿؓൻೆઝԊ֥ഈശခࠇ༯ࢆခࣉྛ࠹ඔbૄ۱ઝԊ࠹ඔఖֆჭनႵ၂۱ջ‫ ֥ݼژ‬16-bit ࠹ +ඔ࠷թఖၛࠣਆ۱๙֡đ๙‫ݖ‬஥ᇂॖၛࡆࡨ࠹ඔఖbૄ۱๙֡नႵ၂۱ઝԊൻೆྐ‫ݼ‬ၛࠣ၂۱ି‫ܔ‬ႨႿ॥ᇅൻ +ೆྐ‫֥ݼ‬॥ᇅྐ‫ݼ‬bൻೆྐ‫ݼ‬ॖၛյषࠇܱоੲѯ‫ିۿ‬b +ઝԊ࠹ඔఖႵ 8 ቆֆჭđ۲ሱ‫׿‬৫‫۽‬ቔđଁ଀ູ PULSE_CNT_Unb +ESP32 ઝԊ࠹ඔఖᆦӻ֥ቋնઝԊ௔ੱູ 40 MHzb + +17.2 ‫ିۿ‬૭ඍ + +17.2.1 ࡏ‫ܒ‬๭ + + ๭ 17­1. PULSE_CNT ֆჭࠎЧࡏ‫ܒ‬๭ + +๭ 17-1 ູઝԊ࠹ඔఖ֥ࠎЧࡏ‫ܒ‬๭bૄ۱ֆჭႵਆ۱๙֡ğch0 ‫ ބ‬ch1bᆃਆ۱๙֥֡‫ିۿ‬ཌྷරbૄ۱๙֡न +Ⴕ၂۱ൻೆྐ‫ބݼ‬၂۱॥ᇅൻೆྐ‫ݼ‬đ‫ି׻‬৵ࢤ֞ྉோႄ࢖bഈശခ‫ބ‬༯ࢆခᇏ֥࠹ඔ‫۽‬ቔଆൔॖၛ‫ٳ‬љࣉྛ +ᄹࡆa҂ᄹ҂ࡨࠇᆀࡨഒ࠹ඔᆴ֥஥ᇂྛູbؓ॥ᇅྐ‫طݼ‬࿽đ๙‫ݖ‬஥ᇂ႗ࡱॖၛ۷‫ڿ‬ഈശခ‫ބ‬༯ࢆခ֥‫۽‬ቔ +ଆൔđЇওğّሇa࣌ᆸ‫ބ‬Ќӻb‫࠹ھ‬ඔఖЧദ൞၂۱ջ‫ ֥ݼژ‬16-bit ࡆࡨ࠹ඔఖb෱֥ᆴॖၛႮೈࡱᆰࢤ‫؀‬ +౼đ႗ࡱ๙‫ھࡼݖ‬ᆴა၂ቆбࢠఖࣉྛбࢠđॖၛӁളᇏ؎b + +ুᶈྐ༏॓࠯ 448 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 17 ઝԊ࠹ඔఖ (PCNT) + +17.2.2 ࠹ඔఖ๙֡ൻೆྐ‫ݼ‬ + +ೂഈ໓෮ඍđ၂۱๙֡৚֥ਆቆൻೆྐ‫ܔିݼ‬ၛ‫؟‬ᇕٚൔ႕ཙઝԊ࠹ඔఖğLCTRL_MODE ‫ ބ‬HCTRL_MODE +‫ٳ‬љႨႿ஥ᇂ֮॥ᇅྐ‫ۚބݼ‬॥ᇅྐ‫ݼ‬ĠPOS_MODE ‫ ބ‬NEG_MODE ‫ٳ‬љႨႿ஥ᇂൻೆྐ‫֥ݼ‬ഈശခ‫ބ‬༯ࢆ +ခbPOS_MODE ‫ ބ‬NEG_MODE ஥ᇂູ 1đ࠹ඔఖ‫־‬ᄹĠ೏ࡼ෱ૌ஥ᇂູ 2 ൈđᄵ࠹ඔఖ‫ࡨ־‬Ġః෱֥ᆴіൕ +࠹ඔఖЌӻჰ൓ᆴđ࠻҂‫־‬ᄹđ္҂‫ࡨ־‬b֒ LCTRL_MODE ࠇ HCTRL_MODE ູ 0đіൕ҂ྩ‫ ڿ‬NEG_MODE +‫ ބ‬POS_MODE ֥‫۽‬ቔଆൔĠູ 1 іൕّሇčࠧ೏ჰট࠹ඔఖԩႿ‫־‬ᄹሑ෿đ֒஥ᇂ POS_MODE ࠇ +NEG_MODE ູ 1 ުđ࠹ඔఖࡼԩႿ‫ࡨ־‬ሑ෿đّᆭၧಖĎĠః෱֥ᆴ߶࣌ᆸ࠹ඔఖ࠹ඔቔႨb + +༯іਙԛਔ၂ུܱႿഈശခؓ࠹ඔఖቔႨ֥২ሰđЇও֮/ۚ‫׈‬௜॥ᇅྐ‫ݼ‬ၛࠣ۲ᇕ஥ᇂ࿊ᄴbູਔౢ༉ॖ࡮đ +༯іඔᆴު૫֥ও‫ݼ‬ଽเࡆਔ၂ུ૭ඍđx սіਔo໭ܱཛpb + +POS_ MODE LCTRL_ MODE HCTRL_ MODE sig l→h when ctrl=0 sig l→h when ctrl=1 +1 (inc) 0 (-) 0 (-) Inc ctr Inc ctr +2 (dec) 0 (-) 0 (-) Dec ctr Dec ctr +0 (-) x x No action No action +1 (inc) 0 (-) 1 (inv) Inc ctr Dec ctr +1 (inc) 1 (inv) 0 (-) Dec ctr Inc ctr +2 (dec) 0 (-) 1 (inv) Dec ctr Inc ctr +1 (inc) 0 (-) 2 (dis) Inc ctr No action +1 (inc) 2 (dis) 0 (-) No action Inc ctr + +‫ھ‬іؓ༯ࢆခ (sig h→l) ္๝ဢൡႨđႨ NEG_MODE টսู POS_MODEb + +ૄ۱ઝԊ࠹ඔఖֆჭᄝᆃ 4 ۱ൻೆᇏनႵ၂۱ੲѯఖđॖၛੲԢᄮലbֆჭ֥ 4 ۱ൻೆྐ‫ݼ‬ॖၛ๙‫ݖ‬ᇂ໊ +PCNT_FILTER_EN_Un টյषੲѯ‫ିۿ‬b၂֊ੲѯఖФఓ‫׮‬đ಩‫ॺޅ‬؇б REG_FILTER_THRES_Un ۱ൈᇒᇛ௹ +ᅎ֥ઝԊ‫߶׻‬Ф‫ݖ‬ੲ‫ו‬đᆃུФ‫ݖ‬ੲ‫֥ו‬ઝԊࡼ҂߶ؓ࠹ඔఖఏ಩‫ޅ‬ቔႨb + +Ԣਔൻೆ๙֡ၛຓđೈࡱ္ିؓ࠹ඔఖࣉྛ၂҆‫ٳ‬॥ᇅbбೂ๙‫ݖ‬ᇂ໊ PCNT_CNT_PAUSE_Unđॖၛᄠ๔࠹ඔ +ఖb๙‫ݖ‬ᇂ໊ PCNT_PLUS_CNT_RST_Un ൌགྷ࠹ඔఖౢਬ‫ିۿ‬b + +17.2.3 ܴҳׄ + +PULSE_CNT ॖၛഡᇂ 5 ۱ܴҳׄđ5 ۱ܴҳׄ‫܋‬Ⴈ၂۱ᇏ؎đॖၛ๙‫ݖ‬۲ሱ֥ᇏ؎൐ିྐ‫ݼ‬षఓࠇ௠зᇏ؎b +ᆃུܴҳׄ‫ٳ‬љ൞ğ + + • ቋն࠹ඔᆴb֒ PULSE_CNT նႿ֩Ⴟ PCNT_CNT_H_LIM_Un ൈđౢॢ PULSE_CNTbఃᇏ + PCNT_CNT_H_LIM_Un ႋഡູᆞඔb + + • ቋཬ࠹ඔᆴb֒ PULSE_CNT ཬႿ֩Ⴟ PCNT_CNT_L_LIM_Un ൈđౢॢ PULSE_CNTbఃᇏ + PCNT_CNT_L_LIM_Un ႋഡູ‫ڵ‬ඔb + + • ਆ۱ᇏࡗᚐᆴb֒ PULSE_CNT ֩Ⴟ PCNT_THR_THRES0_Un ࠇᆀ PCNT_THR_THRES1_Un ൈđӁളཌྷ + ႋ֥ thr_event ྐ‫ݼ‬b + + • ਬb֒ PULSE_CNT ֩Ⴟ 0 ൈđӁളཌྷႋ֥ thr_event ྐ‫ݼ‬b + +17.2.4 ई২ + +๭ 17-2 ູࣇࣇ൐Ⴈ๙֡ 0 ࣉྛ‫־‬ᄹ࠹ඔ֥ൕၩ๭đ๙֡ 0 ֥஥ᇂೂ༯෮ൕb + + • CNT_CH0_POS_MODE_Un=1đࠧᄝ sig_ch0_un ֥ഈശခࣉྛ‫־‬ᄹ࠹ඔb + +ুᶈྐ༏॓࠯ 449 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 17 ઝԊ࠹ඔఖ (PCNT) + • PCNT_CH0_NEG_MODE_Un=0đࠧᄝ sig_ch0_un ֥༯ശခ҂ࣉྛ࠹ඔb + • PCNT_CH0_LCTRL_MODE_Un=0đࠧ֒ ctrl_ch0_un ູ֮‫׈‬௜ൈđؓൻೆ sig_ch0_un ࣉྛ‫־‬ᄹ॥ᇅb + • PCNT_CH0_HCTRL_MODE_Un=2đࠧ֒ ctrl_ch0_un ູۚ‫׈‬௜ൈđؓൻೆ sig_ch0_un ҂ࣉྛ॥ᇅb + • PCNT_CNT_H_LIM_Un=5đ֒ PULSE_CNT ֥ᆴ‫־‬ᄹ֞ PCNT_CNT_H_LIM_UnđPULSE_CNT ْ߭֞ 0b + + ๭ 17­2. PULSE_CNT ‫־‬ᄹ࠹ඔ๭ + + ๭ 17­3. PULSE_CNT ‫࠹ࡨ־‬ඔ๭ + +๭ 17-3 ູࣇࣇ൐Ⴈ๙֡ 0 ࣉྛ‫࠹ࡨ־‬ඔ֥ൕၩ๭đ๭ 17-3 ᇏ๙֡ 0 ֥஥ᇂა๭ 17-2 ᇏ֥஥ᇂ౵љູğ + + • PCNT_CH0_LCTRL_MODE_Un=1đࠧ֒ ctrl_ch0_un ູ֮‫׈‬௜ൈđؓൻೆ sig_ch0_un ࣉྛ‫ࡨ־‬॥ᇅb + • PCNT_CNT_H_LIM_Un=⚶5đ֒ PULSE_CNT ֥ᆴ‫ ֞ࡨ־‬PCNT_CNT_H_LIM_UnđPULSE_CNT ْ߭֞ 0b + +17.2.5 ၮԛᇏ؎ + +PCNT_CNT_THR_EVENT_Un_INğ‫ھ‬ᇏ؎Ⴕ 5 ۱ᇏ؎ჷđࠧ၂۱ቋն࠹ඔᆴᇏ؎đ၂۱ቋཬ࠹ඔᆴᇏ؎đਆ۱ +ᇏࡗᚐᆴᇏ؎ၛࠣ၂۱‫ݖ‬ਬᇏ؎đ෱ૌॖၛ๙‫ݖ‬۲ሱ֥ᇏ؎൐ିྐ‫ݼ‬षఓࠇ௠зᇏ؎b + +17.3 ࠷թఖਙі + + ଀ӫ ૭ඍ ֹᆶ ٠໙ + ஥ᇂ࠷թఖ + PCNT_U0_CONF0_REG ֆჭ 0 ֥஥ᇂ࠷թఖ 0 0x3FF57000 ‫؀‬/ཿ + PCNT_U1_CONF0_REG ֆჭ 1 ֥஥ᇂ࠷թఖ 0 0x3FF5700C ‫؀‬/ཿ + PCNT_U2_CONF0_REG ֆჭ 2 ֥஥ᇂ࠷թఖ 0 0x3FF57018 ‫؀‬/ཿ + PCNT_U3_CONF0_REG ֆჭ 3 ֥஥ᇂ࠷թఖ 0 0x3FF57024 ‫؀‬/ཿ + PCNT_U4_CONF0_REG ֆჭ 4 ֥஥ᇂ࠷թఖ 0 0x3FF57030 ‫؀‬/ཿ + PCNT_U5_CONF0_REG ֆჭ 5 ֥஥ᇂ࠷թఖ 0 0x3FF5703C ‫؀‬/ཿ + PCNT_U6_CONF0_REG ֆჭ 6 ֥஥ᇂ࠷թఖ 0 0x3FF57048 ‫؀‬/ཿ + +ুᶈྐ༏॓࠯ 450 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 17 ઝԊ࠹ඔఖ (PCNT) + + ଀ӫ ૭ඍ ֹᆶ ٠໙ + PCNT_U7_CONF0_REG ֆჭ 7 ֥஥ᇂ࠷թఖ 0 0x3FF57054 ‫؀‬/ཿ + PCNT_U0_CONF1_REG ֆჭ 0 ֥஥ᇂ࠷թఖ 1 0x3FF57004 ‫؀‬/ཿ + PCNT_U1_CONF1_REG ֆჭ 1 ֥஥ᇂ࠷թఖ 1 0x3FF57010 ‫؀‬/ཿ + PCNT_U2_CONF1_REG ֆჭ 2 ֥஥ᇂ࠷թఖ 1 0x3FF5701C ‫؀‬/ཿ + PCNT_U3_CONF1_REG ֆჭ 3 ֥஥ᇂ࠷թఖ 1 0x3FF57028 ‫؀‬/ཿ + PCNT_U4_CONF1_REG ֆჭ 4 ֥஥ᇂ࠷թఖ 1 0x3FF57034 ‫؀‬/ཿ + PCNT_U5_CONF1_REG ֆჭ 5 ֥஥ᇂ࠷թఖ 1 0x3FF57040 ‫؀‬/ཿ + PCNT_U6_CONF1_REG ֆჭ 6 ֥஥ᇂ࠷թఖ 1 0x3FF5704C ‫؀‬/ཿ + PCNT_U7_CONF1_REG ֆჭ 7 ֥஥ᇂ࠷թఖ 1 0x3FF57058 ‫؀‬/ཿ + PCNT_U0_CONF2_REG ֆჭ 0 ֥஥ᇂ࠷թఖ 2 0x3FF57008 ‫؀‬/ཿ + PCNT_U1_CONF2_REG ֆჭ 1 ֥஥ᇂ࠷թఖ 2 0x3FF57014 ‫؀‬/ཿ + PCNT_U2_CONF2_REG ֆჭ 2 ֥஥ᇂ࠷թఖ 2 0x3FF57020 ‫؀‬/ཿ + PCNT_U3_CONF2_REG ֆჭ 3 ֥஥ᇂ࠷թఖ 2 0x3FF5702C ‫؀‬/ཿ + PCNT_U4_CONF2_REG ֆჭ 4 ֥஥ᇂ࠷թఖ 2 0x3FF57038 ‫؀‬/ཿ + PCNT_U5_CONF2_REG ֆჭ 5 ֥஥ᇂ࠷թఖ 2 0x3FF57044 ‫؀‬/ཿ + PCNT_U6_CONF2_REG ֆჭ 6 ֥஥ᇂ࠷թఖ 2 0x3FF57050 ‫؀‬/ཿ + PCNT_U7_CONF2_REG ֆჭ 7 ֥஥ᇂ࠷թఖ 2 0x3FF5705C ‫؀‬/ཿ + ࠹ඔఖᆴ + PCNT_U0_CNT_REG ֆჭ 0 ֥࠹ඔᆴ 0x3FF57060 ᆺ‫؀‬ + PCNT_U1_CNT_REG ֆჭ 1 ֥࠹ඔᆴ 0x3FF57064 ᆺ‫؀‬ + PCNT_U2_CNT_REG ֆჭ 2 ֥࠹ඔᆴ 0x3FF57068 ᆺ‫؀‬ + PCNT_U3_CNT_REG ֆჭ 3 ֥࠹ඔᆴ 0x3FF5706C ᆺ‫؀‬ + PCNT_U4_CNT_REG ֆჭ 4 ֥࠹ඔᆴ 0x3FF57070 ᆺ‫؀‬ + PCNT_U5_CNT_REG ֆჭ 5 ֥࠹ඔᆴ 0x3FF57074 ᆺ‫؀‬ + PCNT_U6_CNT_REG ֆჭ 6 ֥࠹ඔᆴ 0x3FF57078 ᆺ‫؀‬ + PCNT_U7_CNT_REG ֆჭ 7 ֥࠹ඔᆴ 0x3FF5707C ᆺ‫؀‬ + ॥ᇅ࠷թఖ + PCNT_CTRL_REG ෮Ⴕ࠹ඔఖ֥॥ᇅ࠷թఖ 0x3FF570B0 ‫؀‬/ཿ + ᇏ؎࠷թఖ + PCNT_INT_RAW_REG ჰ൓ᇏ؎ሑ෿ 0x3FF57080 ᆺ‫؀‬ + PCNT_INT_ST_REG ௠зᇏ؎ሑ෿ 0x3FF57084 ᆺ‫؀‬ + PCNT_INT_ENA_REG ᇏ؎൐ି໊ 0x3FF57088 ‫؀‬/ཿ + PCNT_INT_CLR_REG ᇏ؎ౢԢ໊ 0x3FF5708C ᆺཿ + ሑ෿࠷թఖ + PCNT_Un_STATUS_REG ᆷൕ࠹ඔఖ֥ሑ෿ 0x3FF57090 ᆺ‫؀‬ + +ুᶈྐ༏॓࠯ 451 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 17 ઝԊ࠹ඔఖ (PCNT) + +17.4 ࠷թఖ + + Register 17.1. PCNT_Un_CONF0_REG (n: 0­7) (0x0+0x0C*n) + + PCNT_CH1P_CLCNTTR_CL_HM1PO_CHDNCETT__RUCLnH_M1P_OCPDONETS___UCMnHO1DP_ECN_NEUGTn__CMHO0DP_CEL_CNUTTnR_CL_HM0PO_CHDNCETT__RUCLnH_M0P_OCPDONETS___UCMnPHOC0DN_ENT_P_EUCTGnHN_RMTP__OCTTDHHNERRTP_E__UCTTSnHHN1RR_TPEE__NCLTS_H_N0LUR_TIPEMn__NCHT_H_NE_ULRNTIn__M_ZFU_IEnLERTNEO_R_U_EnENN__UUnn PCNT_FILTER_THRES_Un + +31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 + +0 0 0 0 0 0 0 0 001111 0x010 Reset + +PCNT_CH1_LCTRL_MODE_Un ֒ ॥ ᇅ ྐ ‫ ׈ ֮ ູ ݼ‬௜ ൈđ Ⴈ Ⴟ ‫ ڿ‬э + CH1_POS_MODE/CH1_NEG_MODE ֥ഡᇂbč‫؀‬/ཿĎ + 0ğ҂ቓྩ‫ڿ‬Ġ1ğّሇčᄹࡆሇູࡨഒđࡨഒሇູᄹࡆĎĠ2, 3ğ࣌ᆸ࠹ඔఖ࠹ඔb + +PCNT_CH1_HCTRL_MODE_Un ֒ ॥ ᇅ ྐ ‫ ׈ ۚ ູ ݼ‬௜ ൈđ Ⴈ Ⴟ ‫ ڿ‬э + CH1_POS_MODE/CH1_NEG_MODE ֥ഡᇂbč‫؀‬/ཿĎ + 0ğ҂ቓྩ‫ڿ‬Ġ1ğّሇčᄹࡆሇູࡨഒđࡨഒሇູᄹࡆĎĠ2, 3ğ࣌ᆸ࠹ඔఖ࠹ඔb + +PCNT_CH1_POS_MODE_Un ႨႿഡᇂ๙֡ 1 ࡟ҩൻೆྐ‫ݼ‬ഈശခ֥‫۽‬ቔଆൔbč‫؀‬/ཿĎ + 1ğᄹࡆ࠹ඔఖĠ2ğࡨഒ࠹ඔఖĠ0, 3: ؓ࠹ඔఖ໭಩‫ޅ‬႕ཙb + +PCNT_CH1_NEG_MODE_Un ႨႿഡᇂ๙֡ 1 ࡟ҩൻೆྐ‫ݼ‬༯ࢆခ֥‫۽‬ቔଆൔbč‫؀‬/ཿĎ + 1ğᄹࡆ࠹ඔఖĠ2ğࡨഒ࠹ඔఖĠ0, 3: ؓ࠹ඔఖ໭಩‫ޅ‬႕ཙb + +PCNT_CH0_LCTRL_MODE_Un ֒ ॥ ᇅ ྐ ‫ ׈ ֮ ູ ݼ‬௜ ൈđ Ⴈ Ⴟ ஥ ᇂ + CH0_POS_MODE/CH0_NEG_MODE ֥ഡᇂྩ‫ڿ‬ٚൔbč‫؀‬/ཿĎ + 0ğ҂ቓྩ‫ڿ‬Ġ1ğّሇčᄹࡆሇູࡨഒđࡨഒሇູᄹࡆĎĠ2, 3ğ࣌ᆸ࠹ඔྩ‫ڿ‬b + +PCNT_CH0_HCTRL_MODE_Un ֒ ॥ ᇅ ྐ ‫ ׈ ۚ ູ ݼ‬௜ ൈđ Ⴈ Ⴟ ஥ ᇂ + CH0_POS_MODE/CH0_NEG_MODE ֥ഡᇂྩ‫ڿ‬ٚൔbč‫؀‬/ཿĎ + 0ğ҂ቓྩ‫ڿ‬Ġ1ğّሇčᄹࡆሇູࡨഒđࡨഒሇູᄹࡆĎĠ2, 3ğ࣌ᆸ࠹ඔྩ‫ڿ‬b + +PCNT_CH0_POS_MODE_Un ႨႿഡᇂ๙֡ 1 ࡟ҩൻೆྐ‫ݼ‬ഈശခ֥‫۽‬ቔଆൔbč‫؀‬/ཿĎ + 1ğᄹࡆ࠹ඔఖĠ2ğࡨഒ࠹ඔఖĠ0, 3: ؓ࠹ඔఖ໭಩‫ޅ‬႕ཙb + +PCNT_CH0_NEG_MODE_Un T ֒๙֡ 0 ֥ൻೆྐ‫ݼ‬ฐҩ֞၂۱༯ࢆခൈđႨႿഡᇂ‫۽‬ቔଆ + ൔbč‫؀‬/ཿĎ1ğᄹࡆ࠹ඔఖĠ2ğࡨഒ࠹ඔఖĠ0, 3: ؓ࠹ඔఖ໭಩‫ޅ‬႕ཙb + +PCNT_THR_THRES1_EN_Un ູֆჭ n ֥ᚐᆴ 1 бࢠఖ֥൐ି໊bč‫؀‬/ཿĎ + +PCNT_THR_THRES0_EN_Un ູֆჭ n ֥ᚐᆴ 0 бࢠఖ֥൐ି໊bč‫؀‬/ཿĎ + +PCNT_THR_L_LIM_EN_Un ູֆჭ n ֥ᚐᆴ 1 бࢠఖ֥൐ି໊bč‫؀‬/ཿĎ + +PCNT_THR_H_LIM_EN_Un ູֆჭ n ֥ thr_h_lim бࢠఖ֥൐ି໊bč‫؀‬/ཿĎ + +PCNT_THR_ZERO_EN_Un ູֆჭ n ֥‫ݖ‬ਬбࢠఖ֥൐ି໊bč‫؀‬/ཿĎ + +PCNT_FILTER_EN_Un ູֆჭ n ֥ൻೆੲѯఖ֥൐ି໊bč‫؀‬/ཿĎ + +PCNT_FILTER_THRES_Un ᄝ APB_CLK ۱ൈᇒᇛ௹ଽູੲѯఖഡᇂቋնᚐᆴbᄝੲѯఖఓ‫׮‬ൈđ + ಩‫ޅ‬б APB_CLK ۱ൈᇒᇛ௹ᅎ֥ઝԊ‫ࡼ׻‬Ф‫ݖ‬ੲ‫ו‬bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 452 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 17 ઝԊ࠹ඔఖ (PCNT) + + Register 17.2. PCNT_Un_CONF1_REG (n: 0­7) (0x4+0x0C*n) + + PCNT_CNT_THRES1_Un PCNT_CNT_THRES0_Un + +31 16 15 0 + + 0x000 0x000 Reset + + PCNT_CNT_THRES1_Un ႨႿ஥ᇂֆჭ n ֥ᚐᆴ 1 ֥ᆴbč‫؀‬/ཿĎ + PCNT_CNT_THRES0_Un ႨႿ஥ᇂֆჭ n ֥ᚐᆴ 0 ֥ᆴbč‫؀‬/ཿĎ + + Register 17.3. PCNT_Un_CONF2_REG (n: 0­7) (0x8+0x0C*n) + + PCNT_CNT_L_LIM_Un PCNT_CNT_H_LIM_Un + +31 16 15 0 + + 0x000 0x000 Reset + + PCNT_CNT_L_LIM_Un ႨႿ஥ᇂֆჭ n ֥࠹ඔఖ֥ቋཬᆴbč‫؀‬/ཿĎ + PCNT_CNT_H_LIM_Un ႨႿ஥ᇂֆჭ n ֥࠹ඔఖ֥ቋնᆴbč‫؀‬/ཿĎ + + Register 17.4. PCNT_Un_CNT_REG (n: 0­7) (0x28+0x0C*n) + + (reserved) PCNT_PLUS_CNT_Un + 0x00000 +31 16 15 0 + +0000000000000000 Reset + + PCNT_PLUS_CNT_Un ‫࠷ھ‬թఖթԥሢֆჭ n ֥֒భ࠹ඔఖ֥ᆴđॖ‫܂‬ೈࡱ‫؀‬౼bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 453 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 17 ઝԊ࠹ඔఖ (PCNT) + + Register 17.5. PCNT_INT_RAW_REG (0x0080) + + (reserved) PCNTP_CCNNTTP__CCTHNNRTTP___CCETHVNNERTTPN___CCETTHV_NNUERTTPN7____CCETTIHV_NNNUERTTTPN6_____CCRETTIHV_NANNUERWTTTPN5_____CCRETTIHV_NANNUERWTTTN4_____CRETTIHV_ANNUERWTTN3____RETTIHV_ANUERWTN2___RETIV_ANUEWTN1__RTI_ANUWT0__RIANWT_RAW + +31 87 6 5 4 3 2 1 0 + + 0x0000000 0 0 0 0 0 0 0 0 Reset + + PCNT_CNT_THR_EVENT_Un_INT_RAW PCNT_CNT_THR_EVENT_Un_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿ + ໊bčᆺ‫؀‬Ď + + Register 17.6. PCNT_INT_ST_REG (0x0084) + + (reserved) PCNTP_CCNNTTP__CCTHNNRTTP___CCETHVNNERTTPN___CCETTHV_NNUERTTPN7____CCETTIHV_NNNUERTTTPN6_____CCSETTIHVT_NNNUERTTTPN5_____CCSETTIHVT_NNNUERTTTN4_____CSETTIHVT_NNUERTTN3____SETTIHVT_NUERTN2___SETIVT_NUETN1__STIT_NUT0__SITNT_ST + +31 87 6 5 4 3 2 1 0 + + 0x0000000 0 0 0 0 0 0 0 0 Reset + + PCNT_CNT_THR_EVENT_Un_INT_ST PCNT_CNT_THR_EVENT_Un_INT ᇏ ؎ ֥ ௠ з ᇏ ؎ ሑ ෿ + ໊bčᆺ‫؀‬Ď + + Register 17.7. PCNT_INT_ENA_REG (0x0088) + + (reserved) PCNTP_CCNNTTP__CCTHNNRTTP___CCETHVNNERTTPN___CCETTHV_NNUERTTPN7____CCETTIHV_NNNUERTTTPN6_____CCEETTIHNV_NNNUERATTTPN5_____CCEETTIHNV_NNNUERATTTN4_____CEETTIHNV_NNUERATTN3____EETTIHNV_NUERATN2___EETINV_NUEATN1__ETIN_NUAT0__EINNAT_ENA + +31 87 6 5 4 3 2 1 0 + + 0x0000000 0 0 0 0 0 0 0 0 Reset + + PCNT_CNT_THR_EVENT_Un_INT_ENA PCNT_CNT_THR_EVENT_Un_INT ᇏ؎֥൐ି໊bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 454 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 17 ઝԊ࠹ඔఖ (PCNT) + + Register 17.8. PCNT_INT_CLR_REG (0x008c) + + (reserved) PCNTP_CCNNTTP__CCTHNNRTTP___CCETHVNNERTTPN___CCETTHV_NNUERTTPN7____CCETTIHV_NNNUERTTTPN6_____CCCETTIHV_NNNLUERRTTTPN5_____CCCETTIHV_NNNLUERRTTTN4_____CCETTIHV_NNLUERRTTN3____CETTIHV_NLUERRTN2___CETIV_NLUERTN1__CTI_NLURT0__CINLRT_CLR + +31 87 6 5 4 3 2 1 0 + + 0x0000000 0 0 0 0 0 0 0 0 Reset + + PCNT_CNT_THR_EVENT_Un_INT_CLR ႨႿౢԢ PCNT_CNT_THR_EVENT_Un_INT ᇏ؎bčᆺཿĎ + + Register 17.9. PCNT_CTRL_REG (0x00b0) + + (reserved) (reservPeCdN) TP_CCNNTTP__CPPALNUUTPSS_CC_ECN_NUNTTP7_T_CPP_RALNUUSTPSTS_CC__EUCN_N7UNTTP6_T_CPP_RALNUUSTPSTS_CC__EUCN_N6UNTTP5_T_CPP_RALNUUSTPSTS_CC__EUCN_N5UNTTP4_T_CPP_RALNUUSTPSTS_CC__EUCN_N4UNTTP3_T_CPP_RALNUUSTPSTS_CC__EUCN_N3UNTTP2_T_CPP_RALNUUSTPSTS_CC__EUCN_N2UNTT1_T_PP_RALUUSSTS__EUC_1UN0T_RST_U0 + +31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + + 0x0000 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reset + + PCNT_CNT_PAUSE_Un ႨႿᄠ๔ֆჭ n ֥࠹ඔఖbč‫؀‬/ཿĎ + PCNT_PLUS_CNT_RST_Un ႨႿౢਬֆჭ n ֥࠹ඔఖbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 455 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 17 ઝԊ࠹ඔఖ (PCNT) + + Register 17.10. PCNT_Un_STATUS_REG (n: 0­7) (0x90+0x0C*n) + + (reserved) PCNTP_CTHNRTP__CZTHENRRTPO__CHT_HLN_ALRTITP__M_CLT_U_HNLLnRTAIM__TTT__PHHULCARRnTNE__TSTUH_0nTR_HLEARST_1_Z_ULEnARTO__UMnODE_Un + +31 76 5 4 3 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 Reset + + PCNT_THR_ZERO_LAT_Un ഈ၂Ցᇏ؎‫ؿ‬ളൈđ࠹ඔఖ࠹֞ 0bčᆺ‫؀‬Ď + PCNT_THR_H_LIM_LAT_Un ഈ၂Ցᇏ؎‫ؿ‬ളൈđ࠹ඔఖ࠹֞ቋնbčᆺ‫؀‬Ď + PCNT_THR_L_LIM_LAT_Un ഈ၂Ցᇏ؎‫ؿ‬ളൈđ࠹ඔఖ࠹֞ቋཬbčᆺ‫؀‬Ď + PCNT_THR_THRES0_LAT_Un ഈ၂Ցᇏ؎‫ؿ‬ളൈđ࠹ඔఖ࠹֞ PCNT_THR_THRES0_Unbčᆺ‫؀‬Ď + PCNT_THR_THRES1_LAT_Un ഈ၂Ցᇏ؎‫ؿ‬ളൈđ࠹ඔఖ࠹֞ PCNT_THR_THRES1_Unbčᆺ‫؀‬Ď + PCNT_THR_ZERO_MODE_Un ‫࠷ھ‬թఖ࠺੣ሢ֒భ࠹ඔఖ֥ሑ෿b0ğ࠹ඔᆴູ +0č࠹ඔᆴູႵ + + ‫ݼژ‬ඔĎĠ1ğ࠹ඔᆴູ -0Ġ2ğ࠹ඔᆴູ‫ڵ‬ඔĠ3ğ࠹ඔᆴູᆞඔbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 456 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 18 ‫ק‬ൈఖቆ (TIMG) + +18 ‫ק‬ൈఖቆ (TIMG) + +18.1 ‫ۀ‬ඍ + +ESP32 ଽᇂ 4 ۱ 64-bit ๙Ⴈ‫ק‬ൈఖbૄ۱‫ק‬ൈఖЇ‫ݣ‬၂۱ 16-bit ყ‫ٳ‬௔ఖ‫ބ‬၂۱ 64-bit ॖሱ‫׮‬ᇗྍࡆᄛཟഈ +Ĕཟ༯࠹ඔఖb + +ESP32 ֥‫ק‬ൈఖ‫ ູٳ‬2 ቆđૄቆ 2 ۱bTIMGn_Tx ֥ n սіቆљđx սі‫ק‬ൈఖщ‫ݼ‬b + +‫ק‬ൈఖหྟğ + + • 16-bit ൈᇒყ‫ٳ‬௔ఖđ‫ٳ‬௔༢ඔູ 2-65536 + + • 64-bit ൈࠎ࠹ඔఖ + + • ॖ஥ᇂ֥ཟഈĔཟ༯ൈࠎ࠹ඔఖğᄹࡆࠇࡨഒ + + • ᄠ๔‫گ߫ބ‬ൈࠎ࠹ඔఖ + + • Бࣞൈሱ‫׮‬ᇗྍࡆᄛ + + • ֒Бࣞᆴၮԛ/֮ႿЌ޹ᆴൈБࣞ + + • ೈࡱ॥ᇅ֥ࠧൈᇗྍࡆᄛ + + • ‫׈‬௜Ԩ‫ؿ‬ᇏ؎‫ބ‬шခԨ‫ؿ‬ᇏ؎ + +18.2 ‫ିۿ‬૭ඍ + +18.2.1 16­bit ყ‫ٳ‬௔ఖ + +ૄ۱‫ק‬ൈఖ‫׻‬ၛ APB ൈᇒč෪ཿ APB_CLKđ௔ੱ๙ӈູ 80 MHzĎቔູࠎԤൈᇒb16-bit ყ‫ٳ‬௔ఖؓ APB ൈ +ᇒࣉྛ‫ٳ‬௔đӁളൈࠎ࠹ඔఖൈᇒčTB_clkĎbTB_clk ૄ‫ݖ‬၂۱ᇛ௹đൈࠎ࠹ඔఖ߶ཟഈඔ၂ࠇᆀཟ༯ඔ၂bᄝ +൐Ⴈ࠷թఖ TIMGn_Tx_DIVIDER ஥ᇂ‫ٳ‬௔ఖԢඔభđсྶܱо‫ק‬ൈఖčౢਬ TIMGn_Tx_DIVIDERĎb‫ק‬ൈఖ൐ି +ൈ஥ᇂყ‫ٳ‬௔ఖ߶֝ᇁ҂ॖყᆩ֥ࢲ‫ݔ‬bყ‫ٳ‬௔ఖॖၛؓ APB ൈᇒࣉྛ 2 ֞ 65536 ֥‫ٳ‬௔bऎุটඪđ +TIMGn_Tx_DIVIDER ູ 1 ࠇ 2 ൈđൈᇒ‫ٳ‬௔ఖ൞ 2ĠTIMGn_Tx_DIVIDER ູ 0 ൈđൈᇒ‫ٳ‬௔ఖ൞ 65536bೂ +TIMGn_Tx_DIVIDER ູః෰಩ၩᆴđൈᇒ߶Фཌྷ๝ඔᆴ‫ٳ‬௔b + +18.2.2 64­bit ൈࠎ࠹ඔఖ + +TIMGn_Tx_INCREASE ᇂ 1 ࠇౢਬॖၛࡼ 64-bit ൈࠎ࠹ඔఖ‫ٳ‬љ஥ᇂູཟഈ࠹ඔࠇཟ༯࠹ඔb๝ൈđ64-bit ൈ +ࠎ࠹ඔఖᆦӻሱ‫׮‬ᇗྍࡆᄛ‫ބ‬ೈࡱࠧൈᇗྍࡆᄛđ࠹ඔఖղ֞ೈࡱഡ‫ק‬ᆴൈ߶Ԩ‫ؿ‬Бࣞ൙ࡱb + +TIMGn_Tx_EN ᇂ 1 ࠇౢਬॖၛ൐ିࠇܱо࠹ඔbౢਬު࠹ඔఖᄠ๔࠹ඔđѩ߶ᄝ TIMGn_Tx_ EN ᇗྍᇂ 1 భЌ +ӻఃᆴ҂эbౢਬ TIMGn_Tx _EN ߶ᇗྍࡆᄛ࠹ඔఖѩ‫ڿ‬э࠹ඔఖ֥ᆴđ֌ᄝഡᇂ TIMGn_Tx_EN భ࠹ඔ҂߶ +߫‫گ‬b + +ೈࡱॖၛ๙‫࠷ݖ‬թఖ TIMGn_Tx_LOAD_LO ‫ ބ‬TIMGn_Tx_LOAD_HI ᇗᇂ࠹ඔఖ֥ᆴbᇗྍࡆᄛൈđ࠷թ +ఖ +TIMGn_Tx_LOAD_LO ‫ ބ‬TIMGn_Tx_LOAD_HI ֥ᆴҌ߶Ф۷ྍ֞ 64-bit ൈࠎ࠹ඔఖଽbБࣞčБࣞൈሱ‫׮‬ᇗྍ +ࡆᄛĎࠇೈࡱčೈࡱࠧൈᇗྍࡆᄛĎ߶Ԩ‫ؿ‬ᇗྍࡆᄛb࠷թఖ TIMGn_Tx_AUTORELOAD ᇂ 1 ॖၛ൐ିБࣞൈ +ሱ‫׮‬ᇗྍࡆᄛbೂ‫ݔ‬Бࣞൈሱ‫׮‬ᇗྍࡆᄛໃФ൐ିđൈࠎ࠹ඔఖ߶ᄝБࣞު࠿࿃ཟഈ࠹ඔࠇཟ༯࠹ඔbᄝ࠷թ +ఖ TIMGn_Tx_LOAD_REG ഈཿ಩ၩᆴॖၛԨ‫ؿ‬ೈࡱࠧൈᇗྍࡆᄛđཿᆴൈ࠹ඔఖᆴ߶৫ख़‫ڿ‬эbೈࡱ္ି๙‫ݖ‬ +‫ڿ‬э TIMGn_Tx_INCREASE ֥ᆴ৫ख़‫ڿ‬эൈࠎ࠹ඔఖ࠹ඔٚཟb + +ুᶈྐ༏॓࠯ 457 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 18 ‫ק‬ൈఖቆ (TIMG) + +ೈࡱ္ି‫؀‬౼ൈࠎ࠹ඔఖb֌ႮႿ࠹ඔఖ൞ 64-bitđCPU ᆺିၛਆ۱ 32-bit ᆴ֥ྙൔ‫؀‬ᆴb࠹ඔఖᆴ൮༵ླေ +Ф෭ೆ TIMGn_TxLO_REG ‫ ބ‬TIMGn_TxHI_REGbᄝ TIMGn_TxUPDATE_REG ഈཿ಩ၩᆴॖၛઔഈࡼ 64-bit ‫ק‬ +ൈఖᆴ෭ೆਆ۱࠷թఖbᆭުđೈࡱॖၛᄝ಩‫ޅ‬ൈࡗ‫؀‬౼࠷թఖbᆃဢॖၛٝᆸ‫؀‬౼࠹ൈఖ֮ሳ‫ۚބ‬ሳൈԛགྷ +‫؀‬ᆴհ༂b + +18.2.3 БࣞӁള + +‫ק‬ൈఖॖၛԨ‫ؿ‬БࣞđБࣞᄵ߶ႄ‫ؿ‬ᇗྍࡆᄛ‫ބ‬ĔࠇԨ‫ؿ‬ᇏ؎bೂБࣞ࠷թఖ TIMGn_Tx_ALARMLO_REG ‫ބ‬ +TIMGn_Tx_ALARMHI_REG ֥ᆴ֩Ⴟ֒భ‫ק‬ൈఖ֥ᆴđᄵБࣞԨ‫ؿ‬bູࢳथ࠷թఖഡᇂ‫ݖ‬ພđ࠹ඔఖᆴӑ‫ݖ‬Б +ࣞᆴ֥໙ีđ֒భ‫ק‬ൈఖᆴۚႿčൡႨႿཟഈ‫ק‬ൈఖĎࠇ֮ႿčൡႨႿཟ༯‫ק‬ൈఖĎ֒భБࣞᆴ္߶Ԩ‫ؿ‬Бࣞb +ᄝᆃᇕ౦ঃ༯đ൐ିБࣞ‫߶ିۿ‬ઔഈԨ‫ؿ‬БࣞbБࣞ൐ିުđБࣞ൐ି໊ሱ‫׮‬ౢਬb + +18.2.4 MWDT + +ૄ۱‫ק‬ൈఖଆॶਸ਼Ї‫ݣ‬၂۱ᇶ༢๤ु૊‫קܐ‬ൈఖč෪ཿູ MWDTĎ‫ބ‬Ⴕܱ࠷թఖbЧᅣਙԛਔ࠷թఖཌྷܱྐ༏đ +‫ିۿ‬૭ඍ౨ҕᄇु૊‫קܐ‬ൈఖᅣࢫb + +18.2.5 ᇏ؎ + + • TIMGn_Tx_INT_WDT_INT ‫ھ‬ᇏ؎ᄝु૊‫קܐ‬ൈఖᇏ؎ࢨ‫؍‬ӑൈުӁളb + + • TIMGn_Tx_INT_T1_INT ‫ھ‬ᇏ؎Ⴎ‫ק‬ൈఖ 1 ഈ֥Бࣞ൙ࡱӁളb + + • TIMGn_Tx_INT_T0_INT ‫ھ‬ᇏ؎Ⴎ‫ק‬ൈఖ 0 ഈ֥Бࣞ൙ࡱӁളb + +18.3 ࠷թఖਙі ૭ඍ TIMG0 TIMG1 ٠໙ + + ଀ӫ ‫ק‬ൈఖ 0 ஥ᇂ࠷թఖ 0x3FF5F000 0x3FF60000 ‫؀‬/ཿ + ‫ק‬ൈఖ 0 ஥ᇂ‫ބ‬॥ᇅ࠷թఖ 0x3FF5F004 0x3FF60004 ᆺ‫؀‬ + TIMGn_T0CONFIG_REG ‫ק‬ൈఖ 0 ֥֒భᆴđ֮ 32 ໊ 0x3FF5F008 0x3FF60008 ᆺ‫؀‬ + TIMGn_T0LO_REG + TIMGn_T0HI_REG ‫ק‬ൈఖ 0 ֥֒భᆴđۚ 32 ໊ 0x3FF5F00C 0x3FF6000C ᆺཿ + + TIMGn_T0UPDATE_REG ཿᆴࡼ֒భ‫ק‬ൈఖ֥ᆴ‫گ‬ᇅ֞ 0x3FF5F010 0x3FF60010 ‫؀‬/ཿ + 0x3FF5F014 0x3FF60014 ‫؀‬/ཿ + TIMGn_T0ALARMLO_REG TIMGn_T0_(LO/HI)_REG 0x3FF5F018 0x3FF60018 ‫؀‬/ཿ + TIMGn_T0ALARMHI_REG 0x3FF5F01C 0x3FF6001C ‫؀‬/ཿ + TIMGn_T0LOADLO_REG ‫ק‬ൈఖ 0 ֥Бࣞᆴđ֮ 32 ໊ + TIMGn_T0LOADHI_REG 0x3FF5F020 0x3FF60020 ᆺཿ + ‫ק‬ൈఖ 0 ֥Бࣞᆴđۚ 32 ໊ + TIMGn_T0LOAD_REG + ‫ק‬ൈఖ 0 ֥ᇗྍࡆᄛᆴđ֮ 32 ໊ + ‫ק‬ൈఖ 1 ஥ᇂ‫ބ‬॥ᇅ࠷թఖ + TIMGn_T1CONFIG_REG ‫ק‬ൈఖ 0 ֥ᇗྍࡆᄛᆴđۚ 32 ໊ + TIMGn_T1LO_REG + TIMGn_T1HI_REG ཿ ᆴ Ֆ + + TIMGn_T1UPDATE_REG TIMGn_T0_(LOADLO/LOADHI)_REG + + TIMGn_T1ALARMLO_REG ഈࡆᄛ‫ק‬ൈఖ + TIMGn_T1ALARMHI_REG + TIMGn_T1LOADLO_REG ‫ק‬ൈఖ 1 ֥஥ᇂ࠷թఖ 0x3FF5F024 0x3FF60024 ‫؀‬/ཿ + ‫ק‬ൈఖ 1 ֥֒భᆴđ֮ 32 ໊ 0x3FF5F028 0x3FF60028 ᆺ‫؀‬ + ‫ק‬ൈఖ 1 ֥֒భᆴđۚ 32 ໊ 0x3FF5F02C 0x3FF6002C ᆺ‫؀‬ + ཿᆴࡼ֒భ‫ק‬ൈఖ֥ᆴ‫گ‬ᇅ֞ + TIMGn_T1_(LO/HI)_REG 0x3FF5F030 0x3FF60030 ᆺཿ + ‫ק‬ൈఖ 1 ֥Бࣞᆴđ֮ 32 ໊ + ‫ק‬ൈఖ 1 ֥Бࣞᆴđۚ 32 ໊ 0x3FF5F034 0x3FF60034 ‫؀‬/ཿ + ‫ק‬ൈఖ 1 ֥ᇗྍࡆᄛᆴđ֮ 32 ໊ 0x3FF5F038 0x3FF60038 ‫؀‬/ཿ + 0x3FF5F03C 0x3FF6003C ‫؀‬/ཿ + +ুᶈྐ༏॓࠯ 458 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 18 ‫ק‬ൈఖቆ (TIMG) + +଀ӫ ૭ඍ TIMG0 TIMG1 ٠໙ + +TIMGn_T1LOADHI_REG ‫ק‬ൈఖ 1 ֥ᇗྍࡆᄛᆴđۚ 32 ໊ 0x3FF5F040 0x3FF60040 ‫؀‬/ཿ + + ཿ ᆴ Ֆ + +TIMGn_T1LOAD_REG TIMGn_T1_(LOADLO/LOADHI)_REG 0x3FF5F044 0x3FF60044 ᆺཿ + ഈࡆᄛ‫ק‬ൈఖ + +༢๤ु૊‫קܐ‬ൈఖ஥ᇂ‫ބ‬॥ᇅ࠷թఖ + +TIMGn_Tx_WDTCONFIG0_REG ु૊‫קܐ‬ൈఖ஥ᇂ࠷թఖ 0x3FF5F048 0x3FF60048 ‫؀‬/ཿ + 0x3FF5F04C 0x3FF6004C ‫؀‬/ཿ +TIMGn_Tx_WDTCONFIG1_REG ु૊‫קܐ‬ൈఖყ‫ٳ‬௔ఖ࠷թఖ 0x3FF5F050 0x3FF60050 ‫؀‬/ཿ + 0x3FF5F054 0x3FF60054 ‫؀‬/ཿ +TIMGn_Tx_WDTCONFIG2_REG ु૊‫קܐ‬ൈఖࢨ‫ ؍‬0 ӑൈൈࡗ 0x3FF5F058 0x3FF60058 ‫؀‬/ཿ + 0x3FF5F05C 0x3FF6005C ‫؀‬/ཿ +TIMGn_Tx_WDTCONFIG3_REG ु૊‫קܐ‬ൈఖࢨ‫ ؍‬1 ӑൈൈࡗ 0x3FF5F060 0x3FF60060 ᆺཿ + 0x3FF5F064 0x3FF60064 ‫؀‬/ཿ +TIMGn_Tx_WDTCONFIG4_REG ु૊‫קܐ‬ൈఖࢨ‫ ؍‬2 ӑൈൈࡗ + 0x3FF5F068 0x3FF60068 ҂‫ק‬ +TIMGn_Tx_WDTCONFIG5_REG ु૊‫קܐ‬ൈఖࢨ‫ ؍‬3 ӑൈൈࡗ 0x3FF5F06C 0x3FF6006C ᆺ‫؀‬ + +TIMGn_Tx_WDTFEED_REG ཿᆴট່ु૊‫קܐ‬ൈఖ 0x3FF5F098 0x3FF60098 ‫؀‬/ཿ + 0x3FF5F09C 0x3FF6009C ᆺ‫؀‬ +TIMGn_Tx_WDTWPROTECT_REG ु૊‫ܐ‬ཿЌ޹࠷թఖ 0x3FF5F0A0 0x3FF600A0 ᆺ‫؀‬ +RTC ཮ሙ஥ᇂ࠷թఖ 0x3FF5F0A4 0x3FF600A4 ᆺཿ + +TIMGn_RTCCALICFG_REG RTC ཮ሙ஥ᇂ࠷թఖ + +TIMGn_RTCCALICFG1_REG RTC ཮ሙ஥ᇂ࠷թఖ 1 +ᇏ؎࠷թఖ + +TIMGn_Tx_INT_ENA_REG ᇏ؎൐ି໊ + +TIMGn_Tx_INT_RAW_REG ჰ൓ᇏ؎ሑ෿ + +TIMGn_Tx_INT_ST_REG ௠зᇏ؎ሑ෿ + +TIMGn_Tx_INT_CLR_REG ᇏ؎ౢԢ໊ + +ুᶈྐ༏॓࠯ 459 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 18 ‫ק‬ൈఖቆ (TIMG) + +18.4 ࠷թఖ + + Register 18.1. TIMGn_TxCONFIG_REG (x: 0­1) (0x0+0x24*x) + + TIMGnT_IMTxG_nET_INMTxG_nIN_CTxR_EAAUSTEORELOAD TIMGn_Tx_DIVIDER TIMGnT_IMTxG_nET_IDMTGxG_EnL__EINTVxTE__LAE_LNINART_ME_NEN + 0x00001 + 31 30 29 28 13 12 11 10 + + 011 0 0 0 Reset + +TIMGn_Tx_EN ᇂ 1 ުđ‫ק‬ൈఖ x ൈࠎ࠹ඔఖ൐ିbč‫؀‬/ཿĎ +TIMGn_Tx_INCREASE ᇂ 1 ުđ‫ק‬ൈఖ x ֥ൈࠎ࠹ඔఖ߶ᄝૄ۱ൈᇒᇛ௹ުᄹࡆbౢਬުđ‫ק‬ൈఖ + + x ൈࠎ࠹ඔఖ߶ᄝૄ۱ൈᇒᇛ௹ުࡨഒbč‫؀‬/ཿĎ +TIMGn_Tx_AUTORELOAD ᇂ 1 ުđ‫ק‬ൈఖ x Бࣞൈሱ‫׮‬ᇗྍࡆᄛ൐ିbč‫؀‬/ཿĎ +TIMGn_Tx_DIVIDER ࠹ൈఖ x ൈᇒ (Tx_clk) ֥ყ‫ٳ‬௔ఖᆴbč‫؀‬/ཿĎ +TIMGn_Tx_EDGE_INT_EN ᇂ 1 ުđБࣞ߶Ӂള၂۱шခԨ‫ؿ‬ᇏ؎bč‫؀‬/ཿĎ +TIMGn_Tx_LEVEL_INT_EN ᇂ 1 ު, Бࣞ߶Ӂള၂۱‫׈‬௜Ԩ‫ؿ‬ᇏ؎bč‫؀‬/ཿĎ +TIMGn_Tx_ALARM_EN ᇂ 1 ު, Бࣞ൐ିbБࣞ൐ିުđՎ໊ሱ‫׮‬ౢਬbč‫؀‬/ཿĎ + + Register 18.2. TIMGn_TxLO_REG (x: 0­1) (0x4+0x24*x) + +31 0 + + 0x000000000 Reset + +TIMGn_TxLO_REG ᄝ TIMGn_TxUPDATE_REG ഈཿᆴުđ‫ק‬ൈఖ x ൈࠎ࠹ඔఖ֥֮ 32 ໊ॖၛФ + ‫؀‬౼bčᆺ‫؀‬Ď + + Register 18.3. TIMGn_TxHI_REG (x: 0­1) (0x8+0x24*x) + +31 0 + + 0x000000000 Reset + +TIMGn_TxHI_REG ᄝ TIMGn_TxUPDATE_REG ഈཿᆴުđ‫ק‬ൈఖ x ൈࠎ࠹ඔఖ֥ۚ 32 ໊ॖၛФ‫؀‬ + ౼bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 460 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 18 ‫ק‬ൈఖቆ (TIMG) + + Register 18.4. TIMGn_TxUPDATE_REG (x: 0­1) (0xC+0x24*x) + +31 0 + + 0x000000000 Reset + +TIMGn_TxUPDATE_REG ཿ಩‫ޅ‬ᆴԨ‫קؿ‬ൈఖ x ൈࠎ࠹ඔఖᆴ۷ྍč‫ק‬ൈఖ x ֒భᆴ߶Фթԥ֞ၛ + ഈ࠷թఖĎbčᆺཿĎ + + Register 18.5. TIMGn_TxALARMLO_REG (x: 0­1Ď (0x10+0x24*x) 0 + +31 Reset + + 0x000000000 + + TIMGn_TxALARMLO_REG ‫ק‬ൈఖ x ൈࠎ࠹ඔఖԨ‫ࣞؿ‬Бᆴ֥֮ 32 ໊bč‫؀‬/ཿĎ + + Register 18.6. TIMGn_TxALARMHI_REG (x: 0­1) (0x14+0x24*x) 0 + +31 Reset + + 0x000000000 + + TIMGn_TxALARMHI_REG ‫ק‬ൈఖ x ൈࠎ࠹ඔఖԨ‫ࣞؿ‬Бᆴ֥ۚ 32 ໊b(‫؀‬/ཿĎ + + Register 18.7. TIMGn_TxLOADLO_REG (x: 0­1) (0x18+0x24*x) 0 + +31 Reset + + 0x000000000 + + TIMGn_TxLOADLO_REG ‫ק‬ൈఖ x ൈࠎ࠹ඔఖᇗྍࡆᄛ֥֮ 32-bit ᆴb(‫؀‬/ཿ) + + Register 18.8. TIMGn_TxLOADHI_REG (x: 0­1) (0x1C+0x24*x) 0 + +31 Reset + + 0x000000000 + + TIMGn_TxLOADHI_REG ‫ק‬ൈఖ x ൈࠎ࠹ඔఖᇗྍࡆᄛ֥ۚ 32-bit ᆴbč‫؀‬/ཿĎ + + Register 18.9. TIMGn_TxLOAD_REG (x: 0­1) (0x20+0x24*x) 0 + +31 Reset + + 0x000000000 + + TIMGn_TxLOAD_REG ཿ಩‫ޅ‬ᆴԨ‫קؿ‬ൈఖ x ൈࠎ࠹ඔఖᇗྍࡆᄛbčᆺཿĎ + +ুᶈྐ༏॓࠯ 461 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 18 ‫ק‬ൈఖቆ (TIMG) + + Register 18.10. TIMGn_Tx_WDTCONFIG0_REG (0x0048) + + TIMGn_TTxI_MWGDnT__TEx_NWTIMDTG_nS_TTGx_0WTIMDTG_nS_TTGx_1WTIMDTG_nS_TTTGxI_M2WGDnTT_IM_TSxG_TnWG_D3TxT__WTEIMDDGTG_EnL__EITNVxT_E_WLE_DNINTT_T_CIEMPNUG_nR_TExS_EWTTIMD_LTGE_nNS_GYTSxT__HWREDSTE_TFL_LAESNHGBTOHOT_MOD_EN + + 31 30 29 28 27 26 25 24 23 22 21 20 18 17 15 14 + + 00 0 0 0 00 0x1 0x1 1 Reset + +TIMGn_Tx_WDT_EN ᇂ 1 ު, SWDT ൐ିbč‫؀‬/ཿĎ +TIMGn_TxS_WDT_STG0 ࢨ‫ ؍‬0 ஥ᇂb0: ܱоđ1: ᇏ؎, 2: ‫ ໊گ‬CPU, 3: ‫໊گ‬༢๤bč‫؀‬/ཿĎ +TIMGn_Tx_WDT_STG1 ࢨ‫ ؍‬1 ஥ᇂb0: ܱоđ1: ᇏ؎, 2: ‫ ໊گ‬CPU, 3: ‫໊گ‬༢๤bč‫؀‬/ཿĎ +TIMGn_Tx_WDT_STG2 ࢨ‫ ؍‬2 ஥ᇂb0: ܱоđ1: ᇏ؎, 2: ‫ ໊گ‬CPU, 3: ‫໊گ‬༢๤bč‫؀‬/ཿĎ +TIMGn_Tx_WDT_STG3 ࢨ‫ ؍‬3 ஥ᇂb0: ܱоđ1: ᇏ؎, 2: ‫ ໊گ‬CPU, 3: ‫໊گ‬༢๤bč‫؀‬/ཿĎ +TIMGn_Tx_WDT_EDGE_INT_EN ᇂ 1 ު, ೂӑ‫קݖ‬ൈఖ x ֥ࢨ‫؍‬ᇏ؎Ӂളൈࡗđ߶ӁളшခԨ‫ؿ‬ᇏ + + ؎bč‫؀‬/ཿĎ + +TIMGn_Tx_WDT_LEVEL_INT_EN ᇂ 1 ު, ೂӑ‫ݖ‬ഡᇂ֥ࢨ‫؍‬ᇏ؎Ӂളൈࡗđ߶Ӂള‫׈‬௜Ԩ‫ؿ‬ᇏ + ؎bč‫؀‬/ཿĎ + +TIMGn_Tx_WDT_CPU_RESET_LENGTH CPU ‫ݼྐ໊گ‬Ӊ؇࿊ᄴb0: 100 ns, 1: 200 ns, 2: 300 ns, + 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µsbč‫؀‬/ཿĎ + +TIMGn_Tx_WDT_SYS_RESET_LENGTH ༢๤‫ݼྐ໊گ‬Ӊ؇࿊ᄴb0: 100 ns, 1: 200 ns, 2: 300 ns, + 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µsbč‫؀‬/ཿĎ + +TIMGn_Tx_WDT_FLASHBOOT_MOD_EN ᇂ 1 ު, Flash ఓ‫׮‬Ќ޹൐ିbč‫؀‬/ཿĎ + + Register 18.11. TIMGn_Tx_WDTCONFIG1_REG (0x004c) + + TIMGn_Tx_WDT_CLK_PRESCALE + + 31 16 + + 0x00001 Reset + +TIMGn_Tx_WDT_CLK_PRESCALE SWDT ൈ ᇒ ყ ‫ ٳ‬௔ ఖ ᆴđ ‫ ٳ‬я ੱ = 12.5 ns * + TIMGn_Tx_WDT_CLK_PRESCALEbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 462 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 18 ‫ק‬ൈఖቆ (TIMG) 0 + + Register 18.12. TIMGn_Tx_WDTCONFIG2_REG (0x0050) Reset + + 31 + + 26000000 + + TIMGn_Tx_WDTCONFIG2_REG SWDT ൈᇒᇛ௹ᇏࢨ‫ ؍‬0 ӑൈൈࡗbč‫؀‬/ཿĎ + + Register 18.13. TIMGn_Tx_WDTCONFIG3_REG (0x0054) 0 + +31 Reset + + 0x007FFFFFF + + TIMGn_Tx_WDTCONFIG3_REG SWDT ൈᇒᇛ௹ᇏࢨ‫ ؍‬1 ӑൈൈࡗbč‫؀‬/ཿĎ + + Register 18.14. TIMGn_Tx_WDTCONFIG4_REG (0x0058) 0 + +31 Reset + + 0x0000FFFFF + + TIMGn_Tx_WDTCONFIG4_REG SWDT ൈᇒᇛ௹ᇏࢨ‫ ؍‬2 ӑൈൈࡗbč‫؀‬/ཿĎ + + Register 18.15. TIMGn_Tx_WDTCONFIG5_REG (0x005c) 0 + +31 Reset + + 0x0000FFFFF + + TIMGn_Tx_WDTCONFIG5_REG SWDT ൈᇒᇛ௹ᇏࢨ‫ ؍‬3 ӑൈൈࡗbč‫؀‬/ཿĎ + + Register 18.16. TIMGn_Tx_WDTFEED_REG (0x0060) 0 + +31 Reset + + 0x000000000 + + TIMGn_Tx_WDTFEED_REG ཿ಩‫ޅ‬ᆴ౺‫ ׮‬SWDTbčᆺཿĎ + + Register 18.17. TIMGn_Tx_WDTWPROTECT_REG (0x0064) + +31 0 + + 0x050D83AA1 Reset + +TIMGn_Tx_WDTWPROTECT_REG ೂ‫࠷ݔ‬թఖᇏႵ‫໊گބ‬ᆴ҂๝֥ᆴđཿЌ޹൐ିbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 463 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 18 ‫ק‬ൈఖቆ (TIMG) + + Register 18.18. TIMGn_RTCCALICFG_REG (0x0068) + + TIMGn_RTC_CALI_START TIMGn_RTC_CALI_MAX TIMGn_RTTIMCG_CnA_RLTITI_MCRG_DCnYA_RLIT_CC_LCKA_LSIE_LSTART_CYCLING(reserved) + 0x01 +31 30 16 15 14 13 12 11 0 + +0 0 0x1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +TIMGn_RTC_CALI_START_CYCLING Ќ਽b(‫؀‬/ཿ) +TIMGn_RTC_CALI_CLK_SEL ࿊ ᄴ ր ཮ ሙ ൈ ᇒb0ğRTC_CLKb1ğRTC20M_D256_CLKb2ğ + + XTAL32K_CLKb(‫؀‬/ཿ) +TIMGn_RTC_CALI_RDY ѓ࠺ЧՑ཮ሙປӮb(ᆺ‫)؀‬ +TIMGn_RTC_CALI_MAX ཮ሙൈࡗđ࠹ඔֆູ໊ր཮ሙൈᇒᇛ௹b(‫؀‬/ཿ) +TIMGn_RTC_CALI_START ೈࡱषఓ཮ሙb(‫؀‬/ཿ) + + Register 18.19. TIMGn_RTCCALICFG1_REG (0x006C) + + TIMGn_RTC_CALI_VALUE (reserved) + +31 75 0 + + 0x00000 0 0 0 0 0 0 Reset + +TIMGn_RTC_CALI_VALUE ր཮ሙൈᇒᇛ௹ඔղ֞ TIMGn_RTC_CALI_MAX ൈ֥཮ሙࢲ‫ݔ‬đֆ໊൞ + XTAL_CLK ᇛ௹b(ᆺ‫)؀‬ + +ুᶈྐ༏॓࠯ 464 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 18 ‫ק‬ൈఖቆ (TIMG) + + Register 18.20. TIMGn_Tx_INT_ENA_REG (0x0098) + + (reserved) TIMGnT_IMTxG_nITN_IMTT_xG_WnIN_DTTT_x__TINI1N_TTI_N_ETTN0_A_EINNAT_ENA + +31 32 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + TIMGn_Tx_INT_WDT_INT_ENA TIMGn_Tx_INT_WDT_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + TIMGn_Tx_INT_T1_INT_ENA TIMGn_Tx_INT_T1_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + TIMGn_Tx_INT_T0_INT_ENA TIMGn_Tx_INT_T0_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + Register 18.21. TIMGn_Tx_INT_RAW_REG (0x009c) + + (reserved) TIMGnT_IMTxG_nITN_IMTT_xG_WnIN_DTTT_x__TINI1N_TTI_N_RTTA0_W_RIANWT_RAW + +31 32 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + TIMGn_Tx_INT_WDT_INT_RAW TIMGn_Tx_INT_WDT_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + TIMGn_Tx_INT_T1_INT_RAW TIMGn_Tx_INT_T1_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + TIMGn_Tx_INT_T0_INT_RAW TIMGn_Tx_INT_T0_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + + Register 18.22. TIMGn_Tx_INT_ST_REG (0x00a0) + + (reserved) TIMGnT_IMTxG_nITN_IMTT_xG_WnIN_DTTT_x__TINI1N_TTI_N_STTT0__SITNT_ST + +31 32 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + TIMGn_Tx_INT_WDT_INT_ST TIMGn_Tx_INT_WDT_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + TIMGn_Tx_INT_T1_INT_ST TIMGn_Tx_INT_T1_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + TIMGn_Tx_INT_T0_INT_ST TIMGn_Tx_INT_T0_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 465 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 18 ‫ק‬ൈఖቆ (TIMG) + + Register 18.23. TIMGn_Tx_INT_CLR_REG (0x00a4) + + (reserved) TIMGnT_IMTxG_nITN_IMTT_xG_WnIN_DTTT_x__TINI1N_TTI_N_CTTL0_R_CINLRT_CLR + +31 32 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + TIMGn_Tx_INT_WDT_INT_CLR ᇂ 1 ‫໊ھ‬ၛౢԢ TIMGn_Tx_INT_WDT_INT ᇏ؎bčᆺཿĎ + TIMGn_Tx_INT_T1_INT_CLR ᇂ 1 ‫໊ھ‬ၛౢԢ TIMGn_Tx_INT_T1_INT ᇏ؎bčᆺཿĎ + TIMGn_Tx_INT_T0_INT_CLR ᇂ 1 ‫໊ھ‬ၛౢԢ TIMGn_Tx_INT_T0_INT ᇏ؎bčᆺཿĎ + +ুᶈྐ༏॓࠯ 466 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 19 ु૊‫קܐ‬ൈఖ (WDT) + +19 ु૊‫קܐ‬ൈఖ (WDT) + +19.1 ‫ۀ‬ඍ + +ESP32 ᇏႵ೘۱ु૊‫קܐ‬ൈఖğਆ۱‫ק‬ൈఖଆॶᇏ۲၂۱čӫቔᇶ༢๤ु૊‫קܐ‬ൈఖđ෪ཿູ MWDTĎđRTC +ଆॶᇏ၂۱čӫቔ RTC ु૊‫קܐ‬ൈఖđ෪ཿູ RWDTĎb҂ॖყᆩ֥ೈࡱࠇ႗ࡱ໙ี߶֝ᇁႋႨӱ྽‫۽‬ቔാӈđ +ु૊‫קܐ‬ൈఖॖၛϺᇹ༢๤Ֆᇏ߫‫گ‬bु૊‫קܐ‬ൈఖႵඹ۱ࢨ‫؍‬bೂ‫֒ݔ‬భࢨ‫؍‬ӑ‫ݖ‬ყ‫ק‬ൈࡗđ֌ીႵ່‫ࠇܐ‬ +ܱоु૊‫קܐ‬ൈఖđૄ۱ࢨ‫؍‬ॖିФ஥Ӯၛ༯೘ࠇඹᇕ‫׮‬ቔᇏ֥၂ᇕbᆃུ‫׮‬ቔ൞ğᇏ؎aCPU ‫໊گ‬aଽ‫گނ‬ +໊‫ބ‬༢๤‫໊گ‬bఃᇏđᆺႵ RWDT ି‫ܔ‬Ԩ‫ؿ‬༢๤‫໊گ‬đࡼ‫໊گ‬Їও RTC ‫ބ‬ᇶ༢๤ᄝଽ֥ᆜ۱ྉோbૄ۱ࢨ‫؍‬ +֥ӑൈൈࡗ‫׻‬ॖֆ‫׿‬ഡᇂb + +ᄝ Flash ఓ‫׮‬௹ࡗđRWDT ‫ֻބ‬၂۱ MWDT ߶ሱ‫׮‬षఓၛ࡟ҩ‫گྩބ‬ఓ‫׮‬໙ีb + +19.2 ᇶေหྟ + + • 4 ۱ࢨ‫؍‬đૄࢨ‫׻؍‬ॖФֆ‫׿‬஥ᇂࠇܱо + + • ۲ࢨ‫؍‬ӑൈൈࡗॖ஥ᇂ + + • ೂࢨ‫؍‬ӑൈđ߶Ґ౼೘֞ඹᇕॖି‫׮‬ቔᇏ֥၂ᇕčᇏ؎aCPU ‫໊گ‬aଽ‫ބ໊گނ‬༢๤‫໊گ‬Ď + + • 32-bit ӑൈ࠹ඔఖ + + • ཿЌ޹đٝᆸ RWDT ‫ ބ‬MWDT ஥ᇂФ҂ཬྏ‫ڿ‬э + + • Flash ఓ‫׮‬Ќ޹ + ೂ‫ݔ‬ᄝყ‫ק‬ൈࡗଽđSPI Flash ֥ఓ‫ݖ׮‬ӱીႵປӮđु૊‫߶ܐ‬ᇗఓᆜ۱ᇶ༢๤ + +19.3 ‫ିۿ‬૭ඍ + +19.3.1 ൈᇒ + +RWDT ֥ൈᇒჷ൞ RTC ત෎ൈᇒ SLOW_CLKbMWDT ൈᇒჷটሱႿ APB ൈᇒ APB_CLKđࣜ‫ݖ‬ॖ஥ᇂ֥ +16-bit ყ‫ٳ‬௔ఖൻԛ۳ MWDTbRWDT ‫ ބ‬MWDT ֥ൈᇒჷႨቔ౺‫ ׮‬32-bit ӑൈ࠹ඔఖb֒࠹ඔఖࢤ࣍֒భࢨ +‫֥؍‬ӑൈൈࡗđࡼᆳྛ֒భࢨ‫؍‬஥ᇂ֥‫׮‬ቔđӑൈ࠹ඔఖ‫໊گ‬đ༯၂ࢨ‫؍‬ఓ‫׮‬b + +19.3.2 ᄎྛ‫ݖ‬ӱ + +RWDT ‫ ބ‬MWDT ൐ିൈ߶࿖ߌ‫۽‬ቔđՖࢨ‫ ؍‬0 ࣉྛ֞ࢨ‫ ؍‬3đᄜ߭֞ࢨ‫ ؍‬0 ᇗྍष൓bૄࢨ‫؍‬ӑൈ‫׮‬ቔ‫ބ‬ӑൈ +ൈࡗॖၛФֆ‫׿‬஥ᇂb + +ೂ‫ݔ‬ӑൈ࠹ൈఖࢤ࣍ࢨ‫؍‬ӑൈൈࡗđၛ༯‫׮‬ቔॖၛФ஥ᇂ֞ૄ۱ࢨ‫؍‬ğ + + • Ԩ‫ؿ‬ᇏ؎ + ೂࢨ‫؍‬ӑൈđᇏ؎ФԨ‫ؿ‬b + + • ‫ ໊گ‬CPU ଽ‫ނ‬ + ೂࢨ‫؍‬ӑൈđ‫໊گ‬ᆷ‫ ק‬CPU ଽ‫ނ‬b‫ ໊گ‬MWDT0 CPU ᆺି‫ ໊گ‬PRO CPUđ‫ ໊گ‬MWDT1 CPU ᆺି‫໊گ‬ + APP CPUb۴ऌ҂๝஥ᇂđ‫ ໊گ‬RWDT CPU ॖၛ‫໊گ‬ਆ۱đ၂۱ࠇ҂‫ ໊گ‬CPU ଽ‫ނ‬b + + • ‫໊گ‬ᇶ༢๤ + ೂࢨ‫؍‬ӑൈđЇও MWDT ᄝଽ֥ᇶ༢๤‫߶׻‬Ф‫໊گ‬bᄝЧ໓ᇏđᇶ༢๤ᆷ֥൞ CPU ‫ބ‬෮Ⴕຓഡb֌ + RTC ൞၂۱২ຓđ҂߶‫໊گ‬b + +ুᶈྐ༏॓࠯ 467 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 19 ु૊‫קܐ‬ൈఖ (WDT) + + • ‫໊گ‬ᇶ༢๤‫ ބ‬RTC + ೂࢨ‫؍‬ӑൈđᇶ༢๤‫ ބ‬RTC ๝ൈ‫໊گ‬bՎ‫׮‬ቔࣇॖᄝ RWDT ᇏൌགྷb + + • ܱо + ‫ؓ؍ࢨھ‬༢๤҂Ӂള႕ཙb + +֒ೈࡱ່‫ܐ‬ൈđु૊‫קܐ‬ൈఖᇗྍ߭֞ࢨ‫ ؍‬0đӑൈ࠹ඔఖՖ 0 ᇗྍष൓b + +19.3.3 ཿЌ޹ + +ਆ۱ MWDT ‫ ބ‬RWDT ‫׻‬ॖФЌ޹҂൳༂ཿ႕ཙbູൌགྷ‫ିۿھ‬đਆ۱ु૊‫׻ܐ‬஥ႵཿૡӼЌ޹࠷թఖb +MWDT ֥࠷թఖູ TIMERS_WDT_WKEY, RWDT ֥࠷թఖູ RTC_CNTL_WDT_WKEYb‫໊گ‬ൈđᆃུ࠷թఖ֥ +Ԛ൓ᆴູ 0x50D83AA1b֒࠷թఖ֥ᆴФ‫ڿ‬эđཿЌ޹൐ିbՎൈđԢਔཿૡӼЌ޹࠷թఖၛຓđᄝЇও່‫ܐ‬ +࠷թఖ֥ః෰಩ၩ WDT ࠷թఖഈཿᆴҠቔ߶Фޭ੻b๷ࡩοၛ༯҄ᇧ٠໙ WDTğ + + 1. ܱоཿЌ޹ + + 2. ۴ऌླေྩ‫࠷ڿ‬թఖࠇ່‫ܐ‬ + + 3. ᇗྍ൐ିཿЌ޹ + +19.3.4 Flash ఓ‫׮‬Ќ޹ + +ᄝ Flash ఓ‫ݖ׮‬ӱᇏđ‫ק‬ൈఖቆ 0čTIMG0Ďᇏ֥ MWDT ‫ ބ‬RWDT ሱ‫׮‬൐ିbਆ۱ु૊‫קܐ‬ൈఖ֥ࢨ‫ ؍‬0 ଏಪ +ູᄝӑൈު‫໊گ‬༢๤bఓ‫ު׮‬đႋ‫ھ‬ౢਬ࠷թఖ TIMERS_WDT_FLASHBOOT_MOD_EN টܱо MWDT Flash ఓ +‫׮‬Ќ޹ӱ྽bؓႿ RWDTđᄵႋ‫ھ‬ౢਬ RTC_CNTL_WDT_FLASHBOOT_MOD_EN bಖުđೈࡱॖၛ஥ᇂ +MWDT ‫ ބ‬RWDTb + +19.3.5 ࠷թఖ + +MWDT ࠷թఖ൞‫ק‬ൈఖሰଆॶ֥၂҆‫ٳ‬đᄝ‫ק‬ൈఖ࠷թఖᇏႵབྷ༥૭ඍbRWDT ࠷թఖ൞ RTC ሰଆॶ֥၂҆ +‫ٳ‬đᄝ RTC ࠷թఖᇏႵབྷ༥૭ඍb + +ুᶈྐ༏॓࠯ 468 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + +20 eFuse ॥ᇅఖ (eFuse) + +20.1 ‫ۀ‬ඍ + +ESP32 ᇏႵ‫؟‬۱ eFuseđఃᇏթԥሢ༢๤ҕඔbቔູ၂ᇕ٤ၞാྟթԥֆ໊đeFuse ֥ bit ၂֊Фഎཿູ 1đ҂ +ି߫‫ ູگ‬0beFuse ॥ᇅఖοᅶೈࡱҠቔປӮؓ eFuse ᇏ۲۱༢๤ҕඔᇏ֥۲۱ bit ֥എཿb + +ᆃུ༢๤ҕඔႵུॖၛ๙‫ ݖ‬eFuse ॥ᇅఖФೈࡱ‫؀‬౼đႵུᆰࢤႮ႗ࡱଆॶ൐Ⴈb + +20.2 ᇶေหྟ + + • 33 ۱༢๤ҕඔ + + • എཿЌ޹čॖ࿊Ď + + • ೈࡱ‫؀‬౼Ќ޹čॖ࿊Ď + +20.3 ‫ିۿ‬૭ඍ + +20.3.1 ࢲ‫ܒ‬ + +eFuse ᇏթԥਔ 33 ۱༢๤ҕඔđ۲۱༢๤ҕඔ໊֥ॺ҂๝đః଀ӫა໊ॺೂі 20-1 ෮ൕbఃᇏđ +efuse_wr_disableaefuse_rd_disableacoding_schemeaBLK3_part_reserve ᆃ 4 ۱༢๤ҕඔა eFuse ॥ᇅఖᆰ +ࢤཌྷܱb + + і 20­1. ༢๤ҕඔ + +ҕඔ ໊ॺ efuse_wr_disable efuse_rd_disable ૭ඍ + +efuse_wr_disable 16 എཿЌ޹ ೈࡱ‫؀‬౼Ќ޹ +efuse_rd_disable 4 +flash_crypt_cnt 7 1 - ॥ᇅ eFuse ॥ᇅఖ +WIFI_MAC_Address 56 +SPI_pad_config_hd 5 0 - ॥ᇅ eFuse ॥ᇅఖ +XPD_SDIO_REG 1 + 2 - ܵ৘ flash ࡆૡ/ࢳૡ +SDIO_TIEH 1 + 3 - Wi-Fi MAC ֹᆶ‫ ބ‬CRC + + 3 - ࡼ SPI I/O ஥ᇂ֞ଖ۱ܵ࢖ + + 5 - ۳ flash ‫ࢫט‬ఖഈ‫׈‬ + + ஥ᇂ flash ‫ࢫט‬ఖ + + 5 - ‫׈‬࿢ğᇂ 1 ൈູ 3.3 VĠ + + ᇂ 0 ൈູ 1.8 V + + थ‫ ק‬XPD_SDIO_REG + +sdio_force 1 5 - ‫ ބ‬SDIO_TIEH + + ൞‫ڎ‬॥ᇅ flash ‫ࢫט‬ఖ + +BLK3_part_reserve 1 5 - ൐Ⴈ BLOCK3 + +SPI_pad_config_clk 5 6 - ࡼ SPI I/O ஥ᇂ֞ଖ۱ܵ࢖ + +SPI_pad_config_q 5 6 - ࡼ SPI I/O ஥ᇂ֞ଖ۱ܵ࢖ + +SPI_pad_config_d 5 6 - ࡼ SPI I/O ஥ᇂ֞ଖ۱ܵ࢖ + +SPI_pad_config_cs0 5 6 - ࡼ SPI I/O ஥ᇂ֞ଖ۱ܵ࢖ + +flash_crypt_config 4 10 3 ܵ৘ flash ࢳૡ/ࡆૡ + +coding_scheme* 2 10 3 ॥ᇅ eFuse ॥ᇅఖ + +console_debug_disable 1 15 - ᇂ 1 ൈđ࣌Ⴈ ROM BASIC + ॥ᇅ෻‫ט‬൫ fallback ଆൔb + +ুᶈྐ༏॓࠯ 469 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + +ҕඔ ໊ॺ efuse_wr_disable efuse_rd_disable ૭ඍ +abstract_done_0 1 +abstract_done_1 1 എཿЌ޹ ೈࡱ‫؀‬౼Ќ޹ +JTAG_disable 1 +download_dis_encrypt 1 12 - थ‫ ק‬Secure Boot ֥ሑ෿ +download_dis_decrypt 1 +download_dis_cache 1 13 - थ‫ ק‬Secure Boot ֥ሑ෿ + +key_status 1 14 - ࣌Ⴈ JTAG +BLOCK1* 256/192/128 +BLOCK2* 256/192/128 15 - ܵ৘ flash ࢳૡ/ࡆૡ +BLOCK3* 256/192/128 +disable_app_cpu 1 15 - ܵ৘ flash ࢳૡ/ࡆૡ +disable_bt 1 +pkg_version 4 15 - ᄝ Download ଆൔᇏܱо +disable_cache 1 Cache +CK8M Frequency 8 + 10 3 थ‫ ק‬BLOCK3 ൞‫ڎ‬ФႨ޼ +vol_level_hp_inv 2 ൐Ⴈ + +dig_vol_l6 4 7 0 ܵ৘ flash ࢳૡ/ࡆૡ + +uart_download_dis 1 8 1 Secure Boot ૡᄂ + + 9 2 Ⴈ޼൐Ⴈૡᄂ + + 3 - ࣌Ⴈ APP CPU + + 3 - ࣌Ⴈড࿩ + + 3 - ‫ٿ‬ልϱЧ + + 3 - ࣌Ⴈ cache + + 4 - RTC8M_CLK ௔ੱ + + ႨႿѓ് CPU ஝ 240 MHz ࠇ + + 3 - flash/PSRAM ஝ 80 MHz ླေ + + ֥‫׈‬࿢໊֖ + + ႨႿթ٢໊֖ 6 ֥ dig regula- + + 11 - tor ֥‫׈‬࿢ཌྷؓႿ 1.2 V ֥ҵ + + ᆴ + + 2 - ᇂ 1 ൈđႥࣲ࣌Ⴈ༯ᄛఓ‫׮‬ଆ + ൔčࣇ ESP32 ECO V3 ᆦӻĎ + +20.3.1.1 ༢๤ҕඔ efuse_wr_disable + +༢๤ҕඔ efuse_wr_disable थ‫ק‬෮Ⴕ֥༢๤ҕඔ൞‫ڎ‬ԩႿഎཿЌ޹ሑ෿bቔູ၂۱༢๤ҕඔđefuse_wr_disable +္थ‫ק‬ఃЧദ൞‫ڎ‬ԩႿഎཿЌ޹ሑ෿b + +೏ଖ۱༢๤ҕඔໃԩႿഎཿЌ޹ሑ෿đᄵՎ༢๤ҕඔໃФഎཿ֥ bit ି‫ܔ‬Ֆ 0 ФഎཿӮ 1bఃၘФഎཿ֥ bit ၘ +ູࣜ 1đ౏҂ॖ۷‫ڿ‬b೏ଖ۱༢๤ҕඔԩႿഎཿЌ޹ሑ෿đᄵՎ༢๤ҕඔ֥ૄ၂۱ bit ‫׻‬໭‫م‬ᄜФ۷‫ڿ‬bఃໃФ +എཿ֥ bit Ⴅჹູ 0đၘФഎཿ֥ bit Ⴅჹູ 1b + +ૄ۱༢๤ҕඔ֥എཿЌ޹ሑ෿ؓႋ efuse_wr_disable ֥၂۱ bitb֒ଖ۱༢๤ҕඔؓႋ֥ bit ູ 0 ൈđіൕՎ༢ +๤ҕඔໃԩႿഎཿЌ޹ሑ෿b֒ଖ۱༢๤ҕඔؓႋ֥ bit ູ 1 ൈđіൕՎ༢๤ҕඔԩႿഎཿЌ޹ሑ෿bೂ‫ݔ‬ଖ +۱༢๤ҕඔၘࣜԩႿഎཿЌ޹ሑ෿đᄵࡼႥჹԩႿՎሑ෿bі 20-1 ૭ඍਔ۲۱༢๤ҕඔ֥എཿЌ޹ሑ෿ऎุ +Ⴎ efuse_wr_disable ֥ଧ۱ bit थ‫ק‬b + +20.3.1.2 ༢๤ҕඔ efuse_rd_disable + +33 ۱༢๤ҕඔᇏႵ 27 ۱҂൳ೈࡱ‫؀‬౼Ќ޹ሑ෿֥ჿඏđᆃ 27 ۱༢๤ҕඔࠧі 20-1 ᇏoefuse_rd_disable ೈ +ࡱ‫؀‬౼Ќ޹p၂ਙᇏđؓႋᆴູo-p֥༢๤ҕඔbᆃུ༢๤ҕඔᄝ಩‫ޅ‬ൈީ‫׻‬ॖ๙‫ ݖ‬eFuse ॥ᇅఖႮೈࡱ‫؀‬౼đ + +ুᶈྐ༏॓࠯ 470 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + +ఃᇏႵ҆‫ٳ‬๝ൈ္Ⴎ႗ࡱଆॶ൐Ⴈb + +ఃჅ֥ 6 ۱༢๤ҕඔᄝໃԩႿೈࡱ‫؀‬౼Ќ޹ሑ෿ൈđ࠻ॖၛФೈࡱ‫؀‬౼္ॖၛФ႗ࡱଆॶ൐Ⴈb֒෱ૌԩႿೈ +ࡱ‫؀‬౼Ќ޹ሑ෿ൈđᆺିФ႗ࡱଆॶ൐Ⴈb + +і 20-1 ᇏ֥oefuse_rd_disable ೈࡱ‫؀‬౼Ќ޹p၂ਙ૭ඍਔᆃ 6 ۱༢๤ҕඔ֥ೈࡱ‫؀‬౼Ќ޹ሑ෿ऎุႮ +efuse_rd_disable ֥ଧ۱ bit थ‫ק‬b༢๤ҕඔ efuse_rd_disable ᇏ֥ଖ۱ bit ູ 0đіൕՎ bit ܵ৘֥༢๤ҕඔໃ +ԩႿೈࡱ‫؀‬౼Ќ޹ሑ෿b೏༢๤ҕඔ efuse_rd_disable ᇏ֥ଖ۱ bit ູ 1đіൕՎ bit ܵ৘֥༢๤ҕඔԩႿೈࡱ +‫؀‬౼Ќ޹ሑ෿bೂ‫ݔ‬ଖ۱༢๤ҕඔၘԩႿೈࡱ‫؀‬౼Ќ޹ሑ෿đᄵࡼႥჹԩႿՎሑ෿b + +20.3.1.3 ༢๤ҕඔ coding_scheme + +ೂі 20-1 ෮ൕđ༢๤ҕඔ BLOCK1aBLOCK2aBLOCK3 ໊֥ॺ൞э߄֥b෱ૌ໊֥ॺႮਸ਼၂۱༢๤ҕ +ඔ +coding_scheme थ‫ק‬bෙಖ BLOCK1aBLOCK2aBLOCK3 ໊֥ॺ൞э߄֥đ֌ᆃ 3 ۱༢๤ҕඔᄝ eFuse ᇏᅝ +Ⴈ֥ bit ඔ൓ᇔ҂эbᆃ 3 ۱༢๤ҕඔა෱ૌᄝ eFuse ᇏ֥թԥᆴᆭࡗթᄝሢщ઒႘ഝܱ༢bऎุҕ࡮і +20-2b + + і 20­2. BLOCK1/2/3 щ઒ + + coding_scheme[1:0] BLOCK1/2/3 ໊ॺ щ઒ٚൔ eFuse ᇏ֥ bit ඔ + 00/11 256 ٤щ઒ 256 + 01 192 3/4 щ઒ 256 + 10 128 ᇗ‫گ‬щ઒ 256 + +ၛ༯ؓ೘ᇕщ઒ٚൔࣉྛࢳ൤đఃᇏđ + +• BLOCKN іൕ༢๤ҕඔ BLOCK1aBLOCK2 ࠇ BLOCK3b + +• BLOCKN [255 : 0]aBLOCKN [191 : 0]aBLOCKN [127 : 0] ‫ٳ‬љіൕ೘ᇕщ઒ٚൔ༯ᆃࠫ۱༢๤ҕඔ + ֥۲۱ bitb + +• eBLOCKN [255 : 0] іൕᆃࠫ۱༢๤ҕඔࣜ‫ݖ‬щ઒ᆭު֥۲۱ bitđࠧᄝ eFuse ᇏ֥۲۱ bitb + +٤щ઒ٚൔ + + eBLOCKN [255 : 0] = BLOCKN [255 : 0] + +3/4 щ઒ٚൔ + +BLOCKNij[7 : 0] = BLOCKN [48i + 8j + 7 : 48i + 8j] i ∈ {0, 1, 2, 3} j ∈ {0, 1, 2, 3, 4, 5} + i ∈ {0, 1, 2, 3} j ∈ {0, 1, 2, 3, 4, 5, 6, 7} +e B LOC K N j [7 : 0] = e B LOC K N [64i + 8j + 7 : 64i + 8j] + i + +ুᶈྐ༏॓࠯ 471 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + BB⊕LLOOBCCLKKONNC Kii0j [[77N::i200[7]] j ∈ {0, 1, 2, 3, 4, 5} + +e B LOC K N j [7 : 0] = ⊕ BLOCKNi1[7 : 0] : 0] j ∈ {6} i ∈ {0, 1, 2, 3} + i : 0] ⊕ BLOCKNi3[7 : 0] + +  ⊕ BLOCKNi4[7 : 0] ⊕ BLOCKNi5[7 + + 5 7 + + (l + 1) BLOCKNil[k] j ∈ {7} + + l=0 k=0 + + ⊕ іൕο໊ၳࠇ + + ‫ ބ‬+ іൕࡆ + +ᇗ‫گ‬щ઒ٚൔ + + eBLOCKN [255 : 128] = eBLOCKN [127 : 0] = BLOCKN [127 : 0] + +20.3.1.4 ༢๤ҕඔ BLK3_part_reserve + +༢๤ҕඔ coding_schemeaBLOCK1aBLOCK2aBLOCK3 ൳༢๤ҕඔ BLK3_part_reserve ჿඏb +֒ BLK3_part_reserve ູ 0 ൈđcoding_schemeaBLOCK1aBLOCK2aBLOCK3 ॖၛ൞ᄍྸ֥಩ၩᆴb +֒ BLK3_part_reserve ູ 1 ൈđcoding_schemeaBLOCK1aBLOCK2aBLOCK3 сಖФ‫ ູקܥ‬3/4 щ઒bਸ਼ຓ +Վൈ BLOCK3[143 : 96] ࠧ eBLOCK3[191 : 128] ҂ᄍྸ൐Ⴈb + +20.3.2 എཿ༢๤ҕඔ + +എཿэӉ༢๤ҕඔ BLOCK1aBLOCK2aBLOCK3 ҂๝Ⴟഎཿ‫ק‬Ӊ༢๤ҕඔb໡ૌѩ҂ᆰࢤഎཿ༢๤ҕඔ +BLOCK1aBLOCK2aBLOCK3 Чദđ‫ط‬൞എཿఃщ઒ᆭު֥ᆴ eBLOCKN [255 : 0]đᆃ۱ᆴ໊֥ॺ൓ᇔ൞ +256b‫ط‬എཿ‫ק‬Ӊ༢๤ҕඔᄵ൞ᆰࢤഎཿ༢๤ҕඔЧദb + +30 ۱‫ק‬Ӊ༢๤ҕඔ֥ૄ၂۱ bit ა 3 ۱эӉ༢๤ҕඔщ઒ᆭު֥ૄ၂۱ bit ‫ٳ׻‬љؓႋ၂۱എཿ࠷թఖ bitđؓ +ႋܱ༢ೂі 20-3 ෮ൕbഎཿ༢๤ҕඔ֥ൈީླေ൐Ⴈ֞ᆃུ࠷թఖ bitb + + і 20­3. എཿ࠷թఖ + + ༢๤ҕඔ ࠷թఖ + ໊ॺ +଀ӫ 16 Bit ଀ӫ Bit +efuse_wr_disable 4 [15:0] [15:0] +efuse_rd_disable 7 [3:0] EFUSE_BLK0_WDATA0_REG [19:16] +flash_crypt_cnt 1 [6:0] [26:20] +uart_download_dis [0] EFUSE_BLK0_WDATA1_REG [27] + 56 [31:0] EFUSE_BLK0_WDATA2_REG [31:0] +WIFI_MAC_Address [55:32] [23:0] + 1 [0] EFUSE_BLK0_WDATA3_REG [0] +disable_app_cpu 1 [0] [1] +disable_bt 4 [3:0] EFUSE_BLK0_WDATA4_REG [2], [11:9] +pkg_version 1 [0] [3] +disable_cache 5 [4:0] [8:4] +SPI_pad_config_hd 1 [0] [14] +BLK3_part_reserve 8 [7:0] [7:0] +CK8M Frequency 1 [0] [14] +XPD_SDIO_REG + +ুᶈྐ༏॓࠯ 472 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + ༢๤ҕඔ ࠷թఖ + ໊ॺ +଀ӫ 1 Bit ଀ӫ Bit +SDIO_TIEH 1 [0] [15] +sdio_force 5 [0] EFUSE_BLK0_WDATA5_REG [16] +SPI_pad_config_clk 5 [4:0] [4:0] +SPI_pad_config_q 5 [4:0] EFUSE_BLK0_WDATA6_REG [9:5] +SPI_pad_config_d 5 [4:0] [14:10] +SPI_pad_config_cs0 2 [4:0] EFUSE_BLK1_WDATA0_REG [19:15] +vol_level_hp_inv 4 [1:0] EFUSE_BLK1_WDATA1_REG [23:22] +dig_vol_l6 4 [3:0] EFUSE_BLK1_WDATA2_REG [27:24] +flash_crypt_config 2 [3:0] EFUSE_BLK1_WDATA3_REG [31:28] +coding_scheme 1 [1:0] EFUSE_BLK1_WDATA4_REG [1:0] +console_debug_disable 1 [0] EFUSE_BLK1_WDATA5_REG [2] +abstract_done_0 1 [0] EFUSE_BLK1_WDATA6_REG [4] +abstract_done_1 1 [0] EFUSE_BLK1_WDATA7_REG [5] +JTAG_disable 1 [0] EFUSE_BLK2_WDATA0_REG [6] +download_dis_encrypt 1 [0] EFUSE_BLK2_WDATA1_REG [7] +download_dis_decrypt 1 [0] EFUSE_BLK2_WDATA2_REG [8] +download_dis_cache 1 [0] EFUSE_BLK2_WDATA3_REG [9] +key_status [0] EFUSE_BLK2_WDATA4_REG [10] + [31:0] EFUSE_BLK2_WDATA5_REG [31:0] +BLOCK1 256/192/128 [63:32] EFUSE_BLK2_WDATA6_REG [31:0] + [95:64] EFUSE_BLK2_WDATA7_REG [31:0] +BLOCK2 256/192/128 [127:96] EFUSE_BLK3_WDATA0_REG [31:0] + [159:128] EFUSE_BLK3_WDATA1_REG [31:0] +BLOCK3 256/192/128 [191:160] EFUSE_BLK3_WDATA2_REG [31:0] + [223:192] EFUSE_BLK3_WDATA3_REG [31:0] + [255:224] EFUSE_BLK3_WDATA4_REG [31:0] + [31:0] EFUSE_BLK3_WDATA5_REG [31:0] + [63:32] EFUSE_BLK3_WDATA6_REG [31:0] + [95:64] EFUSE_BLK3_WDATA7_REG [31:0] + [127:96] [31:0] + [159:128] [31:0] + [191:160] [31:0] + [223:192] [31:0] + [255:224] [31:0] + [31:0] [31:0] + [63:32] [31:0] + [95:64] [31:0] + [127:96] [31:0] + [159:128] [31:0] + [191:160] [31:0] + [223:192] [31:0] + [255:224] [31:0] + +ুᶈྐ༏॓࠯ 473 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + +എཿ༢๤ҕඔ֥ੀӱೂ༯: + 1. ஥ᇂ࠷թఖ EFUSE_CLK ֥ EFUSE_CLK_SEL0 ໊aEFUSE_CLK_SEL1 ໊ა࠷թఖ EFUSE_DAC_CONF + ֥ EFUSE_DAC_CLK_DIV ໊b + 2. ࡼླေഎཿ֥ bit ؓႋ֥࠷թఖ bit ᇂ 1b + 3. ؓ࠷թఖ EFUSE_CONF ཿೆ 0x5A5Ab + 4. ؓ࠷թఖ EFUSE_CMD ཿೆ 0x2b + 5. ੽࿘࠷թఖ EFUSE_CMD ᆰ֞ఃູ 0x0đࠇᆀ֩րഎཿປӮᇏ؎Ӂളb + 6. ؓ࠷թఖ EFUSE_CONF ཿೆ 0x5AA5b + 7. ؓ࠷թఖ EFUSE_CMD ཿೆ 0x1b + 8. ੽࿘࠷թఖ EFUSE_CMD ᆰ֞ఃູ 0x0đࠇᆀ֩ր‫؀‬౼ປӮᇏ؎Ӂളb + 9. ࡼၘഎཿਔ֥ bit ؓႋ֥࠷թఖ bit ᇂ 0b + +ೂі 20-4 ෮ൕđ࠷թఖ EFUSE_CLK ֥ EFUSE_CLK_SEL0 ໊aEFUSE_CLK_SEL1 ໊ა࠷թఖ +EFUSE_DAC_CONF ֥ EFUSE_DAC_CLK_DIV ໊֥஥ᇂᆴ൞ၛ֒భ APB_CLK ֥௔ੱູ၇ऌ֥b + + і 20­4. ൈ྽஥ᇂ + +࠷թఖ ؓႋ࠷թఖ໊֥஥ᇂᆴ APB_CLK ௔ੱ +EFUSE_CLK +EFUSE_DAC_CONF 26 MHz 40 MHz 80 MHz + + EFUSE_CLK_SEL0[7:0] 250 160 80 + + EFUSE_CLK_SEL1[7:0] 255 255 128 + + EFUSE_DAC_CLK_DIV[7:0] 52 80 100 + +ၛ༯ਆᇕٚ‫م‬ॖၛ്љഎཿ/‫؀‬౼ປӮᇏ؎֥Ӂളğ +ٚ‫م‬၂ğ + + 1. ੽࿘࠷թఖ EFUSE_INT_RAW ֥ bit 1/0đᆰ֞ bit 1/0 ູ 1đіൕഎཿ/‫؀‬౼ປӮᇏ؎Ӂളb + 2. ࡼ࠷թఖ EFUSE_INT_CLR ֥ bit 1/0 ᇂ 1 ၛౢԢഎཿ/‫؀‬౼ປӮᇏ؎b +ٚ‫ؽم‬ğ + 1. ࡼ࠷թఖ EFUSE_INT_ENA ֥ bit 1/0 ᇂ 1đ൐ eFuse ॥ᇅఖି‫ؿܔ‬ԛഎཿ/‫؀‬౼ປӮᇏ؎b + 2. ஥ᇂ Interrupt Matrix ൐ CPU ି‫ܔ‬ཙႋ EFUSE_INT ᇏ؎b + 3. എཿ/‫؀‬౼ປӮᇏ؎Ӂളb + 4. Ұ࿘࠷թఖ EFUSE_INT_ST ֥ bit 1/0 ၛ஑؎എཿ/‫؀‬౼ປӮᇏ؎Ӂളb + 5. ؓ࠷թఖ EFUSE_INT_CLR ֥ bit 1/0 ᇂ 1 ၛౢഎཿ/‫؀‬౼ປӮᇏ؎b +എཿ҂๝֥༢๤ҕඔđമᇀ൞๝၂۱༢๤ҕඔᇏ֥҂๝ bit ‫׻‬ॖၛᄝ‫؟‬Ցഎཿᇏ‫ٳ‬љປӮb֌໡ૌࡹၰ࣐ਈࡨ +ഒഎཿՑඔđࠧଖ۱༢๤ҕඔᇏ֥෮Ⴕླေഎཿ֥ bit ‫׻‬ᄝ၂ՑഎཿᇏປӮbѩ౏֒ efuse_wr_disable ֥ଖ۱ +bit ܵ৘֥෮Ⴕ༢๤ҕඔ‫׻‬എཿᆭުđࣼ৫ࠧഎཿ efuse_wr_disable ֥Վ bitbമᇀॖၛᄝ๝၂Ցഎཿᇏ࠻എཿ + +ুᶈྐ༏॓࠯ 474 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + +efuse_wr_disable ֥ଖ۱ bit ܵ৘֥෮Ⴕ༢๤ҕඔđ๝ൈ္എཿ efuse_wr_disable ֥Վ bitbਸ਼ຓđ࿸࣌ؓၘࣜഎ +ཿਔ֥ bit ᇗ‫گ‬എཿb + +20.3.3 ೈࡱ‫؀‬౼༢๤ҕඔ + +30 ۱‫ק‬Ӊ༢๤ҕඔ֥ૄ၂۱ bit ა 3 ۱эӉ༢๤ҕඔЧദ֥ૄ၂۱ bit ‫ٳ׻‬љؓႋ၂۱ೈࡱ‫؀‬౼࠷թఖ bitđؓ +ႋܱ༢ೂі 20-5 ෮ൕb๙‫ݖ‬ೈࡱ‫؀‬౼ᆃུ࠷թఖࠧॖࠆᆩ༢๤ҕඔ֥ᆴb ༢๤ҕඔ BLOCK1aBLOCK2a +BLOCK3 ໊֥ॺ൞҂‫֥ק‬bෙಖೂі 20-5 ෮ൕđᆃ 3 ۱ҕඔ۲ሱؓႋ 256 ۱࠷թఖ bitđ֌൞ᄝ 3/4 щ઒‫ބ‬ᇗ +‫گ‬щ઒ଆൔ༯đᆃ 256 ۱࠷թఖ bit ᇏ֥Ⴕ҆‫ٳ‬൞໭ི֥bᄝ٤щ઒ଆൔ༯đBLOCKN [255 : 0] ֥ૄ၂۱ bit +ؓႋ֥࠷թఖ bit ‫׻‬൞ႵႨ֥bᄝ 3/4 щ઒ଆൔ༯đᆺႵ BLOCKN [191 : 0] ؓႋ֥࠷թఖ bit ൞ႵႨ֥bᄝᇗ +‫گ‬щ઒ଆൔ༯đᆺႵ BLOCKN [127 : 0] ؓႋ֥࠷թఖ bit ႵႨbᄝ҂๝щ઒ٚൔ༯đೈࡱՖ໭ི֥࠷թఖ bit +ᇏ‫؀‬ԛ֥ᆴ໭ၩၬbೈࡱՖႵႨ֥࠷թఖ bit ‫؀‬ԛ֥ᆴ൞༢๤ҕඔ BLOCK1aBLOCK2aBLOCK3 Чദđ҂൞ +ᆃࠫ۱༢๤ҕඔщ઒ᆭު֥ᆴb + + і 20­5. ೈࡱ‫؀‬౼࠷թఖ + + ༢๤ҕඔ ࠷թఖ + ໊ॺ +଀ሳ 16 Bit ଀ӫ Bit +efuse_wr_disable 4 [15:0] [15:0] +efuse_rd_disable 7 [3:0] EFUSE_BLK0_RDATA0_REG [19:16] +flash_crypt_cnt 1 [6:0] [26:20] +uart_download_dis [0] [27] + [31:0] [31:0] +WIFI_MAC_Address 56 [55:32] EFUSE_BLK0_RDATA1_REG [23:0] + [0] EFUSE_BLK0_RDATA2_REG [0] + [0] [1] +disable_app_cpu 1 [3:0] [2], [11:9] + [0] [3] +disable_bt 1 [4:0] [8:4] + [0] [14] +pkg_version 4 [7:0] [7:0] + [0] [14] +disable_cache 1 [0] EFUSE_BLK0_RDATA3_REG [15] + [0] [16] +SPI_pad_config_hd 5 [4:0] [4:0] + [4:0] [9:5] +BLK3_part_reserve 1 [4:0] [14:10] + [4:0] [19:15] +CK8M Frequency 8 [1:0] [23:22] + [3:0] [27:24] +XPD_SDIO_REG 1 [3:0] EFUSE_BLK0_RDATA4_REG [31:28] + [1:0] [1:0] +SDIO_TIEH 1 [0] [2] + [0] [4] +sdio_force 1 [0] [5] + [0] [6] +SPI_pad_config_clk 5 [0] [7] + [0] [8] +SPI_pad_config_q 5 + +SPI_pad_config_d 5 + +SPI_pad_config_cs0 5 EFUSE_BLK0_RDATA5_REG + +vol_level_hp_inv 2 + +dig_vol_l6 4 + +flash_crypt_config 4 + +coding_scheme 2 + +console_debug_disable 1 + +abstract_done_0 1 + +abstract_done_1 1 + +JTAG_disable 1 EFUSE_BLK0_RDATA6_REG + +download_dis_encrypt 1 + +download_dis_decrypt 1 + +ুᶈྐ༏॓࠯ 475 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + ༢๤ҕඔ ࠷թఖ + ໊ॺ +଀ሳ 1 Bit ଀ӫ Bit +download_dis_cache 1 [0] [9] +key_status 256/192/128 [0] EFUSE_BLK1_RDATA0_REG [10] +BLOCK1 [31:0] EFUSE_BLK1_RDATA1_REG [31:0] + [63:32] EFUSE_BLK1_RDATA2_REG [31:0] +BLOCK2 256/192/128 [95:64] EFUSE_BLK1_RDATA3_REG [31:0] + [127:96] EFUSE_BLK1_RDATA4_REG [31:0] +BLOCK3 256/192/128 [159:128] EFUSE_BLK1_RDATA5_REG [31:0] + [191:160] EFUSE_BLK1_RDATA6_REG [31:0] + [223:192] EFUSE_BLK1_RDATA7_REG [31:0] + [255:224] EFUSE_BLK2_RDATA0_REG [31:0] + [31:0] EFUSE_BLK2_RDATA1_REG [31:0] + [63:32] EFUSE_BLK2_RDATA2_REG [31:0] + [95:64] EFUSE_BLK2_RDATA3_REG [31:0] + [127:96] EFUSE_BLK2_RDATA4_REG [31:0] + [159:128] EFUSE_BLK2_RDATA5_REG [31:0] + [191:160] EFUSE_BLK2_RDATA6_REG [31:0] + [223:192] EFUSE_BLK2_RDATA7_REG [31:0] + [255:224] EFUSE_BLK3_RDATA0_REG [31:0] + [31:0] EFUSE_BLK3_RDATA1_REG [31:0] + [63:32] EFUSE_BLK3_RDATA2_REG [31:0] + [95:64] EFUSE_BLK3_RDATA3_REG [31:0] + [127:96] EFUSE_BLK3_RDATA4_REG [31:0] + [159:128] EFUSE_BLK3_RDATA5_REG [31:0] + [191:160] EFUSE_BLK3_RDATA6_REG [31:0] + [223:192] EFUSE_BLK3_RDATA7_REG [31:0] + [255:224] [31:0] + +20.3.4 ႗ࡱଆॶ൐Ⴈ༢๤ҕඔ + +႗ࡱଆॶ൐Ⴈ༢๤ҕඔ൞๙‫׈ݖ‬ਫ਼৵ࢤൌགྷ֥đೈࡱ໭‫ۄم‬ყᆃ۱‫ݖ‬ӱb႗ࡱଆॶ൐Ⴈ֥‫׻‬൞༢๤ҕඔЧദb +ؓႿ BLOCK1aBLOCK2aBLOCK3 ‫ط‬࿽đ႗ࡱଆॶ൐Ⴈ֥൞ࢳ઒ᆭު֥ᆴđ҂൞෱ૌщ઒ᆭު֥ᆴb + +20.3.5 ᇏ؎ + + • EFUSE_PGM_DONE_INTğ֒ eFuse എཿປӮުđՎᇏ؎ФԨ‫ؿ‬b + + • EFUSE_READ_DONE_INTğ֒ eFuse ‫؀‬౼ປӮުđՎᇏ؎ФԨ‫ؿ‬b + +ুᶈྐ༏॓࠯ 476 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + +20.4 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + + ଀ӫ ْ߭ eFuse BLOCK 0 ᇏ word 0 ֥ᆴ 0x3FF5A000 ᆺ‫؀‬ + eFuse ‫؀‬౼࠷թఖ ْ߭ eFuse BLOCK 0 ᇏ word 1 ֥ᆴ 0x3FF5A004 ᆺ‫؀‬ + EFUSE_BLK0_RDATA0_REG ْ߭ eFuse BLOCK 0 ᇏ word 2 ֥ᆴ 0x3FF5A008 ᆺ‫؀‬ + EFUSE_BLK0_RDATA1_REG ْ߭ eFuse BLOCK 0 ᇏ word 3 ֥ᆴ 0x3FF5A00C ᆺ‫؀‬ + EFUSE_BLK0_RDATA2_REG ْ߭ eFuse BLOCK 0 ᇏ word 4 ֥ᆴ 0x3FF5A010 ᆺ‫؀‬ + EFUSE_BLK0_RDATA3_REG ْ߭ eFuse BLOCK 0 ᇏ word 5 ֥ᆴ 0x3FF5A014 ᆺ‫؀‬ + EFUSE_BLK0_RDATA4_REG ْ߭ eFuse BLOCK 0 ᇏ word 6 ֥ᆴ 0x3FF5A018 ᆺ‫؀‬ + EFUSE_BLK0_RDATA5_REG ْ߭ eFuse BLOCK 1 ᇏ word 0 ֥ᆴ 0x3FF5A038 ᆺ‫؀‬ + EFUSE_BLK0_RDATA6_REG ْ߭ eFuse BLOCK 1 ᇏ word 1 ֥ᆴ 0x3FF5A03C ᆺ‫؀‬ + EFUSE_BLK1_RDATA0_REG ْ߭ eFuse BLOCK 1 ᇏ word 2 ֥ᆴ 0x3FF5A040 ᆺ‫؀‬ + EFUSE_BLK1_RDATA1_REG ْ߭ eFuse BLOCK 1 ᇏ word 3 ֥ᆴ 0x3FF5A044 ᆺ‫؀‬ + EFUSE_BLK1_RDATA2_REG ْ߭ eFuse BLOCK 1 ᇏ word 4 ֥ᆴ 0x3FF5A048 ᆺ‫؀‬ + EFUSE_BLK1_RDATA3_REG ْ߭ eFuse BLOCK 1 ᇏ word 5 ֥ᆴ 0x3FF5A04C ᆺ‫؀‬ + EFUSE_BLK1_RDATA4_REG ْ߭ eFuse BLOCK 1 ᇏ word 6 ֥ᆴ 0x3FF5A050 ᆺ‫؀‬ + EFUSE_BLK1_RDATA5_REG ْ߭ eFuse BLOCK 1 ᇏ word 7 ֥ᆴ 0x3FF5A054 ᆺ‫؀‬ + EFUSE_BLK1_RDATA6_REG ْ߭ eFuse BLOCK 2 ᇏ word 0 ֥ᆴ 0x3FF5A058 ᆺ‫؀‬ + EFUSE_BLK1_RDATA7_REG ْ߭ eFuse BLOCK 2 ᇏ word 1 ֥ᆴ 0x3FF5A05C ᆺ‫؀‬ + EFUSE_BLK2_RDATA0_REG ْ߭ eFuse BLOCK 2 ᇏ word 2 ֥ᆴ 0x3FF5A060 ᆺ‫؀‬ + EFUSE_BLK2_RDATA1_REG ْ߭ eFuse BLOCK 2 ᇏ word 3 ֥ᆴ 0x3FF5A064 ᆺ‫؀‬ + EFUSE_BLK2_RDATA2_REG ْ߭ eFuse BLOCK 2 ᇏ word 4 ֥ᆴ 0x3FF5A068 ᆺ‫؀‬ + EFUSE_BLK2_RDATA3_REG ْ߭ eFuse BLOCK 2 ᇏ word 5 ֥ᆴ 0x3FF5A06C ᆺ‫؀‬ + EFUSE_BLK2_RDATA4_REG ْ߭ eFuse BLOCK 2 ᇏ word 6 ֥ᆴ 0x3FF5A070 ᆺ‫؀‬ + EFUSE_BLK2_RDATA5_REG ْ߭ eFuse BLOCK 2 ᇏ word 7 ֥ᆴ 0x3FF5A074 ᆺ‫؀‬ + EFUSE_BLK2_RDATA6_REG ْ߭ eFuse BLOCK 3 ᇏ word 0 ֥ᆴ 0x3FF5A078 ᆺ‫؀‬ + EFUSE_BLK2_RDATA7_REG ْ߭ eFuse BLOCK 3 ᇏ word 1 ֥ᆴ 0x3FF5A07C ᆺ‫؀‬ + EFUSE_BLK3_RDATA0_REG ْ߭ eFuse BLOCK 3 ᇏ word 2 ֥ᆴ 0x3FF5A080 ᆺ‫؀‬ + EFUSE_BLK3_RDATA1_REG ْ߭ eFuse BLOCK 3 ᇏ word 3 ֥ᆴ 0x3FF5A084 ᆺ‫؀‬ + EFUSE_BLK3_RDATA2_REG ْ߭ eFuse BLOCK 3 ᇏ word 4 ֥ᆴ 0x3FF5A088 ᆺ‫؀‬ + EFUSE_BLK3_RDATA3_REG ْ߭ eFuse BLOCK 3 ᇏ word 5 ֥ᆴ 0x3FF5A08C ᆺ‫؀‬ + EFUSE_BLK3_RDATA4_REG ْ߭ eFuse BLOCK 3 ᇏ word 6 ֥ᆴ 0x3FF5A090 ᆺ‫؀‬ + EFUSE_BLK3_RDATA5_REG ْ߭ eFuse BLOCK 3 ᇏ word 7 ֥ᆴ 0x3FF5A094 ᆺ‫؀‬ + EFUSE_BLK3_RDATA6_REG + EFUSE_BLK3_RDATA7_REG എཿ eFuse BLOCK 0 ᇏ word 0 ֥ᆴ 0x3FF5A01c ‫؀‬/ཿ + eFuse എཿ࠷թఖ എཿ eFuse BLOCK 0 ᇏ word 1 ֥ᆴ 0x3FF5A020 ‫؀‬/ཿ + EFUSE_BLK0_WDATA0_REG എཿ eFuse BLOCK 0 ᇏ word 2 ֥ᆴ 0x3FF5A024 ‫؀‬/ཿ + EFUSE_BLK0_WDATA1_REG എཿ eFuse BLOCK 0 ᇏ word 3 ֥ᆴ 0x3FF5A028 ‫؀‬/ཿ + EFUSE_BLK0_WDATA2_REG എཿ eFuse BLOCK 0 ᇏ word 4 ֥ᆴ 0x3FF5A02c ‫؀‬/ཿ + EFUSE_BLK0_WDATA3_REG എཿ eFuse BLOCK 0 ᇏ word 5 ֥ᆴ 0x3FF5A030 ‫؀‬/ཿ + EFUSE_BLK0_WDATA4_REG എཿ eFuse BLOCK 0 ᇏ word 6 ֥ᆴ 0x3FF5A034 ‫؀‬/ཿ + EFUSE_BLK0_WDATA5_REG എཿ eFuse BLOCK 1 ᇏ word 0 ֥ᆴ 0x3FF5A098 ‫؀‬/ཿ + EFUSE_BLK0_WDATA6_REG എཿ eFuse BLOCK 1 ᇏ word 1 ֥ᆴ 0x3FF5A09c ‫؀‬/ཿ + EFUSE_BLK1_WDATA0_REG + EFUSE_BLK1_WDATA1_REG + +ুᶈྐ༏॓࠯ 477 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + +଀ӫ ૭ඍ ֹᆶ ٠໙ +EFUSE_BLK1_WDATA2_REG എཿ eFuse BLOCK 1 ᇏ word 2 ֥ᆴ 0x3FF5A0a0 ‫؀‬/ཿ +EFUSE_BLK1_WDATA3_REG എཿ eFuse BLOCK 1 ᇏ word 3 ֥ᆴ 0x3FF5A0a4 ‫؀‬/ཿ +EFUSE_BLK1_WDATA4_REG എཿ eFuse BLOCK 1 ᇏ word 4 ֥ᆴ 0x3FF5A0a8 ‫؀‬/ཿ +EFUSE_BLK1_WDATA5_REG എཿ eFuse BLOCK 1 ᇏ word 5 ֥ᆴ 0x3FF5A0ac ‫؀‬/ཿ +EFUSE_BLK1_WDATA6_REG എཿ eFuse BLOCK 1 ᇏ word 6 ֥ᆴ 0x3FF5A0b0 ‫؀‬/ཿ +EFUSE_BLK1_WDATA7_REG എཿ eFuse BLOCK 1 ᇏ word 7 ֥ᆴ 0x3FF5A0b4 ‫؀‬/ཿ +EFUSE_BLK2_WDATA0_REG എཿ eFuse BLOCK 2 ᇏ word 0 ֥ᆴ 0x3FF5A0b8 ‫؀‬/ཿ +EFUSE_BLK2_WDATA1_REG എཿ eFuse BLOCK 2 ᇏ word 1 ֥ᆴ 0x3FF5A0bc ‫؀‬/ཿ +EFUSE_BLK2_WDATA2_REG എཿ eFuse BLOCK 2 ᇏ word 2 ֥ᆴ 0x3FF5A0c0 ‫؀‬/ཿ +EFUSE_BLK2_WDATA3_REG എཿ eFuse BLOCK 2 ᇏ word 3 ֥ᆴ 0x3FF5A0c4 ‫؀‬/ཿ +EFUSE_BLK2_WDATA4_REG എཿ eFuse BLOCK 2 ᇏ word 4 ֥ᆴ 0x3FF5A0c8 ‫؀‬/ཿ +EFUSE_BLK2_WDATA5_REG എཿ eFuse BLOCK 2 ᇏ word 5 ֥ᆴ 0x3FF5A0cc ‫؀‬/ཿ +EFUSE_BLK2_WDATA6_REG എཿ eFuse BLOCK 2 ᇏ word 6 ֥ᆴ 0x3FF5A0d0 ‫؀‬/ཿ +EFUSE_BLK2_WDATA7_REG എཿ eFuse BLOCK 2 ᇏ word 7 ֥ᆴ 0x3FF5A0d4 ‫؀‬/ཿ +EFUSE_BLK3_WDATA0_REG എཿ eFuse BLOCK 3 ᇏ word 0 ֥ᆴ 0x3FF5A0d8 ‫؀‬/ཿ +EFUSE_BLK3_WDATA1_REG എཿ eFuse BLOCK 3 ᇏ word 1 ֥ᆴ 0x3FF5A0dc ‫؀‬/ཿ +EFUSE_BLK3_WDATA2_REG എཿ eFuse BLOCK 3 ᇏ word 2 ֥ᆴ 0x3FF5A0e0 ‫؀‬/ཿ +EFUSE_BLK3_WDATA3_REG എཿ eFuse BLOCK 3 ᇏ word 3 ֥ᆴ 0x3FF5A0e4 ‫؀‬/ཿ +EFUSE_BLK3_WDATA4_REG എཿ eFuse BLOCK 3 ᇏ word 4 ֥ᆴ 0x3FF5A0e8 ‫؀‬/ཿ +EFUSE_BLK3_WDATA5_REG എཿ eFuse BLOCK 3 ᇏ word 5 ֥ᆴ 0x3FF5A0ec ‫؀‬/ཿ +EFUSE_BLK3_WDATA6_REG എཿ eFuse BLOCK 3 ᇏ word 6 ֥ᆴ 0x3FF5A0f0 ‫؀‬/ཿ +EFUSE_BLK3_WDATA7_REG എཿ eFuse BLOCK 3 ᇏ word 7 ֥ᆴ 0x3FF5A0f4 ‫؀‬/ཿ +॥ᇅ࠷թఖ +EFUSE_CLK_REG ൈ྽஥ᇂ࠷թఖ 0x3FF5A0F8 ‫؀‬/ཿ +EFUSE_CONF_REG Ҡቔ઒࠷թఖ 0x3FF5A0FC ‫؀‬/ཿ +EFUSE_CMD_REG ‫؀‬/ཿᆷ਷࠷թఖ 0x3FF5A104 ‫؀‬/ཿ +ᇏ؎࠷թఖ +EFUSE_INT_RAW_REG ჰ൓ᇏ؎ሑ෿ 0x3FF5A108 ᆺ‫؀‬ +EFUSE_INT_ST_REG ௠зᇏ؎ሑ෿ 0x3FF5A10C ᆺ‫؀‬ +EFUSE_INT_ENA_REG ᇏ؎൐ି໊ 0x3FF5A110 ‫؀‬/ཿ +EFUSE_INT_CLR_REG ᇏ؎ౢԢ໊ 0x3FF5A114 ᆺཿ +ః෱࠷թఖ +EFUSE_DAC_CONF_REG eFuse ൈ྽஥ᇂ 0x3FF5A118 ‫؀‬/ཿ +EFUSE_DEC_STATUS_REG 3/4 щ઒ٚൔ֥ሑ෿ 0x3FF5A11C ᆺ‫؀‬ + +ুᶈྐ༏॓࠯ 478 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + +20.5 ࠷թఖ + + Register 20.1. EFUSE_BLK0_RDATA0_REG (0x000) + + (reserved) EFUSE_RD_UART_DOEWFNULSOEA_RDD_D_FISLASH_CRYPT_CNEFTUSE_RD_EFUSE_RD_DIS EFUSE_RD_EFUSE_WR_DIS + +31 28 27 26 20 19 16 15 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_RD_UART_DOWNLOAD_DIS uart_download_dis ֥ᆴđࣇؓ ESP32 ECO V3 Ⴕིbčᆺ‫؀‬Ď + EFUSE_RD_FLASH_CRYPT_CNT flash_crypt_cnt ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_EFUSE_RD_DIS efuse_rd_disable ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_EFUSE_WR_DIS efuse_wr_disable ֥ᆴbčᆺ‫؀‬Ď + + Register 20.2. EFUSE_BLK0_RDATA1_REG (0x004) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_BLK0_RDATA1_REG WIFI_MAC_Address ֮ 32 ໊֥ᆴbčᆺ‫؀‬Ď + + Register 20.3. EFUSE_BLK0_RDATA2_REG (0x008) + + (reserved) EFUSE_RD_WIFI_MAC_CRC_HIGH + +31 24 23 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_RD_WIFI_MAC_CRC_HIGH WIFI_MAC_Address ۚ 24 ໊֥ᆴbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 479 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + Register 20.4. EFUSE_BLK0_RDATA3_REG (0x00c) + + (reserved) EFUSE_RD_CHIP_VERE_FPUKSGE_RD_SPI_EPFAUDS_EECF_ORUNDSFEE_IGCF_RUH_HDSIPEED__CF_VRUHEDSIRPE___C_DVRHEISDIRP____CCPVAHKECIRGPH__EDVEISR__BDTIS_APP_CPU + +31 12 11 98 43 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_RD_CHIP_VER_PKG ‫܋‬Ⴕඹ۱ bit ѓ࠺‫ٿ‬ልϱЧđᆃ൞భ೘໊bčᆺ‫؀‬Ď + EFUSE_RD_SPI_PAD_CONFIG_HD SPI_pad_config_hd ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_CHIP_VER_DIS_CACHE ࣌Ⴈ cache ‫ିۿ‬bčᆺ‫؀‬Ď + EFUSE_RD_CHIP_VER_PKG ‫܋‬Ⴕඹ۱ bit ѓ࠺‫ٿ‬ልϱЧđᆃ൞ቋ໊ۚbčᆺ‫؀‬Ď + EFUSE_RD_CHIP_VER_DIS_BT ࣌Ⴈড࿩bčᆺ‫؀‬Ď + EFUSE_RD_CHIP_VER_DIS_APP_CPU ࣌Ⴈ APP CPUbčᆺ‫؀‬Ď + + Register 20.5. EFUSE_BLK0_RDATA4_REG (0x010) + + (reserved) EFUSEEF_RUDSEE_SF_RUDDSIOE__S_FRDODIOR__CXTEPIEDH_SD(reIOserved) ESFUSE_RD_CK8M_FREQ + +31 17 16 15 14 13 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_RD_SDIO_FORCE sdio_force ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_SDIO_TIEH SDIO_TIEH ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_XPD_SDIO XPD_SDIO_REG ֥ᆴbčᆺ‫؀‬Ď + ESFUSE_RD_CK8M_FREQ RTC8M_CLK ௔ੱbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 480 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + Register 20.6. EFUSE_BLK0_RDATA5_REG (0x014) + + EFUSE_RD_FLASH_CREYFUPTS_EC_RODN_FDIGIG_EVFOULS_EL_6RD(_rVesOeLrv_eLdE)VEL_HP_INEVFUSE_RD_SPI_PAD_CONFEIGFU_CSES_0RD_SPI_PAD_CONFEIGFU_DSE_RD_SPI_PAD_CONFEIGFU_QSE_RD_SPI_PAD_CONFIG_CLK + +31 28 27 24 23 22 21 20 19 15 14 10 9 54 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_RD_FLASH_CRYPT_CONFIG flash_crypt_config ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_DIG_VOL_L6 ႨႿթ٢໊֖ 6 ֥ dig regulator ֥‫׈‬࿢ཌྷؓႿ 1.2 V ֥ҵᆴbčᆺ‫؀‬Ď + EFUSE_RD_VOL_LEVEL_HP_INV ႨႿѓ് CPU ஝ 240 MHz ࠇ flash/PSRAM ஝ 80 MHz ླေ֥ + + ‫׈‬࿢໊֖b0x0ğҐႨ໊֖ 7Ġ0x1ğҐႨ໊֖ 6Ġ0x2ğҐႨ໊֖ 5Ġ0x3ğҐႨ໊֖ 4bčᆺ‫؀‬Ď + EFUSE_RD_SPI_PAD_CONFIG_CS0 SPI_pad_config_cs0 ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_SPI_PAD_CONFIG_D SPI_pad_config_d ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_SPI_PAD_CONFIG_Q SPI_pad_config_q ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_SPI_PAD_CONFIG_CLK SPI_pad_config_clk ֥ᆴbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 481 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + Register 20.7. EFUSE_BLK0_RDATA6_REG (0x018) + + (reserved) EFUSEEF_RUDSEE_KF_RUEYDS_EE_SDF_TRUISADSATEE_UBDF_LSRUISEDS_AEE_DBDF_LLRUI_SEDSC_AEE_ADBDF_CLLRUI_SHEDSD_AE(E_EDrBAe_CLLsRB_REeDSEr_YvEN__JPeDAFTCTdAUBOR)GSSNYE_EPD__TREO1DFNU_ECS_EO0_NRSDO_LCEO_DDIENBGU_GS_CDHISEAMBELE + +31 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_RD_KEY_STATUS key_status ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_DISABLE_DL_CACHE download_dis_cache ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_DISABLE_DL_DECRYPT download_dis_decrypt ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_DISABLE_DL_ENCRYPT download_dis_encrypt ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_DISABLE_JTAG JTAG_disable ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_ABS_DONE_1 abstract_done_1 ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_ABS_DONE_0 abstract_done_0 ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_CONSOLE_DEBUG_DISABLE console_debug_disable ֥ᆴbčᆺ‫؀‬Ď + EFUSE_RD_CODING_SCHEME coding_scheme ֥ᆴbčᆺ‫؀‬Ď + + Register 20.8. EFUSE_BLK0_WDATA0_REG (0x01c) + + (reserved) EFUSE_UART_DOWNLEOFUADSE_D_FISLASH_CRYPT_CNT EFUSE_RD_DIS EFUSE_WR_DIS + +31 28 27 26 20 19 16 15 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_UART_DOWNLOAD_DIS എཿ uart_download_dis ֥ᆴđࣇؓ ESP32 ECO V3 Ⴕིbč‫؀‬/ཿĎ + EFUSE_FLASH_CRYPT_CNT എཿ flash_crypt_cnt ֥ᆴbč‫؀‬/ཿĎ + EFUSE_RD_DIS എཿ efuse_rd_disable ֥ᆴbč‫؀‬/ཿĎ + EFUSE_WR_DIS എཿ efuse_wr_disable ֥ᆴbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 482 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + Register 20.9. EFUSE_BLK0_WDATA1_REG (0x020) + +31 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_BLK0_WDATA1_REG എཿ WIFI_MAC_Address ֮ 32 ໊֥ᆴbč‫؀‬/ཿĎ + + Register 20.10. EFUSE_BLK0_WDATA2_REG (0x024) + + (reserved) IFI_MAC_CRC_HIGH + EFUSE_W +31 24 23 + 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_WIFI_MAC_CRC_HIGH എཿ WIFI_MAC_Address ۚ 24 ໊֥ᆴbč‫؀‬/ཿĎ + + Register 20.11. EFUSE_BLK0_WDATA3_REG (0x028) + + (reserved) EFUSE_CHIP_VER_PKEGFUSE_SPI_PADE_FCUOSNEEFF_IGCUHS_HEEIPFD__CUVHSEEEIRPF___CUDVHSEISEIRP____CCPVAHKECIRGPH__EDVEISR__BDTIS_APP_CPU + +31 12 11 98 43 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_CHIP_VER_PKG ‫܋‬Ⴕඹ۱ bit ‫܂‬എཿ‫ٿ‬ልϱЧđᆃ൞భ೘໊bč‫؀‬/ཿĎ + EFUSE_SPI_PAD_CONFIG_HD എཿ SPI_pad_config_hd ֥ᆴbč‫؀‬/ཿĎ + EFUSE_CHIP_VER_DIS_CACHE എཿު࣌Ⴈ cache ‫ିۿ‬bč‫؀‬/ཿĎ + EFUSE_CHIP_VER_PKG ‫܋‬Ⴕඹ۱ bit ‫܂‬എཿ‫ٿ‬ልϱЧđᆃ൞ቋ໊ۚb‫؀‬/ཿĎ + EFUSE_CHIP_VER_DIS_BT എཿު࣌Ⴈড࿩bč‫؀‬/ཿĎ + EFUSE_CHIP_VER_DIS_APP_CPU എཿު࣌Ⴈ APP CPUbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 483 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + Register 20.12. EFUSE_BLK0_WDATA4_REG (0x02c) + + (reserved) EFUSEEF_SUDSIEEOF__SUFDSOIEOR__CXTEPIEDH_SDIO (reserved) ESFUSE_CK8M_FREQ + +31 17 16 15 14 13 87 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_SDIO_FORCE എཿ SDIO_TIEH ֥ᆴbč‫؀‬/ཿĎ + EFUSE_SDIO_TIEH എཿ SDIO_TIEH ֥ᆴbč‫؀‬/ཿĎ + EFUSE_XPD_SDIO എཿ XPD_SDIO_REG ֥ᆴbč‫؀‬/ཿĎ + ESFUSE_CK8M_FREQ എཿ RTC8M_CLK ௔ੱbč‫؀‬/ཿĎ + + Register 20.13. EFUSE_BLK0_WDATA5_REG (0x030) + + EFUSE_FLASH_CRYPTE_FCUOSEN_FDIGIG_VOLE_FLU6SE_VO(Lre_LseErVvEedL_) HP_INV EFUSE_SPI_PAD_CONFIG_CEFSU0SE_SPI_PAD_CONFIG_DEFUSE_SPI_PAD_CONFIG_QEFUSE_SPI_PAD_CONFIG_CLK + +31 28 27 24 23 22 21 20 19 15 14 10 9 54 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_FLASH_CRYPT_CONFIG എཿ flash_crypt_config ֥ᆴbč‫؀‬/ཿĎ + EFUSE_DIG_VOL_L6 എཿ໊֖ 6 ֥ dig regulator ֥‫׈‬࿢ཌྷؓႿ 1.2 V ֥ҵᆴbč‫؀‬/ཿĎ + EFUSE_VOL_LEVEL_HP_INV എཿ CPU ஝ 240 MHz ࠇ flash/PSRAM ஝ 80 MHz ླေ֥‫׈‬࿢໊֖b + + 0x0ğҐႨ໊֖ 7Ġ0x1ğҐႨ໊֖ 6Ġ0x2ğҐႨ໊֖ 5Ġ0x3ğҐႨ໊֖ 4bč‫؀‬/ཿĎ + EFUSE_SPI_PAD_CONFIG_CS0 എཿ SPI_pad_config_cs0 ֥ᆴbč‫؀‬/ཿĎ + EFUSE_SPI_PAD_CONFIG_D എཿ SPI_pad_config_d ֥ᆴbč‫؀‬/ཿĎ + EFUSE_SPI_PAD_CONFIG_Q എཿ SPI_pad_config_q ֥ᆴbč‫؀‬/ཿĎ + EFUSE_SPI_PAD_CONFIG_CLK എཿ SPI_pad_config_clk ֥ᆴbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 484 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + Register 20.14. EFUSE_BLK0_WDATA6_REG (0x034) + + (reserved) EFUSEEF_KUESYEE_F_SDUTISSAEEATF_UBDULSISSEEE_AF_DBDULLIS_SEECE_AF_ADBDUCLLIS_SHEEDE_AEF_EDBAUCLLBS_RES(EE_YreN__JPsDATCTeABORrGvSENYeF_EPdDU_T)OS1EN_ECE_FO0UNSSEO_LCEO_DDIENBGU_GS_CDHISEAMBELE + +31 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_KEY_STATUS എཿ key_status ֥ᆴbč‫؀‬/ཿĎ + EFUSE_DISABLE_DL_CACHE എཿ download_dis_cache ֥ᆴbč‫؀‬/ཿĎ + EFUSE_DISABLE_DL_DECRYPT എཿ download_dis_decrypt ֥ᆴbč‫؀‬/ཿĎ + EFUSE_DISABLE_DL_ENCRYPT എཿ download_dis_encrypt ֥ᆴbč‫؀‬/ཿĎ + EFUSE_DISABLE_JTAG എཿ JTAG_disable ֥ᆴbč‫؀‬/ཿĎ + EFUSE_ABS_DONE_1 എཿ abstract_done_1 ֥ᆴbč‫؀‬/ཿĎ + EFUSE_ABS_DONE_0 എཿ abstract_done_0 ֥ᆴbč‫؀‬/ཿĎ + EFUSE_CONSOLE_DEBUG_DISABLE എཿ console_debug_disable ֥ᆴbč‫؀‬/ཿĎ + EFUSE_CODING_SCHEME എཿ coding_scheme ֥ᆴbč‫؀‬/ཿĎ + + Register 20.15. EFUSE_BLK1_RDATAn_REG (n: 0­7) (0x38+4*n) 0 + +31 Reset + + 0x000000000 + + EFUSE_BLK1_RDATAn_REG BLOCK1 ᇏ word n ֥ᆴbčᆺ‫؀‬Ď + + Register 20.16. EFUSE_BLK2_RDATAn_REG (n: 0­7) (0x58+4*n) 0 + +31 Reset + + 0x000000000 + + EFUSE_BLK2_RDATAn_REG BLOCK2 ᇏ word n ֥ᆴbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 485 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) 0 + + Register 20.17. EFUSE_BLK3_RDATAn_REG (n: 0­7) (0x78+4*n) Reset + + 31 + + 0x000000000 + + EFUSE_BLK3_RDATAn_REG BLOCK3 ᇏ word n ֥ᆴbčᆺ‫؀‬Ď + + Register 20.18. EFUSE_BLK1_WDATAn_REG (n: 0­7) (0x98+4*n) 0 + +31 Reset + + 0x000000000 + + EFUSE_BLK1_WDATAn_REG BLOCK1 ᇏ word n ֥ᆴbč‫؀‬/ཿĎ + + Register 20.19. EFUSE_BLK2_WDATAn_REG (n: 0­7) (0xB8+4*n) 0 + +31 Reset + + 0x000000000 + + EFUSE_BLK2_WDATAn_REG BLOCK2 ᇏ word n ֥ᆴbč‫؀‬/ཿĎ + + Register 20.20. EFUSE_BLK3_WDATAn_REG (n: 0­7) (0xD8+4*n) 0 + +31 Reset + + 0x000000000 + + EFUSE_BLK3_WDATAn_REG BLOCK3 ᇏ word n ֥ᆴbč‫؀‬/ཿĎ + + Register 20.21. EFUSE_CLK_REG (0x0f8) + + (reserved) EFUSE_CLK_SEL1 EFUSE_CLK_SEL0 + +31 16 15 87 0 + +0000000000000000 0x040 0x052 Reset + + EFUSE_CLK_SEL1 eFuse ൈᇒ஥ᇂሳ‫؍‬bč‫؀‬/ཿĎ + EFUSE_CLK_SEL0 eFuse ൈᇒ஥ᇂሳ‫؍‬bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 486 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + Register 20.22. EFUSE_CONF_REG (0x0fc) + + (reserved) EFUSE_OP_CODE + 0x00000 +31 16 15 0 + +0000000000000000 Reset + + EFUSE_OP_CODE eFuse Ҡቔ઒࠷թఖbč‫؀‬/ཿĎ + + Register 20.23. EFUSE_CMD_REG (0x104) + + (reserved) EFUSEEF_PUGSEM__RCEMADD_CMD + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_PGM_CMD ࡼՎ໊ᇂ 1 ၛष൓എཿҠቔĠഎཿປӮު߫‫ ູگ‬0bč‫؀‬/ཿĎ + EFUSE_READ_CMD ࡼՎ໊ᇂ 1 ၛष൓‫؀‬౼ҠቔĠ‫؀‬౼ປӮު߫‫ ູگ‬0bč‫؀‬/ཿĎ + + Register 20.24. EFUSE_INT_RAW_REG (0x108) + + (reserved) EFUSEEF_PUGSEM__RDEOANDE__DINOTN_ER_AINWT_RAW + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_PGM_DONE_INT_RAW EFUSE_PGM_DONE_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + EFUSE_READ_DONE_INT_RAW EFUSE_READ_DONE_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 487 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + + Register 20.25. EFUSE_INT_ST_REG (0x10c) + + (reserved) EFUSEEF_PUGSEM__RDEOANDE__DINOTN_ES_TINT_ST + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_PGM_DONE_INT_ST EFUSE_PGM_DONE_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + EFUSE_READ_DONE_INT_ST EFUSE_READ_DONE_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + + Register 20.26. EFUSE_INT_ENA_REG (0x110) + + (reserved) EFUSEEF_PUGSEM__RDEOANDE__DINOTN_EE_NINAT_ENA + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_PGM_DONE_INT_ENA EFUSE_PGM_DONE_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + EFUSE_READ_DONE_INT_ENA EFUSE_READ_DONE_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬/ཿĎ + + Register 20.27. EFUSE_INT_CLR_REG (0x114) + + (reserved) EFUSEEF_PUGSEM__RDEOANDE__DINOTN_EC_LINRT_CLR + +31 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_PGM_DONE_INT_CLR ࡼՎ໊ᇂ 1 ၛౢԢ EFUSE_PGM_DONE_INT ᇏ؎bčᆺཿĎ + EFUSE_READ_DONE_INT_CLR ࡼՎ໊ᇂ 1 ၛౢԢ EFUSE_READ_DONE_INT ᇏ؎bčᆺཿĎ + +ুᶈྐ༏॓࠯ 488 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 20 eFuse ॥ᇅఖ (eFuse) + Register 20.28. EFUSE_DAC_CONF_REG (0x118) + + (reserved) EFUSE_DAC_CLK_DIV + +31 87 0 + +000000000000000000000000 40 Reset + + EFUSE_DAC_CLK_DIV eFuse ൈ྽஥ᇂ࠷թఖbč‫؀‬/ཿĎ + + Register 20.29. EFUSE_DEC_STATUS_REG (0x11c) + + (reserved) EFUSE_DEC_WARNINGS + +31 12 11 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + EFUSE_DEC_WARNINGS ೏Վ࠷թఖ֥ଖ໊ᇂ 1đᄵࢳ઒ 3/4 щ઒ٚൔൈ۷ᆞଖུհ༂bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 489 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +21 චཌచӚࢤ१ (TWAI) + +21.1 ‫ۀ‬ඍ + +චཌచӚࢤ१ (Two-wire Automotive Interface, TWAI ®) ླྀၰ൞၂ᇕ‫؟‬ᇶࠏa‫؟‬Ѭ֥๙ྐླྀၰđऎႵ࡟ҩհ༂a‫ؿ‬ +ෂհ༂ྐ‫ݼ‬ၛࠣଽᇂБ໓Ⴊ༵ᇘҊ֩‫ିۿ‬bTWAI ླྀၰൡႨႿచӚ‫۽ބ‬ြႋႨčॖҕ࡮ TWAI ླྀၰ૭ඍĎb +ESP32 Ї‫ݣ‬၂۱ TWAI ॥ᇅఖđॖ๙‫ݖ‬ຓ҆൬‫ؿ‬ఖ৵ࢤ֞ TWAI ሹཌbTWAI ॥ᇅఖЇ‫ݣ‬၂༢ਙ༵ࣉ֥‫ିۿ‬đႨ +๯ܼٗđॖႨႿೂచӚӁ௖a‫۽‬ြሱ‫߄׮‬॥ᇅaੌდሱ‫֩߄׮‬b + +21.2 ᇶေหྟ + +ESP32 TWAI ॥ᇅఖऎႵၛ༯หྟğ + • ࡙ಸ ISO 11898-1 ླྀၰčCAN ܿٓ 2.0Ď + • ᆦӻѓሙ۬ൔč11-bit ѓ്‫ژ‬Ď‫ބ‬ঔᅚ۬ൔč29-bit ѓ്‫ژ‬Ď + • ᆦӻ 25 Kbit/s ~ 1 Mbit/s ໊෎ੱ + • ᆦӻ‫؟‬ᇕҠቔଆൔ + – ᆞӈଆൔ + – ᆺ๐ଆൔč҂႕ཙሹཌĎ + – ሱҩଆൔč‫ؿ‬ෂඔऌൈ҂ླႋճĎ + • 64-byte ࢤ൬ FIFO + • ห൹‫ؿ‬ෂ + – ֆՑ‫ؿ‬ෂč‫ؿ‬ളհ༂ൈ҂߶ሱ‫׮‬ᇗྍ‫ؿ‬ෂĎ + – ሱ‫ؿ‬ሱ൬čTWAI ॥ᇅఖ๝ൈ‫ؿ‬ෂ‫ࢤބ‬൬Б໓Ď + • ࢤ൬ੲѯఖčᆦӻֆੲѯఖ‫ބ‬චੲѯఖଆൔĎ + • հ༂࡟ҩაԩ৘ + – հ༂࠹ඔ + – հ༂Бࣞཋᇅॖ஥ᇂ + – հ༂ս઒ѽሚ + – ᇘҊ‫ש‬ാѽሚ + +21.3 ‫ླྀྟିۿ‬ၰ + +21.3.1 TWAI ྟି + +TWAI ླྀၰ৵ࢤሹཌຩ઎ᇏ֥ਆ۱ࠇ‫؟‬۱ࢫׄđѩᄍྸ۲ࢫׄၛ࿼Ӿཋᇅ֥ྙൔࣉྛБ໓ࢌ޺bTWAI ሹཌऎႵ +ၛ༯ྟିğ +ֆ๙֡๙ྐა҂݂ਬщ઒ğ TWAI ሹཌႮӵᄛሢ໊֥ֆ๙֡ቆӮđၹՎູ϶ච‫۽‬๙ྐb๝҄‫ט‬ᆜ္ᄝֆ๙֡ᇏ +ࣉྛđၹՎ҂ླః෰๙֡čೂൈᇒ๙֡‫ބ‬൐ି๙֡ĎbTWAI ഈБ໓໊֥ੀҐႨ҂݂ਬщ઒ (NRZ) ٚൔb + +ুᶈྐ༏॓࠯ 490 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +໊ᆴğֆ๙֡ॖԩႿཁྟሑ෿ࠇႅྟሑ෿đཁྟሑ෿֥આࠠᆴູ 0đႅྟሑ෿֥આࠠᆴູ 1b‫ؿ‬ෂཁྟሑ෿ඔऌ +֥ࢫׄሹ൞б‫ؿ‬ෂႅྟሑ෿ඔऌ֥ࢫׄႪ༵ࠩۚbሹཌഈ֥ః෰໾৘‫ିۿ‬čೂđҵ‫׈ٳ‬௜ĎႮః۲ሱႋႨൌ +གྷb +໊แԉğ TWAI Б໓֥ଖུთၘࣜ‫໊ݖ‬แԉbૄ‫ؿ‬ෂଖ۱ཌྷ๝ᆴčೂཁྟඔᆴࠇႅྟඔᆴĎ֥৵࿃໴۱໊ުđ +ླሱ‫׮‬Ҭೆ၂۱޺Ҁ໊b๝৘đࢤ൬֞ 5 ۱৵࿃໊֥ࢤ൬ఖႋࡼ༯၂۱໊൪ູแԉ໊b໊แԉႋႨႿၛ༯თğ +SOFaᇘҊთa॥ᇅთaඔऌთ‫ ބ‬CRC ྽ਙčॖҕ࡮ֻ 21.3.2 ᅣĎb +‫؟‬Ѭğ֒۲ࢫׄ৵ࢤ֞๝۱ሹཌഈൈđᆃུࢫׄࡼࢤ൬ཌྷ๝໊֥b۲ࢫׄഈ֥ඔऌࡼЌӻ၂ᇁđԢ٤‫ؿ‬ളሹཌ +հ༂čॖҕ࡮ֻ 21.3.3 ᅣĎb +‫؟‬ᇶࠏğ಩ၩࢫׄ‫׻‬ॖ‫ؿ‬ఏඔऌԮൻbೂ‫֒ݔ‬భၘႵᆞᄝࣉྛ֥ඔऌԮൻđᄵࢫׄࡼ֩ր֒భԮൻࢲඏުᄜ‫ؿ‬ +ఏఃඔऌԮൻb +Б໓Ⴊ༵ࠩაᇘҊğ೏ਆ۱ࠇ‫؟‬۱ࢫׄ๝ൈ‫ؿ‬ఏඔऌԮൻđᄵ TWAI ླྀၰࡼಒЌఃᇏ၂۱ࢫׄࠆ֤ሹཌ֥Ⴊ༵ +ᇘҊಃb۲ࢫׄ෮‫ؿ‬ෂБ໓֥ᇘҊთथ‫ק‬ଧ۱ࢫׄॖၛࠆ֤Ⴊ༵ᇘҊb +հ༂࡟ҩა๙Бğ۲ࢫׄࡼࠒࠞ࡟ҩሹཌഈ֥հ༂đѩ๙‫ؿݖ‬ෂհ༂ᆠট๙Б࡟ҩ֥֞հ༂b +‫ܣ‬ᅰཋᇅğ೏၂ቆհ༂࠹ඔ၇ऌܿ‫ק‬ᄹࡆ/ࡨഒൈđ۲ࢫׄࡼົ޹‫ھ‬ቆհ༂࠹ඔb֒հ༂࠹ඔӑ‫ݖ‬၂‫ק‬ᚐᆴൈđ +ؓႋࢫׄࡼሱ‫ܱ׮‬оၛ๼ԛຩ઎b +ॖ஥ᇂ໊෎ੱğֆ۱ TWAI ሹཌ໊֥෎ੱ൞ॖ஥ᇂ֥b֌൞đ๝۱ሹཌᇏ֥෮Ⴕࢫׄྶၛཌྷ๝໊෎ੱ‫۽‬ +ቔb +‫ؿ‬ෂఖაࢤ൬ఖğ҂ં‫ޅ‬ൈđ಩ၩ TWAI ࢫׄ‫׻‬ॖቔູ‫ؿ‬ෂఖ‫ࢤބ‬൬ఖb + + • ӁളБ໓֥ࢫູׄ‫ؿ‬ෂఖb౏‫ࡼׄࢫھ‬၂ᆰቔູ‫ؿ‬ෂఖđᆰ֞ሹཌॢ༽ࠇ‫ׄࢫھ‬ാಀᇘҊb౨ᇿၩđໃ‫ש‬ + ാᇘҊ֥‫؟‬۱ࢫׄ‫׻‬ॖቔູ‫ؿ‬ෂఖb + + • ෮Ⴕ٤‫ؿ‬ෂఖ֥ࢫׄ‫ࡼ׻‬ቔູࢤ൬ఖb + +21.3.2 TWAI Б໓ + +TWAI ࢫׄ൐ႨБ໓‫ؿ‬ෂඔऌđѩᄝࡓҩ֞ሹཌഈթᄝհ༂ൈཟః෰ࢫׄ‫ؿ‬ෂհ༂ྐ‫ݼ‬bБ໓‫ູٳ‬҂๝֥ᆠো +྘đଖུᆠো྘ࡼऎႵ҂๝֥ᆠ۬ൔb +TWAI ླྀၰႵၛ༯ᆠো྘ğ + + • ඔऌᆠ + • ჹӱᆠ + • հ༂ᆠ + • ‫ݖ‬ᄛᆠ + • ᆠࡗए +TWAI ླྀၰႵၛ༯ᆠ۬ൔğ + • ѓሙ۬ൔ (SFF) Ⴎ 11-bit ѓ്‫ژ‬ቆӮ + • ঔᅚ۬ൔ (EFF) Ⴎ 29-bit ѓ്‫ژ‬ቆӮ + +ুᶈྐ༏॓࠯ 491 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +21.3.2.1 ඔऌᆠ‫ބ‬ჹӱᆠ + +ࢫׄ൐Ⴈඔऌᆠཟః෰ࢫׄ‫ؿ‬ෂඔऌđॖ‫ڵ‬ᄛ 0 ~ 8 ሳࢫඔऌbࢫׄ൐Ⴈჹӱᆠཟః෰ࢫׄ౨౰ऎႵཌྷ๝ѓ് +‫֥ژ‬ඔऌᆠđၹՎჹӱᆠᇏ҂Ї‫ݣ‬಩‫ޅ‬ඔऌሳࢫb֌൞đඔऌᆠ‫ބ‬ჹӱᆠᇏЇ‫؟ྸݣ‬ཌྷ๝თb༯๭ 21-1 ෮ൕູ +҂๝ᆠো྘‫ބ‬҂๝ᆠ۬ൔᇏЇ‫֥ݣ‬თ‫ބ‬ሰთb + + ๭ 21­1. ඔऌᆠ‫ބ‬ჹӱᆠᇏ໊֥თ + +ᇘҊთ +֒ਆ۱ࠇ‫؟‬۱ࢫׄ๝ൈ‫ؿ‬ෂඔऌᆠ‫ބ‬ჹӱᆠൈđࡼ۴ऌᇘҊთ໊֥ྐ༏টथ‫ק‬ሹཌഈࠆ֤Ⴊ༵ᇘҊ֥ࢫׄbᄝ +ᇘҊთቔႨൈđೂ‫ݔ‬၂۱ࢫׄᄝ‫ؿ‬ෂႅྟ໊֥๝ൈ࡟ҩ֞ਔ၂۱ཁྟ໊đᆃіൕႵః෰ࢫׄႪ༵Ⴟਔᆃ۱ႅྟ +໊bପહđᆃ۱‫ؿ‬ෂႅྟ໊֥ࢫׄၘ‫ש‬ാሹཌᇘҊđႋ৫ࠧሇູࢤ൬ఖb + +ᇘҊთᇶေႮᆠѓ്‫ژ‬ቆӮb۴ऌཁྟ໊սі֥આࠠᆴູ 0đႅྟ໊սі֥આࠠᆴູ 1đႵၛ༯ܿੰ: + + • ID ᆴቋཬ֥ᆠࡼሹ൞ࠆ֤ᇘҊb + + • ೂ‫ ݔ‬ID ‫۬ބ‬ൔཌྷ๝đႮႿඔऌᆠ֥ RTR ູ໊ཁྟ໊đඔऌᆠࡼႪ༵Ⴟჹӱᆠb + + • ೂ‫ ݔ‬ID ֥భ 11 ໊ཌྷ๝đႮႿঔᅚᆠ֥ SRR ໊൞ႅྟđၹ‫ط‬ѓሙ۬ൔᆠࡼሹႪ༵Ⴟঔᅚ۬ൔᆠb + +॥ᇅთ +॥ᇅთᇶေႮඔऌӉ؇ս઒ (DLC) ቆӮđDLC іൕ၂۱ඔऌᆠᇏ֥‫ڵ‬ᄛ֥ඔऌሳࢫඔਈđࠇ၂۱ჹӱᆠ౨౰֥ +ඔऌሳࢫඔਈbDLC Ⴊ༵‫ؿ‬ෂቋۚႵ໊ིb + +ඔऌთ +ඔऌთᇏЇ‫ݣ‬၂۱ඔऌᆠᆇൌ‫ڵ‬ᄛ֥ඔऌሳࢫbჹӱᆠᇏ҂Ї‫ݣ‬ඔऌთb + +ুᶈྐ༏॓࠯ 492 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +CRC თ +CRC თᇶေႮ CRC ྽ਙቆӮbCRC ྽ਙ൞၂۱ 15-bit ֥࿖ߌ಺Ⴥ཮ဒщ઒đ۴ऌඔऌᆠࠇჹӱᆠᇏ֥ໃแԉ +ଽಸčՖ SOF ֞ඔऌთଌແ֥෮ႵଽಸĎᇏ࠹ෘ‫ط‬টb + +ಒಪთ +ಒಪ (ACK) თႮಒಪҢ‫ބ‬ಒಪ‫ژࢸٳ‬ቆӮđᇶေ‫ູିۿ‬ğࢤ൬ఖཟ‫ؿ‬ෂఖБۡၘᆞಒࢤ൬֞ႵིБ໓b + + і 21­1. SFF ‫ ބ‬EFF ᇏ֥ඔऌᆠ‫ބ‬ჹӱᆠ + +ඔऌ/ჹӱᆠ ૭ඍ +SOF ᆠఏ൓ (SOF) ൞၂۱ႨႿ๝҄ሹཌഈࢫ֥ׄֆ۱ཁྟ໊b +Base ID ࠎѓ്‫( ژ‬ID.28 ~ ID.18) ൞ SFF ֥ 11-bit ѓ്‫ژ‬đࠇᆀ൞ EFF ᇏ 29-bit ѓ്‫ژ‬ + ֥భ 11-bitb +RTR ჹӱ‫ؿ‬ෂ౨౰໊ (RTR) ཁൕ֒భБ໓൞ඔऌᆠčཁྟĎߎ൞ჹӱᆠčႅྟĎbᆃ + ၩ໅ሢđ֒ଖ۱ඔऌᆠ‫ބ‬၂۱ჹӱᆠႵཌྷ๝ѓ്‫ژ‬ൈđඔऌᆠ൓ᇔႪ༵Ⴟჹӱ +SRR ᆠᇘҊb +IDE ᄝ EFF ᇏ‫ؿ‬ෂูսჹӱ౨౰໊ (SRR)đၛูս SFF ᇏཌྷ๝໊ᇂ֥ RTR ໊b + ѓ്‫ژ‬ঔᅚ໊ (IED) ཁൕ֒భБ໓൞ SFF čཁྟĎߎ൞ EFFčႅྟĎbᆃၩ໅ሢđ +Extd ID ֒ଖ SFF ᆠ‫ ބ‬EFF ᆠႵཌྷ๝ࠎѓ്‫ژ‬ൈđSFF ᆠࡼ൓ᇔႪ༵Ⴟ EFF ᆠᇘҊb +r1 ঔᅚѓ്‫( ژ‬ID.17 ~ ID.0) ൞ EFF ᇏ 29-bit ѓ്‫֥ژ‬ഺჅ 18-bitb +r0 r1čЌ਽໊ 1Ď൓ᇔ൞ཁྟ໊b +DLC r0čЌ਽໊ 0Ď൓ᇔ൞ཁྟ໊b + ඔऌӉ؇ս઒ (DLC) ູ 4-bitsđ౏ႋЇ‫ ݣ‬0 ~ 8 ᇏ಩၂ඔᆴbඔऌᆠ൐Ⴈ DLC +ඔऌሳࢫ іൕሱദЇ‫֥ݣ‬ඔऌሳࢫඔਈbჹӱᆠ൐Ⴈ DLC іൕՖః෰ࢫׄ౨౰֥ඔऌሳ + ࢫඔਈb +CRC ྽ਙ іൕඔऌᆠ֥ඔऌ‫ڵ‬ᄛਈb‫ھ‬ሳࢫඔਈႋა DLC ֥ᆴ௄஥b൮༵‫ؿ‬ෂඔऌሳࢫ +CRC ‫ژࢸٳ‬ 0đ۲ඔऌሳࢫႪ༵‫ؿ‬ෂቋۚႵ໊ིb +ಒಪҢ CRC ྽ਙ൞၂۱ 15-bit ֥࿖ߌ಺Ⴥ཮ဒщ઒b + CRC ‫ژࢸٳ‬൞቎࿖ CRC ྽ਙ֥ֆ၂ႅྟ໊b +ಒಪ‫ژࢸٳ‬ ಒಪҢႨႿࢤ൬ఖࢫׄđіൕ൞‫ၘڎ‬Ӯ‫ࢤۿ‬൬ඔऌᆠࠇჹӱᆠb‫ؿ‬ෂఖࢫׄࡼ +EOF ᄝಒಪҢᇏ‫ؿ‬ෂ၂۱ႅྟ໊đೂ‫ࢤݔ‬൬֥֞ᆠીႵհ༂đᄵࢤ൬ఖࢫׄႋႨ၂ + ۱ཁྟู໊սಒಪҢb + ಒಪ‫ژࢸٳ‬൞၂۱ֆ၂֥ႅྟ໊b + ᆠࢲඏ (EOF) ѓᆽሢඔऌᆠࠇჹӱᆠ֥ࢲඏđႮ௾۱ႅྟ໊ቆӮb + +ুᶈྐ༏॓࠯ 493 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +21.3.2.2 հ༂ᆠ‫ݖބ‬ᄛᆠ + +հ༂ᆠ + +֒ଖࢫׄ࡟ҩ֞ሹཌհ༂ൈđࡼ‫ؿ‬ෂ၂۱հ༂ᆠbհ༂ᆠႮ၂۱ห൹֥հ༂ѓᆽ‫ܒ‬Ӯđ‫ھ‬ѓᆽႮଖཌྷ๝ᆴ֥ੂ +۱৵࿃໊ቆӮđၹ‫ّິط‬ਔ໊แԉ֥ܿᄵb෮ၛđ֒ଖࢫׄ࡟ҩ֞ሹཌհ༂ѩ‫ؿ‬ෂհ༂ᆠൈđఃჅࢫ္ׄࡼཌྷ +ႋֹ࡟ҩ֞၂۱แԉհ༂ѩ۲ሱ‫ؿ‬ෂհ༂ᆠb္ࣼ൞ඪđ֒‫ؿ‬ളሹཌհ༂ൈđ๙‫ݖ‬ഈඍ‫ݖ‬ӱॖࡼ‫ھ‬Б໓Ԯ‫־‬ᇀ +ሹཌഈ֥෮Ⴕࢫׄb + +֒ଖࢫׄ࡟ҩ֞ሹཌհ༂ൈđ‫ࡼׄࢫھ‬Ⴟ༯၂۱໊‫ؿ‬ෂհ༂ᆠbห২ğೂ‫ݔ‬ሹཌհ༂ো྘ູ CRC հ༂đପહհ +༂ᆠࡼՖಒಪ‫֥ژࢸٳ‬༯၂۱໊ष൓čॖҕ࡮ֻ 21.3.3 ᅣĎb༯๭ 21-2 ෮ൕູ၂۱հ༂ᆠ෮Ї‫֥ݣ‬҂๝ +თğ + + ๭ 21­2. հ༂ᆠᇏ໊֥თ + +հ༂ᆠ і 21­2. հ༂ᆠ +հ༂ѓᆽ + ૭ඍ +հ༂ѓᆽ‫ࡆן‬ հ༂ѓᆽЇওਆᇕྙൔ: ᇶ‫׮‬հ༂ѓᆽ‫ބ‬Ф‫׮‬հ༂ѓᆽđᇶ‫׮‬հ༂ѓᆽႮ 6 ۱ཁྟ໊ + ቆӮđФ‫׮‬հ༂ѓᆽႮ 6 ۱ႅྟ໊ቆӮčФః෰ࢫ֥ׄཁྟ໊Ⴊ༵ᇘҊൈԢຓĎbᇶ +հ༂‫ژࢸٳ‬ ‫׮‬հ༂ࢫׄ‫ؿ‬ෂᇶ‫׮‬հ༂ѓᆽđФ‫׮‬հ༂ࢫׄ‫ؿ‬ෂФ‫׮‬հ༂ѓᆽb + հ༂ѓᆽ‫ࡆן‬თ֥ᇶေଢ֥൞ᄍྸሹཌഈ֥ః෰ࢫׄ‫ؿ‬ෂ۲ሱ֥ᇶ‫׮‬հ༂ѓᆽb‫ࡆן‬ + თ֥ٓຶॖၛ൞ 0 ~ 6 ໊đᄝ࡟ҩֻ֞၂۱ႅྟ໊ൈࢲඏčೂ࡟ҩ֞‫ژࢸٳ‬ഈֻ֥၂ + ۱໊ൈĎb + ‫ژࢸٳ‬თѓᆽሢհ༂/‫ݖ‬ᄛᆠࢲඏđႮ 8 ۱ႅྟ໊‫ܒ‬Ӯb + +‫ݖ‬ᄛᆠ +‫ݖ‬ᄛᆠაЇ‫ݣ‬ᇶ‫׮‬հ༂ѓᆽ֥հ༂ᆠႵሢཌྷ๝໊֥თb‫ؽ‬ᆀᇶေ౵љᄝႿԨ‫ؿؿ‬ෂ‫ݖ‬ᄛᆠ่֥ࡱb༯๭ 21-3 +෮ൕູ‫ݖ‬ᄛᆠᇏЇ‫໊֥ݣ‬თğ + + ๭ 21­3. ‫ݖ‬ᄛᆠᇏ໊֥თ + +ুᶈྐ༏॓࠯ 494 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +‫ݖ‬ᄛᆠ і 21­3. ‫ݖ‬ᄛᆠ +‫ݖ‬ᄛѓᆽ +‫ݖ‬ᄛѓᆽ‫ࡆן‬ ૭ඍ +‫ݖ‬ᄛ‫ژࢸٳ‬ Ⴎ 6 ۱ཁྟ໊‫ܒ‬Ӯbაᇶ‫׮‬հ༂ѓᆽཌྷ๝b + ᄍྸః෰ࢫׄ‫ؿ‬ෂ‫ݖ‬ᄛѓᆽ֥‫ࡆן‬đაհ༂ѓᆽ‫ࡆן‬ཌྷරb + Ⴎ 8 ۱ႅྟ໊‫ܒ‬Ӯbაհ༂‫ژࢸٳ‬ཌྷ๝b + + ༯ਙ౦ঃࡼԨ‫ؿؿ‬ෂ‫ݖ‬ᄛᆠğ + 1. ࢤ൬ఖଽ҆ေ౰࿼Ӿ‫ؿ‬ෂ༯၂۱ඔऌᆠࠇჹӱᆠb + 2. ᄝࡗཱུთު֥൮۱‫ؽֻބ‬۱໊ഈ࡟ҩ֞ཁྟ໊b + 3. ೂ‫ݔ‬ᄝհ༂‫ֻ֥ژࢸٳ‬ϖ۱čቋު၂۱Ď໊ഈ࡟ҩ֞ཁྟ໊b౨ᇿၩđᄝᆃᇕ౦ঃ༯ TEC ‫ ބ‬REC ֥ᆴࡼ + ҂߶ᄹࡆčॖҕ࡮ֻ 21.3.3 ᅣĎb + + ႮႿഈඍ౦ঃ‫ؿ‬ෂ‫ݖ‬ᄛᆠൈđྶડቀၛ༯ܿ‫ק‬ğ + • ֻ 1 ่౦ঃ༯‫ؿ‬ෂ֥‫ݖ‬ᄛᆠᆺିՖࡗཱུთުֻ֥၂۱໊ष൓b + • ֻ 2a3 ่౦ঃ༯‫ؿ‬ෂ֥‫ݖ‬ᄛᆠྶՖ࡟ҩ֞ཁྟ໊֥ު၂۱໊ष൓b + • ေ࿼Ӿ‫ؿ‬ෂ༯၂۱ඔऌᆠࠇჹӱᆠđቋ‫؟‬ॖളӮਆ۱‫ݖ‬ᄛᆠb + + 21.3.2.3 ᆠࡗए + + ᆠࡗएԉ֒۲ᆠᆭࡗ֥‫ژۯٳ‬bඔऌᆠ‫ބ‬ჹӱᆠсྶაభ၂ᆠႨ၂۱ᆠࡗए‫ۯٳ‬षđ҂ંభ૫֥ᆠ൞‫ޅ‬ো྘ +čඔऌᆠaჹӱᆠaհ༂ᆠa‫ݖ‬ᄛᆠĎb֌൞đհ༂ᆠ‫ݖބ‬ᄛᆠᄵ໭ླაభ၂۱ᆠ‫ۯٳ‬षb + + ༯๭ 21-4 ෮ൕູᆠࡗएᇏЇ‫֥ݣ‬თğ + +ᆠࡗए ๭ 21­4. ᆠࡗएᇏ֥თ +ࡗཱུთ +‫ܫ‬ఏԮෂ і 21­4. ᆠࡗए + +ሹཌॢ༽ ૭ඍ + ࡗཱུთႮ 3 ۱ႅྟ໊‫ܒ‬Ӯb + Ф‫׮‬հ༂ࢫׄ‫ؿ‬ෂБ໓ުđࢫׄᇏྶЇ‫ݣ‬၂۱‫ܫ‬ఏԮෂთđႮ 8 ۱ႅྟ໊‫ܒ‬Ӯbᇶ‫׮‬ + հ༂ࢫׄᇏ҂‫ݣ‬ᆃ۱თb + ሹཌॢ༽თӉ؇಩ၩb‫ؿ‬ෂ SOF ൈđሹཌॢ༽ࢲඏb೏ࢫׄᇏႵ‫ܫ‬ఏԮෂđᄵ SOF + ႋᄝࡗཱུთުֻ֥၂໊‫ؿ‬ෂb + +ুᶈྐ༏॓࠯ 495 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +21.3.3 TWAI հ༂ +21.3.3.1 հ༂ো྘ + +TWAI ᇏ֥ሹཌհ༂Їওၛ༯ো྘ğ +໊հ༂ +֒ࢫׄ‫ؿ‬ෂ၂۱໊ᆴčཁྟ໊ࠇႅྟ໊Ď֌࡟ҩ֞ཌྷّ໊֥ൈčೂđ‫ؿ‬ෂཁྟ໊ൈ࡟ҩ֞ਔႅྟ໊Ďđࣼ߶‫ؿ‬ള +໊հ༂b֌൞đೂ‫ؿݔ‬ෂ໊֥൞ႅྟ໊đ౏໊ႿᇘҊთࠇಒಪҢࠇФ‫׮‬հ༂ѓᆽᇏđପહՎൈ࡟ҩ֞ཁྟ໊֥ +߅္҂߶ಪ‫ູ໊ק‬հ༂b +แԉհ༂ +֒࡟ҩ֞ཌྷ๝ᆴ֥ 6 ۱৵࿃໊ൈčິّ໊แԉ֥щ઒ܿᄵĎđ‫ؿ‬ളแԉհ༂b +CRC հ༂ +ඔऌᆠ‫ބ‬ჹӱᆠ֥ࢤ൬ఖࡼ۴ऌࢤ൬໊֥֞࠹ෘ CRC ᆴb֒ࢤ൬ఖ࠹ෘ֥ᆴაࢤ൬֥֞ඔऌᆠ‫ބ‬ჹӱᆠᇏ֥ +CRC ྽ਙ҂௄஥ൈđ߶‫ؿ‬ള CRC հ༂b +۬ൔհ༂ +֒ଖ۱Б໓ᇏ֥‫۬קܥ‬ൔ໊ᇏЇ‫ݣ‬٤‫໊م‬ൈđॖ࡟ҩ֞۬ൔհ༂bбೂđr1 ‫ ބ‬r0 თсྶ‫ູקܥ‬ཁྟb +ಒಪհ༂ +֒‫ؿ‬ෂఖ໭‫م‬ᄝಒಪҢᇏ࡟ҩ֞ཁྟ໊ൈđࡼ‫ؿ‬ളಒಪհ༂b + +21.3.3.2 հ༂ሑ෿ + +TWAI ๙‫ૄݖ‬۱ࢫׄົ޹ਆ۱հ༂࠹ඔটൌགྷ‫ܣ‬ᅰࢸ‫ק‬đ࠹ඔඔᆴथ‫ק‬հ༂ሑ෿bᆃਆ۱հ༂࠹ඔ‫ٳ‬љູğ‫ؿ‬ෂ +հ༂࠹ඔ (TEC) ‫ࢤބ‬൬հ༂࠹ඔ (REC)bTWAI Ї‫ݣ‬ၛ༯հ༂ሑ෿b +ᇶ‫׮‬հ༂ +ᇶ‫׮‬հ༂ࢫׄॖҕა֞ሹཌࢌ޺ᇏđ౏ᄝ࡟ҩ֞հ༂ൈॖၛ‫ؿ‬ෂᇶ‫׮‬հ༂ѓᆽb +Ф‫׮‬հ༂ +Ф‫׮‬հ༂ࢫׄॖҕა֞ሹཌࢌ޺ᇏđ֌ᄝ࡟ҩ֞հ༂ൈᆺି‫ؿ‬ෂ၂ՑФ‫׮‬հ༂ѓᆽbФ‫׮‬հ༂ࢫׄ‫ؿ‬ෂඔऌᆠ +ࠇჹӱᆠުđྶᄝު࿃֥ᆠࡗएᇏഡᇂ‫ܫ‬ఏԮෂთb +৖ཌ +࣌ᆸ৖ཌࢫׄၛ಩ၩٚൔ‫ۄ‬ಠሹཌčೂđ҂ᄍྸఃࣉྛඔऌԮൻĎb + +21.3.3.3 հ༂࠹ඔ + +TEC ‫ ބ‬REC ۴ऌၛ༯ܿᄵ‫־‬ᄹ/‫ࡨ־‬b౨ᇿၩđ၂่Б໓ԮൻᇏॖႋႨ‫؟‬۱ܿᄵb + + 1. ֒ࢤ൬ఖ࡟ҩ֞հ༂ൈđREC ඔᆴࡼᄹࡆ 1b֒࡟ҩ֥֞հ༂ູ‫ؿ‬ෂᇶ‫׮‬հ༂ѓᆽࠇ‫ݖ‬ᄛѓᆽ௹ࡗ໊֥ + հ༂Ԣຓb + + 2. ‫ؿ‬ෂհ༂ѓᆽުđ֒ࢤ൬ఖֻ၂۱࡟ҩ໊֥֞൞ཁྟ໊ൈđREC ඔᆴࡼᄹࡆ 8b + + 3. ֒‫ؿ‬ෂఖ‫ؿ‬ෂհ༂ѓᆽൈđTEC ඔᆴᄹࡆ 8b֌൞đၛ༯౦ঃ҂ൡႨႿ‫ܿھ‬ᄵğ + + • ‫ؿ‬ෂఖູФ‫׮‬հ༂ሑ෿đၹູᄝႋճҢໃ࡟ҩ֞ཁྟ໊‫ط‬Ӂളႋճհ༂đ౏ᄝ‫ؿ‬ෂФ‫׮‬հ༂ѓᆽൈ + ࡟ҩ֞ཁྟ໊ൈđᄵ TEC ඔᆴ҂ႋᄹࡆb + +ুᶈྐ༏॓࠯ 496 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + • ‫ؿ‬ෂఖᄝᇘҊ௹ࡗၹแԉհ༂‫ؿط‬ෂհ༂ѓᆽđ౏แԉ໊Ч‫ھ‬൞ႅྟ໊֌൞࡟ҩ֞ཁྟ໊đᄵ TEC + ඔᆴ҂ႋᄹࡆb + + 4. ೏‫ؿ‬ෂఖᄝ‫ؿ‬ෂᇶ‫׮‬հ༂ѓᆽ‫ݖބ‬ᄛѓᆽൈ࡟ҩ໊֞հ༂đᄵ TEC ඔᆴᄹࡆ 8b + 5. ೏ࢤ൬ఖᄝ‫ؿ‬ෂᇶ‫׮‬հ༂ѓᆽ‫ݖބ‬ᄛѓᆽൈ࡟ҩ໊֞հ༂đᄵ REC ඔᆴᄹࡆ 8b + 6. ಩ၩࢫׄᄝ‫ؿ‬ෂᇶ‫׮‬/Ф‫׮‬հ༂ѓᆽࠇ‫ݖ‬ᄛѓᆽުđࢫׄࣇିӵᄛቋ‫ ؟‬7 ۱৵࿃ཁྟ໊bᄝč‫ؿ‬ෂᇶ‫׮‬հ + + ༂ѓᆽࠇ‫ݖ‬ᄛѓᆽൈĎ࡟ҩֻ֞ 14 ۱৵࿃ཁྟ໊đࠇᄝФ‫׮‬հ༂ѓᆽު࡟ҩֻ֞ 8 ۱৵࿃ཁྟ໊ުđ‫ؿ‬ + ෂఖࡼ൐ః TEC ඔᆴᄹࡆ 8đ‫ࢤط‬൬ఖࡼ൐ః REC ඔᆴᄹࡆ 8bૄᄹࡆ 8 ۱৵࿃ཁྟ໊֥๝ൈđč‫ؿ‬ෂఖ + ֥ĎTEC ‫ބ‬čࢤ൬ఖ֥ĎREC ඔᆴ္ࡼᄹࡆ 8b + 7. ૄ֒‫ؿ‬ෂఖӮ‫ؿۿ‬ෂБ໓ުčࢤ൬֞ ACKđ౏ᆰ֞ EOF ປӮໃ‫ؿ‬ളհ༂ĎđTEC ඔᆴࡼࡨཬ 1đԢ٤ TEC + ֥ඔᆴၘູࣜ 0b + 8. ֒ࢤ൬ఖӮ‫ࢤۿ‬൬Б໓ުčಒಪҢభໃ࡟ҩ֞հ༂đ౏Ӯ‫ؿۿ‬ෂ ACKĎđᄵ REC ඔᆴࡼཌྷႋࡨཬb + + • ೏ REC ඔᆴ໊Ⴟ 1 ~ 127 ᆭࡗđᄵఃᆴࡨཬ 1b + • ೏ REC ඔᆴնႿ 127đᄵఃᆴࡨཬ֞ 127b + • ೏ REC ඔᆴູ 0đᄵಯЌӻູ 0b + 9. ֒၂۱ࢫ֥ׄ TEC ‫ބ‬/ࠇ REC ඔᆴնႿ֩Ⴟ 128 ൈđ‫ׄࢫھ‬эູФ‫׮‬հ༂ࢫׄb֝ᇁࢫׄ‫ؿ‬ളഈඍሑ෿ + ్ߐ֥հ༂đ‫ׄࢫھ‬ಯ‫ؿ‬ෂᇶ‫׮‬հ༂ѓᆽb౨ᇿၩđ၂֊ REC ඔᆴ֞ղ 128đު࿃಩‫ޅ‬ᄹࡆ‫ھ‬ᆴ֥‫׮‬ቔ + ‫׻‬൞໭ི֥đᆰ֞ REC ඔᆴْ߭֞ 128 ၛ༯b + 10. ֒ଖࢫ֥ׄ TEC ඔᆴնႿ֩Ⴟ 256 ൈđ‫ࡼׄࢫھ‬эູ৖ཌࢫׄb + 11. ֒ଖФ‫׮‬հ༂ࢫ֥ׄ TEC ‫ ބ‬REC ඔᆴ‫ཬ׻‬Ⴟ֩Ⴟ 127đᄵ‫ࡼׄࢫھ‬эູᇶ‫׮‬հ༂ࢫׄb + 12. ֒৖ཌࢫׄᄝሹཌഈ࡟ҩ֞ 128 Ց 11 ۱৵࿃ႅྟ໊ުđ‫ׄࢫھ‬ॖэູᇶ‫׮‬հ༂ࢫׄčTEC ‫ ބ‬REC ඔᆴ + ‫׻‬ᇗഡູ 0Ďb + +21.3.4 TWAI ໊ൈ྽ +21.3.4.1 ଀ၬ໊ + +TWAI ླྀၰᄍྸ TWAI ሹཌၛห‫໊֥ק‬෎ੱᄎྛb֌൞đሹཌଽ֥෮Ⴕࢫׄсྶၛ๤၂໊෎ੱᄎྛb + • ଀ၬ໊෎ੱູૄ૰‫ؿ‬ෂбหඔਈb + • ଀ၬ໊ൈࡗູ 1/଀ၬ໊෎ੱb + +ૄ۱଀ၬ໊ൈࡗᇏ‫؟ݣ‬۱‫؍‬đૄ‫؍‬Ⴎ‫؟‬۱ൈࡗ‫( حק‬Time Quanta) ቆӮbൈࡗ‫ູحק‬ቋཬൈࡗֆ໊đቔູ၂ᇕყ +‫ٳ‬௔ൈᇒྐ‫ݼ‬ႋႨႿ۲۱ࢫׄᇏb༯๭ 21-5 ෮ൕູ၂۱଀ၬ໊ൈࡗଽ෮Ї‫؍֥ݣ‬b +TWAI ॥ᇅఖࡼᄝ၂۱ൈࡗ‫֥حק‬ൈࡗ҄ӉᇏࣉྛҠቔđૄ۱ൈࡗ‫حק‬ᇏ‫ٳ߶׻‬༅ TWAI ֥ሹཌሑ෿bೂ‫ݔ‬ਆ۱ +৵࿃֥ൈࡗ‫حק‬ᇏሹཌሑ෿҂๝čႅྟ-ཁྟđࠇّᆭĎđၩ໅ሢႵшခӁളbPBS1 ‫ ބ‬PBS2 ֥ࢌׄࡼФ൪ູҐ +ဢׄđ౏Ґဢ֥ሹཌඔᆴູࠧᆃ۱໊֥ඔᆴb + +ুᶈྐ༏॓࠯ 497 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + ๭ 21­5. ໊ൈ྽‫ܒ‬Ӯ + + і 21­5. ଀ၬ໊ൈ྽ᇏЇ‫؍֥ݣ‬ + +‫؍‬ ૭ඍ +๝҄‫( ؍‬SS) SSč๝҄‫؍‬Ď֥Ӊ؇ູ 1 ۱ൈࡗ‫حק‬b೏෮Ⴕࢫׄ‫׻‬๝҄ᆞӈđᄵ໊шခႋ໊Ⴟ‫؍ھ‬ + ଽb +ߏԊൈ௹‫ ؍‬1 PBS1 ֥Ӊ؇ॖູ 1 ~ 16 ۱ൈࡗ‫حק‬đႨႿҀӊຩ઎ᇏ֥໾৘࿼Ӿൈࡗbॖᄹࡆ PBS1 +(PBS1) ֥Ӊ؇đՖ‫ط‬۷‫ֹݺ‬ൌགྷ๝҄b +ߏԊൈ௹‫ ؍‬2 PBS2 ֥Ӊ؇ॖູ 1 ~ 8 ۱ൈࡗ‫حק‬đႨႿҀӊࢫׄᇏ֥ྐ༏ԩ৘ൈࡗbॖ෪؋ PBS2 +(PBS2) ֥Ӊ؇đՖ‫ط‬۷‫ֹݺ‬ൌགྷ๝҄b + +21.3.4.2 ႗๝҄აᄜ๝҄ + +ႮႿൈᇒொ၍‫׮׵ބ‬đ๝၂ሹཌഈࢫ໊֥ׄൈ྽ॖି߶ຂ৖ཌྷ໊‫؍‬bၹ‫ط‬đ໊шခॖି߶ொ၍֞๝҄‫֥؍‬భުb +ᆌؓഈඍ໊шခொ၍֥໙ี TWAI ิ‫؟܂‬ᇕ๝҄ٚൔbഡ໊шခொ၍֥ TQčൈࡗ‫حק‬Ďඔਈູཌྷ໊հ༂oepđ +‫ھ‬ᆴა SS ཌྷܱb + + • ᇶ‫׮‬ཌྷ໊հ༂ (e > 0)ğ໊шခ໊Ⴟ๝҄‫؍‬ᆭުҐဢׄᆭభčࠧđшခཟުொ၍Ďb + + • Ф‫׮‬ཌྷ໊հ༂ (e < 0)ğ໊шခ໊Ⴟభ۱໊֥Ґဢׄᆭު๝҄‫؍‬ᆭభčࠧđшခཟభொ၍Ďb + +ູࢳथཌྷ໊հ༂đॖࣉྛਆᇕ๝҄ٚൔđࠧ႗๝҄აᄜ๝҄b႗๝҄აᄜ๝҄቎൯ၛ༯ܿᄵğ + + • ֆ۱໊ൈ྽ᇏࣇॖ‫ؿ‬ള၂Ց๝҄b + + • ๝҄ࣇॖ‫ؿ‬ളᄝႅྟ໊֞ཁྟ໊֥шခഈb + +႗๝҄ +ሹཌॢ༽௹ࡗđ႗๝҄‫ؿ‬ളᄝႅྟ໊֞ཁྟ໊֥э߄шခഈčೂ SOF ໊ഈĎbՎൈđ෮Ⴕࢫׄ‫ࡼ׻‬ᇗఓఃଽ҆ +໊ൈ྽đՖ‫ط‬൐‫ھ‬э߄шခ໊Ⴟᇗఓ໊ൈ྽֥๝҄‫؍‬ଽb + +ᄜ๝҄ +٤ሹཌॢ༽௹ࡗđᄜ๝҄‫ؿ‬ളᄝႅྟ໊֞ཁྟ໊֥э߄шခഈbೂ‫ݔ‬шခഈႵᇶ‫׮‬ཌྷ໊հ༂ (e > 0)đᄵ PBS1 +Ӊ؇ࡼᄹࡆbೂ‫ݔ‬шခഈႵФ‫׮‬ཌྷ໊հ༂ (e < 0)đᄵ PBS2 Ӊ؇ࡼࡨཬb + +PBS1/PBS2 ऎุᄹࡆ‫֥ཬࡨބ‬ൈࡗ‫حק‬౼थႿཌྷ໊հ༂֥धؓᆴđ๝ൈ္൳ॖ஥ᇂ֥๝๋҄ॺ (SJW) ඔᆴཋ +ᇅb + + • ֒ཌྷ໊հ༂֥धؓᆴཬႿ֩Ⴟ SJW ඔᆴൈđPBS1/PBS2 ࡼᄹࡆ/ࡨཬ e ۱ൈࡗ‫حק‬b‫ݖھ‬ӱა႗๝҄ऎ + Ⴕཌྷ๝ི‫ݔ‬b + + • ֒ཌྷ໊հ༂֥धؓᆴնႿ SJW ඔᆴൈđPBS1/PBS2 ࡼᄹࡆ/ࡨཬა SJW ཌྷ๝ඔᆴ֥ൈࡗ‫حק‬bᆃၩ໅ + ሢđᄝປಆࢳथཌྷ໊հ༂ᆭభđॖିླေ‫؟‬۱๝໊҄b + +ুᶈྐ༏॓࠯ 498 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +21.4 ࢲ‫ۀܒ‬ඍ + + ๭ 21­6. TWAI ‫੻ۀ‬๭ + +ESP32 ᇏЇ‫ݣ‬၂۱ TWAI ॥ᇅఖb๭ 21-6 ෮ൕູ TWAI ॥ᇅఖ֥ᇶေ‫ିۿ‬ଆॶb + +21.4.1 ࠷թఖଆॶ + +ESP32 ֥ CPU ൐Ⴈ 32-bit ؓఊሳ٠໙ຓഡb֌൞đTWAI ॥ᇅఖᇏ֥ն҆‫࠷ٳ‬թఖࣇթԥቋ֮Ⴕིሳࢫ (bits +[7:0]) ഈ֥ႵႨඔऌbၹՎᄝᆃུ࠷թఖᇏđbits [31:8] ᄝཿೆൈФޭ੻đᄝ‫؀‬౼ൈْ߭ 0b + +஥ᇂ࠷թఖ +஥ᇂ࠷թఖթԥ TWAI ॥ᇅఖ֥۲஥ᇂཛđೂ໊෎ੱaҠቔଆൔaࢤ൬ੲѯఖ֩bᆺႵᄝ TWAI ॥ᇅఖԩႿ‫໊گ‬ +ଆൔൈđҌॖྩ‫ڿ‬஥ᇂ࠷թఖčॖҕ࡮ֻ 21.5.1 ᅣĎb + +ᆷ਷࠷թఖ +CPU ๙‫ݖ‬ᆷ਷࠷թఖ౺‫ ׮‬TWAI ॥ᇅఖᆳྛ಩ༀđೂ‫ؿ‬ෂБ໓ࠇౢԢࢤ൬ߏԊఖbᆺႵᄝ TWAI ॥ᇅఖԩႿҠ +ቔଆൔൈđҌॖྩ‫ڿ‬ᆷ਷࠷թఖčॖҕ࡮ֻ 21.5.1 ᅣĎb + +ᇏ؎ & ሑ෿࠷թఖ +ᇏ؎࠷թఖཁൕ TWAI ॥ᇅఖᇏ‫ؿ‬ള֥൙ࡱčૄ۱൙ࡱႮ၂۱ֆ‫໊֥׿‬іൕĎbሑ෿࠷թఖཁൕ TWAI ॥ᇅఖ֥ +֒భሑ෿b + +հ༂ܵ৘࠷թఖ +հ༂ܵ৘࠷թఖЇওհ༂࠹ඔ‫ބ‬ѽሚ࠷թఖbհ༂࠹ඔ࠷թఖіൕ TEC ‫ ބ‬REC ֥ඔᆴbѽሚ࠷թఖ‫ڵ‬ᄳ࠺੣ +ཌྷܱྐ༏đೂ TWAI ॥ᇅఖᄝ‫ޅ‬ԩ࡟ҩ֞ሹཌհ༂đࠇ‫ޅ‬ൈ‫ש‬ാᇘҊb + +‫ؿ‬ෂߏԊ࠷թఖ +‫ؿ‬ෂߏԊఖնཬູ 13 ሳࢫđႨႿթԥ TWAI ֥ր‫ؿ‬ෂБ໓b + +ুᶈྐ༏॓࠯ 499 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +ࢤ൬ߏԊ࠷թఖ +ࢤ൬ߏԊఖնཬູ 13 ሳࢫđႨႿթԥֆ۱Б໓bࢤ൬ߏԊఖ൞ࣉೆࢤ൬ FIFO ֥Գ१đࢤ൬ FIFO ᇏֻ֥၂۱ +Б໓ࡼФ႘ഝ֞ࢤ൬ߏԊఖᇏb + +౨ᇿၩđ‫ؿ‬ෂߏԊ࠷թఖaࢤ൬ߏԊ࠷թఖ‫ࢤބ‬൬ੲѯ࠷թఖֹ֥ᆶٓຶཌྷ๝čֹᆶொ၍Ї‫ ݣ‬0x0040 ~ +0x0070Ďbᆃུ࠷թఖ֥٠໙ಃཋ቎࿖ၛ༯ܿᄵğ + + • ֒ TWAI ॥ᇅఖԩႿ‫໊گ‬ଆൔൈđ‫ֹھ‬ᆶٓຶФ႘ഝ֞ࢤ൬ੲѯ࠷թఖᇏb + + • TWAI ॥ᇅఖԩႿҠቔଆൔൈğ + + – ֹؓᆶٓຶ֥෮Ⴕ‫؀‬౼‫׻‬႘ഝႿࢤ൬ߏԊ࠷թఖᇏb + + – ֹؓᆶٓຶ֥෮Ⴕཿೆ‫׻‬႘ഝႿ‫ؿ‬ෂߏԊ࠷թఖᇏb + +21.4.2 ໊ੀԩ৘ఖ + +໊ੀԩ৘ (BSP) ଆॶ‫ڵ‬ᄳؓ‫ؿ‬ෂߏԊఖ֥ඔऌࣉྛᆠԩ৘ (ೂđ໊แԉ‫ ࡆڸބ‬CRC თ) ѩູ໊ൈ྽આࠠ (BTL) ଆ +ॶളӮ໊ੀb๝ൈđBSP ଆॶߎ‫ڵ‬ᄳԩ৘Ֆ BTL ଆॶᇏࢤ൬໊֥ੀčೂđಀแԉ‫ބ‬ဒᆣ CRCĎđѩࡼԩ৘Б໓ +ᇂႿࢤ൬ FIFObBSP ߎ‫ڵ‬ᄳ࡟ҩ TWAI ሹཌഈ֥հ༂ѩࡼՎোհ༂Бۡ۳հ༂ܵ৘આࠠ (EML)b + +21.4.3 հ༂ܵ৘આࠠ + +հ༂ܵ৘આࠠ (EML) ଆॶ‫ڵ‬ᄳ۷ྍ TEC ‫ ބ‬REC ඔᆴđ࠺੣հ༂ྐ༏čೂđհ༂ো྘‫ބ‬հ༂໊ᇂĎđ۷ྍ॥ᇅఖ +֥հ༂ሑ෿đಒЌ BSP ଆॶ‫ؿ‬ෂᆞಒ֥հ༂ѓᆽbՎຓđ‫ھ‬ଆॶߎ‫ڵ‬ᄳ࠺੣ TWAI ॥ᇅఖ‫ש‬ാᇘҊൈ֥ bit ໊ +ᇂb + +21.4.4 ໊ൈ྽આࠠ + +໊ൈ྽આࠠ (BTL) ଆॶ‫ڵ‬ᄳၛყ༵஥ᇂ໊֥෎ੱ‫ؿ‬ෂ‫ࢤބ‬൳Б໓bBTL ଆॶߎ‫ڵ‬ᄳ๝໊҄ൈ྽đಒЌඔऌԮൻ +֥໗‫ྟק‬b໊෎ੱႮ‫؟‬۱ॖщӱ֥‫؍‬ቆӮđ౏Ⴈ޼ॖഡᇂૄ۱‫ ֥؍‬TQčൈࡗ‫حק‬ĎӉ؇đট‫ט‬ᆜБ໓Ԯൻ෎ +ੱb + +21.4.5 ࢤ൬ੲѯఖ + +ࢤ൬ੲѯఖ൞၂۱ॖщӱ֥Б໓‫ݖ‬ੲֆჭđᄍྸ TWAI ॥ᇅఖ۴ऌБ໓֥ѓ്‫ژ‬თࢤ൬ࠇऋध‫ھ‬Б໓b๙‫ࢤݖ‬ +൬ੲѯఖ֥Б໓ҌିФթԥ֞ࢤ൬ FIFO ᇏbႨ޼ॖ஥ᇂࢤ൬ੲѯఖ֥ଆൔğֆੲѯఖaචੲѯఖb + +21.4.6 ࢤ൬ FIFO + +ࢤ൬ FIFO ൞նཬູ 64-byte ֥ߏԊఖč໊Ⴟ TWAI ॥ᇅఖଽ҆Ďđ‫ڵ‬ᄳթԥ๙‫ࢤݖ‬൬ੲѯఖ֥ࢤ൬Б໓bࢤ൬ +FIFO ᇏթԥ֥Б໓նཬॖၛ҂๝č3 ~ 13 byte ٓຶᆭࡗĎb֒ࢤ൬ FIFO ູડൈčࠇഺჅ֥ॢࡗ҂ቀၛປಆթԥ +༯၂۱ࢤ൬Б໓ĎđࡼԨ‫ؿ‬ၮԛᇏ؎đު࿃֥ࢤ൬Б໓ࡼ‫ש‬ാđᆰ֞ࢤ൬ FIFO ᇏౢԢԛቀ‫֥ܔ‬թԥॢࡗbࢤ൬ +FIFO ᇏֻ֥၂่Б໓ࡼФ႘ഝ֞ 13-byte ֥ࢤ൬ߏԊఖᇏđᆰ֞‫ھ‬Б໓ФౢԢč๙‫ݖ‬൤٢ࢤ൬ߏԊఖᆷ਷Ďb +ౢԢުđࢤ൬ߏԊఖࡼ࠿࿃႘ഝࢤ൬ FIFO ᇏ֥༯၂่Б໓đࢤ൬ FIFO ᇏഈ၂่ၘౢԢБ໓֥ॢࡗࡼФ൤ +٢b + +21.5 ‫ିۿ‬૭ඍ + +21.5.1 ଆൔ + +ESP32 TWAI ॥ᇅఖႵਆᇕ‫۽‬ቔଆൔğ‫໊گ‬ଆൔ‫ބ‬Ҡቔଆൔbࡼ TWAI_RESET_MODE ໊ᇂ 1đࣉೆ‫໊گ‬ଆൔĠ +ᇂ 0đࣉೆҠቔଆൔb + +ুᶈྐ༏॓࠯ 500 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +21.5.1.1 ‫໊گ‬ଆൔ + +ေྩ‫ ڿ‬TWAI ॥ᇅఖ֥۲ᇕ஥ᇂ࠷թఖđླࣉೆ‫໊گ‬ଆൔbࣉೆ‫໊گ‬ଆൔൈđTWAI ॥ᇅఖӞָა TWAI ሹཌ؎ +ष৵ࢤb‫໊گ‬ଆൔ༯đTWAI ॥ᇅఖࡼ໭‫ؿم‬ෂ಩‫ޅ‬Б໓čЇওհ༂ྐ‫ݼ‬Ďb಩‫ޅ‬ᆞᄝࣉྛ֥Б໓Ԯൻࡼ৫ࠧФ +ᇔᆸb๝ဢ֥đTWAI ॥ᇅఖᄝ‫ھ‬ଆൔ༯္ࡼ໭‫ࢤم‬൬಩‫ޅ‬Б໓b + +21.5.1.2 Ҡቔଆൔ + +ࣉೆҠቔଆൔުđTWAI ॥ᇅఖაሹཌཌྷ৵đѩ౏ཿЌ޹۲஥ᇂ࠷թఖđၛಒЌ॥ᇅఖ֥஥ᇂᄝᄎྛ௹ࡗЌӻ၂ +ᇁbҠቔଆൔ༯đTWAI ॥ᇅఖॖၛ‫ؿ‬ෂ‫ࢤބ‬൬Б໓čЇওհ༂ྐ‫ݼ‬Ďđ֌ऎุ౼थႿ TWAI ॥ᇅఖ஥ᇂႿଧᇕ +ᄎྛሰଆൔbTWAI ॥ᇅఖᆦӻၛ༯೘ᇕሰଆൔğ + + • ᆞӈଆൔğ TWAI ॥ᇅఖॖၛ‫ؿ‬ෂ‫ࢤބ‬൬Ї‫ݣ‬հ༂ྐ‫ݼ‬ᄝଽ֥Б໓čೂđհ༂ᆠ‫ݖބ‬ᄛᆠĎb + + • ሱҩଆൔğაᆞӈଆൔཌྷ๝đ֌ᄝ‫ھ‬ଆൔ༯đTWAI ॥ᇅఖ‫ؿ‬ෂБ໓ൈđࠧ൐ᄝ CRC თᆭުીႵࢤ൬֞ႋ + ճྐ‫ݼ‬đ္҂߶Ӂളႋճհ༂b๙ӈᄝ TWAI ॥ᇅఖሱҩൈ൐Ⴈ‫ھ‬ଆൔb + + • ᆺ๐ଆൔğ TWAI ॥ᇅఖॖၛࢤ൬Б໓đ֌ᄝ TWAI ሹཌഈЌӻປಆФ‫׮‬bၹՎđTWAI ॥ᇅఖࡼ໭‫ؿم‬ෂ + ಩‫ޅ‬Б໓aႋճࠇհ༂ྐ‫ݼ‬bհ༂࠹ඔࡼЌӻ‫ࢲײ‬ሑ෿b‫ھ‬ଆൔႨႿ TWAI ሹཌࡓ॥b + +౨ᇿၩđ๼ԛ‫໊گ‬ଆൔުčೂđࣉೆҠቔଆൔൈĎđTWAI ॥ᇅఖླ֩ր 11 ۱৵࿃ႅྟ໊ԛགྷđҌିປಆ৵ࢤഈ +TWAI ሹཌčࠧđॖၛ‫ؿ‬ෂࠇࢤ൬Б໓Ďb + +21.5.2 ໊ൈ྽ + +TWAI ॥ᇅఖ֥‫۽‬ቔ໊෎ੱсྶᄝ॥ᇅఖԩႿ‫໊گ‬ଆൔൈࣉྛ஥ᇂbᄝ࠷թఖ +TWAI_BUS_TIMING_0_REG ‫ ބ‬TWAI_BUS_TIMING_1_REG ᇏ஥ᇂ໊෎ੱđᆃਆ۱࠷թఖЇ‫ݣ‬ၛ༯თğ + +༯і 21-6 ෮ൕູ TWAI_BUS_TIMING_0_REG Ї‫໊֥ݣ‬თb + + і 21­6. TWAI_CLOCK_DIVIDER_REG ֥ bit ྐ༏; TWAI ֹᆶ 0x18 + +Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 +Reserved SJW.1 SJW.0 BRP.5 BRP.4 BRP.3 BRP.2 BRP.1 BRP.0 + +ඪૼğ + +• ყ‫ٳ‬௔ᆴ (BRP)ğTWAI ൈࡗ‫حק‬ൈᇒႮ APB ൈᇒ‫ٳ‬௔֤֞đAPB ൈᇒ๙ӈູ 80 MHzbॖ๙‫ݖ‬ၛ༯‫܄‬ൔ + ࠹ෘ‫ٳ‬௔ඔᆴđఃᇏ tT q ູൈࡗ‫֥حק‬ൈᇒᇛ௹đtCLK ູ APB ൈᇒᇛ௹ğ + tT q = 2 × tCLK × (25 × BRP.5 + 24 × BRP.4 + 23 × BRP.3 + 22 × BRP.2 + 21 × BRP.1 + 20 × BRP.0 + 1) + +• ๝๋҄ॺ (SJW)ğSJW ඔᆴᄝ SJW.0 ‫ ބ‬SJW.1 ᇏ஥ᇂđ࠹ෘ‫܄‬ൔູğSJW = (2 x SJW.1 + SJW.0 + 1)b + +༯і 21-7 ෮ൕູ TWAI_BUS_TIMING_1_REG Ї‫໊֥ݣ‬თb + + і 21­7. TWAI_BUS_TIMING_1_REG ֥ bit ྐ༏; TWAI ֹᆶ 0x1c + +Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 + PBS2.2 PBS2.1 PBS2.0 PBS1.3 PBS1.2 PBS1.1 PBS1.0 +Ќ਽ SAM + +ඪૼğ + +• PBS1: ۴ऌၛ༯‫܄‬ൔ࠹ෘߏԊൈ௹‫ ؍‬1 ᇏ֥ൈࡗ‫حק‬ඔਈğ(8 x PBS1.3 + 4 x PBS1.2 + 2 x PBS1.1 + + PBS1.0 + 1)b + +ুᶈྐ༏॓࠯ 501 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + • PBS2: ۴ऌၛ༯‫܄‬ൔ࠹ෘߏԊൈ௹‫ ؍‬2 ᇏ֥ൈࡗ‫حק‬ඔਈğ(4 x PBS2.2 + 2 x PBS2.1 + PBS2.0 + 1)b + • SAM: ‫ھ‬ᆴᇂ 1 ఓ‫׮‬೘ׄҐဢbႨႿ֮/ᇏ෎ሹཌđႵ০Ⴟ‫ݖ‬ੲሹཌഈ֥ࡕ‫ݼྐڂ‬b + +21.5.3 ᇏ؎ܵ৘ + +ESP32 TWAI ॥ᇅఖิ‫܂‬ਔ௾ᇕᇏ؎đૄᇕᇏ؎Ⴎ࠷թఖ TWAI_INT_RAW_REG ᇏ֥၂۱໊іൕbေԨ‫ؿ‬ଖ۱ +ห‫֥ק‬ᇏ؎đྶഡᇂ TWAI_INT ENA_REG ᇏཌྷႋ֥൐ି໊b +TWAI ॥ᇅఖิ‫܂‬ਔၛ༯௾ᇕᇏ؎ğ + + • ࢤ൬ᇏ؎ + • ‫ؿ‬ෂᇏ؎ + • հ༂Бࣞᇏ؎ + • ඔऌၮԛᇏ؎ + • Ф‫׮‬հ༂ᇏ؎ + • ᇘҊ‫ש‬ാᇏ؎ + • ሹཌհ༂ᇏ؎ +ᆺေᄝ TWAI_INT_RAW_REG ၂۱ࠇ‫؟‬۱ᇏ؎ູ໊ 1đTWAI ॥ᇅఖᇏ֥ᇏ؎ྐ‫ູࠧݼ‬Ⴕིđ֒ +TWAI_INT_RAW_REG ᇏ֥෮Ⴕ໊‫׻‬ФౢԢൈđTWAI ॥ᇅఖᇏ֥ᇏ؎ྐ‫ݼ‬ᄵാིb࠷թఖ +TWAI_INT_RAW_REG Ф‫؀‬౼ުđఃᇏ֥ն‫؟‬ඔᇏ؎໊ࡼሱ‫׮‬ౢԢb֌൞đࢤ൬ᇏ؎҂Їওᄝଽđᆰ֞๙‫ݖ‬ +TWAI_RELEASE_BUF ᆷ਷໊ౢԢ෮Ⴕࢤ൬Б໓ުđࢤ൬ᇏ؎໊ҌିФౢԢb + +21.5.3.1 ࢤ൬ᇏ؎ (RXI) + +֒ TWAI ࢤ൬ FIFO ᇏႵր‫؀‬౼Б໓ൈčTWAI_RX_MESSAGE_CNT_REG > 0Ďđ‫߶׻‬Ԩ‫ ؿ‬RXIb +TWAI_RX_MESSAGE_CNT_REG ᇏ࠺੣֥Б໓ඔਈЇওࢤ൬ FIFO ᇏ֥ႵིБ໓‫ބ‬ၮԛБ໓bᆰ֞๙‫ݖ‬ +TWAI_RELEASE_BUF ᆷ਷໊ౢԢ෮Ⴕ‫ܫ‬ఏࢤ൬Б໓ުđRXI Ҍ߶ാིb + +21.5.3.2 ‫ؿ‬ෂᇏ؎ (TXI) + +ૄ֒‫ؿ‬ෂߏԊఖॢ༽đࡼః෰Б໓ࡆᄛ֞‫ؿ‬ෂߏԊఖᇏ֩ր‫ؿ‬ෂൈđ‫߶׻‬Ԩ‫ ؿ‬TXIbၛ༯౦ঃ༯đ‫ؿ‬ෂߏԊఖࡼ +эູॢ༽đ๝ൈ TXI ࡼാིğ + + • Б໓‫ؿ‬ෂၘӮ‫ۿ‬ປӮčೂđႋճໃ‫ؿ‬གྷհ༂Ďb಩‫ؿޅ‬ෂാϧࡼሱ‫׮‬ᇗ‫ؿ‬b + • ֆՑ‫ؿ‬ෂၘປӮčTWAI_TX_COMPLETE ໊ᆷൕ‫ؿ‬ෂӮ‫ۿ‬ა‫ڎ‬Ďb + • ൐Ⴈ TWAI_ABORT_TX ᆷ਷໊ᇔᆸБ໓‫ؿ‬ෂb + +21.5.3.3 հ༂Бࣞᇏ؎ (EWI) + +ૄ֒࠷թఖ TWAI_STATUS_REG ᇏ TWAI_ERR_ST ࠇ TWAI_BUS_OFF_ST ໊֥ᆴ‫ڿ‬эൈčೂđՖ 0 эູ 1 ࠇ +ّᆭĎđ‫߶׻‬Ԩ‫ ؿ‬EWIb۴ऌ EWI Ԩ‫ؿ‬ൈ TWAI_ERR_ST ࠇ TWAI_BUS_OFF_ST ֥ᆴ‫ٳ‬Ӯၛ༯ࠫᇕ౦ঃğ + + • ೂ‫ ݔ‬TWAI_ERR_ST = 0 ࠇ TWAI_BUS_OFF_ST = 0ğ + +ুᶈྐ༏॓࠯ 502 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + – ೂ‫ ݔ‬TWAI ॥ᇅఖԩႿᇶ‫׮‬հ༂ሑ෿đᄵіൕ TEC ‫ ބ‬REC ֥ᆴ‫ْ֞߭׻‬ਔ + TWAI_ERR_WARNING_LIMIT_REG ෮ഡ֥ᚐᆴᆭ༯b + + – ೂ‫ ݔ‬TWAI ॥ᇅఖՎభᆞԩႿሹཌ߫‫گ‬ሑ෿đᄵіൕՎൈሹཌ߫‫ၘگ‬Ӯ‫ۿ‬ປӮb + +• ೂ‫ ݔ‬TWAI_ERR_ST = 1 ࠇ TWAI_BUS_OFF_ST = 0ğіൕ TEC ࠇ REC ඔᆴၘӑ‫ݖ‬ + TWAI_ERR_WARNING_LIMIT_REG ෮ഡ֥ᚐᆴb + +• ೂ‫ ݔ‬TWAI_ERR_ST = 1 ࠇ TWAI_BUS_OFF_ST = 1ğіൕ TWAI ॥ᇅఖၘࣉೆ BUS_OFF ሑ෿čၹ TEC + >= 256Ďb + +• ೂ‫ ݔ‬TWAI_ERR_ST = 0 ࠇ TWAI_BUS_OFF_ST = 1ğіൕ BUS_OFF ߫‫گ‬௹ࡗđTWAI ॥ᇅఖ֥ TEC ඔ + ᆴၘ֮Ⴟ TWAI_ERR_WARNING_LIMIT_REG ෮ഡ֥ᚐᆴb + +21.5.3.4 ඔऌၮԛᇏ؎ (DOI) + +ೈࡱ‫؀‬౼ࢤ൬ߏԊఖᇏ֥Б໓ൈđ೏‫ھ‬Б໓ඔऌູၮԛ໭ིБ໓đࡼԨ‫ ؿ‬DOIb + +21.5.3.5 Ф‫׮‬հ༂ᇏ؎ (TXI) + +ૄ֒ TWAI ॥ᇅఖՖᇶ‫׮‬հ༂эູФ‫׮‬հ༂đࠇّᆭൈđ‫߶׻‬Ԩ‫ ؿ‬EPIb + +21.5.3.6 ᇘҊ‫ש‬ാᇏ؎ (ALI) + +ૄ֒ TWAI ॥ᇅఖӇ൫‫ؿ‬ෂБ໓౏‫ש‬ാᇘҊൈđ‫߶׻‬Ԩ‫ ؿ‬ALIbTWAI ॥ᇅఖ‫ש‬ാᇘҊ֥ bit ໊ᇂࡼሱ‫࠺׮‬੣ᄝ +ᇘҊ‫ש‬ാѽሚ࠷թఖ (TWAI_ARB LOST CAP_REG) ᇏbᇘҊ‫ש‬ാѽሚ࠷թఖФౢԢč๙‫ ݖ‬CPU ‫؀‬౼‫࠷ھ‬թఖĎ +ᆭభđࡼ҂߶ᄜ࠺੣ྍ‫ؿ‬ള֥ᇘҊാϧൈ֥ bit ໊ᇂb + +21.5.3.7 ሹཌհ༂ᇏ؎ (BEI) + +ૄ֒ TWAI ॥ᇅఖᄝ TWAI ሹཌഈ࡟ҩ֞հ༂ൈđ‫߶׻‬Ԩ‫ ؿ‬BEIb‫ؿ‬ളሹཌհ༂ൈđሹཌհ༂֥ো྘‫ؿބ‬ളհ༂ +ൈ֥ bit ໊ᇂ‫ࡼ׻‬ሱ‫࠺׮‬੣ᄝհ༂ѽሚ࠷թఖ (TWAI_ERR_CODE_CAP_REG) ᇏbհ༂ѽሚ࠷թఖФౢԢč๙‫ݖ‬ +CPU ֥‫؀‬౼Ďᆭభđࡼ҂߶ᄜ࠺੣ྍ֥ሹཌհ༂ྐ༏b + +21.5.4 ‫ؿ‬ෂߏԊఖაࢤ൬ߏԊఖ +21.5.4.1 ߏԊఖ‫ۀ‬ඍ + + і 21­8. SFF ა EFF ֥ߏԊఖ҃अ + +ѓሙ۬ൔ (SFF) ଽಸ ঔᅚ۬ൔ (EFF) ଽಸ +TWAI ֹᆶ TX/RX ᆠྐ༏ TWAI ֹᆶ TX/RX ᆠྐ༏ +0x40 TX/RX identifier 1 0x40 TX/RX identifier 1 +0x44 TX/RX identifier 2 0x44 TX/RX identifier 2 +0x48 TX/RX data byte 1 0x48 TX/RX identifier 3 +0x4c TX/RX data byte 2 0x4c TX/RX identifier 4 +0x50 TX/RX data byte 3 0x50 TX/RX data byte 1 +0x54 TX/RX data byte 4 0x54 TX/RX data byte 2 +0x58 TX/RX data byte 5 0x58 TX/RX data byte 3 +0x5c 0x5c + +ুᶈྐ༏॓࠯ 503 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + ѓሙ۬ൔ (SFF) ଽಸ ঔᅚ۬ൔ (EFF) ଽಸ + TWAI ֹᆶ TX/RX data byte 6 TWAI ֹᆶ TX/RX data byte 4 + 0x60 TX/RX data byte 7 0x60 TX/RX data byte 5 + 0x64 TX/RX data byte 8 0x64 TX/RX data byte 6 + 0x68 Ќ਽ 0x68 TX/RX data byte 7 + 0x6c Ќ਽ 0x6c TX/RX data byte 8 + 0x70 0x70 + +і 21-8 ෮ൕູ‫ؿ‬ෂߏԊఖ‫ࢤބ‬൬ߏԊఖ֥࠷թఖ҃अb‫ؿ‬ෂ‫ࢤބ‬൬ߏԊ࠷թఖ֥٠໙ֹᆶٓຶཌྷ๝đ౏ᆺႵ +֒ TWAI ॥ᇅఖԩႿҠቔଆൔൈҌॖ٠໙bCPU ֥ཿೆҠቔࡼ٠໙‫ؿ‬ෂߏԊ࠷թఖđCPU ֥‫؀‬౼Ҡቔࡼ٠໙ࢤ +൬ߏԊ࠷թఖb + +‫ؿ‬ෂߏԊ࠷թఖႨႿ஥ᇂ TWAI ֥ր‫ؿ‬ෂБ໓bCPU ߶ᄝ‫ؿ‬ෂߏԊ࠷թఖࣉྛཿೆҠቔđᆷ‫ק‬Б໓֥ᆠো྘a +ᆠ۬ൔaᆠ ID ‫ބ‬ᆠඔऌčႵིᄛ‫ހ‬Ďb၂֊‫ؿ‬ෂߏԊఖ஥ᇂປӮުđCPU ߶ࡼ TWAI_CMD_REG ᇏ֥ +TWAI_TX_REQ ໊ᇂ 1đၛष൓Б໓‫ؿ‬ෂb + + • ೏൞ሱ‫ؿ‬ሱ൬౨౰đэ۷ູࡼ TWAI_SELF_RX_REQ ᇂ 1b + + • ೏൞ֆՑ‫ؿ‬ෂđླေ๝ൈࡼ TWAI_TX_REQ ‫ ބ‬TWAI_ABORT_TX ᇂ 1b + +ࢤ൬ߏԊ࠷թఖ႘ഝ֞ࢤ൬ FIFO ᇏֻ֥၂่Б໓bCPU ߶ᄝࢤ൬ߏԊ࠷թఖᇏࣉྛ‫؀‬౼Ҡቔđࠆ౼ֻ၂่Б +໓֥ᆠো྘aᆠ۬ൔaᆠ ID ‫ބ‬ᆠඔऌčႵིᄛ‫ހ‬Ďb‫؀‬౼ປࢤ൬ߏԊ࠷թఖᇏ֥Б໓ުđCPU ๙‫ࡼݖ‬ +TWAI_CMD_REG ᇏ֥ TWAI_RELEASE_BUF ໊ᇂ 1 টটౢԢࢤ൬ߏԊ࠷թఖđ೏ࢤ൬ FIFO ᇏಯႵրԩ৘֥Б +໓đοᅶࢤ൬Б໓֥༵ުՑ྽ࡼቋᄪࢤ൬֥֞Б໓႘ഝ֞ࢤ൬ߏԊ࠷թఖb + +21.5.4.2 ᆠྐ༏ + +ᆠྐ༏֥Ӊ؇ູ 1-byteđᇶေႨႿૼಒБ໓֥ᆠো྘aᆠ۬ൔၛࠣඔऌӉ؇b༯і 21-9 ෮ൕູᆠྐ༏ +თb + + і 21­9. TX/RX ᆠྐ༏ (SFF/EFF)ĠTWAI ֹᆶ 0x40 + +Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 + RTR X X XDLC.3 DLC.2 DLC.1 DLC.0 +Ќ਽ FF + +ඪૼğ + +• FF: ᇶေૼಒଖБ໓උႿ EFF ߎ൞ SFFb֒ FF ູ໊ 1 ൈđ‫ھ‬Б໓ູ EFFđ֒ FF ູ໊ 0 ൈđ‫ھ‬Б໓ູ SFFb + +• RTR: ᇶေૼಒଖБ໓൞ඔऌᆠߎ൞ჹӱᆠb֒ RTR ູ໊ 1 ൈđ‫ھ‬Б໓ູჹӱᆠđ֒ RTR ູ໊ 0 ൈđ‫ھ‬ + Б໓ູඔऌᆠb + +• DLC: ᇶေૼಒඔऌᆠᇏ֥ඔऌሳࢫඔਈđࠇՖჹӱᆠᇏ౨౰֥ඔऌሳࢫඔਈbTWAI ඔऌᆠ֥ቋնᄛ‫ູހ‬ + 8 ۱ඔऌሳࢫđၹՎ DLC ֥ඔᆴٓຶႋ൞ 0 ~ 8b + +• X: ໭ܱ bitđॖၛ൞಩ၩᆴb + +21.5.4.3 ᆠѓ്‫ژ‬ + +೏Б໓ູ SFFđᄵؓႋ֥ᆠѓ്‫ژ‬თູ 2-bytes (11-bits)Ġ೏Б໓ູ EFFđᄵؓႋ֥ᆠѓ്‫ژ‬თູ 4-bytes +(29-bits)b + +ুᶈྐ༏॓࠯ 504 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +༯і Table 21-10-21-11 ෮ൕູ SFF (11-bits) Б໓֥ᆠѓ്‫ژ‬თb + і 21­10. TX/RX ѓ്‫ ژ‬1 (SFF); TWAI ֹᆶ 0x44 + +Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 + ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 +Ќ਽ ID.28 + + і 21­11. TX/RX ѓ്‫ ژ‬2 (SFF); TWAI ֹᆶ 0x48 + +Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 + ID.19 ID.18 X1 X2 X2 X2 X2 +Ќ਽ ID.20 + +༯і 21-12-21-15 ෮ൕູ EFF (29-bits) Б໓֥ᆠѓ്‫ژ‬თb + і 21­12. TX/RX ѓ്‫ ژ‬1 (EFF); TWAI ֹᆶ 0x44 + +Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 + ID.27 ID.26 ID.25 ID.24 ID.23 ID.22 ID.21 +Ќ਽ ID.28 + + і 21­13. TX/RX ѓ്‫ ژ‬2 (EFF); TWAI ֹᆶ 0x48 + +Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 + ID.19 ID.18 ID.17 ID.16 ID.15 ID.14 ID.13 +Ќ਽ ID.20 + + і 21­14. TX/RX ѓ്‫ ژ‬3 (EFF); TWAI ֹᆶ 0x4c + +Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 + ID.5 +Ќ਽ ID.12 ID.11 ID.10 ID.9 ID.8 ID.7 ID.6 + + і 21­15. TX/RX ѓ്‫ ژ‬4 (EFF); TWAI ֹᆶ 0x50 + +Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 + ID.3 ID.2 ID.1 ID.0 X1 X2 X2 +Ќ਽ ID.4 + +21.5.4.4 ᆠඔऌ + +ᆠඔऌთЇ‫ؿݣ‬ෂࠇࢤ൬֥ඔऌᆠđٓຶູ 0 ~ 8 bytesbఃᇏ֥Ⴕིሳࢫඔႋა DLC ཌྷ๝b֌൞đೂ‫ ݔ‬DLC +ඔᆴնႿ 8đᄵᆠඔऌთ֥Ⴕིሳࢫඔಯູ 8bჹӱᆠᇏ҂Ї‫ݣ‬ඔऌᄛ‫ހ‬đၹՎ҂թᄝᆠඔऌთb + +бೂđ֒‫ؿ‬ෂ 5 ۱ඔऌሳࢫ֥ඔऌᆠൈđCPU ႋᄝ DLC თᇏཿೆඔᆴ 5đѩࡼඔऌཿೆඔऌთ 1 ~ 5 ሳࢫؓႋ +֥࠷թఖb๝ဢđ֒ࢤ൬ DLC ູ 5 ֥ඔऌᆠൈđᆺႵ 1 ~ 5 ඔऌሳࢫᇏЇ‫ ݣ‬CPU ॖၛ‫؀‬౼֥Ⴕིᄛ‫ހ‬ඔ +ऌb + +21.5.5 ࢤ൬ FIFO ‫ބ‬ඔऌၮԛ + +ࢤ൬ FIFO ൞၂۱ 64-bytes ֥ଽ҆ߏԊఖđႨႿၛ༵ࣉ༵ԛ֥ჰᄵթԥࢤ൬֥֞Б໓b၂่ࢤ൬Б໓ॖᄝࢤ൬ +FIFO ᇏᅝ 3 ~ 13 bytes ॢࡗđ౏ఃᇏሳࢫ྽აࢤ൬ߏԊఖ֥࠷թఖֹᆶඨ྽ཌྷ๝bࢤ൬ߏԊ࠷թఖࡼФ႘ഝ֞ + +ুᶈྐ༏॓࠯ 505 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + ࢤ൬ FIFO ᇏֻ၂่Б໓b + + ֒ TWAI ॥ᇅఖࢤ൬֞၂่Б໓ൈđTWAI_RX_MESSAGE_COUNTER ֥ᆴࡼᄹࡆ 1đቋնᆴູ 64bೂ‫ࢤݔ‬൬ + FIFO ᇏႵቀ‫֥ܔ‬ഺჅॢࡗđБ໓ଽಸࡼФཿೆ֞ࢤ൬ FIFO ᇏb‫؀‬౼ࢤ൬ߏԊఖᇏ֥ཨ༏ުđ๙‫ࡼݖ‬ + TWAI_RELEASE_BUF ໊֥ᇂ 1đ൤٢ࢤ൬ FIFO ֻ၂่Б໓෮ᅝ֥ॢࡗđTWAI_RX_MESSAGE_COUNTER ֥ + ᆴ္ࡼࡨཬ 1bಖުđࢤ൬ߏԊఖࡼ႘ഝࢤ൬ FIFO ᇏ֥༯၂่Б໓b + + ֒ TWAI ॥ᇅఖࢤ൬֞၂่Б໓đ֌ࢤ൬ FIFO ીႵቀ‫ࡗॢܔ‬ປᆜֹթԥᆃ่ࢤ൬Б໓ൈč҂ં൞ၹູБ໓ଽಸ + նཬնႿࢤ൬ FIFO ᇏ֥ॢ༽ॢࡗđߎ൞ၹູࢤ൬ FIFO ၘડĎđࢤ൬ FIFO ࡼᄝଽ҆ࡼၮԛБ໓ѓ࠺ູ໭ིbު + ࿃ࢤ൬֥֞ၮԛБ໓ಯࡼᄹࡆ TWAI_RX_MESSAGE_COUNTER ֥ᆴ֞ቋնᆴ 64b + + ູਔౢԢࢤ൬ FIFO ᇏ֥ၮԛБ໓đႋᇗ‫טگ‬Ⴈ TWAI_RELEASE_BUFđᆰ֞ TWAI_RX_MESSAGE_COUNTER + ູ 0bᆃဢॖၛ‫؀‬౼ࢤ൬ FIFO ᇏ֥෮ႵႵིБ໓đѩౢԢ෮ႵၮԛБ໓b + + 21.5.6 ࢤ൬ੲѯఖ + + ࢤ൬ੲѯఖᄍྸ TWAI ॥ᇅఖ۴ऌБ໓ ID ‫ݖ‬ੲࢤ൬Б໓čႵൈॖၛ‫ݖ‬ੲБ໓ֻ֥၂۱ඔऌሳࢫ‫ބ‬ᆠো྘Ďbᆺ + Ⴕ๙‫ݖݖ‬ੲ֥Б໓Ҍିթԥ֞ࢤ൬ FIFO ᇏbࢤ൬ੲѯఖ֥൐Ⴈॖၛ၂‫ק‬ӱ؇ֹࡨ౞ TWAI ॥ᇅఖ֥ᄎྛ‫ހڵ‬ +čೂđॖࡨഒ൐Ⴈࢤ൬ FIFO ‫ؿބ‬ളࢤ൬ᇏ؎֥ՑඔĎđၹູ TWAI ॥ᇅఖࡼᆺླေҠቔ၂ཬ҆‫ݖٳ‬ੲު֥Б + ໓b + + ᆺႵ֒ TWAI ॥ᇅఖԩႿ‫໊گ‬ଆൔൈđҌॖၛ٠໙ࢤ൬ੲѯఖ֥஥ᇂ࠷թఖđၹູᆃུ஥ᇂ࠷թఖ‫ؿބ‬ෂ/ࢤ൬ + ߏԊ࠷թఖֹ֥ᆶॢࡗཌྷ๝b + + ࢤ൬ੲѯఖ֥஥ᇂ࠷թఖႮ 32-bit ֥ Code ᆴ‫ ބ‬32-bit ֥ Mask ᆴቆӮbCode ᆴࡼᆷ‫ק‬၂ᇕ໊ஆਙଆൔđૄ่ + ‫ݖ‬ੲБ໓ᇏ໊֥‫׻‬сྶ௄஥‫ھ‬ଆൔđҌି൐‫ھ‬Б໓๙‫ݖݖ‬ੲbMask ᆴॖ௠з Code ᆴᇏ֥ଖ໊ུčࡼ௠з໊ഡ + ᇂູo҂ཌྷܱp໊֥Ďbೂ๭ 21-7 ෮ൕđູਔ൐Б໓๙‫ݖݖ‬ੲđૄ่‫ݖ‬ੲБ໓֥ ID ‫׻‬сྶ௄஥ Code ᆴ෮ഡଆ + ൔࠇᆀФ Mask ᆴ௠зb + + ๭ 21­7. ࢤ൬ੲѯఖ + + TWAI ॥ᇅఖ֥ࢤ൬ੲѯఖᄍྸ 32-bit ֥ Code ᆴ‫ ބ‬Mask ᆴ‫ק‬ၬֆ۱ੲѯఖčֆੲѯଆൔĎđࠇਆ۱ੲѯఖ +čචੲѯଆൔĎbࢤ൬ੲѯఖೂ‫ࢳޅ‬༅ 32-bit ֥ code ᆴ‫ ބ‬mask ᆴđ౼थႿੲѯଆൔၛࠣࢤ൬Б໓֥۬ൔčೂđ + + SFF ߎ൞ EFFĎb + + 21.5.6.1 ֆੲѯଆൔ + + ࡼ TWAI_RX_FILTER_MODE ໊֥ᇂ 1đॖఓ‫׮‬ֆੲѯଆൔbՎުđ32-bit code/mask ֥ᆴࡼ‫ק‬ၬֆ۱ੲѯ + ఖb + ֆ۱ੲѯఖॖ‫ݖ‬ੲඔऌᆠ‫ބ‬ჹӱᆠᇏ֥ၛ༯໊ğ + + • SFF + – 11-bit ID ᆜุ + – RTR bit + +ুᶈྐ༏॓࠯ 506 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + – ඔऌሳࢫ 1 ‫ބ‬ඔऌሳࢫ 2 + • EFF + + – 29-bit ID ᆜุ + – RTR bit +༯๭ 21-8 ෮ൕູֆੲѯଆൔ༯ೂ‫ࢳޅ‬༅ 32-bit code/mask ֥ᆴb + + ๭ 21­8. ֆੲѯଆൔ + +21.5.6.2 චੲѯଆൔ + +ࡼ TWAI_RX_FILTER_MODE ໊֥ᇂ 0đॖఓ‫׮‬චੲѯଆൔbՎުđ32-bit code/mask ֥ᆴࡼ‫ק‬ၬਆ۱ੲѯఖᆭ +၂đࠧੲѯఖ 1 ࠇੲѯఖ 2bචੲѯଆൔ༯đೂ‫ݔ‬Б໓๙‫ݖ‬ᆃਆ۱ੲѯఖᇏ֥ᇀഒ၂۱đᄵіൕ‫ھ‬Б໓ၘӮ‫ۿ‬ +๙‫ݖݖ‬ੲb +ᆃਆ۱ੲѯఖॖၛ‫ݖ‬ੲඔऌᆠ‫ބ‬ჹӱᆠᇏ֥ၛ༯໊ğ + + • SFF + – 11-bit ID ᆜุ + – RTR bit + – ඔऌሳࢫ 1 (ࣇൡႨႿੲѯఖ 1) + + • EFF + – 29-bit ID ֥భ 16-bit + +༯๭ 21-9 ෮ൕູචੲѯଆൔ༯ೂ‫ࢳޅ‬༅ 32-bit code/mask ֥ᆴb + +21.5.7 հ༂ܵ৘ + +TWAI ླྀၰေ౰ૄ۱ TWAI ࢫׄᇏ‫׻‬Ї‫ؿݣ‬ෂհ༂࠹ඔ (TEC) ‫ࢤބ‬൬հ༂࠹ඔ (REC)bᆃਆ۱հ༂࠹ඔ֥ඔᆴथ +‫ק‬ਔ TWAI ॥ᇅఖ֒భ֥հ༂ሑ෿čೂđᇶ‫׮‬հ༂aФ‫׮‬հ༂a৖ཌĎbTWAI ॥ᇅఖࡼ TEC ‫ ބ‬REC ֥ඔᆴ‫ٳ‬љ +թԥᄝ TWAI_TX_ERR_CNT_REG ‫ ބ‬TWAI_RX_ERR_CNT_REG ᇏđCPU ॖෛൈࣉྛ‫؀‬౼bԢਔհ༂ሑ෿ᆭຓđ + +ুᶈྐ༏॓࠯ 507 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + ๭ 21­9. චੲѯଆൔ + +TWAI ॥ᇅఖߎิ‫܂‬հ༂Бࣞཋᇅ (EWL) ֥‫ିۿ‬đᆃ۱‫ିۿ‬ॖᄝ TWAI ॥ᇅఖࣉೆФ‫׮‬հ༂ሑ෿ᆭభđิྜႨ޼ +֒భ‫ؿ‬ള֥࿸ᇗሹཌհ༂b +TWAI ॥ᇅఖ֥֒భհ༂ሑ෿๙‫ݖ‬ၛ༯۲ඔᆴ‫ބ‬ሑ෿ุ໊གྷđࠧğTECaRECaTWAI_ERR_ST ‫ބ‬ +TWAI_BUS_OFF_STbᆃུඔᆴ‫ބ‬ሑ෿໊֥э߄္ࡼԨ‫ؿ‬ᇏ؎đՖ‫ྜิط‬Ⴈ޼֒భ֥հ༂ሑ෿э߄čॖҕ࡮ֻ +21.5.3 ᅣĎb༯๭ 21-10 ෮ൕູհ༂ሑ෿aഈඍඔᆴ‫ބ‬ሑ෿໊ၛࠣհ༂ሑ෿ཌྷܱᇏ؎ᆭࡗ֥ܱ༢b + +ুᶈྐ༏॓࠯ ๭ 21­10. հ༂ሑ෿э߄ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + + 508 + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +21.5.7.1 հ༂Бࣞཋᇅ + +հ༂Бࣞཋᇅ (EWL) ູ TEC ‫ ބ‬REC ֥ॖ஥ᇂᚐᆴđ೏հ༂࠹ඔඔᆴӑ‫ھݖ‬ᚐᆴđࡼԨ‫ ؿ‬EWI ᇏ؎bEWL ࡼቔ +ູ၂۱Бࣞ‫ิିۿ‬ൕ֒భ‫ؿ‬ള֥࿸ᇗ TWAI ሹཌհ༂đ౏ᄝ TWAI ॥ᇅఖࣉೆФ‫׮‬հ༂ሑ෿ᆭభФԨ‫ؿ‬bEWL +ඔᆴႋᄝ࠷թఖ TWAI_ERR_WARNING_LIMIT_REG ᇏࣉྛ஥ᇂđ஥ᇂ๝ൈ TWAI ॥ᇅఖсྶԩႿ‫໊گ‬ଆൔ༯b +TWAI_ERR_WARNING_LIMIT_REG ଏಪඔᆴູ 96b + +֒ TEC ‫ބ‬/ࠇ REC ඔᆴնႿ֩Ⴟ EWL ඔᆴൈđTWAI_ERR_ST ໊ࡼ৫ࠧФᇂ 1b๝৘đ֒ TEC ‫ ބ‬REC ඔᆴ‫׻‬ +ཬႿ EWL ඔᆴൈđTWAI_ERR_ST ໊ࡼ৫ࠧ‫ ູ໊گ‬0bᆺေ TWAI_ERR_STčࠇ TWAI_BUS_OFF_STĎ໊ᆴ‫ؿ‬ +ളэ߄đь߶Ԩ‫ؿ‬հ༂Бࣞᇏ؎b + +21.5.7.2 Ф‫׮‬հ༂ + +֒ TEC ࠇ REC ඔᆴնႿ 127 ൈđTWAI ॥ᇅఖԩႿФ‫׮‬հ༂ሑ෿b๝৘đ֒ TEC ‫ ބ‬REC ඔᆴ‫ཬ׻‬Ⴟ֩Ⴟ 127 +ൈđTWAI ॥ᇅఖࣉೆᇶ‫׮‬հ༂ሑ෿bૄ֒ TWAI ॥ᇅఖՖᇶ‫׮‬հ༂ሑ෿эູФ‫׮‬հ༂ሑ෿đࠇّᆭൈđ‫ࡼ׻‬Ԩ +‫ؿ‬Ф‫׮‬հ༂ᇏ؎b + + 21.5.7.3 ৖ཌሑ෿ა৖ཌ߫‫گ‬ + + ֒ TEC ඔᆴնႿ 255 ൈđTWAI ॥ᇅఖࡼࣉೆ৖ཌሑ෿bࣉೆ৖ཌሑ෿ުđTWAI ॥ᇅఖࡼሱ‫ྛࣉ׮‬ၛ༯‫׮‬ + ቔğ + + • REC ඔᆴᇂູ 0 + • TEC ඔᆴᇂູ 127 + • TWAI_BUS_OFF_ST ໊ᇂ 1 + • ࣉೆ‫໊گ‬ଆൔ + ૄ֒ TWAI_BUS_OFF_ST ໊čࠇ TWAI_ERR_ST ໊Ďඔᆴ‫ؿ‬ളэ߄ൈđ‫ࡼ׻‬Ԩ‫ؿ‬հ༂Бࣞᇏ؎b + ູਔْ߭ᇶ‫׮‬հ༂ሑ෿đTWAI ॥ᇅఖсྶࣉྛ৖ཌ߫‫گ‬bေఓ‫׮‬৖ཌ߫‫گ‬đ൮༵ླေ๼ԛ‫໊گ‬ଆൔđࣉೆҠቔ + ଆൔbಖުေ౰ TWAI ॥ᇅఖᄝሹཌഈ࡟ҩ֞ 128 Ց 11 ۱৵࿃ႅྟ໊b + ૄ၂Ց TWAI ॥ᇅఖ࡟ҩ֞ 11 ۱৵࿃ႅྟ໊ൈđTEC ඔᆴ‫ཬࡨࡼ׻‬đၛሔሶ৖ཌ߫‫ࣉگ‬ӱb֒৖ཌ߫‫گ‬ປӮު +čTEC ඔᆴՖ 127 ࡨཬ֞ 0ĎđTWAI_BUS_OFF_ST ໊ࡼሱ‫ ູ໊گ׮‬0đՖ‫ط‬Ԩ‫ؿ‬հ༂Бࣞᇏ؎b + +21.5.8 հ༂ѽሚ + +հ༂ѽሚ (ECC) ‫ିۿ‬ᄍྸ TWAI ॥ᇅఖၛհ༂ս઒֥ྙൔ࠺੣ TWAI ሹཌհ༂֥հ༂ো྘‫ ބ‬bit ໊ᇂb֒࡟ҩ֞ +၂۱ TWAI ሹཌհ༂ൈđሹཌհ༂ᇏ؎ࡼФԨ‫ؿ‬đཌྷႋ֥հ༂ս઒ࡼ࠺੣ᄝ TWAI_ERR_CODE_CAP_REG ᇏb +࠷թఖ TWAI_ERR_CODE_CAP_REG ᇏթԥ֥֒భհ༂ս઒Ф‫؀‬౼ᆭభđު࿃֥ሹཌհ༂ᇏ؎Ԩ‫ؿ‬ൈđࡼ҂߶ +ᄜ࠺੣հ༂ս઒b + +༯і 21-16 ෮ൕູ࠷թఖ TWAI_ERR_CODE_CAP_REG ᇏ֥თğ + + і 21­16. TWAI_ERR_CODE_CAP_REG ֥ bit ྐ༏; TWAI ֹᆶ 0x30 + +Bit 31-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 + SEG.4 SEG.3 SEG.2 SEG.1 SEG.0 +Ќ਽ ERRC.1 ERRC.0 DIR + +ඪૼğ + +ুᶈྐ༏॓࠯ 509 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + • հ༂ս઒ (ERRC)ğіൕሹཌհ༂֥ো྘b00 սі໊հ༂đ01 սі۬ൔհ༂đ10 սіแԉհ༂đ11 սі + ః෰հ༂ো྘b + + • Ԯൻٚཟ (DIR)ğіൕሹཌհ༂‫ؿ‬ളൈđTWAI ॥ᇅఖԩႿ‫ؿ‬ෂఖሑ෿ߎ൞ࢤ൬ఖሑ෿b0 սі‫ؿ‬ෂఖđ1 + սіࢤ൬ఖb + + • հ༂‫( ؍‬SEG)ğіൕሹཌհ༂‫ؿ‬ളᄝ TWAI Б໓֥ଧ۱‫؍‬b +༯і 21-17 ෮ൕູ SEG.0 ~ SEG.4 ໊֥ྐ༏b + + і 21­17. SEG.4 ­ SEG.0 ໊֥ྐ༏ + +Bit SEG.4 Bit SEG.3 Bit SEG.2 Bit SEG.1 Bit SEG.0 ૭ඍ + 0 0 0 1 1 ᆠఏ൓ + 0 0 0 1 0 ID.28 ~ ID.21 + 0 0 1 1 0 ID.20 ~ ID.18 + 0 0 1 0 0 bit SRTR + 0 0 1 0 1 bit IDE + 0 0 1 1 1 ID.17 ~ ID.13 + 0 1 1 1 1 ID.12 ~ ID.5 + 0 1 1 1 0 ID.4 ~ ID.0 + 0 1 1 0 0 bit RTR + 0 1 1 0 1 Ќ਽໊ 1 + 0 1 0 0 1 Ќ਽໊ 0 + 0 1 0 1 1 ඔऌӉ؇ս઒ + 0 1 0 1 0 ඔऌთ + 0 1 0 0 0 CRC ྽ਙ + 1 1 0 0 0 CRC ‫ژࢸٳ‬ + 1 1 0 0 1 ಒಪҢ + 1 1 0 1 1 ಒಪ‫ژࢸٳ‬ + 1 1 0 1 0 ᆠࢲඏ + 1 0 0 1 0 ࡗཱུთ + 1 0 0 0 1 ᇶ‫׮‬հ༂ѓᆽ + 1 0 1 1 0 Ф‫׮‬հ༂ѓᆽ + 1 0 0 1 1 ࡙ಸཁྟ໊ + 1 0 1 1 1 հ༂‫ژࢸٳ‬ + 1 1 1 0 0 ‫ݖ‬ᄛѓᆽ + +ඪૼğ + +• Bit SRTR: ѓሙ۬ൔ RTR bitb + +• Bit IDE: ѓ്‫ژ‬ঔᅚ໊b0 іൕѓሙ۬ൔb + +21.5.9 ᇘҊ‫ש‬ാѽሚ + +ᇘҊ‫ש‬ാѽሚ (ALC) ‫ିۿ‬ᄍྸ TWAI ॥ᇅఖ࠺੣‫ש‬ാᇘҊ֥ bit ໊ᇂb֒ TWAI ॥ᇅఖ‫ש‬ാᇘҊൈđbit ໊ᇂࡼФ +࠺੣ᄝ࠷թఖ TWAI_ARB LOST CAP_REG ᇏđ๝ൈԨ‫ؿ‬ᇘҊ‫ש‬ാᇏ؎b + +ު࿃֥ᇘҊ‫ש‬ാᇏ؎Ԩ‫ؿ‬ൈđbit ໊ᇂࡼ҂߶Ф࠺੣ᄝ TWAI_ARB LOST CAP_REG ᇏđᆰ֞ + +ুᶈྐ༏॓࠯ 510 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + +TWAI_ERR_CODE_CAP_REG ᇏ֥֒భᇘҊ‫ש‬ാѽሚФ‫؀‬౼b +༯і 21-18 ෮ൕູ TWAI_ERR_CODE_CAP_REG ᇏ໊֥თĠ༯๭ 21-11 ෮ൕູ၂่ TWAI Б໓֥ bit ໊ +ᇂb + + і 21­18. TWAI_ARB LOST CAP_REG ᇏ໊֥ྐ༏; TWAI ֹᆶ 0x2c + +Bit 31-5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 +Ќ਽ BITNO.4 BITNO.3 BITNO.2 BITNO.1 BITNO.0 + +ඪૼğ + +• ໊‫( ݼ‬BITNO)ğіൕ‫ש‬ാᇘҊ֥ TWAI Б໓ֻ֥ n ۱໊b + + ๭ 21­11. ‫ש‬ാᇘҊ֥ bit ໊ᇂ + +21.6 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + + ଀ӫ ଆൔ࠷թఖ 0x3FF6B000 ‫؀‬/ཿ + ஥ᇂ࠷թఖ ൈ྽஥ᇂ࠷թఖ 0 0x3FF6B018 ᆺ‫؀ | ؀‬/ཿ + TWAI_MODE_REG ൈ྽஥ᇂ࠷թఖ 1 0x3FF6B01C ᆺ‫؀ | ؀‬/ཿ + TWAI_BUS_TIMING_0_REG հ༂࠷թఖ 0x3FF6B034 ᆺ‫؀ | ؀‬/ཿ + TWAI_BUS_TIMING_1_REG ඔऌ࠷թఖ 0 0x3FF6B040 ᆺཿ | ‫؀‬/ཿ + TWAI_ERR_WARNING_LIMIT_REG ඔऌ࠷թఖ 1 0x3FF6B044 ᆺཿ | ‫؀‬/ཿ + TWAI_DATA_0_REG ඔऌ࠷թఖ 2 0x3FF6B048 ᆺཿ | ‫؀‬/ཿ + TWAI_DATA_1_REG ඔऌ࠷թఖ 3 0x3FF6B04C ᆺཿ | ‫؀‬/ཿ + TWAI_DATA_2_REG ඔऌ࠷թఖ 4 0x3FF6B050 ᆺཿ | ‫؀‬/ཿ + TWAI_DATA_3_REG ඔऌ࠷թఖ 5 0x3FF6B054 ᆺཿ | ‫؀‬/ཿ + TWAI_DATA_4_REG ඔऌ࠷թఖ 6 0x3FF6B058 ᆺཿ | ‫؀‬/ཿ + TWAI_DATA_5_REG ඔऌ࠷թఖ 7 0x3FF6B05C ᆺཿ | ‫؀‬/ཿ + TWAI_DATA_6_REG ඔऌ࠷թఖ 8 0x3FF6B060 ᆺཿ | ᆺ‫؀‬ + TWAI_DATA_7_REG ඔऌ࠷թఖ 9 0x3FF6B064 ᆺཿ | ᆺ‫؀‬ + TWAI_DATA_8_REG ඔऌ࠷թఖ 10 0x3FF6B068 ᆺཿ | ᆺ‫؀‬ + TWAI_DATA_9_REG ඔऌ࠷թఖ 11 0x3FF6B06C ᆺཿ | ᆺ‫؀‬ + TWAI_DATA_10_REG ඔऌ࠷թఖ 12 0x3FF6B070 ᆺཿ | ᆺ‫؀‬ + TWAI_DATA_11_REG ൈᇒ‫ٳ‬௔࠷թఖ 0x3FF6B07C ҂‫ק‬ + TWAI_DATA_12_REG + TWAI_CLOCK_DIVIDER_REG ᆷ਷࠷թఖ 0x3FF6B004 ᆺཿ + ॥ᇅ࠷թఖ + TWAI_CMD_REG ሑ෿࠷թఖ 0x3FF6B008 ᆺ‫؀‬ + ሑ෿࠷թఖ + TWAI_STATUS_REG + +ুᶈྐ༏॓࠯ 511 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) ૭ඍ ֹᆶ ٠໙ + ᇘҊ‫ש‬ാ࠷թఖ 0x3FF6B02C ᆺ‫؀‬ + ଀ӫ հ༂ѽࠆ࠷թఖ 0x3FF6B030 ᆺ‫؀‬ + TWAI_ARB_LOST_CAP_REG ࢤ൬հ༂࠷թఖ 0x3FF6B038 ᆺ‫؀ | ؀‬/ཿ + TWAI_ERR_CODE_CAP_REG ‫ؿ‬ෂհ༂࠷թఖ 0x3FF6B03C ᆺ‫؀ | ؀‬/ཿ + TWAI_RX_ERR_CNT_REG ࢤ൬ඔऌ࠷թఖ 0x3FF6B074 ᆺ‫؀‬ + TWAI_TX_ERR_CNT_REG + TWAI_RX_MESSAGE_CNT_REG ᇏ؎࠷թఖ 0x3FF6B00C ᆺ‫؀‬ + ᇏ؎࠷թఖ ᇏ؎൐ି࠷թఖ 0x3FF6B010 ‫؀‬/ཿ + TWAI_INT_RAW_REG + TWAI_INT_ENA_REG + +21.7 ࠷թఖ + + Register 21.1. TWAI_MODE_REG (0x0000) + + (reserved) TWAI_TRWXA_IF_TISLWTEEALRIF_T__LWTMISEAOTSI_EDTRNE_EM_SOOENDTLE_YM_MODOEDE + +31 43 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset + + TWAI_RESET_MODE ஥ᇂ TWAI ॥ᇅఖҠቔଆൔb1ğ‫໊گ‬ଆൔĠ0ğҠቔଆൔč‫؀‬/ཿĎ + + TWAI_LISTEN_ONLY_MODE ᇂ 1 ࣉೆᆺ๐ଆൔđԩႿ‫ھ‬ଆൔ༯֥ࢫׄᆺࢤ൬ሹཌഈඔऌđ҂Ӂള + ႋճྐ‫ݼ‬đ္҂۷ྍࢤ൬հ༂࠹ඔbč‫؀‬/ཿĎ + + TWAI_SELF_TEST_MODE ᇂ 1 ఓ‫׮‬ሱҩଆൔđՎଆൔ༯‫ؿ‬ෂࢫׄ‫ؿ‬ෂປඔऌު໭ླႋճྐ‫ّݼ‬ + ঌb‫ھ‬ଆൔӈ஥‫ކ‬ሱࢤሱ൬ᆷ਷ҩ൫ଖ۱ࢫׄbč‫؀‬/ཿĎ + + TWAI_RX_FILTER_MODE ஥ᇂੲѯଆൔb0: චੲѯଆൔĠ1: ֆੲѯଆൔč‫؀‬/ཿĎ + + Register 21.2. TWAI_BUS_TIMING_0_REG (0x0018) + + (reserved) TWAI_SYNC_JUMP_WTIDWTAHI_BAUD_PRESC + +31 87 65 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 Reset + + TWAI_BAUD_PRESC ყ‫ٳ‬௔ᆴđथ‫ٳק‬௔б২bčᆺ‫؀ | ؀‬/ཿĎ + TWAI_SYNC_JUMP_WIDTH ๝๋҄ॺ ( SJW )đٓຶູ 1 ~ 4 ۱ൈࡗ‫حק‬bčᆺ‫؀ | ؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 512 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.3. TWAI_BUS_TIMING_1_REG (0x001C) + + (reserved) TWAI_TIMET_WSAAMI_PTIME_SEG2 TWAI_TIME_SEG1 + +31 876 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0x0 0x0 Reset + + TWAI_TIME_SEG1 ߏԊൈ௹‫ ؍‬1 ֥ॺ؇bčᆺ‫؀ | ؀‬/ཿĎ + TWAI_TIME_SEG2 ߏԊൈ௹‫ ؍‬2 ֥ॺ؇bčᆺ‫؀ | ؀‬/ཿĎ + TWAI_TIME_SAMP Ґဢׄඔଢb0ğҐဢ 1 ՑĠ1ğҐဢ೘Ցčᆺ‫؀ | ؀‬/ཿĎ + + Register 21.4. TWAI_ERR_WARNING_LIMIT_REG (0x0034) + + (reserved) TWAI_ERR_WARNING_LIMIT + +31 87 0 + +000000000000000000000000 0x60 Reset + + TWAI_ERR_WARNING_LIMIT հ༂Бࣞᚐᆴđ֒಩၂հ༂࠹ඔඔᆴӑ‫ھݖ‬ᚐᆴࠇᆀ෮Ⴕհ༂࠹ඔ + ඔᆴ‫ཬ׻‬Ⴟ‫ھ‬ᚐᆴൈđࡼԨ‫ؿ‬հ༂Бࣞᇏ؎č൐ିྐ‫ݼ‬Ⴕི౦ঃ༯Ďbčᆺ‫؀ | ؀‬/ཿĎ + + Register 21.5. TWAI_DATA_0_REG (0x0040) + + (reserved) TWAI_TX_BYTE_0 | TWAI_ACCEPTANCE_CODE_0 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_0 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 0 ۱ሳࢫଽಸbčᆺཿĎ + TWAI_ACCEPTANCE_CODE_0 ‫໊گ‬ଆൔ༯đթԥሢੲѯщ઒ֻ֥ 0 ۱ሳࢫbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 513 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.6. TWAI_DATA_1_REG (0x0044) + + (reserved) TWAI_TX_BYTE_1 | TWAI_ACCEPTANCE_CODE_1 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_1 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 1 ۱ሳࢫଽಸbčᆺཿĎ + TWAI_ACCEPTANCE_CODE_1 ‫໊گ‬ଆൔ༯đթԥሢੲѯщ઒ֻ֥ 1 ۱ሳࢫbč‫؀‬/ཿĎ + + Register 21.7. TWAI_DATA_2_REG (0x0048) + + (reserved) TWAI_TX_BYTE_2 | TWAI_ACCEPTANCE_CODE_2 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_2 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 2 ۱ሳࢫଽಸbčᆺཿĎ + TWAI_ACCEPTANCE_CODE_2 ‫໊گ‬ଆൔ༯đթԥሢੲѯщ઒ֻ֥ 2 ۱ሳࢫbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 514 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.8. TWAI_DATA_3_REG (0x004C) + + (reserved) TWAI_TX_BYTE_3 | TWAI_ACCEPTANCE_CODE_3 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_3 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 3 ۱ሳࢫଽಸbčᆺཿĎ + TWAI_ACCEPTANCE_CODE_3 ‫໊گ‬ଆൔ༯đթԥሢੲѯщ઒ֻ֥ 3 ۱ሳࢫbč‫؀‬/ཿĎ + + Register 21.9. TWAI_DATA_4_REG (0x0050) + + (reserved) TWAI_TX_BYTE_4 | TWAI_ACCEPTANCE_MASK_0 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_4 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 4 ۱ሳࢫଽಸbčᆺཿĎ + TWAI_ACCEPTANCE_MASK_0 ‫໊گ‬ଆൔ༯đթԥሢੲѯщ઒ֻ֥ 0 ۱ሳࢫbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 515 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.10. TWAI_DATA_5_REG (0x0054) + + (reserved) TWAI_TX_BYTE_5 | TWAI_ACCEPTANCE_MASK_1 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_5 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 5 ۱ሳࢫଽಸbčᆺཿĎ + TWAI_ACCEPTANCE_MASK_1 ‫໊گ‬ଆൔ༯đթԥሢੲѯщ઒ֻ֥ 1 ۱ሳࢫbč‫؀‬/ཿĎ + + Register 21.11. TWAI_DATA_6_REG (0x0058) + + (reserved) TWAI_TX_BYTE_6 | TWAI_ACCEPTANCE_MASK_2 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_6 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 6 ۱ሳࢫଽಸbčᆺཿĎ + TWAI_ACCEPTANCE_MASK_2 ‫໊گ‬ଆൔ༯đթԥሢੲѯщ઒ֻ֥ 2 ۱ሳࢫbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 516 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.12. TWAI_DATA_7_REG (0x005C) + + (reserved) TWAI_TX_BYTE_7 | TWAI_ACCEPTANCE_MASK_3 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_7 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 7 ۱ሳࢫଽಸbčᆺཿĎ + TWAI_ACCEPTANCE_MASK_3 ‫໊گ‬ଆൔ༯đթԥሢੲѯщ઒ֻ֥ 3 ۱ሳࢫbč‫؀‬/ཿĎ + + Register 21.13. TWAI_DATA_8_REG (0x0060) + + (reserved) TWAI_TX_BYTE_8 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_8 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 8 ۱ሳࢫଽಸbčᆺཿĎ + + Register 21.14. TWAI_DATA_9_REG (0x0064) + + (reserved) TWAI_TX_BYTE_9 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_9 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 9 ۱ሳࢫଽಸbčᆺཿĎ + +ুᶈྐ༏॓࠯ 517 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.15. TWAI_DATA_10_REG (0x0068) + + (reserved) TWAI_TX_BYTE_10 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_10 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 10 ۱ሳࢫଽಸbčᆺཿĎ + + Register 21.16. TWAI_DATA_11_REG (0x006C) + + (reserved) TWAI_TX_BYTE_11 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_11 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 11 ۱ሳࢫଽಸbčᆺཿĎ + + Register 21.17. TWAI_DATA_12_REG (0x0070) + + (reserved) TWAI_TX_BYTE_12 + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_BYTE_12 Ҡቔଆൔ༯đթԥሢր‫ؿ‬ෂඔऌֻ֥ 12 ۱ሳࢫଽಸbčᆺཿĎ + +ুᶈྐ༏॓࠯ 518 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.18. TWAI_CLOCK_DIVIDER_REG (0x007C) + + (reserved) TWAI_EXT_(MreOseDrvEed) TWAI_CLOCTWK_AOI_FCFD + +31 876 432 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0 0 0x0 Reset + + TWAI_CD ஥ᇂൻԛൈᇒ CLKOUT ֥‫ٳ‬௔༢ඔbč‫؀‬/ཿĎ + + TWAI_CLOCK_OFF ‫໊گ‬ଆൔ༯ॖ஥b1ğܱоൻԛ֥ CLKOUT ൈᇒĠ0ğյष CLKOUT ൈᇒčᆺ + ‫؀ | ؀‬/ཿĎ + + TWAI_EXT_MODE ‫໊گ‬ଆൔ༯ॖ஥đଏಪᆴູ 1b0ğࠎԤଆൔĠ1ğঔᅚଆൔđ࡙ಸ CAN 2.0Bčᆺ + ‫؀ | ؀‬/ཿĎ + + Register 21.19. TWAI_CMD_REG (0x0004) + + (reserved) TWAI_TSWEALIF_T_CWRLXAR_I__TRORWEEVQALEIER_TAARWSBUAEONI__RBTTUX__FTRXEQ + +31 54 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + TWAI_TX_REQ ᇂ 1 ౺‫ׄࢫ׮‬ष൓‫ؿ‬ෂඔऌ಩ༀbčᆺཿĎ + TWAI_ABORT_TX ᇂ 1 ౼ཨ֒భߎໃष൓֥‫ؿ‬ෂ಩ༀbčᆺཿĎ + TWAI_RELEASE_BUF ᇂ 1 ൤٢ࢤ൬ߏԊఖbčᆺཿĎ + TWAI_CLR_OVERRUN ᇂ 1 ౢԢඔऌၮԛሑ෿bčᆺཿĎ + TWAI_SELF_RX_REQ ሱࢤሱ൬ଁ਷bᇂ 1 ᄍྸ‫ؿ‬ෂࢫׄ‫ؿ‬ෂඔऌ֥๝ൈࢤ൬ሹཌഈ֥ඔऌbčᆺ + + ཿĎ + +ুᶈྐ༏॓࠯ 519 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.20. TWAI_STATUS_REG (0x0008) + + (reserved) TWAI_TBWUASI__TEOWRFARFI___TSSTWXTTA_SI_TTRWXA_IS_TTTWXA_CI_TOTWXMA_PBI_TLUOWEFVTA_EESIR_TRRXU_NB_USFT_ST + +31 87 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 Reset + + TWAI_RX_BUF_ST ೏ᆴູ 1đіૼࢤ൬ߏԊఖᇏඔऌ҂ູॢđᇀഒႵ၂۱ၘࣜࢤ൬֥֞ඔऌЇbčᆺ + ‫؀‬Ď + + TWAI_OVERRUN_ST ೏ᆴູ 1đіૼࢤ൬ FIFO ᇏթԥ֥ඔऌၘડđӁളਔၮԛbčᆺ‫؀‬Ď + TWAI_TX_BUF_ST ೏ᆴູ 1đіૼ‫ؿ‬ෂߏԊఖູॢđᄍྸཿೆր‫ؿ‬ෂඔऌbčᆺ‫؀‬Ď + TWAI_TX_COMPLETE ೏ᆴູ 1đіૼӮ‫ۿ‬Ֆሹཌഈࢤ൬֞၂۱ඔऌЇbčᆺ‫؀‬Ď + TWAI_RX_ST ೏ᆴູ 1đіૼࢫׄᆞᄝՖሹཌഈࢤ൬ඔऌbčᆺ‫؀‬Ď + TWAI_TX_ST ೏ᆴູ 1đіૼࢫׄᆞᄝສሹཌഈ‫ؿ‬ෂඔऌbčᆺ‫؀‬Ď + TWAI_ERR_ST ೏ᆴູ 1đіૼࢤ൬հ༂࠹ඔ‫ؿބ‬ෂհ༂࠹ඔᇏᇀഒႵ၂۱ඔᆴնႿ֩Ⴟ࠷թఖ + + TWAI_ERR_WARNING_LIMIT_REG ᇏ஥ᇂ֥ඔᆴčᆺ‫؀‬Ď + TWAI_BUS_OFF_ST ೏ᆴູ 1đіૼࢫׄԩႿ৖ཌሑ෿đ҂ᄜཙႋሹཌഈ֥ඔऌԮൻbčᆺ‫؀‬Ď + + Register 21.21. TWAI_ARB LOST CAP_REG (0x002C) + + (reserved) TWAI_ARB_LOST_CAP + +31 54 0 + +000000000000000000000000000 0x0 Reset + + TWAI_ARB_LOST_CAP ࠺੣ሢ‫ؿ‬ෂࢫׄᇘҊ‫ש‬ാ֥ bit ໊ᇂbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 520 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.22. TWAI_ERR_CODE_CAP_REG (0x0030) + + (reserved) TWAI_ECTCW_ATIY_EPCEC_DIRETCWTIAOI_NECC_SEGMENT + +31 87 654 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0x0 Reset + + TWAI_ECC_SEGMENT ࠺੣հ༂‫ؿ‬ള໊֥ᇂđབྷ࡮і 21-16bčᆺ‫؀‬Ď + TWAI_ECC_DIRECTION ࠺੣հ༂ൈࢫ֥ׄඔऌԮൻٚཟb1ğࢤ൬ඔऌൈ‫ؿ‬ളհ༂Ġ0ğ‫ؿ‬ෂඔऌ + + ൈ‫ؿ‬ളհ༂čᆺ‫؀‬Ď + + TWAI_ECC_TYPE ࠺੣հ༂োљğ00ğ໊հ༂Ġ01ğ۬ൔհ༂Ġ10ğแԉհ༂Ġ11ğః෰հ-čᆺ‫؀‬Ď + + Register 21.23. TWAI_RX_ERR_CNT_REG (0x0038) + + (reserved) TWAI_RX_ERR_CNT + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_RX_ERR_CNT ࢤ൬հ༂࠹ඔđඔᆴэ߄‫ؿ‬ളᄝࢤ൬ሑ෿༯bčᆺ‫؀ | ؀‬/ཿĎ + + Register 21.24. TWAI_TX_ERR_CNT_REG (0x003C) + + (reserved) TWAI_TX_ERR_CNT + +31 87 0 + +000000000000000000000000 0x0 Reset + + TWAI_TX_ERR_CNT ‫ؿ‬ෂհ༂࠹ඔđඔᆴэ߄‫ؿ‬ളᄝ‫ؿ‬ෂሑ෿༯bčᆺ‫؀ | ؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 521 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.25. TWAI_RX_MESSAGE_CNT_REG (0x0074) + + (reserved) TWAI_RX_MESSAGE_COUNTER + +31 76 0 + +0000000000000000000000000 0x0 Reset + + TWAI_RX_MESSAGE_COUNTER թԥሢࢤ൬ FIFO ᇏඔऌЇ֥۱ඔbčᆺ‫؀‬Ď + + Register 21.26. TWAI_INT_RAW_REG (0x000C) + + (reserved) TWAI_TBWUASI__TAEWRRABRI___(rELIeNORsTeRS_r_TvSTPe_WTAdINA)STIS__TOISWVVTEAE_IIR_TNERWTRU_ARSNI__TT_WTWINXAA_TRII_N_NSRT_TX_INS_ITTN_TS_TST + +31 87 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + TWAI_RX_INT_ST ࢤ൬ᇏ؎b೏ᆴູ 1đіૼࢤ൬ FIFO ҂ູॢđႵࢤ൬ඔऌրԩ৘bčᆺ‫؀‬Ď + + TWAI_TX_INT_ST ‫ؿ‬ෂᇏ؎b೏ᆴູ 1đіૼࢫׄඔऌ‫ؿ‬ෂ಩ༀࢲඏđॖၛᆳྛྍ֥ඔऌ‫ؿ‬ෂ಩ + ༀbčᆺ‫؀‬Ď + + TWAI_ERR_WARN_INT_ST հ༂Бࣞᇏ؎b೏ᆴູ 1đіૼሑ෿࠷թఖᇏհ༂ሑ෿ྐ‫ބݼ‬৖ཌྐ‫ݼ‬ + ‫ؿ‬ളэ߄č0 эູ 1 ࠇ 1 эູ 0Ďbčᆺ‫؀‬Ď + + TWAI_OVERRUN_INT_ST ඔऌၮԛᇏ؎b೏ᆴູ 1đіૼ֒భࢤ൬ߏթᇏթԥ֥Б໓ູၮԛാི + Б໓bčᆺ‫؀‬Ď + + TWAI_ERR_PASSIVE_INT_ST Ф‫׮‬հ༂ᇏ؎b೏ᆴູ 1đіૼࢫׄႮႿհ༂࠹ඔඔᆴ֥э߄đᄝᇶ + ‫׮‬հ༂ሑ෿აФ‫׮‬հ༂ሑ෿ࡗ‫ؿ‬ളਔ్ߐbčᆺ‫؀‬Ď + + TWAI_ARB_LOST_INT_ST ᇘҊ‫ש‬ാᇏ؎b೏ᆴູ 1đіૼ‫ؿ‬ෂࢫׄ‫ש‬ാᇘҊbčᆺ‫؀‬Ď + + TWAI_BUS_ERR_INT_ST հ༂ᇏ؎b೏ᆴູ 1đіૼࢫׄ࡟ҩ֞ሹཌഈ‫ؿ‬ളਔհ༂bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 522 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 21 චཌచӚࢤ१ (TWAI) + + Register 21.27. TWAI_INT ENA_REG (0x0010) + + (reserved) TWAI_TBWUASI__TAEWRRABRI___(rELIeNORsTeRS_r_TvETPe_WNAdINAA)STIS__TOIEWVNVEAEA_IIR_TNERWTRU_ARENI__TN_WTWIANXAA_TRII_N_NERTN_X_IANE_INTN_ATE_NEANA + +31 87 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + TWAI_RX_INT_ENA ᇂ 1 ൐ିࢤ൬ᇏ؎bč‫؀‬/ཿĎ + TWAI_TX_INT_ENA ᇂ 1 ൐ି‫ؿ‬ෂᇏ؎bč‫؀‬/ཿĎ + TWAI_ERR_WARN_INT_ENA ᇂ 1 ൐ିհ༂Бࣞᇏ؎bč‫؀‬/ཿĎ + TWAI_OVERRUN_INT_ENA ᇂ 1 ൐ିඔऌၮԛᇏ؎bč‫؀‬/ཿĎ + TWAI_ERR_PASSIVE_INT_ENA ᇂ 1 ൐ିФ‫׮‬հ༂ᇏ؎bč‫؀‬/ཿĎ + TWAI_ARB_LOST_INT_ENA ᇂ 1 ൐ିᇘҊ‫ש‬ാᇏ؎bč‫؀‬/ཿĎ + TWAI_BUS_ERR_INT_ENA ᇂ 1 ൐ିհ༂ᇏ؎bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 523 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 22 AES ࡆ෎ఖ (AES) + +22 AES ࡆ෎ఖ (AES) + +22.1 ‫ۀ‬ඍ + +ESP32 ଽᇂ AESčۚࠩࡆૡѓሙĎࡆ෎ఖđཌྷбႿᆺႨೈࡱࣉྛ AES ᄎෘđAES ࡆ෎ఖି‫ࠞܔ‬նֹิۚᄎෘ +෎؇bAES ࡆ෎ఖᆦӻ FIPS PUB 197 ѓሙđି‫ܔ‬ൌགྷ AES-128đAES-192đAES-256 ࡆૡაࢳૡᄎෘb + +22.2 ᇶေหྟ + + • ᆦӻ AES-128 ࡆࢳૡᄎෘ + • ᆦӻ AES-192 ࡆࢳૡᄎෘ + • ᆦӻ AES-256 ࡆࢳૡᄎෘ + • ᆦӻ 4 ᇕૡᄂሳࢫ྽‫ ބ‬4 ᇕ໓Чሳࢫ྽ + +22.3 ‫ିۿ‬૭ඍ + +22.3.1 ᄎෘଆൔ + +AES ࡆ෎ఖᆦӻ AES-128/192/256 ࡆࢳૡ 6 ᇕᄎෘb஥ᇂ࠷թఖ AES_MODE_REG ၛൌགྷ҂๝ᄎෘb࠷թఖ +AES_MODE_REG ֥ᆴა۲ᇕᄎෘ֥ؓႋܱ༢ೂі 22-1 ෮ൕb + + і 22­1. ᄎෘଆൔ + +AES_MODE_REG[2:0] ᄎෘ +0 AES-128 ࡆૡ +1 AES-192 ࡆૡ +2 AES-256 ࡆૡ +4 AES-128 ࢳૡ +5 AES-192 ࢳૡ +6 AES-256 ࢳૡ + +22.3.2 ૡᄂaૼ໓aૡ໓ + +࠷թఖ AES_KEY_n_REG թ٢ૡᄂbૄ۱࠷թఖ໊ॺ‫׻‬൞ 32 ໊đ‫܋‬Ⴕ 8 ۱࠷թఖbೂ‫ ູݔ‬AES-128 ࡆࢳૡᄎ +ෘđᄵ 128 ໊ૡᄂᄝ࠷թఖ AES_KEY_0_REG ~ AES_KEY_3_REG ᇏbೂ‫ ູݔ‬AES-192 ࡆࢳૡᄎෘđᄵ 192 +໊ૡᄂᄝ࠷թఖ AES_KEY_0_REG ~ AES_KEY_5_REG ᇏbೂ‫ ູݔ‬AES-256 ࡆࢳૡᄎෘđᄵ 256 ໊ૡᄂᄝ࠷ +թఖ AES_KEY_0_REG ~ AES_KEY_7_REG ᇏb + +࠷թఖ AES_TEXT_m_REG թ٢ૼ໓ࠇૡ໓bૄ۱࠷թఖ໊ॺ‫׻‬൞ 32 ໊đ‫܋‬Ⴕ 4 ۱࠷թఖbೂ‫ູݔ‬ +AES-128/192/265 ࡆૡᄎෘđᄵᄎෘष൓ᆭభႨૼ໓Ԛ൓߄࠷թఖ AES_TEXT_m_REGbᄎෘປӮᆭުđAES +ࡆ෎ఖࡼϜૡ໓۷ྍೆ࠷թఖ AES_TEXT_m_REGbೂ‫ ູݔ‬AES-128/192/256 ࢳૡᄎෘđᄵᄎෘष൓ᆭభႨૡ +໓Ԛ൓߄࠷թఖ AES_TEXT_m_REGbᄎෘປӮᆭުđAES ࡆ෎ఖࡼϜૼ໓۷ྍೆ࠷թఖ +AES_TEXT_m_REGb + +22.3.3 ሳࢫ྽ + +ૡᄂሳࢫ྽ + +࠷թఖ AES_ENDIAN_REG ֥ Bit 0aBit 1 ॥ᇅૡᄂ֥ሳࢫ྽đऎุ࡮і 22-3aі 22-4aі 22-5bі 22-3 ᇏ +֥ w[0] ~ w[3]aі 22-4 ᇏ֥ w[0] ~ w[5]aі 22-5 ᇏ֥ w[0] ~ w[7] ࢥູѓሙ FIPS PUB 197 ᇏo5.2 Key + +ুᶈྐ༏॓࠯ 524 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 22 AES ࡆ෎ఖ (AES) + +Expansionp෮ඍothe first Nk words of the expanded keypbBit ၂ਙᆷૼ w[0] ~ w[7] ૄ۱ word ᇏ֥۲۱ሳࢫb +೘ᅦііૼਔᄝඹᇕ҂๝ሳࢫ྽༯đ࠷թఖ AES_KEY_n_REG ᇏ֥ૄ۱ሳࢫೂ‫ܒޅ‬Ӯothe first Nk words of the +expanded keypb + +໓Чሳࢫ྽ + +࠷թఖ AES_ENDIAN_REG ֥ Bit 2aBit 3 ॥ᇅൻೆ໓Ч֥ሳࢫ྽đBit 4aBit 5 ॥ᇅൻԛ໓Ч֥ሳࢫ྽bൻೆ໓ +Чᄝ AES-128/192/256 ࡆૡᄎෘൈᆷ֥൞ૼ໓đᄝ AES-128/192/256 ࢳૡᄎෘൈᆷ֥൞ૡ໓bൻԛ໓Чᄝ +AES-128/192/256 ࡆૡᄎෘൈᆷ֥൞ૡ໓đᄝ AES-128/192/256 ࢳૡᄎෘൈᆷ֥൞ૼ໓bऎุ࡮і 22-2bі +22-2 ᇏ֥ State ູѓሙ FIPS PUB 197 ᇏo3.4 The Statep෮ඍothe AES algorithm’s operations are performed +on a tow-dimensional array of bytes called the StatepbՎііૼਔᄝඹᇕ҂๝ሳࢫ྽༯đ࠷թఖ +AES_TEXT_m_REG ᇏ֥ૄ۱ሳࢫ෮թ٢֥ૼ໓ࠇૡ໓ೂ‫ܒޅ‬Ӯ Stateb + + і 22­2. AES ໓Чሳࢫ྽ + +AES_ENDIAN_REG[3]/[5] AES_ENDIAN_REG[2]/[4] Plaintext/Ciphertext +0 0 +0 1 State c +1 0 +1 1 0 0 1 2 3 + 1 AES_TEXT_3_REG[31:24] AES_TEXT_0_REG[31:24] + r AES_TEXT_3_REG[23:16] AES_TEXT_2_REG[31:24] AES_TEXT_1_REG[31:24] AES_TEXT_0_REG[23:16] + 2 AES_TEXT_3_REG[15:8] AES_TEXT_0_REG[15:8] + 3 AES_TEXT_3_REG[7:0] AES_TEXT_2_REG[23:16] AES_TEXT_1_REG[23:16] AES_TEXT_0_REG[7:0] + + State 0 AES_TEXT_2_REG[15:8] AES_TEXT_1_REG[15:8] 3 + AES_TEXT_3_REG[7:0] AES_TEXT_0_REG[7:0] + 0 AES_TEXT_3_REG[15:8] AES_TEXT_2_REG[7:0] AES_TEXT_1_REG[7:0] AES_TEXT_0_REG[15:8] + 1 AES_TEXT_3_REG[23:16] AES_TEXT_0_REG[23:16] + r AES_TEXT_3_REG[31:24] c AES_TEXT_0_REG[31:24] + 2 + 3 0 1 2 3 + AES_TEXT_0_REG[31:24] AES_TEXT_3_REG[31:24] + State AES_TEXT_0_REG[23:16] AES_TEXT_2_REG[7:0] AES_TEXT_1_REG[7:0] AES_TEXT_3_REG[23:16] + AES_TEXT_0_REG[15:8] AES_TEXT_3_REG[15:8] + 0 AES_TEXT_0_REG[7:0] AES_TEXT_2_REG[15:8] AES_TEXT_1_REG[15:8] AES_TEXT_3_REG[7:0] + 1 + r 0 AES_TEXT_2_REG[23:16] AES_TEXT_1_REG[23:16] 3 + 2 AES_TEXT_0_REG[7:0] AES_TEXT_3_REG[7:0] + 3 AES_TEXT_0_REG[15:8] AES_TEXT_2_REG[31:24] AES_TEXT_1_REG[31:24] AES_TEXT_3_REG[15:8] + AES_TEXT_0_REG[23:16] AES_TEXT_3_REG[23:16] + State AES_TEXT_0_REG[31:24] c AES_TEXT_3_REG[31:24] + + 0 1 2 + 1 + r AES_TEXT_1_REG[31:24] AES_TEXT_2_REG[31:24] + 2 + 3 AES_TEXT_1_REG[23:16] AES_TEXT_2_REG[23:16] + + AES_TEXT_1_REG[15:8] AES_TEXT_2_REG[15:8] + + AES_TEXT_1_REG[7:0] AES_TEXT_2_REG[7:0] + + c + + 1 2 + + AES_TEXT_1_REG[7:0] AES_TEXT_2_REG[7:0] + + AES_TEXT_1_REG[15:8] AES_TEXT_2_REG[15:8] + + AES_TEXT_1_REG[23:16] AES_TEXT_2_REG[23:16] + + AES_TEXT_1_REG[31:24] AES_TEXT_2_REG[31:24] + +ুᶈྐ༏॓࠯ 525 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + ুᶈྐ༏॓࠯ і 22­3. AES­128 ૡᄂሳࢫ྽ 22 AES ࡆ෎ఖ (AES) + + AES_ENDIAN_REG[1] AES_ENDIAN_REG[0] Bit w[0] w[1] w[2] w[3] + 0 0 [31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] + 0 1 [23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] + 1 0 [15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] + 1 1 [7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] + [31:24] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] + [23:16] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] + [15:8] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] + [7:0] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] + [31:24] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] + [23:16] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] + [15:8] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] + [7:0] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] + [31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] + [23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] + [15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] + [7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] + + і 22­4. AES­192 ૡᄂሳࢫ྽ + + 526 AES_ENDIAN_REG[1] AES_ENDIAN_REG[0] Bit w[0] w[1] w[2] w[3] w[4] w[5] +ّঌ໓֖ၩ࡮ 0 0 [31:24] AES_KEY_5_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] + 0 1 [23:16] AES_KEY_5_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] + 1 0 [15:8] AES_KEY_5_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] + 1 1 [7:0] AES_KEY_5_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] + [31:24] AES_KEY_5_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] + [23:16] AES_KEY_5_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] + [15:8] AES_KEY_5_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] + [7:0] AES_KEY_5_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] + [31:24] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] + [23:16] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] + [15:8] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] + [7:0] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] + [31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] + [23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] + [15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] + [7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] + +ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) і 22­5. AES­256 ૡᄂሳࢫ྽ + + AES_ENDIAN_REG[1] AES_ENDIAN_REG[0] Bit w[0] w[1] w[2] w[3] w[4] w[5] w[6] w[7] + 0 0 [31:24] AES_KEY_7_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] + 0 1 [23:16] AES_KEY_7_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] + 1 0 [15:8] AES_KEY_7_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] + 1 1 [7:0] AES_KEY_7_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] + [31:24] AES_KEY_7_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0] + [23:16] AES_KEY_7_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8] + [15:8] AES_KEY_7_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16] + [7:0] AES_KEY_7_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24] + [31:24] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_7_REG[31:24] + [23:16] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_7_REG[23:16] + [15:8] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_7_REG[15:8] + [7:0] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_7_REG[7:0] + [31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_7_REG[7:0] + [23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_7_REG[15:8] + [15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_7_REG[23:16] + [7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_7_REG[31:24] + 22 AES ࡆ෎ఖ (AES) + +22.3.4 ࡆૡაࢳૡᄎෘ + +ֆՑᄎෘ + 1. Ԛ൓߄࠷թఖ AES_MODE_REGaAES_KEY_n_REGaAES_TEXT_m_REGaAES_ENDIAN_REGb + 2. ؓ࠷թఖ AES_START_REG ཿೆ 1b + 3. ੽࿘࠷թఖ AES_IDLE_REGđᆰ֞Ֆ࠷թఖ AES_IDLE_REG ‫؀‬ԛ 1b + 4. Ֆ࠷թఖ AES_TEXT_m_REG ‫؀‬౼ࢲ‫ݔ‬b + +৵࿃ᄎෘ +ૄՑᄎෘປӮᆭުđᆺႵ࠷թఖ AES_TEXT_m_REG ߶Ф AES ࡆ෎ఖ۷ྍđࠧ࠷թఖ AES_MODE_REGa +AES_KEY_n_REGaAES_ENDIAN_REG ᇏ֥ଽಸ҂߶э߄b෮ၛࣉྛ৵࿃ᄎෘൈॖၛࡥ߄Ԛ൓߄Ҡቔb + + 1. ۷ྍ࠷թఖ AES_MODE_REGaAES_KEY_n_REGaAES_ENDIAN_REG ᇏླေ۷ྍ֥đఃჅ҂ቓэ‫׮‬b + 2. ۷ྍ࠷թఖ AES_TEXT_m_REGb + 3. ؓ࠷թఖ AES_START_REG ཿೆ 1b + 4. ੽࿘࠷թఖ AES_IDLE_REGđᆰ֞Ֆ࠷թఖ AES_IDLE_REG ‫؀‬ԛ 1b + 5. Ֆ࠷թఖ AES_TEXT_m_REG ‫؀‬౼ࢲ‫ݔ‬b + +22.3.5 ᄎྛིੱ + +AES ૄࡆૡ၂۱ྐ༏ॶླေ 11 ~ 15 ۱ൈᇒᇛ௹đૄࢳૡ၂۱ྐ༏ॶླေ 21 ࠇ 22 ۱ൈᇒᇛ௹b + +22.4 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + + ଀ӫ AES ࡆ෎ఖ֥ᄎෘଆൔ 0x3FF01008 ‫؀‬Ĕཿ + ஥ᇂ࠷թఖ ሳࢫ྽஥ᇂ࠷թఖ 0x3FF01040 ‫؀‬Ĕཿ + AES_MODE_REG + AES_ENDIAN_REG AES ૡᄂ࠷թఖ 0 0x3FF01010 ‫؀‬Ĕཿ + ૡᄂ࠷թఖ AES ૡᄂ࠷թఖ 1 0x3FF01014 ‫؀‬Ĕཿ + AES_KEY_0_REG AES ૡᄂ࠷թఖ 2 0x3FF01018 ‫؀‬Ĕཿ + AES_KEY_1_REG AES ૡᄂ࠷թఖ 3 0x3FF0101C ‫؀‬Ĕཿ + AES_KEY_2_REG AES ૡᄂ࠷թఖ 4 0x3FF01020 ‫؀‬Ĕཿ + AES_KEY_3_REG AES ૡᄂ࠷թఖ 5 0x3FF01024 ‫؀‬Ĕཿ + AES_KEY_4_REG AES ૡᄂ࠷թఖ 6 0x3FF01028 ‫؀‬Ĕཿ + AES_KEY_5_REG AES ૡᄂ࠷թఖ 7 0x3FF0102C ‫؀‬Ĕཿ + AES_KEY_6_REG + AES_KEY_7_REG AES ࡆૡ/ࢳૡඔऌ࠷թఖ 0 0x3FF01030 ‫؀‬Ĕཿ + ࡆૡĔࢳૡඔऌ࠷թఖ AES ࡆૡ/ࢳૡඔऌ࠷թఖ 1 0x3FF01034 ‫؀‬Ĕཿ + AES_TEXT_0_REG AES ࡆૡ/ࢳૡඔऌ࠷թఖ 2 0x3FF01038 ‫؀‬Ĕཿ + AES_TEXT_1_REG AES ࡆૡ/ࢳૡඔऌ࠷թఖ 3 0x3FF0103C ‫؀‬Ĕཿ + AES_TEXT_2_REG + AES_TEXT_3_REG AES ᄎෘఓ‫׮‬॥ᇅ࠷թఖ 0x3FF01000 ᆺཿ + ॥ᇅĔሑ෿࠷թఖ + AES_START_REG + +ুᶈྐ༏॓࠯ 527 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 22 AES ࡆ෎ఖ (AES) ૭ඍ ֹᆶ ٠໙ + AES ॢ༽ሑ෿࠷թఖ + ଀ӫ 0x3FF01004 ᆺ‫؀‬ + AES_IDLE_REG + +22.5 ࠷թఖ + + Register 22.1. AES_START_REG (0x000) + + (reserved) AES_START + +31 10 + + 0x00000000 x Reset + +AES_START ཿೆ 1 ൐ି AES ᄎෘbčᆺཿĎ + + Register 22.2. AES_IDLE_REG (0x004) AES_IDLE + + (reserved) 10 + +31 1 Reset + + 0x00000000 + + AES_IDLE AES ॢ༽࠷թఖbAES ࡆ෎ఖᄎྛൈ‫؀‬ԛ 0đॢ༽ൈ‫؀‬ԛ 1bčᆺ‫؀‬Ď + + Register 22.3. AES_MODE_REG (0x008) AES_MODE + + (reserved) 32 0 + +31 0 Reset + + 0x00000000 + + AES_MODE ࿊ᄴ AES ࡆ෎ఖᄎෘଆൔbབྷ౦౨࡮і 22-1bč‫؀‬ĔཿĎ + + Register 22.4. AES_KEY_n_REG (n: 0­7) (0x10+4*n) 0 + +31 Reset + + 0x000000000 + + AES_KEY_n_REG (n: 0­7) AES ૡᄂ࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 528 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 22 AES ࡆ෎ఖ (AES) 0 + + Register 22.5. AES_TEXT_m_REG (m: 0­3) (0x30+4*m) Reset + + 31 + + 0x000000000 + + AES_TEXT_m_REG (m: 0­3) ૼ໓‫ބ‬ૡ໓࠷թఖbč‫؀‬ĔཿĎ + + Register 22.6. AES_ENDIAN_REG (0x040) AES_ENDIAN + + (reserved) 65 0 + +31 1 1 1 1 1 1 Reset + + 0x0000000 + + AES_ENDIAN ሳࢫ྽࿊ᄴ࠷թఖbབྷ౦౨࡮і 22-2bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 529 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 23 SHA ࡆ෎ఖ (SHA) + +23 SHA ࡆ෎ఖ (SHA) + +23.1 ‫ۀ‬ඍ + +ཌྷбႿᄝೈࡱᇏֆ‫׿‬ᄎྛ SHA čνಆ‫ݗ‬༐ෘ‫م‬ĎđSHA ࡆ෎ఖି‫ॹܔ‬෎ิശ SHA ֥ᄎྛ෎؇bSHA ࡆ෎ఖᆦ +ӻඹᇕѓሙ FIPS PUB 180-4 ᄎෘğSHA-1aSHA-256aSHA-384 ‫ ބ‬SHA-512b + +23.2 ᇶေหྟ + + • ᆦӻ SHA-1 ᄎෘ + + • ᆦӻ SHA-256 ᄎෘ + + • ᆦӻ SHA-384 ᄎෘ + + • ᆦӻ SHA-512 ᄎෘ + +23.3 ‫ିۿ‬૭ඍ + +23.3.1 แԉࢳ༅ྐ༏ + +SHA ࡆ෎ఖૄՑᆺିࢤ൳၂۱ྐ༏ॶbೈࡱࡼᆜ۱ྐ༏οᅶѓሙoFIPS PUB 180-4pᇏo5.2 Parsing the +Messagep֥ေ౰߃‫ູٳ‬၂۱၂۱֥ྐ༏ॶđૄՑᆺࡼ၂۱ྐ༏ॶཿೆ࠷թఖ SHA_TEXT_n_REGbೂ‫ݔ‬൞ +SHA-1aSHA-256 ᄎෘđᄵೈࡱૄՑࡼ 512 bit ֥ॶཿೆ࠷թఖ SHA_TEXT_0_REG ~ SHA_TEXT_15_REGb +ೂ‫ݔ‬൞ SHA-384aSHA-512 ᄎෘđᄵೈࡱૄՑࡼ 1024 bit ֥ॶཿೆ࠷թఖ +SHA_TEXT_0_REG ~ SHA_TEXT_31_REGb + +SHA ࡆ෎ఖ҂ିሱ‫׮‬ປӮѓሙoFIPS PUB 180-4pᇏo5.1 Padding the Messagep෮ေ౰֥แԉҠቔĠᄝࡼྐ +༏ൻೆ֞ࡆ෎ఖᆭభđླႮೈࡱটປӮแԉҠቔb + +ѓሙoFIPS PUB 180-4pᇏo2.2.1 Parametersp૭ඍoM0(i) is the left-most word of message block ipđՎ word +թ٢ᄝ࠷թఖ SHA_TEXT_0_REG ᇏbၛՎো๷࠷թఖ SHA_TEXT_1_REG ᇏթ٢֥൞ྐ༏ᇏଖ۱ॶՖቐཟႷ +ֻ֥‫ؽ‬۱ wordll + +23.3.2 ྐ༏ᅋေ + +‫ݗ‬༐ᄎෘປӮᆭުđྐ༏ᅋေФ SHA ࡆ෎ఖ۷ྍೆ࠷թఖ SHA_TEXT_n_REGbೂ‫ݔ‬൞ SHA-1 ᄎෘđᄵ 160 +bit ྐ༏ᅋေթ٢ᄝ࠷թఖ SHA_TEXT_0_REG ~ SHA_TEXT_4_REGbೂ‫ݔ‬൞ SHA-256 ᄎෘđᄵ 256 bit ྐ༏ +ᅋေթ٢ᄝ࠷թఖ SHA_TEXT_0_REG ~ SHA_TEXT_7_REGbೂ‫ݔ‬൞ SHA-384 ᄎෘđᄵ 384 bit ྐ༏ᅋေթ +٢ᄝ࠷թఖ SHA_TEXT_0_REG ~ SHA_TEXT_11_REGbೂ‫ݔ‬൞ SHA-512 ᄎෘđᄵ 512 bit ྐ༏ᅋေթ٢ᄝ࠷ +թఖ SHA_TEXT_0_REG ~ SHA_TEXT_15_REGb + +ѓሙoFIPS PUB 180-4pᇏo2.2.1 Parametersp૭ඍoH(N) is the final hash value and is used to determine the +message digestpaoH0(i) is the left-most word of hash value ipbᄵྐ༏ᅋေᇏቋቐш word H0(N) ᄝ࠷թఖ +SHA_TEXT_0_REG ᇏbၛՎো๷ྐ༏ᅋေᇏՖቐᇀႷֻ֥‫ؽ‬۱ word H1(N) ᄝ࠷թఖ SHA_TEXT_1_REG ᇏ +ll + +23.3.3 ‫ݗ‬༐ᄎෘ + +ᄎෘ SHA-1aSHA-256aSHA-384 ‫ ބ‬SHA-512 ۲Ⴕ၂ቆ॥ᇅ࠷թఖĠ҂๝֥‫ݗ‬༐ᄎෘ൐Ⴈ҂๝֥॥ᇅ࠷թఖb +ᄎෘ SHA-1 ൐Ⴈ࠷թఖ SHA_SHA1_START_REGaSHA_SHA1_CONTINUE_REGaSHA_SHA1_LOAD_REG ‫ބ‬ +SHA_SHA1_BUSY_REGbᄎෘ SHA-256 ൐Ⴈ࠷թఖ SHA_SHA256_START_REGa +SHA_SHA256_CONTINUE_REGaSHA_SHA256_LOAD_REG ‫ ބ‬SHA_SHA256_BUSY_REGbᄎෘ SHA-384 ൐ + +ুᶈྐ༏॓࠯ 530 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 23 SHA ࡆ෎ఖ (SHA) + +Ⴈ࠷թఖ SHA_SHA384_START_REGaSHA_SHA384_CONTINUE_REGaSHA_SHA384_LOAD_REG ‫ބ‬ +SHA_SHA384_BUSY_REGbᄎෘ SHA-512 ൐Ⴈ࠷թఖ SHA_SHA512_START_REGa +SHA_SHA512_CONTINUE_REGaSHA_SHA512_LOAD_REG ‫ބ‬ +SHA_SHA512_BUSY_REGbऎุҠቔੀӱೂ༯b + + 1. Ҡቔֻ၂۱ྐ༏ॶ + (a) Ⴈֻ၂۱ྐ༏ॶԚ൓߄࠷թఖ SHA_TEXT_n_REGb + (b) ؓ࠷թఖ SHA_X_START_REG ཿೆ 1b + (c) ੽࿘࠷թఖ SHA_X_BUSY_REGđᆰ֞Ֆ࠷թఖ SHA_X_BUSY_REG ‫؀‬ԛ 0b + + 2. ࿖ߌҠቔྐ༏֥ު࿃ૄ၂۱ॶ + (a) Ⴈު࿃֥ྐ༏ॶԚ൓߄࠷թఖ SHA_TEXT_n_REGb + (b) ؓ࠷թఖ SHA_X_CONTINUE_REG ཿೆ 1b + (c) ੽࿘࠷թఖ SHA_X_BUSY_REGđᆰ֞Ֆ࠷թఖ SHA_X_BUSY_REG ‫؀‬ԛ 0b + + 3. ࠆ౼ྐ༏ᅋေ + (a) ؓ࠷թఖ SHA_X_LOAD_REG ཿೆ 1b + (b) ੽࿘࠷թఖ SHA_X_BUSY_REGđᆰ֞Ֆ࠷թఖ SHA_X_BUSY_REG ‫؀‬ԛ 0b + (c) Ֆ࠷թఖ SHA_TEXT_n_REG ౼ԛྐ༏ᅋေb + +23.3.4 ᄎྛིੱ + +SHA ࡆ෎ఖླေ 60 ᇀ 100 ۱ൈᇒᇛ௹টԩ৘၂۱ྐ༏ॶၛࠣ 8 ᇀ 20 ۱ൈᇒᇛ௹ট࠹ෘቋު֥ྐ༏ᅋ +ေb + +23.4 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + + ଀ӫ SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 0 0x3FF03000 ‫؀‬/ཿ + ࡆૡĔࢳૡඔऌ࠷թఖ SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 1 0x3FF03004 ‫؀‬/ཿ + SHA_TEXT_0_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 2 0x3FF03008 ‫؀‬/ཿ + SHA_TEXT_1_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 3 0x3FF0300C ‫؀‬/ཿ + SHA_TEXT_2_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 4 0x3FF03010 ‫؀‬/ཿ + SHA_TEXT_3_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 5 0x3FF03014 ‫؀‬/ཿ + SHA_TEXT_4_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 6 0x3FF03018 ‫؀‬/ཿ + SHA_TEXT_5_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 7 0x3FF0301C ‫؀‬/ཿ + SHA_TEXT_6_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 8 0x3FF03020 ‫؀‬/ཿ + SHA_TEXT_7_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 9 0x3FF03024 ‫؀‬/ཿ + SHA_TEXT_8_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 10 0x3FF03028 ‫؀‬/ཿ + SHA_TEXT_9_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 11 0x3FF0302C ‫؀‬/ཿ + SHA_TEXT_10_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 12 0x3FF03030 ‫؀‬/ཿ + SHA_TEXT_11_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 13 0x3FF03034 ‫؀‬/ཿ + SHA_TEXT_12_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 14 0x3FF03038 ‫؀‬/ཿ + SHA_TEXT_13_REG + SHA_TEXT_14_REG + +ুᶈྐ༏॓࠯ 531 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 23 SHA ࡆ෎ఖ (SHA) + +଀ӫ ૭ඍ ֹᆶ ٠໙ +SHA_TEXT_15_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 15 0x3FF0303C ‫؀‬/ཿ +SHA_TEXT_16_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 16 0x3FF03040 ‫؀‬/ཿ +SHA_TEXT_17_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 17 0x3FF03044 ‫؀‬/ཿ +SHA_TEXT_18_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 18 0x3FF03048 ‫؀‬/ཿ +SHA_TEXT_19_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 19 0x3FF0304C ‫؀‬/ཿ +SHA_TEXT_20_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 20 0x3FF03050 ‫؀‬/ཿ +SHA_TEXT_21_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 21 0x3FF03054 ‫؀‬/ཿ +SHA_TEXT_22_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 22 0x3FF03058 ‫؀‬/ཿ +SHA_TEXT_23_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 23 0x3FF0305C ‫؀‬/ཿ +SHA_TEXT_24_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 24 0x3FF03060 ‫؀‬/ཿ +SHA_TEXT_25_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 25 0x3FF03064 ‫؀‬/ཿ +SHA_TEXT_26_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 26 0x3FF03068 ‫؀‬/ཿ +SHA_TEXT_27_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 27 0x3FF0306C ‫؀‬/ཿ +SHA_TEXT_28_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 28 0x3FF03070 ‫؀‬/ཿ +SHA_TEXT_29_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 29 0x3FF03074 ‫؀‬/ཿ +SHA_TEXT_30_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 30 0x3FF03078 ‫؀‬/ཿ +SHA_TEXT_31_REG SHA ࡆૡ/ࢳૡඔऌ࠷թఖ 31 0x3FF0307C ‫؀‬/ཿ +॥ᇅĔሑ෿࠷թఖ +SHA_SHA1_START_REG ‫ؿ‬ఏ SHA1 ᄎෘ֥॥ᇅ࠷թఖ 0x3FF03080 ᆺཿ +SHA_SHA1_CONTINUE_REG ࠿࿃ SHA1 ᄎෘ֥॥ᇅ࠷թఖ 0x3FF03084 ᆺཿ +SHA_SHA1_LOAD_REG ࠹ෘቋᇔ SHA1 ‫ݗ‬༐ᄎෘࢲ‫֥ݔ‬॥ᇅ࠷թఖ 0x3FF03088 ᆺཿ +SHA_SHA1_BUSY_REG SHA1 ᄎෘ֥ሑ෿࠷թఖ 0x3FF0308C ᆺ‫؀‬ +SHA_SHA256_START_REG ‫ؿ‬ఏ SHA256 ᄎෘ֥॥ᇅ࠷թఖ 0x3FF03090 ᆺཿ +SHA_SHA256_CONTINUE_REG ࠿࿃ SHA256 ᄎෘ֥॥ᇅ࠷թఖ 0x3FF03094 ᆺཿ +SHA_SHA256_LOAD_REG ࠹ෘቋᇔ SHA256 ‫ݗ‬༐ᄎෘࢲ‫֥ݔ‬॥ᇅ࠷թఖ 0x3FF03098 ᆺཿ +SHA_SHA256_BUSY_REG SHA256 ᄎෘ֥ሑ෿࠷թఖ 0x3FF0309C ᆺ‫؀‬ +SHA_SHA384_START_REG ‫ؿ‬ఏ SHA384 ᄎෘ֥॥ᇅ࠷թఖ 0x3FF030A0 ᆺཿ +SHA_SHA384_CONTINUE_REG ࠿࿃ SHA384 ᄎෘ֥॥ᇅ࠷թఖ 0x3FF030A4 ᆺཿ +SHA_SHA384_LOAD_REG ࠹ෘቋᇔ SHA384 ‫ݗ‬༐ᄎෘࢲ‫֥ݔ‬॥ᇅ࠷թఖ 0x3FF030A8 ᆺཿ +SHA_SHA384_BUSY_REG SHA384 ᄎෘ֥ሑ෿࠷թఖ 0x3FF030AC ᆺ‫؀‬ +SHA_SHA512_START_REG ‫ؿ‬ఏ SHA512 ᄎෘ֥॥ᇅ࠷թఖ 0x3FF030B0 ᆺཿ +SHA_SHA512_CONTINUE_REG ࠿࿃ SHA512 ᄎෘ֥॥ᇅ࠷թఖ 0x3FF030B4 ᆺཿ +SHA_SHA512_LOAD_REG ࠹ෘቋᇔ SHA512 ‫ݗ‬༐ᄎෘࢲ‫֥ݔ‬॥ᇅ࠷թఖ 0x3FF030B8 ᆺཿ +SHA_SHA512_BUSY_REG SHA512 ᄎෘ֥ሑ෿࠷թఖ 0x3FF030BC ᆺ‫؀‬ + +ুᶈྐ༏॓࠯ 532 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 23 SHA ࡆ෎ఖ (SHA) + +23.5 ࠷թఖ + + Register 23.1. SHA_TEXT_n_REG (n: 0­31) (0x0+4*n) + +31 0 + + 0x000000000 Reset + +SHA_TEXT_n_REG (n: 0­31) SHA ྐ༏ॶ‫ݗބ‬༐ᄎෘࢲ‫࠷ݔ‬թఖbč‫؀‬/ཿĎ SHA_SHA1_START + + Register 23.2. SHA_SHA1_START_REG (0x080) 10 + + (reserved) 0 Reset + +31 SHA_SHA1_CONTINUE + + 0x00000000 10 + + SHA_SHA1_START ཿೆ 1 ֻؓ၂۱ྐ༏ॶࣉྛ SHA-1 ᄎෘbčᆺཿĎ 0 Reset + + Register 23.3. SHA_SHA1_CONTINUE_REG (0x084) SHA_SHA1_LOAD + + (reserved) 10 + +31 0 Reset + + 0x00000000 + + SHA_SHA1_CONTINUE ཿೆ 1 ؓު࿃֥ྐ༏ॶ࠿࿃ࣉྛ SHA-1 ᄎෘbčᆺཿĎ + + Register 23.4. SHA_SHA1_LOAD_REG (0x088) + + (reserved) + +31 + + 0x00000000 + + SHA_SHA1_LOAD ཿೆ 1 ࢲඏ SHA-1 ᄎෘđ࠹ෘቋᇔ֥ᄎෘࢲ‫ݔ‬bčᆺཿĎ + +ুᶈྐ༏॓࠯ 533 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 23 SHA ࡆ෎ఖ (SHA) + + Register 23.5. SHA_SHA1_BUSY_REG (0x08C) + + (reserved) SHA_SHA1_BUSY + +31 10 + + 0x00000000 0 Reset + + SHA_SHA1_BUSY SHA-1 ᄎෘሑ෿࠷թఖğ1ğSHA ࡆ෎ఖᆞᄝԩ৘ඔऌĠ0ğॢ༽bčᆺ‫؀‬Ď + + Register 23.6. SHA_SHA256_START_REG (0x090) SHA_SHA256_START + + (reserved) 10 + +31 0 Reset + + 0x00000000 + + SHA_SHA256_START ཿೆ 1 ֻؓ၂۱ྐ༏ॶࣉྛ SHA-256 ᄎෘbčᆺཿĎ + + Register 23.7. SHA_SHA256_CONTINUE_REG (0x094) SHA_SHA256_CONTINUE + + (reserved) 10 + +31 0 Reset + + 0x00000000 + + SHA_SHA256_CONTINUE ཿೆ 1 ؓު࿃֥ྐ༏ॶ࠿࿃ࣉྛ SHA-256 ᄎෘbčᆺཿĎ + + Register 23.8. SHA_SHA256_LOAD_REG (0x098) SHA_SHA256_LOAD + + (reserved) 10 + +31 0 Reset + + 0x00000000 + + SHA_SHA256_LOAD ཿೆ 1 ࢲඏ SHA-256 ᄎෘđ࠹ෘቋᇔ֥ᄎෘࢲ‫ݔ‬bčᆺཿĎ + +ুᶈྐ༏॓࠯ 534 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 23 SHA ࡆ෎ఖ (SHA) + + Register 23.9. SHA_SHA256_BUSY_REG (0x09C) + + (reserved) SHA_SHA256_BUSY + +31 10 + + 0x00000000 0 Reset + + SHA_SHA256_BUSY SHA-256 ᄎෘሑ෿࠷թఖğ1ğSHA ࡆ෎ఖᆞᄝԩ৘ඔऌĠ0ğॢ༽bčᆺ‫؀‬Ď + + Register 23.10. SHA_SHA384_START_REG (0x0A0) SHA_SHA512_START + + (reserved) 10 + +31 0 Reset + + 0x00000000 + + SHA_SHA384_START ཿೆ 1 ֻؓ၂۱ྐ༏ॶࣉྛ SHA-384 ᄎෘbčᆺཿĎ + + Register 23.11. SHA_SHA384_CONTINUE_REG (0x0A4) SHA_SHA384_CONTINUE + + (reserved) 10 + +31 0 Reset + + 0x00000000 + + SHA_SHA384_CONTINUE ཿೆ 1 ؓު࿃֥ྐ༏ॶ࠿࿃ࣉྛ SHA-384 ᄎෘbčᆺཿĎ + + Register 23.12. SHA_SHA384_LOAD_REG (0x0A8) SHA_SHA384_LOAD + + (reserved) 10 + +31 0 Reset + + 0x00000000 + + SHA_SHA384_LOAD ཿೆ 1 ࢲඏ SHA-384 ᄎෘđ࠹ෘቋᇔ֥ᄎෘࢲ‫ݔ‬bčᆺཿĎ + +ুᶈྐ༏॓࠯ 535 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 23 SHA ࡆ෎ఖ (SHA) + + Register 23.13. SHA_SHA384_BUSY_REG (0x0AC) + + (reserved) SHA_SHA384_BUSY + +31 10 + + 0x00000000 0 Reset + + SHA_SHA384_BUSY SHA-384 ᄎෘሑ෿࠷թఖğ1ğSHA ࡆ෎ఖᆞᄝԩ৘ඔऌĠ0ğॢ༽bčᆺ‫؀‬Ď + + Register 23.14. SHA_SHA512_START_REG (0x0B0) SHA_SHA512_START + + (reserved) 10 + +31 0 Reset + + 0x00000000 + + SHA_SHA512_START ཿೆ 1 ֻؓ၂۱ྐ༏ॶࣉྛ SHA-512 ᄎෘbčᆺཿĎ + + Register 23.15. SHA_SHA512_CONTINUE_REG (0x0B4) SHA_SHA512_CONTINUE + + (reserved) 10 + +31 0 Reset + + 0x00000000 + + SHA_SHA512_CONTINUE ཿೆ 1 ؓު࿃֥ྐ༏ॶ࠿࿃ࣉྛ SHA-512 ᄎෘbčᆺཿĎ + + Register 23.16. SHA_SHA512_LOAD_REG (0x0B8) SHA_SHA512_LOAD + + (reserved) 10 + +31 0 Reset + + 0x00000000 + + SHA_SHA512_LOAD ཿೆ 1 ࢲඏ SHA-512 ᄎෘđ࠹ෘቋᇔ֥ᄎෘࢲ‫ݔ‬bčᆺཿĎ + +ুᶈྐ༏॓࠯ 536 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 23 SHA ࡆ෎ఖ (SHA) + + Register 23.17. SHA_SHA512_BUSY_REG (0x0BC) + + (reserved) SHA_SHA512_BUSY + +31 10 + + 0x00000000 0 Reset + + SHA_SHA512_BUSY SHA-512 ᄎෘሑ෿࠷թఖğ1ğSHA ࡆ෎ఖᆞᄝԩ৘ඔऌĠ0ğॢ༽bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 537 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 24 RSA ࡆ෎ఖ (RSA) + +24 RSA ࡆ෎ఖ (RSA) + +24.1 ‫ۀ‬ඍ + +RSA ࡆ෎ఖູ‫؟‬ᇕᄎႨႿ RSA ٤ؓӫൔࡆૡဆෘ‫֥ࣚۚم‬؇࠹ෘิ‫܂‬႗ࡱᆦӻbᆃུۚࣚ؇࠹ෘЇওնඔଆ +ૢᄎෘaնඔଆӰᄎෘ‫ބ‬նඔӰ‫م‬ᄎෘ֩b +RSA ࡆ෎ఖࠞնֹࢆ֮ਔᆃ೘ᇕᄎෘ֥ೈࡱ‫گ‬ᄖ؇đѩ౏ᆦӻ‫؟‬ᇕᄎෘሰӉ؇đ൐֤ᄎෘིੱ҂Фশ‫ٮ‬b + +24.2 ᇶေหྟ + + • ᆦӻնඔଆૢᄎෘ + • ᆦӻնඔଆӰᄎෘ + • ᆦӻնඔӰ‫م‬ᄎෘ + • ᆦӻ‫؟‬ᇕᄎෘሰӉ؇ + +24.3 ‫ିۿ‬૭ඍ + +24.3.1 Ԛ൓߄ + +๙‫ݖ‬൐ିؓႋ֥ຓഡൈᇒѩ౏ౢਬ DPORT_RSA_PD_CTRL_REG ࠷թఖᇏ֥ DPORT_RSA_PD ໊ࠧॖၛ‫໊گ‬ +൤٢ѩ൐ି RSA ࡆ෎ఖb +֒ RSA ࡆ෎ఖФ‫໊گ‬൤٢ުđ࠷թఖ RSA_CLEAN_REG ‫ ֞؀‬0đԚ൓߄ष൓b႗ࡱࡼ 4 ॶթԥఖԚ൓߄ູ 0b +Ԛ൓߄‫ݖ‬ӱປӮުđ࠷թఖ RSA_CLEAN_REG ‫ ֞؀‬1bၹՎđRSA ࡆ෎ఖФ‫໊گ‬ᆭުֻ၂Ց൐Ⴈൈđೈࡱླေ +༵Ұ࿘࠷թఖ RSA_CLEAN_REGđၛಒЌ RSA ࡆ෎ఖԩႿॖ‫۽‬ቔሑ෿b + +24.3.2 նඔଆૢᄎෘ + +նඔଆૢᄎෘ֥ෘ‫م‬൞ Z = XY mod M đ෱൞ࠎႿ Montgomery Multiplication č૎ۢઔ০Ӱ‫م‬Ďൌགྷ֥b෮ၛ +ؓႿնඔଆૢᄎෘđԢਔླေᄎෘሰ XaY aM ຓđߎླေ‫ح‬ຓਆ۱ᄎෘሰđࠧҕඔ r ‫ ބ‬M ′bᆃਆ۱ҕඔླ +ေ๙‫ݖ‬ೈࡱิభᄎෘ֤֞b +RSA ࡆ෎ఖᆦӻ N ∈ {512, 1024, 1536, 2048, 2560, 3072, 3584, 4096} 8 ᇕӉ؇֥նඔଆૢᄎෘbࠧ ZaXaY a +M ‫ ބ‬r ໊֥ॺູᆃ 8 ᇕᇏ֥಩ၩ၂ᇕđ֌൞෱ૌ໊֥ॺсྶ‫׻‬ཌྷ๝đ‫ ط‬M ′ ໊֥ॺ൓ᇔ൞ 32b +ഡࣉᇅඔ + + b = 232 + +ᄵᄎෘሰॖၛႮ೏‫ۄ‬۱ b ࣉᇅඔটіൕğ + N + + n= + 32 + + Z = (Zn−1Zn−2 · · · Z0)b + X = (Xn−1Xn−2 · · · X0)b + Y = (Yn−1Yn−2 · · · Y0)b + M = (Mn−1Mn−2 · · · M0)b + + r = (rn−1rn−2 · · · r0)b + +ুᶈྐ༏॓࠯ 538 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 24 RSA ࡆ෎ఖ (RSA) + +ఃᇏ Zn−1 ~ Z0aXn−1 ~ X0aYn−1 ~ Y0aMn−1 ~ M0arn−1 ~ r0 ‫ٳ‬љіൕ၂۱ b ࣉᇅඔđ໊ॺࢥູ 32b౏ +Zn−1aXn−1aYn−1aMn−1arn−1 ‫ٳ‬љູ ZaXaY aM ar ቋ໊֥ۚ b ࣉᇅඔđ‫ ط‬Z0aX0aY0aM0ar0 ‫ٳ‬љ +ູ ZaXaY aM ar ቋ໊֥֮ b ࣉᇅඔb + +ਸ਼ഡ + + R = bn + +ᄵ࠹ෘ֤ҕඔğ + +  r = R2 mod M (1) + + M ′′ × M + 1 = R × R−1 (2) + + M ′ = M ′′ mod b + +č‫܄‬ൔ (2) ֥ྙൔൡႨႿ൐Ⴈঔᅚ‫ࣉؽ‬ᇅ GCD ෘ‫֥م‬ᄎෘbĎ + +նඔଆૢᄎෘ֥ೈࡱੀӱູğ + +1. ؓ࠷թఖ RSA_MODEXP_MODE_REG ཿೆ ( N − 1)b + 512 + +2. ࡼ XiaYiaMiari (i ∈ [0, n) ∩ N) ‫ٳ‬љཿೆթԥఖ RSA_X_MEMaRSA_Y_MEMaRSA_M_MEMa + RSA_Z_MEMbૄॶթԥఖ֥ಸਈ‫׻‬൞ 128 wordbૄॶթԥఖ֥ૄ၂۱ word ‫ݺې‬թ٢၂۱ b ࣉᇅඔbᆃ + ུթԥఖ‫׻‬൞ֹ֮ᆶթ٢ᄎෘሰ໊֥֮ࣉᇅඔđֹۚᆶթ٢ᄎෘሰ໊֥ۚࣉᇅඔb + + ᆺླေ۴ऌᄎෘሰӉ؇đࡼ۲۱ᄎෘሰᇏႵི֥ඔऌཿೆթԥఖđીႵ൐Ⴈ֥֞թԥఖॖၛ൞಩ၩᆴb + +3. ࡼ M ′ ཿೆ࠷թఖ RSA_M_PRIME_REGb + +4. ؓ࠷թఖ RSA_MODEXP_START_REG ཿೆ 1b + +5. ֩րᄎෘࢲඏb੽࿘࠷թఖ RSA_INTERRUPT_REG ᆰ֞‫ ֞؀‬1đࠇᆀ֩ր RSA_INTR ᇏ؎Ӂളb + +6. Ֆթԥఖ RSA_Z_MEM ‫؀‬ԛᄎෘࢲ‫ ݔ‬Zi (i ∈ [0, n) ∩ N)b +7. ؓ࠷թఖ RSA_INTERRUPT_REG ཿೆ 1 ၛౢԢᇏ؎b + +ᄎෘࢲඏުđ࠷թఖ RSA_MODEXP_MODE_REG ᇏթԥ֥ᄎෘሰӉ؇ྐ༏ၛࠣթԥఖ RSA_Y_MEM ᇏ֥ Yia +թԥఖ RSA_M_MEM ᇏ֥ Mia࠷թఖ RSA_M_PRIME_REG ᇏ֥ M ′ ‫׻‬҂߶э߄b֌൞đթԥఖ +RSA_X_MEM ᇏ֥ Xi აթԥఖ RSA_Z_MEM ᇏ֥ ri ‫ࣜၘ׻‬Ф‫ۂڭ‬ਔb෮ၛ֒ླေ৵࿃ᄎෘൈđᆺླေ۷ྍс +ླ֥࠷թఖაթԥఖࠧॖb + +24.3.3 նඔଆӰᄎෘ + +նඔଆӰᄎෘ္൞ࠎႿ Montgomery Multiplication ൌགྷᄎෘ Z = X × Y mod M đ෮ၛ္ླေೂൔ 1aൔ 2 ყ +༵๙‫ݖ‬ೈࡱ࠹ෘ֤֞ r ‫ ބ‬M ′b + +RSA ࡆ෎ఖ္ᆦӻ 8 ᇕᄎෘሰӉ؇֥նඔଆӰᄎෘbնඔଆӰᄎෘҐႨೈ႗ࡱཌྷࢲ‫֥ކ‬ٚൔđᄎෘ௹ࡗླေೈ +ࡱࢺೆ၂Ցb + +նඔଆӰᄎෘ֥ೈࡱੀӱູğ + +1. ؓ࠷թఖ RSA_MULT_MODE_REG ཿೆ ( N − 1)b + 512 + +2. ࡼ XiaMiari (i ∈ [0, n) ∩ N) ‫ٳ‬љཿೆթԥఖ RSA_X_MEMaRSA_M_MEMaRSA_Z_MEMb๝ဢᆺླေ + ۴ऌᄎෘሰӉ؇đࡼ۲۱ᄎෘሰᇏႵི֥ඔऌཿೆթԥఖđીႵ൐Ⴈ֥֞թԥఖॖၛ൞಩ၩᆴb + +ুᶈྐ༏॓࠯ 539 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 24 RSA ࡆ෎ఖ (RSA) + + 3. ࡼ M ′ ཿೆ࠷թఖ RSA_M_PRIME_REGb + 4. ؓ࠷թఖ RSA_MULT_START_REG ཿೆ 1b + 5. ֩րֻ၂੽ᄎෘࢲඏb੽࿘࠷թఖ RSA_INTERRUPT_REG ᆰ֞‫ ֞؀‬1đࠇᆀ֩ր RSA_INTR ᇏ؎Ӂളb + 6. ؓ࠷թఖ RSA_INTERRUPT_REG ཿೆ 1 ၛౢԢᇏ؎b + 7. ࡼ Yi (i ∈ [0, n) ∩ N) ཿೆթԥఖ RSA_X_MEMbᆺླေ۴ऌᄎෘሰӉ؇đࡼᄎෘሰᇏႵི֥ඔऌཿೆթԥ + + ఖđીႵ൐Ⴈ֥֞թԥఖ҂Ⴈ۷‫ڿ‬b + 8. ؓ࠷թఖ RSA_MULT_START_REG ཿೆ 1b + 9. ֩րֻ‫੽ؽ‬ᄎෘࢲඏb੽࿘࠷թఖ RSA_INTERRUPT_REG ᆰ֞‫ ֞؀‬1đࠇᆀ֩ր RSA_INTR ᇏ؎Ӂളb + 10. Ֆթԥఖ RSA_Z_MEM ‫؀‬ԛᄎෘࢲ‫ ݔ‬Zi (i ∈ [0, n) ∩ N)b + 11. ؓ࠷թఖ RSA_INTERRUPT_REG ཿೆ 1 ၛౢԢᇏ؎b +ᄎෘࢲඏުđᆺႵ࠷թఖ RSA_MULT_MODE_REG ᇏթԥ֥ᄎෘଆൔაᄎෘሰӉ؇ྐ༏ၛࠣթԥఖ +RSA_M_MEM ᇏ֥ Mia࠷թఖ RSA_M_PRIME_REG ᇏ֥ M ′ ીႵФ‫ۂڭ‬b෮ၛ৵࿃ᄎෘൈđॖၛ҂ᄜؓᆃུ +࠷թఖაթԥఖᇗ‫گ‬ཿೆb + +24.3.4 նඔӰ‫م‬ᄎෘ + +նඔӰ‫م‬ᄎෘൌགྷਔ Z = X × Y bఃᇏᄎෘሰ Z ֥Ӊ؇൞ᄎෘሰ XaY Ӊ؇֥ਆПb෮ၛ RSA ࡆ෎ఖᆺᆦӻ +4 ᇕ N ∈ {512, 1024, 1536, 2048} ᄎෘሰӉ؇֥նඔӰ‫م‬ᄎෘbᄎෘሰ Z ֥Ӊ؇ Nˆ ູ 2 × N b + +൮༵‫ܒ‬ᄯ Xˆ aYˆ đ෱ૌაᄎෘሰ Z ֥Ӊ؇၂ᇁ (Nˆ )b + + N + n= + + 32 + Nˆ = 2 × N + + Nˆ + nˆ = = 2n + + 32 + + Xˆ = (Xˆnˆ−1Xˆnˆ−2 · · · Xˆ0)b = (00 · · · 0 X)b = (00 · · · 0 Xn−1Xn−2 · · · X0)b + + n n + + Yˆ = (Yˆnˆ−1Yˆnˆ−2 · · · Yˆ0)b = (Y 00 · · · 0)b = (Yn−1Yn−2 · · · Y0 00 · · · 0)b + + n n + +նඔӰ‫م‬ᄎෘ֥ೈࡱੀӱູğ + +1. ؓ࠷թఖ RSA_MULT_MODE_REG ཿೆ ( Nˆ − 1 + 8)b + 512 + +2. ࡼ XˆiaYˆi (i ∈ [0, nˆ) ∩ N) ‫ٳ‬љཿೆթԥఖ RSA_X_MEMaRSA_Z_MEMb + + ᆺླေ۴ऌᄎෘሰӉ؇đࡼᆃਆ۱ᄎෘሰᇏႵི֥ඔऌཿೆթԥఖđીႵ൐Ⴈ֥֞թԥఖॖၛ൞಩ၩᆴb + ཿೆթԥఖ֥೏‫ ۄ‬b ࣉᇅඔᇏႵ၂϶‫׻‬൞ 0đᆃུ 0 ҂ॖࠇಌb + +3. ؓ࠷թఖ RSA_MULT_START_REG ཿೆ 1b + +4. ֩րᄎෘࢲඏb੽࿘࠷թఖ RSA_INTERRUPT_REG ᆰ֞‫ ֞؀‬1đࠇᆀ֩ր RSA_INTR ᇏ؎Ӂളb + +5. Ֆթԥఖ RSA_Z_MEM ‫؀‬ԛᄎෘࢲ‫ ݔ‬Zi (i ∈ [0, nˆ) ∩ N)b +6. ؓ࠷թఖ RSA_INTERRUPT_REG ཿೆ 1 ၛౢԢᇏ؎b + +ᄎෘࢲඏުđᆺႵ࠷թఖ RSA_MULT_MODE_REG ᇏթԥ֥ᄎෘଆൔაᄎෘሰӉ؇ྐ༏ીФ۷‫ڿ‬b + +ুᶈྐ༏॓࠯ 540 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 24 RSA ࡆ෎ఖ (RSA) + +24.4 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + + ଀ӫ թԥ M’ ֥࠷թఖ 0x3FF02800 ‫؀‬/ཿ + ஥ᇂ࠷թఖ + RSA_M_PRIME_REG ଆૢᄎෘଆൔ 0x3FF02804 ‫؀‬/ཿ + ଆૢᄎෘ࠷թఖ ఏ൓໊ 0x3FF02808 ᆺཿ + RSA_MODEXP_MODE_REG + RSA_MODEXP_START_REG ଆӰᄎෘଆൔ 0x3FF0280C ‫؀‬/ཿ + ଆӰᄎෘ࠷թఖ ఏ൓໊ 0x3FF02810 ᆺཿ + RSA_MULT_MODE_REG + RSA_MULT_START_REG RSA ᇏ؎࠷թఖ 0x3FF02814 ‫؀‬/ཿ + ః෰࠷թఖ RSA ౢԢ࠷թఖ 0x3FF02818 ᆺ‫؀‬ + RSA_INTERRUPT_REG + RSA_CLEAN_REG + +ুᶈྐ༏॓࠯ 541 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 24 RSA ࡆ෎ఖ (RSA) + +24.5 ࠷թఖ + + Register 24.1. RSA_M_PRIME_REG (0x800) + +31 0 + + 0x000000000 Reset + + RSA_M_PRIME_REG Վ࠷թఖЇ‫ ݣ‬M’bč‫؀‬/ཿĎ + + Register 24.2. RSA_MODEXP_MODE_REG (0x804) + + (reserved) RSA_MODEXP_MODE + +31 32 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 Reset + + RSA_MODEXP_MODE Վ࠷թఖЇ‫ݣ‬ଆૢᄎෘ֥ଆൔbč‫؀‬/ཿĎ + + Register 24.3. RSA_MODEXP_START_REG (0x808) + + (reserved) RSA_MODEXP_START + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RSA_MODEXP_START ཿೆ 1 ၛष൓ଆૢᄎෘbčᆺཿĎ + + Register 24.4. RSA_MULT_MODE_REG (0x80C) + + (reserved) RSA_MULT_MODE + +31 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RSA_MULT_MODE Վ࠷թఖЇ‫ݣ‬ଆӰ‫ބ‬Ӱ‫م‬ᄎෘbčᆺཿĎ + +ুᶈྐ༏॓࠯ 542 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 24 RSA ࡆ෎ఖ (RSA) + + Register 24.5. RSA_MULT_START_REG (0x810) + + (reserved) RSA_MULT_START + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RSA_MULT_START ཿೆ 1 ၛष൓ଆӰ‫ބ‬Ӱ‫م‬ᄎෘbčᆺཿĎ + + Register 24.6. RSA_INTERRUPT_REG (0x814) + + (reserved) RSA_INTERRUPT + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RSA_INTERRUPT RSA ᇏ؎ሑ෿࠷թఖb၂Ցᄎෘࢲඏࠧ‫ ֞؀‬1bč‫؀‬/ཿĎ + + Register 24.7. RSA_CLEAN_REG (0x818) + + (reserved) RSA_CLEAN + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RSA_CLEAN ၂֊թԥఖԚ൓߄ࢲඏđՎ໊ࠧ‫ ֞؀‬1bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 543 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 25 ෛࠏඔ‫ؿ‬ളఖ (RNG) + +25 ෛࠏඔ‫ؿ‬ളఖ (RNG) + +25.1 ‫ۀ‬ඍ + +ESP32 ଽᇂ၂۱ᆇෛࠏඔ‫ؿ‬ളఖđఃളӮ֥ 32 ໊ෛࠏඔॖቔູࡆૡ֩Ҡቔ֥ࠎԤb + +25.2 ᇶေหྟ + +ESP32 ֥ෛࠏඔ‫ؿ‬ളఖॖ๙‫ݖ‬໾৘‫ݖ‬ӱ‫ط‬٤ෘ‫م‬ളӮᆇෛࠏඔđ෮ႵളӮ֥ෛࠏඔᄝห‫ຶٓק‬ଽԛགྷ֥‫ੱۀ‬ປ +ಆ၂ᇁb + +25.3 ‫ିۿ‬૭ඍ + +༢๤ॖၛՖෛࠏඔ‫ؿ‬ളఖ֥࠷թఖ RNG_DATA_REG ᇏ‫؀‬౼ෛࠏඔđૄ۱‫ ֥֞؀‬32 ໊ෛࠏඔ‫׻‬൞ᆇෛࠏඔđ +ᄮലჷູ༢๤ᇏ֥ಣᄮല‫ބ‬ၳ҄ൈᇒb +ऎุটඪđᆃུಣᄮലॖၛটሱ SAR ADC ࠇۚ෎ ADC ࠇਆᆀ࡙Ⴕb֒ྉோ֥ SAR ADC ࠇۚ෎ ADC ‫۽‬ቔൈđ +ࣼ߶Ӂളбหੀđѩ๙‫ݖ‬ၳࠇ (XOR) આࠠᄎෘቔູෛࠏඔᇕሰࣉೆෛࠏඔളӮఖb + + ๭ 25­1. ᄮലჷ + +֒ SAR ADC յषൈđૄ۱ RTC8M_CLK č8 MHzĎൈᇒᇛ௹ଽčটሱଽ҆ RC ᆒ֕ఖđབྷ࡮ 3 ‫ބ໊گ‬ൈᇒ ᅣ +ࢫĎđෛࠏඔ‫ؿ‬ളఖࡼࠆ֤ 2 ໊֥᧦bၹՎđູਔࠆ֤ቋն֥᧦ᆴđࡹၰ‫؀‬౼ RNG_DATA_REG ࠷թఖൈ֥෎ੱ +҂ӑ‫ ݖ‬500 kHzb +֒ۚ෎ ADC յषൈđૄ۱ APB ൈᇒᇛ௹č๙ӈູ 80 MHzĎଽđෛࠏඔ‫ؿ‬ളఖࡼࠆ֤ 2 ໊֥᧦bၹՎđູਔࠆ +֤ቋն֥᧦ᆴđࡹၰ‫؀‬౼ RNG_DATA_REG ࠷թఖൈ֥෎ੱ҂ӑ‫ ݖ‬5 MHzb +໡ૌᄝࣇյषۚ෎ ADC ֥ሑ෿༯đၛ 5 MHz ֥෎ੱՖ RNG_DATA_REG ‫؀‬౼ਔ 2 GB ֥ඔऌဢЧđѩ൐Ⴈ +Dieharder ෛࠏඔҩ൫สࡱčϱЧ 3.31.1ĎؓဢЧࣉྛਔҩ൫bቋᇔđဢЧ๙‫ݖ‬ਔ෮Ⴕҩ൫b + +25.4 щӱᆷଲ + +ᄝ൐Ⴈ ESP32 ֥ෛࠏඔളӮఖൈđႋ‫ھ‬ᇀഒյष SAR ADC ࠇۚ෎ ADCđ‫ڎ‬ᄵॖି߶֝ᇁӁളເෛࠏඔđႋᇿ +ၩх૧bఃᇏđ + + • SAR ADC ॖ๙‫ ݖ‬DIG ADC ॥ᇅఖյषđབྷ࡮ 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ ᅣࢫb + • ۚ෎ ADC ᄝ Wi-Fi ࠇড࿩षఓൈሱ‫׮‬յषb + +ুᶈྐ༏॓࠯ 544 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 25 ෛࠏඔ‫ؿ‬ളఖ (RNG) + +ඪૼğ +ᇿၩđᄝ Wi-Fi षఓൈđࠞ؊౦ঃ༯ۚ෎ ADC Ⴕ‫؀‬ᆴЎ‫֥ބ‬ॖିđᆃ߶ࢆ֮᧦ᆴbၹՎđࡹၰᄝ Wi-Fi षఓൈđ๝ൈ +๙‫ ݖ‬DIG ADC1 ॥ᇅఖյष SAR ADC Ӂളෛࠏඔb + +ᄝ൐ႨෛࠏඔളӮఖൈđ౨‫؟‬Ց‫؀‬౼ RNG_DATA_REG ࠷թఖ֥ᆴđᆰᇀࠆ֤ቀ‫֥؟ܔ‬ෛࠏඔbᄝ‫؀‬౼࠷թఖ +ൈđᇿၩ॥ᇅ෎ੱ҂ေӑ‫ݖ‬ഈֻٚ 25.3 ཬࢫ֥ࢺകb + +25.5 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + ෛࠏඔඔऌ 0x3FF75144 ᆺ‫؀‬ + ଀ӫ + RNG_DATA_REG + +25.6 ࠷թఖ + + Register 25.1. RNG_DATA_REG (0x144) + +31 0 + + 0x000000000 Reset + +RNG_DATA_REG ෛࠏඔটჷbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 545 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 26 ோຓթԥఖࡆૡაࢳૡ (FLASH) + +26 ோຓթԥఖࡆૡაࢳૡ (FLASH) + +26.1 ‫ۀ‬ඍ + +ESP32 ༢ਙ֥‫ॻ؟‬ྉோླေࡼӱ྽‫ބ‬ඔऌթԥᄝோຓ flashbோຓ flash ॖၛႨটթԥህႵೈࡱaૹ‫֥ۋ‬Ⴈ޼ඔ +ऌčбೂႨট٠໙඲Ⴕຩ઎֥௝ऌĎ֩bESP32 ֥ flash ࡆૡଆॶି‫ࡼܔ‬ս઒ࣉྛࡆૡđಖުࡼࡆૡᆭު֥ս +઒ཿೆோຓ flashb֒ CPU ๙‫ ݖ‬cache ‫؀‬ோຓ flash ൈđflash ࢳૡଆॶି‫؀ࡼܔ‬౼֥֞ᆷ਷‫ބ‬ඔऌሱ‫ࢳྛࣉ׮‬ +ૡbESP32 ๙‫ ݖ‬flash ࡆࢳૡଆॶູႨ޼֥ႋႨս઒ิ‫܂‬ਔνಆЌᅰb + +26.2 ᇶေหྟ + + • ‫؟‬ᇕૡᄂളӮٚൔ + • ࡆૡ‫ݖ‬ӱླေೈࡱҕა + • ۚ෎֥ࢳૡ‫ݖ‬ӱđ໭ླೈࡱҕა + • ࠷թఖ஥ᇂa༢๤ҕඔaఓ‫( ׮‬boot) ଆൔ‫܋‬๝थ‫ ק‬flash ࡆࢳૡ‫ିۿ‬ + +26.3 ‫ିۿ‬૭ඍ + + ๭ 26­1. Flash ࡆࢳૡଆॶࡏ‫ܒ‬ + +Flash ࡆࢳૡଆॶЇ‫ݣ‬೘۱҆‫ٳ‬đ‫ٳ‬љ൞ૡᄂളӮଆॶ (Key Generator)aflash ࡆૡ (Flash Encryption) ଆॶ‫ބ‬ +flash ࢳૡ (Flash Decryption) ଆॶđೂ๭ 26-1 ෮ൕbKey Generator Ф Flash Encryption ა Flash Decryption ‫܋‬ +๝൐ႨbFlash Encryption ა Flash Decryption ॖၛ๝ൈ‫۽‬ቔb + +ຓഡ DPort ࠷թఖᇏა flash ࡆࢳૡཌྷܱ֥࠷թఖ൞ DPORT_SLAVE_SPI_CONFIG_REG ᇏ֥ +DPORT_SPI_ENCRYPT_ENABLE ໊‫ ބ‬DPORT_SPI_DECRYPT_ENABLE ໊bFlash ࡆࢳૡଆॶߎ߶Ֆຓഡ +eFuse ॥ᇅఖᇏࠆ౼ 6 ۱༢๤ҕඔđ෱ૌ൞ coding_schemeaBLOCK1aflash_crypt_configa +download_dis_encryptaflash_crypt_cnt ‫ ބ‬download_dis_decryptb + +ুᶈྐ༏॓࠯ 546 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 26 ோຓթԥఖࡆૡაࢳૡ (FLASH) + +26.3.1 Key Generator ଆॶ + +Key Generator ൮༵၇ऌ༢๤ҕඔ coding_schemeaBLOCK1 ളӮ +Keyo = f (coding_scheme, BLOCK1)b + +ಖު Key Generator ۴ऌ༢๤ҕඔ flash_crypt_config ‫ ބ‬flash ࡆࢳૡଆॶ٠໙֥ோຓ flash ֥ൌֹᆶ Addrea +Addrd ‫ٳ‬љᄎෘԛ +Keye = g(Keyo, f lash_crypt_conf ig, Addre)a +Keyd = g(Keyo, f lash_crypt_conf ig, Addrd)b + +֒༢๤ҕඔ flash_crypt_config ູಆ 0 ൈđKeyeaKeyd აோຓ flash ֥ൌֹᆶ໭ܱb֒༢๤ҕඔ +flash_crypt_config ູԢಆ 0 ᆭຓ಩ၩᆴൈđோຓ flash ૄ 8 ۱ word ऎႵ၂۱ః‫׿‬ห֥ Keye ‫ ބ‬Keydb + +26.3.2 Flash Encryption ଆॶ + +Flash Encryption ൞၂۱ຓഡଆॶđሱദջႵ࠷թఖđᆃུ࠷թఖॖၛФ CPU ᆰࢤ٠໙bଆॶଽ֥࠷թఖaຓ +ഡ DPort ࠷թఖa༢๤ҕඔaboot ଆൔ‫܋‬๝஥ᇂѩ൐Ⴈᆃ၂ଆॶb + +Վଆॶ‫۽‬ቔൈླေೈࡱҕაđఃੀӱູğ + + 1. ࡼ࠷թఖ DPORT_SLAVE_SPI_CONFIG_REG ֥ DPORT_SPI_ENCRYPT_ENABLE ໊ᇂ 1b + + 2. ࡼሙСཿோຓ flash ֥ൌֹᆶแೆ࠷թఖ FLASH_ENCRYPT_ADDRESS_REGđՎֹᆶᆴсྶ൞ 8-word ؓ + ఊ֥b + + 3. ࡼրࡆૡ֥ 8-word ս઒ᇏ֥ቋֹ֮ᆶ֥ word แೆ࠷թఖ FLASH_ENCRYPT_BUFFER_0_REGđՑֹ֮ + ᆶ֥ word แೆ FLASH_ENCRYPT_BUFFER_1_REGđၛՎো๷ᆰᇀแೆ + FLASH_ENCRYPT_BUFFER_7_REGb + + 4. ࡼ࠷թఖ FLASH_ENCRYPT_START_REG ᇂ 1b + + 5. ੽࿘࠷թఖ FLASH_ENCRYPT_DONE_REGđᆰ֞‫ ֞؀‬1b + + 6. ‫ט‬Ⴈ‫ݦ‬ඔđ๙‫ݖ‬ຓഡ SPI0 ؓோຓ flash ֥ 8-word ؓఊֹ֥ᆶཿೆ಩ၩ 8-word ս઒b + +҄ᇧ 1 ᇀ 5 Ҡቔ Flash Encryption ଆॶؓ 8-word ս઒ࣉྛࡆૡbࡆૡෘ‫م‬൐Ⴈ֥ૡᄂࣼ൞ Keyebࡆૡࢲ‫္ݔ‬ +൞ 8 ۱ wordb҄ᇧ 6 Ҡቔຓഡ SPI0 ࡼ Flash Encryption ֥ࡆૡࢲ‫ݔ‬ཿೆோຓ flashb҄ᇧ 6 ᇏ‫ט‬Ⴈ֥‫ݦ‬ඔ߶Ⴕ +၂۱ҕඔ൞ཿோຓ flash ֥ൌֹᆶđᆃ۱ൌֹᆶсྶ൞ 8-word ؓఊ֥đ౏сྶა҄ᇧ 2 ᇏแೆ࠷թఖ +FLASH_ENCRYPT_ADDRESS_REG ֥ᆴ၂ᇁbෙಖ҄ᇧ 6 ᇏ‫ט‬Ⴈ֥‫ݦ‬ඔߎ߶Ⴕ၂۱ҕඔ൞ 8-word ս઒đ֌൞ +ᄝᆳྛਔ҄ᇧ 1 ᇀ 5 ֥౦ঃ༯đᆃ۱ҕඔ໭ၩၬđຓഡ SPI0 Վൈ൐Ⴈ֥൞ࡆૡު֥ࢲ‫ݔ‬b೏ Flash Encryption +ԩႿໃ‫۽‬ቔሑ෿ࠇᆀ҂ᆳྛ҄ᇧ 1 ᇀ 5đପહ҄ᇧ 6 ҂߶൐Ⴈࡆૡࢲ‫طݔ‬൞‫ݦ‬ඔᇏ֥ҕඔb + +Flash Encryption ൞‫ڎ‬ԩႿ‫۽‬ቔሑ෿౼थႿğ + + • SPI Flash Boot ଆൔ༯ + + ֒࠷թఖ DPORT_SLAVE_SPI_CONFIG_REG ֥ DPORT_SPI_ENCRYPT_ENABLE ູ໊ 1 ൈđFlash + Encryption ԩႿ‫۽‬ቔሑ෿đ‫ڎ‬ᄵԩႿໃ‫۽‬ቔሑ෿b + + • Download Boot ଆൔ༯ + + ֒࠷թఖ DPORT_SLAVE_SPI_CONFIG_REG ֥ DPORT_SPI_ENCRYPT_ENABLE ູ໊ 1 ౏༢๤ҕඔ + download_dis_encrypt ູ 0 ൈđFlash Encryption ԩႿ‫۽‬ቔሑ෿đ‫ڎ‬ᄵԩႿໃ‫۽‬ቔሑ෿b + +ෙಖᆜ۱‫ݖ‬ӱ‫׻‬Ⴕೈࡱҕაđ֌൞ࡆૡު֥ս઒໭‫م‬Фೈࡱᆰࢤ‫؀‬౼bࡆૡު֥ս઒Фᆰࢤཿ֞ோຓ flash ᇏb +ෙಖ CPU ॖၛ҂๙‫ ݖ‬cache ‫ط‬ᆰࢤ‫؀‬ோຓ flash Ֆ‫ࡆ֤֞ط‬ૡս઒đ֌ೈࡱߎ൞धؓ໭‫ࠆم‬౼֞ૡᄂ + +ুᶈྐ༏॓࠯ 547 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 26 ோຓթԥఖࡆૡაࢳૡ (FLASH) + +K eye b + +26.3.3 Flash Decryption ଆॶ + +Flash Decryption ѩ٤ຓഡଆॶđሱദ҂ջ࠷թఖđၹՎ҂ିФ CPU ᆰࢤ٠໙bຓഡ DPort ࠷թఖa༢๤ҕඔa +boot ଆൔ‫܋‬๝஥ᇂѩ൐Ⴈᆃ၂ଆॶb + +֒Վଆॶ‫۽‬ቔൈđCPU ๙‫ ݖ‬cache ‫؀‬౼ோຓ flash ᇏ֥ᆷ਷აඔऌbFlash Decryption ࡼሱ‫׮‬Ϝ‫؀‬౼֥֞ᆷ਷ა +ඔऌࣉྛࢳૡbࢳૡ֥ᆜ۱‫ݖ‬ӱ໭ླೈࡱҕაѩ౏ؓ cache ൞๩ૼ֥bࢳૡෘ‫م‬൐Ⴈ֥ૡᄂࣼ൞ KeydđՎૡ +ᄂ๝ဢ໭‫م‬Фೈࡱࠆ౼b + +֒Վଆॶໃ‫۽‬ቔൈđ҂ؓ flash ᇏ֥ଽಸӁളቔႨđ໭ં൞ࡆૡଽಸߎ൞ໃࡆૡଽಸđၹՎ CPU ๙‫ ݖ‬cache ‫؀‬ +౼֥֞൞ flash ᇏ֥ჰ൓ଽಸb + +Flash Decryption ൞‫ڎ‬ԩႿ‫۽‬ቔሑ෿౼थႿğ + + • SPI Flash Boot ଆൔ༯ + + ֒༢๤ҕඔ flash_crypt_cntč7 bit ॺĎᇏႵఅඔ۱ bit ູ 1 ൈđFlash Decryption ԩႿ‫۽‬ቔሑ෿đ‫ڎ‬ᄵԩႿ + ໃ‫۽‬ቔሑ෿b + + • Download Boot ଆൔ༯ + + ֒࠷թఖ DPORT_SLAVE_SPI_CONFIG_REG ֥ DPORT_SPI_DECRYPT_ENABLE ູ໊ 1 ౏༢๤ҕඔ + download_dis_decrypt ູ 0 ൈđFlash Decryption ԩႿ‫۽‬ቔሑ෿đ‫ڎ‬ᄵԩႿໃ‫۽‬ቔሑ෿b + +26.4 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ + Flash ࡆૡ buffer ࠷թఖ 0 0x3FF5B000 ᆺཿ + ଀ӫ Flash ࡆૡ buffer ࠷թఖ 1 0x3FF5B004 ᆺཿ + FLASH_ENCRYPTION_BUFFER_0_REG Flash ࡆૡ buffer ࠷թఖ 2 0x3FF5B008 ᆺཿ + FLASH_ENCRYPTION_BUFFER_1_REG Flash ࡆૡ buffer ࠷թఖ 3 0x3FF5B00C ᆺཿ + FLASH_ENCRYPTION_BUFFER_2_REG Flash ࡆૡ buffer ࠷թఖ 4 0x3FF5B010 ᆺཿ + FLASH_ENCRYPTION_BUFFER_3_REG Flash ࡆૡ buffer ࠷թఖ 5 0x3FF5B014 ᆺཿ + FLASH_ENCRYPTION_BUFFER_4_REG Flash ࡆૡ buffer ࠷թఖ 6 0x3FF5B018 ᆺཿ + FLASH_ENCRYPTION_BUFFER_5_REG Flash ࡆૡ buffer ࠷թఖ 7 0x3FF5B01C ᆺཿ + FLASH_ENCRYPTION_BUFFER_6_REG ࡆૡҠቔ॥ᇅ࠷թఖ 0x3FF5B020 ᆺཿ + FLASH_ENCRYPTION_BUFFER_7_REG ோຓ flash ֹᆶ࠷թఖ 0x3FF5B024 ᆺཿ + FLASH_ENCRYPTION_START_REG ࡆૡҠቔሑ෿࠷թఖ 0x3FF5B028 ᆺ‫؀‬ + FLASH_ENCRYPTION_ADDRESS_REG + FLASH_ENCRYPTION_DONE_REG + +26.5 ࠷թఖ 0 + + Register 26.1. FLASH_ENCRYPTION_BUFFER_n_REG (n: 0­7) (0x0+4*n) Reset + + 31 + + 0x000000000 + + FLASH_ENCRYPTION_BUFFER_n_REG ࢳૡ֥ buffer ඔbčᆺཿĎ + +ুᶈྐ༏॓࠯ 548 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 26 ோຓթԥఖࡆૡაࢳૡ (FLASH) + + Register 26.2. FLASH_ENCRYPTION_START_REG (0x020) + + (reserved) FLASH_START + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + FLASH_START ࡼՎ໊ᇂູ 1đఓ‫ࡆ׮‬ૡҠቔbčᆺཿĎ + + Register 26.3. FLASH_ENCRYPTION_ADDRESS_REG (0x024) + +31 0 + + 0x000000000 Reset + + FLASH_ENCRYPTION_ADDRESS_REG ோຓ flash ֥ൌֹᆶđᆃ۱ൌֹᆶсྶ൞ 8-word ؓఊ + ֥bčᆺཿĎ + + Register 26.4. FLASH_ENCRYPTION_DONE_REG (0x028) + + (reserved) FLASH_DONE + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + FLASH_DONE ࡆૡҠቔປӮުđՎູ໊ 1bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 549 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + +27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + +27.1 ‫ۀ‬ඍ + +ESP32 ᇏ֥ૄ۱ຓഡ‫ބ‬թԥఖ๙‫ ݖ‬MMUčթԥఖܵ৘ֆჭĎࠇ MPUčթԥఖЌ޹ֆჭĎФ٠໙b۴ऌ OS ۳ +ჍႋႨ֥ಃཋđMPU ‫ ބ‬MMU ॖၛᄍྸࠇ࣌ᆸႋႨ٠໙թԥఖଖ҆‫ބٳ‬ຓഡbMMU ߎॖၛࣉྛྴֹᆶ‫ބ‬ൌֹ +ᆶ֥ሇߐđࡼோഈࠇோຓթԥఖֹ֥ᆶٓຶ႘ഝ֞ଖ۱ྴ୅թԥఖ౵თbᆃུ႘ഝॖ۴ऌႋႨӱ྽஥ᇂđၹՎ +ૄ۱ႋႨӱ྽֥ଽթॖ۴ऌఃᄎྛ෮ླࣉྛ஥ᇂbOS ‫ބ‬ႋႨӱ྽ᄎྛൈđ‫ٳ‬љ஥Ⴕ၂۱ࣉӱ‫ݼ‬čࠧ PIDĎđႨ +Ⴟ౵‫ٳ‬дՎbࣉӱ‫܋ݼ‬Ⴕ 8 ۱bૄ۱ OS ‫ބ‬ႋႨӱ྽‫׻‬Ⴕሱ֥࠭႘ഝ‫ބ‬ಃཋb + +27.2 ᇶေหྟ + + • PRO_CPU ა APP_CPU ۲Ⴕ 8 ۱ࣉӱ + + • MPU/MMU ࠎႿࣉӱ֥ PID ؓோഈթԥఖaோຓթԥఖaຓഡࣉྛܵ৘ + + • ோഈթԥఖႮ MPU/MMU ܵ৘ + + • ோຓթԥఖႮ MMU ܵ৘ + + • ຓഡႮ MPU ܵ৘ + +27.3 ‫ିۿ‬૭ඍ + +27.3.1 PID ॥ᇅఖ + +ᄝ ESP32 ᇏđPID ॥ᇅఖԉ֒ᆷൕఖđཟ MMU/MPU ๙ᆩ֒భᄎྛս઒֥ӱ྽֥ PIDbOS ૄՑࡼഈ༯໓్ߐ +֞ਸ਼၂ႋႨൈ, ߶۷ྍ PID ॥ᇅఖᇏ֥ PIDb๙‫ݖ‬஥ᇂđPID ॥ᇅఖॖၛ࡟ҩᇏ؎ѩሱ‫ ࡼ׮‬PID ్ߐ֞ OS ֥ +PIDb + +༢๤ᇏႵਆ۱ຓഡ PID ॥ᇅఖđ‫ٳ‬љႨႿ ESP32 ᇏ֥ਆ۱ CPUbૄ۱ CPU ۲Ⴕ၂۱ PID ॥ᇅఖđି‫ܔ‬ᄝླေ +ൈᄍྸ҂๝֥ CPU ഈᄎྛ҂๝֥ࣉӱb + +27.3.2 MPU/MMU + +MPU ‫ ބ‬MMU ࠎႿ٠໙ຓഡ‫ބ‬թԥఖ֥ࣉӱܵ৘ோഈթԥఖđோຓթԥఖ‫ބ‬ຓഡb֒ս઒൫๭٠໙൳ +MMU/MPU Ќ޹֥թԥఖ౵თࠇຓഡൈđMMU ࠇ MPU ࡼՖᄎྛ‫ࣉھ‬ӱ֥ CPU ෮ؓႋ֥ PID ളӮఖࢤ൬ +PIDb + +MMU ‫ ބ‬MPU ࣇࠎႿ‫ ھ‬PID ؓோഈթԥఖ‫ބ‬ோຓթԥఖࣉྛܵ৘đѩ҂ॉ੮ᄎྛս઒֥൞ଧ۱ CPU; ၹՎđଽ +҆թԥఖ‫ބ‬ຓഡ֥ MMU ‫ ބ‬MPU ᆺႵ 8 ۱҂๝ PID ֥஥ᇂ࿊ཛbཌྷбᆭ༯đܵ৘ோຓթԥఖ֥ MMU ҂ࣇ് +љ PIDđ‫്ߎ౏ط‬љ‫ؿ‬ෂ౨౰٠໙ோຓթԥఖ֥ CPUbࠧ҂ંӱ྽ᄎྛᄝ APP_CPU ࠇ PRO_CPU ഈđMMU +‫׻‬ऎႵૄ۱ PID ֥஥ᇂ࿊ཛbൌ࠽ႋႨᇏؓႿ๝၂۱ࣉӱ֥஥ᇂđ൐֤টሱਆ۱ CPU ֥٠໙ି‫ࠆܔ‬౼֞ཌྷ๝ +֥ଽಸđ֌ᆃဢቓѩ҂൞႗ࡱေ౰b + +ࠎႿ PID ֥஥ᇂ࿊ཛđMPU ॖၛᄍྸࠇऋधࣉӱ٠໙թԥఖ౵თࠇຓഡbMMU ္ऎႵ‫ିۿھ‬đѩ౏ିࡼࣉӱ +֥ྴֹᆶ٠໙ሇߐູൌֹᆶ٠໙đՖ‫ط‬٠໙ॖିປಆ҂๝֥໾৘թԥఖ౵თbၹՎđMMU ܵ৘֥թԥఖ෮ൌགྷ +֥႘ഝॖၛࠎႿࣉӱ‫ٳ‬љ஥ᇂb + +27.3.2.1 ళೆൔթԥఖ + +ோഈթԥఖႮ‫ ֥קܥିۿ‬MPUđॖ஥ᇂ֥ MPU ‫ ބ‬MMU ܵ৘ğ + +ুᶈྐ༏॓࠯ 550 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + + і 27­1. ோഈթԥఖ֥ MPU ‫ ބ‬MMU ࢲ‫ܒ‬ + +թԥఖ଀ሳ նཬ ֹᆶٓຶ ܵ৘թԥఖ֥ MPU +ROM0 +ROM1 384 KB ष൓ ࢲඏ Static MPU +SRAM0 64 KB Static MPU + 64 KB 0x4000_0000 0x4005_FFFF Static MPU +SRAM1 (‫ֹ؟‬ᆶ٠໙) 128 KB SRAM0 MMU + 128 KB 0x3FF9_0000 0x3FF9_FFFF Static MPU +SRAM2 128 KB Static MPU +RTC FAST (‫ֹ؟‬ᆶ٠໙) 32 KB 0x4007_0000 0x4007_FFFF Static MPU +RTC SLOW 72 KB Static MPU + 128 KB 0x4008_0000 0x4009_FFFF SRAM2 MMU + 8 KB RTC FAST MPU + 8 KB 0x3FFE_0000 0x3FFF_FFFF RTC FAST MPU + 8 KB RTC SLOW MPU + 0x400A_0000 0x400B_FFFF + + 0x4000_0000 0x4000_7FFF + + 0x3FFA_E000 0x3FFB_FFFF + + 0x3FFC_0000 0x3FFD_FFFF + + 0x3FF8_0000 0x3FF8_1FFF + + 0x400C_0000 0x400C_1FFF + + 0x5000_0000 0x5000_1FFF + +Static MPU + +ROM0đROM1đSRAM0 ֥֮ 64 KBđSRAM1 ‫ ބ‬SRAM2 ֥֮ 72 KB Ⴎ Static MPU ॥ᇅbᆃུ MPU Ⴎ႗ࡱ +॥ᇅđ҂ିႮೈࡱ஥ᇂb෱ૌࣇ๙‫֒ݖ‬భࣉӱ֥ PID ܵ৘ࣉӱؓթԥఖ౵თ֥٠໙b֒ࣉӱ֥ PID ູ 0 ࠇ 1 ൈđ +ॖၛ൐Ⴈі 27-1 ᇏᆷ‫ֹ֥ק‬ᆶ‫؀؍‬౼č֒թԥఖູ RAM ൈႨཌྷႋֹᆶ‫؍‬ཿೆĎթԥఖb֒ PID ູ 2 ֞ 7đթ +ԥఖ҂ॖФ٠໙b + +RTC FAST & RTC SLOW MPU + +8 KB ֥ RTC FAST Memory ၛࠣ 8 KB ֥ RTC SLOW Memory Ⴎਆ۱ॖ஥ᇂ֥ MPU ॥ᇅb๙‫ݖ‬஥ᇂ +RTC_CNTL_ RTC_PID_CONFIG_REG ‫ ބ‬DPORT_AHBLITE_MPU_TABLE_RTC_REG ࠷թఖđMPU ॖၛᄍྸࠇ +࣌ᆸૄ۱ֆ‫ ֥׿‬PID ٠໙թԥఖb๙‫ݖ‬ഡᇂᆃུ࠷թఖᇏଖ۱໊đॖၛᄍྸཌྷႋ֥ PID Ֆթԥఖ‫؀‬౼ࠇཿೆඔ +ऌđౢԢ‫໊ھ‬ᄵ࣌ᆸཌྷႋ֥ PID Ֆթԥఖ‫؀‬౼ࠇཿೆඔऌbPID ູ 0 ‫ ބ‬1 ֥ࣉӱ൓ᇔॖၛ٠໙ RTC SLOW թ +ԥఖđ‫ھ‬஥ᇂ໭‫ڿྩم‬bі 27-2 ‫ ބ‬27-3 ૭ඍਔ࠷թఖ໊ა PID ᆭࡗ֥႘ഝܱ༢b + + і 27­2. ܵ৘ RTC FAST Memory ֥ MPU + + шࢸֹᆶ ಃཋ + PID +նཬ ֮ ۚ + RTC_CNTL_RTC_PID_CONFIG ໊ +8 KB 0x3FF8_0000 0x3FF8_1FFF 01234567 +8 KB 0x400C_0000 0x400C_1FFF 01234567 + + і 27­3. ܵ৘ RTC SLOW Memory ֥ MPU + +նཬ шࢸֹᆶ PID = 0/1 ಃཋ + ֮ ۚ PID + +8 KB 0x5000_0000 0x5000_1FFF ‫؀‬/ཿ DPORT_AHBLITE_MPU_TABLE_RTC_REG ໊ + 234567 + 012345 + +ুᶈྐ༏॓࠯ 551 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + +࠷թఖ RTC_CNTL_RTC_PID_CONFIG_REG ൞ RTC ຓഡ֥၂҆‫ٳ‬đᆺିႮ PID ູ 0 ֥ࣉӱྩ‫࠷ ;ڿ‬թఖ +DPORT _AHBLITE_MPU_TABLE_RTC_REG ൞၂۱ Dport ࠷թఖđॖၛႮ PID ູ 0 ࠇ 1 ֥ࣉӱྩ‫ڿ‬b + +ܵ৘ SRAM0 ‫ ބ‬SRAM2 ۚ 128 KB ֥ MMU + +SRAM0 ֥ۚ 128 KB ‫ ބ‬SRAM ֥ۚ 128 KB ‫׻‬Ⴎ MMU ܵ৘bᆃུ MMU ҂ࣇॖၛ‫ ބ‬MPU ၂ဢᄍྸࠇ࣌ᆸࣉ +ӱ٠໙෱ૌܵ৘֥թԥఖٓຶđ‫ ࡼܔିߎ౏ط‬CPU ‫؀‬౼ࠇཿೆֹ֥ᆶčྴֹᆶĎሇߐ֞թԥఖᇏॖି҂๝ֹ֥ +ᆶčൌֹᆶĎb + +ູਔൌགྷᆃ၂ׄđோഈ RAM MMU ࡼఃܵ৘֥թԥఖٓຶ߃‫ ູٳ‬16 ်b်նཬॖ஥ᇂູ 8 KBđ4 KB ‫ ބ‬2 KBb +်֒նཬູ 8 KB ൈđ16 ်Ї‫ݣ‬ਔᆜ۱ 128 KB ֥թԥఖॢࡗ; ်֒նཬູ 4 KB ࠇ 2 KB ൈđթԥఖॢࡗ֥ଌ +؊ࡼႵ‫ٳ‬љູ 64 KB ࠇ 96 KB ౵თ҂൳ MPU ܵ৘bোරႿྴֹᆶ‫ބ‬ൌֹᆶđ်္ॖ‫ֹྴູٳ‬ᆶ်‫ބ‬ൌֹᆶ် +ਆᇕğMMU ॖၛࡼྴֹᆶ်ଽֹ֥ᆶሇߐູൌֹᆶ်ଽֹ֥ᆶb + +ؓႿ PID ູ 0 ‫ ބ‬1 ֥ࣉӱđྴֹᆶ်აൌֹᆶ်ֹ֥ᆶ႘ഝ൞၂ؓ၂֥bࠧؓଖ۱ྴֹᆶ်֥‫؀‬౼ࠇཿೆሹФ +ሇߐູؓປಆཌྷ๝֥ൌֹᆶ်֥‫؀‬౼ࠇཿೆbᆃᄍྸᄝ PID 0 ‫ބ‬/ࠇ 1 ༯ᄎྛ֥Ҡቔ༢๤ሹ൞ି‫ܔ‬٠໙ᆜ۱໾৘ +թԥఖٓຶb + +֌൞ؓႿ PID ູ 2 ֞ 7 ֥ࣉӱđMMU ॖၛࠎႿૄ۱ PIDđᇗྍ஥ᇂૄ۱ྴֹᆶ်đ൐ః႘ഝ֞҂๝֥ൌֹᆶ +်bၹՎđؓྴֹᆶ်ଽ֥ொ၍ਈ֥‫؀‬౼‫ބ‬ཿೆॖФሇߐູؓ҂๝ൌֹᆶ်ଽ֥ཌྷ๝ொ၍ਈ֥‫؀‬౼‫ބ‬ཿೆbೂ +๭ 27-1 ෮ൕđCPUčᄎྛ PID ູ 2 ֞ 7 ֥ࣉӱĎӇ൫٠໙թԥఖֹᆶ 0x3FFC_2345b‫ֹھ‬ᆶᄝྴֹᆶ် 1 ֥ +թԥఖ౵თଽđொ၍ਈູ 0x0345bMMU Фᆷൕࡼ‫ ھ‬PID ֥ࣉӱؓྴֹᆶ် 1 ֥٠໙ሇߐູൌֹᆶ် 2 ֥٠ +໙bၹՎđթԥఖ٠໙Фᇗྍ‫ק‬ཟູ٠໙ྴ୅ֹᆶ် 2 ᇏཌྷ๝֥ொ၍đൌ࠽٠໙֥ൌֹᆶູ 0x3FFC_4345bၛ +༯ൕ২ᇏ်֥նཬູ 8 KBb + +CPU VIRTUAL MMU PHYSICAL + 3FFC_0000 + PAGE 0 3FFC_2000 PAGE 0 3FFC_0000 + 3FFC_2345 PAGE 1 3FFC_4000 3FFC_2000 + 3FFC_6000 3FFC_4345 PAGE 1 3FFC_4000 + PAGE 2 PAGE 2 3FFC_6000 + + PAGE 15 3FFD_E000 PAGE 15 3FFD_E000 + 3FFE_0000 3FFE_0000 + + ๭ 27­1. MMU ٠໙ൕ২ + + і 27­4. ܵ৘ோഈ SRAM 0 ‫ ބ‬SRAM2 ഺჅ 128 KB ֥ MMU ်ଆൔ + +DPORT_IMMU_PAGE_MODE DPORT_DMMU_PAGE_MODE ်նཬ +0 0 8 KB +1 1 4 KB +2 2 2 KB + +ুᶈྐ༏॓࠯ 552 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + +٤ MMU ܵ৘֥թԥఖ + +ؓႿ MMU ܵ৘֥ SRAM0 ‫ ބ‬SRAM2 ౵თđ်նཬॖ஥ᇂູ 8 KBđ4 KB ‫ ބ‬2 KBbೂі 27-4 ෮ൕđ်նཬ๙ +‫࠷ݖ‬թఖ DPORT_IMMU_PAGE_MODE_REG ‫ ބ‬DPORT_DMMU_PAGE_MODE_REG ᇏ֥ +DPORT_IMMU_PAGE_MODE (ؓႿ SRAM0) ‫ ބ‬DPORT_DMMU_PAGE_MODE (ؓႿ SRAM2) ໊ഡᇂbၹູૄ۱ +թԥఖ౵თ်֥ඔਈ‫ ູקܥ‬16đ෮ၛ်֒նཬູ 8 KB ൈđᆃ 16 ်‫֥ۂڭ‬թԥఖॢࡗູ 128 KBĠ်֒նཬູ +4 KB ൈđ‫֥ۂڭ‬թԥఖॢࡗູ 64 KBĠ်֒նཬູ 2 KB ൈđ‫֥ۂڭ‬թԥఖॢࡗູ 32 KBb + +ၹՎđؓႿ 8 KB ်đᆜ۱թԥఖႮ MMU ܵ৘Ġ֌ؓႿః෱်նཬđթԥఖ֥ 128 KB Ⴕ၂҆‫ٳ‬҂൳ MMU ܵ +৘bऎุ൞đؓႿ 4 KB ်֥նཬđ҂൳ MMU ܵ৘֥౵თ൞ 0x4009_0000 ֞ 0x4009_FFFF ‫ ބ‬0x3FFD_0000 +֞ 0x3FFD_FFFFĠؓႿ 2 KB ်֥նཬđ҂൳ MMU ܵ৘֥౵თ൞ 0x4008_8000 ֞ 0x4009_FFFF ‫ބ‬ +0x3FFC_8000 ֞ 0x3FFD_FFFFbᆃུٓຶॖႮ PID ູ 0 ࠇ 1 ֥ࣉӱ‫؀‬ཿĠPID ູ 2 ֞ 7 ֥ࣉӱ໭‫م‬٠໙Վթ +ԥఖb + +թԥఖॢࡗᇏđ်֥҃अ൞ཌྟ֥đࠧđMMU ܵ৘֥ SRAM0 ် n ‫ֹ֥ۂڭ‬ᆶٓຶູ +0x40080000 + (pagesize ∗ n) ֞ 0x40080000 + (pagesize ∗ (n + 1) − 1)Ġ๝৘đMMU ܵ৘֥ SRAM2 ် n ‫֥ۂڭ‬ +ֹᆶٓຶູ 0x3F F C0000 + (pagesize ∗ n) ֞ 0x3F F C0000 + (pagesize ∗ (n + 1) − 1)bі 27-5 ‫ ބ‬27-6 ૭ඍਔ +҂๝်նཬଆൔ༯đႮ MMU ܵ৘֥ SRAM0 ‫ ބ‬SRAM2 ෮Ⴕ်ֹᆶٓຶb + + і 27­5. SRAM0 MMU ်шࢸֹᆶ + +် 8 KB ် 4 KB ် 2 KB ် + +0 ֮ ۚ ֮ ۚ ֮ ۚ +1 +2 40080000 40081FFF 40080000 40080FFF 40080000 400807FF +3 +4 40082000 40083FFF 40081000 40081FFF 40080800 40080FFF +5 +6 40084000 40085FFF 40082000 40082FFF 40081000 400817FF +7 +8 40086000 40087FFF 40083000 40083FFF 40081800 40081FFF +9 +10 40088000 40089FFF 40084000 40084FFF 40082000 400827FF +11 +12 4008A000 4008BFFF 40085000 40085FFF 40082800 40082FFF +13 +14 4008C000 4008DFFF 40086000 40086FFF 40083000 400837FF +15 +ഺჅॢࡗ 4008E000 4008FFFF 40087000 40087FFF 40083800 40083FFF + + 40090000 40091FFF 40088000 40088FFF 40084000 400847FF + + 40092000 40093FFF 40089000 40089FFF 40084800 40084FFF + + 40094000 40095FFF 4008A000 4008AFFF 40085000 400857FF + + 40096000 40097FFF 4008B000 4008BFFF 40085800 40085FFF + + 40098000 40099FFF 4008C000 4008CFFF 40086000 400867FF + + 4009A000 4009BFFF 4008D000 4008DFFF 40086800 40086FFF + + 4009C000 4009DFFF 4008E000 4008EFFF 40087000 400877FF + + 4009E000 4009FFFF 4008F000 4008FFFF 40087800 40087FFF + + - - 40090000 4009FFFF 40088000 4009FFFF + +ুᶈྐ༏॓࠯ 553 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + + і 27­6. SRAM2 MMU ်шࢸֹᆶ + +် 8 KB ် 4 KB ် 2 KB ် + +0 ֮ ۚ ֮ ۚ ֮ ۚ +1 +2 3FFC0000 3FFC1FFF 3FFC0000 3FFC0FFF 3FFC0000 3FFC07FF +3 +4 3FFC2000 3FFC3FFF 3FFC1000 3FFC1FFF 3FFC0800 3FFC0FFF +5 +6 3FFC4000 3FFC5FFF 3FFC2000 3FFC2FFF 3FFC1000 3FFC17FF +7 +8 3FFC6000 3FFC7FFF 3FFC3000 3FFC3FFF 3FFC1800 3FFC1FFF +9 +10 3FFC8000 3FFC9FFF 3FFC4000 3FFC4FFF 3FFC2000 3FFC27FF +11 +12 3FFCA000 3FFCBFFF 3FFC5000 3FFC5FFF 3FFC2800 3FFC2FFF +13 +14 3FFCC000 3FFCDFFF 3FFC6000 3FFC6FFF 3FFC3000 3FFC37FF +15 +ഺჅॢࡗ 3FFCE000 3FFCFFFF 3FFC7000 3FFC7FFF 3FFC3800 3FFC3FFF + + 3FFD0000 3FFD1FFF 3FFC8000 3FFC8FFF 3FFC4000 3FFC47FF + + 3FFD2000 3FFD3FFF 3FFC9000 3FFC9FFF 3FFC4800 3FFC4FFF + + 3FFD4000 3FFD5FFF 3FFCA000 3FFCAFFF 3FFC5000 3FFC57FF + + 3FFD6000 3FFD7FFF 3FFCB000 3FFCBFFF 3FFC5800 3FFC5FFF + + 3FFD8000 3FFD9FFF 3FFCC000 3FFCCFFF 3FFC6000 3FFC67FF + + 3FFDA000 3FFDBFFF 3FFCD000 3FFCDFFF 3FFC6800 3FFC6FFF + + 3FFDC000 3FFDDFFF 3FFCE000 3FFCEFFF 3FFC7000 3FFC77FF + + 3FFDE000 3FFDFFFF 3FFCF000 3FFCFFFF 3FFC7800 3FFC7FFF + + - - 3FFD0000 3FFDFFFF 3FFC8000 3FFDFFFF + +MMU ႘ഝ + +SRAM0 MMU ‫ ބ‬SRAM2 MMUđ๙‫ݖ‬၂ቆ 16 ۱࠷թఖ॥ᇅ٠໙ಃཋ‫ֹྴބ‬ᆶ်֞ൌֹᆶ်֥႘ഝbაః෱ն +‫؟‬ඔ MMU ҂๝֥൞đૄ۱࠷թఖ॥ᇅ၂۱ൌֹᆶ်đ‫ط‬҂൞၂۱ྴֹᆶ်bᆃུ࠷թఖथ‫ק‬ଧུ PID ֥ࣉӱ +ॖၛ٠໙໾৘թԥఖၛࠣଧ۱ྴֹᆶ်႘ഝ֞‫࠷ھ‬թఖ॥ᇅ֥ൌֹᆶ်bі 27-7 ૭ඍਔᆃུ࠷թఖ໊֥bླ +ေᇿၩ֥൞đᆃུ࠷թఖᆺ॥ᇅ PID ູ 2 ֞ 7 ֥ࣉӱ֥٠໙ಃཋĠPID ູ 0 ࠇ 1 ֥ࣉӱሹ൞ॖၛ‫؀‬ཿ෮Ⴕ်֥đ +ѩ౏ીႵྴֹᆶ֞ൌֹᆶ֥႘ഝbࠧ໭ંᆃུ࠷թఖ֥ഡᇂೂ‫ޅ‬đ֒ PID ູ 0 ࠇ 1 ֥ࣉӱ٠໙် x ൈđሹ൞٠ +໙ൌֹᆶ် xbᆃ 16 ۱࠷թఖ‫ބ‬॥ᇅ်նཬ֥࠷թఖ DPORT_IMMU_PAGE_MODE_REG ‫ބ‬ +DPORT_DMMU_PAGE_MODE_REG ᆺିႮ PID ູ 0 ࠇ 1 ֥ࣉӱཿೆb + +ুᶈྐ༏॓࠯ 554 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + + і 27­7. DPORT_DMMU_TABLEn_REG ‫ ބ‬DPORT_IMMU_TABLEn_REG + +[6:4] PID 2~ 7 ֥٠໙ಃཋ [3:0] ֹᆶಃཋ +0 PID 2 ~ 7 ֥ࣉӱ‫׻‬ીႵ٠໙ಃཋb 0x00 ྴ୅် 0 ॖ٠໙‫ھ‬໾৘်b +1 PID 2 ~ 7 ֥ࣉӱ‫׻‬Ⴕ٠໙ಃཋb 0x01 ྴ୅် 1 ॖ٠໙‫ھ‬໾৘်b +2 ᆺႵ PID 2 ֥ࣉӱႵ٠໙ಃཋb 0x02 ྴ୅် 2 ॖ٠໙‫ھ‬໾৘်b +3 ᆺႵ PID 3 ֥ࣉӱႵ٠໙ಃཋb 0x03 ྴ୅် 3 ॖ٠໙‫ھ‬໾৘်b +4 ᆺႵ PID 4 ֥ࣉӱႵ٠໙ಃཋb 0x04 ྴ୅် 4 ॖ٠໙‫ھ‬໾৘်b +5 ᆺႵ PID 5 ֥ࣉӱႵ٠໙ಃཋb 0x05 ྴ୅် 5 ॖ٠໙‫ھ‬໾৘်b +6 ᆺႵ PID 6 ֥ࣉӱႵ٠໙ಃཋb 0x06 ྴ୅် 6 ॖ٠໙‫ھ‬໾৘်b +7 ᆺႵ PID 7 ֥ࣉӱႵ٠໙ಃཋb 0x07 ྴ୅် 7 ॖ٠໙‫ھ‬໾৘်b + 0x08 ྴ୅် 8 ॖ٠໙‫ھ‬໾৘်b + 0x09 ྴ୅် 9 ॖ٠໙‫ھ‬໾৘်b + 0x10 ྴ୅် 10 ॖ٠໙‫ھ‬໾৘်b + 0x11 ྴ୅် 11 ॖ٠໙‫ھ‬໾৘်b + 0x12 ྴ୅် 12 ॖ٠໙‫ھ‬໾৘်b + 0x13 ྴ୅် 13 ॖ٠໙‫ھ‬໾৘်b + 0x14 ྴ୅် 14 ॖ٠໙‫ھ‬໾৘်b + 0x15 ྴ୅် 15 ॖ٠໙‫ھ‬໾৘်b + +SRAM0 ‫ ބ‬SRAM2 MMU ֥ҵၳ + +Ⴎ SRAM0 MMU ܵ৘֥թԥఖ๙‫ݖ‬ԩ৘ఖᆷ਷ሹཌФ٠໙đ‫ط‬ԩ৘ఖ๙‫ݖ‬ඔऌሹཌ٠໙Ⴎ SRAM2 MMU ॥ᇅ +֥թԥఖbၹՎđ๙ӈ֥ቓ‫م‬൞ࡼս઒թԥᄝ SRAM0 ֥ MMU ်ᇏđࡼඔऌթᄝ SRAM2 ֥ MMU ်ᇏbၹູ +๙ӈ౦ঃ༯đᆃུ PID ֥ႋႨӱ྽໭ླྩ‫ڿ‬ሱ֥࠭ս઒đPID ູ 2 ֞ 7 ࣉӱؓ SRAM0 ֥ MMU ်֥٠໙൞ᆺ +‫֥؀‬bಖ‫ط‬đᆃུႋႨӱ྽сྶି‫ڿྩܔ‬ఃඔऌ҆‫ٳ‬đၹՎᄍྸ෱ૌ‫؀‬ཿ໊Ⴟ SRAM2 ᇏ֥ MMU ်bೂഈ෮ +ඍđPID ູ 0 ࠇ 1 ֥ࣉӱ൓ᇔି‫؀ܔ‬ཿ٠໙ਆ۱ SRAM0 ‫ ބ‬SRAM2b + +DMA MPU + +ႋႨӱ྽ॖିླေ஥ᇂ DMA ࡼඔऌᆰࢤ‫ؿ‬ෂ֞෱ૌॖၛ॥ᇅ֥ຓഡđࠇᆀՖᆃུຓഡᇏ‫ؿ‬ෂඔऌb๙‫ݖ‬٠໙ +DMAđ‫ذ‬ၩࣉӱॖିࡼඔऌ‫گ‬ᇅ֞ః໭‫م‬ᆞӈ٠໙֥թԥఖ౵თđࠇᆀࡼՖః໭‫م‬ᆞӈ٠໙֥թԥఖ౵თ‫گ‬ᇅ +ඔऌbູਔٝᆸᆃᇕ౦ঃ‫ؿ‬ളđDMA MPU ॖၛႨႿ࣌ᆸটሱႿऎႵૹ‫ۋ‬ඔऌ֥թԥఖ౵თ֥ DMA Ԯ +ൻb + +ؓႿோഈ SRAM1 ‫ ބ‬SRAM2 թԥఖᇏ֥ૄ۱ 8 KB ౵თđMPU ๙‫ ݖ‬DPORT_AHB_MPU_TABLE_n_REG ࠷թ +ఖᇏ֥ଖ۱໊টᄍྸࠇ࣌ᆸ DMA ٠໙Վ౵თbDMA MPU ࣇ൐Ⴈᆃ໊ུটथ‫ק‬൞‫ڎ‬ॖၛष൓ DMA Ԯൻ; ѩ҂ +ॉ੮ࣉӱ֥ PIDb೏ OS ၛၳ‫ܒ‬ٚൔཋᇅఃࣉӱđᄝഈ༯໓్ߐൈđOS ླေ۴ऌေᄎྛ֥ࣉӱটᇗྍ஥ᇂᆃུ +࠷թఖ֥ᆴb + +і 27-8 བྷ༥ඪૼਔؓ SRAM1 ‫ ބ‬SRAM2 ֥ૄ۱ 8 KB ౵თ֥٠໙ࣉྛܵ৘֥࠷թఖ໊b֒࠷թఖ໊Фᇂ 1 ൈđ +DAM ॖၛ‫؀‬/ཿؓႋ֥ 8 KB թԥఖॢࡗb֒‫໊ھ‬ФౢԢൈđDMA ؓ‫ֹھ‬ᆶॢࡗ֥٠໙ࡼФ࣌ᆸb + +ুᶈྐ༏॓࠯ 555 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + + і 27­8. ᆌؓ DMA ֥ MPU ഡᇂ + +նཬ шࢸֹᆶ ಃཋ + +8 KB ֮ ۚ ࠷թఖ ໊ +8 KB +8 KB ோഈ SRAM 2 +8 KB +8 KB 0x3FFA_E000 0x3FFA_FFFF DPORT_AHB_MPU_TABLE_0_REG 0 +8 KB +8 KB 0x3FFB_0000 0x3FFB_1FFF DPORT_AHB_MPU_TABLE_0_REG 1 +8 KB +8 KB 0x3FFB_2000 0x3FFB_3FFF DPORT_AHB_MPU_TABLE_0_REG 2 +8 KB +8 KB 0x3FFB_4000 0x3FFB_5FFF DPORT_AHB_MPU_TABLE_0_REG 3 +8 KB +8 KB 0x3FFB_6000 0x3FFB_7FFF DPORT_AHB_MPU_TABLE_0_REG 4 +8 KB +8 KB 0x3FFB_8000 0x3FFB_9FFF DPORT_AHB_MPU_TABLE_0_REG 5 +8 KB +8 KB 0x3FFB_A000 0x3FFB_BFFF DPORT_AHB_MPU_TABLE_0_REG 6 +8 KB +8 KB 0x3FFB_C000 0x3FFB_DFFF DPORT_AHB_MPU_TABLE_0_REG 7 +8 KB +8 KB 0x3FFB_E000 0x3FFB_FFFF DPORT_AHB_MPU_TABLE_0_REG 8 +8 KB +8 KB 0x3FFC_0000 0x3FFC_1FFF DPORT_AHB_MPU_TABLE_0_REG 9 +8 KB +8 KB 0x3FFC_2000 0x3FFC_3FFF DPORT_AHB_MPU_TABLE_0_REG 10 + +8 KB 0x3FFC_4000 0x3FFC_5FFF DPORT_AHB_MPU_TABLE_0_REG 11 +8 KB +8 KB 0x3FFC_6000 0x3FFC_7FFF DPORT_AHB_MPU_TABLE_0_REG 12 +8 KB +8 KB 0x3FFC_8000 0x3FFC_9FFF DPORT_AHB_MPU_TABLE_0_REG 13 +8 KB +8 KB 0x3FFC_A000 0x3FFC_BFFF DPORT_AHB_MPU_TABLE_0_REG 14 +8 KB +8 KB 0x3FFC_C000 0x3FFC_DFFF DPORT_AHB_MPU_TABLE_0_REG 15 +8 KB +8 KB 0x3FFC_E000 0x3FFC_FFFF DPORT_AHB_MPU_TABLE_0_REG 16 +8 KB +8 KB 0x3FFD_0000 0x3FFD_1FFF DPORT_AHB_MPU_TABLE_0_REG 17 +8 KB + 0x3FFD_2000 0x3FFD_3FFF DPORT_AHB_MPU_TABLE_0_REG 18 + + 0x3FFD_4000 0x3FFD_5FFF DPORT_AHB_MPU_TABLE_0_REG 19 + + 0x3FFD_6000 0x3FFD_7FFF DPORT_AHB_MPU_TABLE_0_REG 20 + + 0x3FFD_8000 0x3FFD_9FFF DPORT_AHB_MPU_TABLE_0_REG 21 + + 0x3FFD_A000 0x3FFD_BFFF DPORT_AHB_MPU_TABLE_0_REG 22 + + 0x3FFD_C000 0x3FFD_DFFF DPORT_AHB_MPU_TABLE_0_REG 23 + + 0x3FFD_E000 0x3FFD_FFFF DPORT_AHB_MPU_TABLE_0_REG 24 + + ோഈ SRAM 1 + + 0x3FFE_0000 0x3FFE_1FFF DPORT_AHB_MPU_TABLE_0_REG 25 + + 0x3FFE_2000 0x3FFE_3FFF DPORT_AHB_MPU_TABLE_0_REG 26 + + 0x3FFE_4000 0x3FFE_5FFF DPORT_AHB_MPU_TABLE_0_REG 27 + + 0x3FFE_6000 0x3FFE_7FFF DPORT_AHB_MPU_TABLE_0_REG 28 + + 0x3FFE_8000 0x3FFE_9FFF DPORT_AHB_MPU_TABLE_0_REG 29 + + 0x3FFE_A000 0x3FFE_BFFF DPORT_AHB_MPU_TABLE_0_REG 30 + + 0x3FFE_C000 0x3FFE_DFFF DPORT_AHB_MPU_TABLE_0_REG 31 + + 0x3FFE_E000 0x3FFE_FFFF DPORT_AHB_MPU_TABLE_1_REG 0 + + 0x3FFF_0000 0x3FFF_1FFF DPORT_AHB_MPU_TABLE_1_REG 1 + + 0x3FFF_2000 0x3FFF_3FFF DPORT_AHB_MPU_TABLE_1_REG 2 + + 0x3FFF_4000 0x3FFF_5FFF DPORT_AHB_MPU_TABLE_1_REG 3 + + 0x3FFF_6000 0x3FFF_7FFF DPORT_AHB_MPU_TABLE_1_REG 4 + + 0x3FFF_8000 0x3FFF_9FFF DPORT_AHB_MPU_TABLE_1_REG 5 + + 0x3FFF_A000 0x3FFF_BFFF DPORT_AHB_MPU_TABLE_1_REG 6 + +ুᶈྐ༏॓࠯ 556 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + +նཬ шࢸֹᆶ ಃཋ + +8 KB ֮ ۚ ࠷թఖ ໊ +8 KB + 0x3FFF_C000 0x3FFF_DFFF DPORT_AHB_MPU_TABLE_1_REG 7 + + 0x3FFF_E000 0x3FFF_FFFF DPORT_AHB_MPU_TABLE_1_REG 8 + +࠷թఖ DPROT_AHB_MPU_TABLE_0_REG ა DPROT_AHB_MPU_TABLE_1_REG ໊Ⴟ DPort ֹᆶॢࡗᇏbᆺ +Ⴕ PID ູ 0 ࠇ 1 ֥ࣉӱॖၛྩ‫ڿ‬ᆃਆ۱࠷թఖb + + ඪૼğ + ᄝ႗ࡱᇏđႵ 3 ่ᆷ਷ሹཌ‫ٳ‬љؓႋ V Addr1aV Addr2 ‫ ބ‬V Addr3đᆃ 3 ่ሹཌॖၛ๝ൈ‫ؿ‬ఏ‫؀‬/౼ᆷ٠໙đ֌൞ᆺ + Ⴕ၂۱٠໙൞ᆇൌ֥bೂ‫ݔ‬ໃФ௠з֥ሹཌӑ‫ݖ‬ਔ၂۱đପહ෮Ⴕ MMU іཛ֥ bit8 ႋ‫ھ‬ᇂ 0b‫ڎ‬ᄵđ֒໭ི֥ MMU + іཛФଖ۱٠໙൐Ⴈൈđࠧ൐Վ٠໙ԩીႵӱ྽đcache ္ࡼФ຀ᇾb + +27.3.2.2 ோຓթԥఖ + +ؓோຓ೺թ‫ބ‬ோຓ SPI RAM ֥٠໙๙‫ ݖ‬Cache ൌགྷđѩ౏Ⴎ MMU ܵ৘b۴ऌࣉӱ֥ PID ၛࠣᄎྛ‫ࣉھ‬ӱ֥ +CPUđCache MMU ॖၛൌགྷ҂๝֥႘ഝđቓ‫م‬োරႿோഈթԥఖ MMUbࠧđؓႿթԥఖ֥ૄ۱ྴֹᆶ်đ‫׻‬ +Ⴕؓႋ࠷թఖབྷ༥ඪૼ‫ֹྴھ‬ᆶ်ႋ႘ഝ֞ଧ၂۱ൌֹᆶ်b֌ܵ৘ோഈթԥఖ֥ MMU ‫ ބ‬Cache MMU ᆭࡗ +թᄝҵၳb൮༵đCache MMU ऎႵ‫֥קܥ‬်૫նཬčோຓ೺թ်նཬູ 64 KBđோຓ RAM ်նཬູ 32 KBĎĠ +ఃՑđCache MMU ऎႵႨႿૄ۱ PID ‫ބ‬ԩ৘ఖଽ‫֥ނ‬ཁൔ႘ഝіđ҂๙‫ ݖ‬MMU ஥ᇂཛট॥ᇅ٠໙ಃཋbᄝ༯ +໓ᇏđMMU ႘ഝ஥ᇂ࠷թఖࡼФ๤ӫູo஥ᇂཛpbᆃུ࠷թఖᆺିႮ PID ູ 0 ࠇ 1 ֥ࣉӱ٠໙ĠPID ູ 2 ֞ +7 ֥ࣉӱсྶ๙‫ ݖ‬PID ູ 0 ࠇ 1 ֥ࣉӱট‫ڿ‬э෱ૌ֥ MMU ഡᇂb + +ೂഈ෮ඍđMMU ஥ᇂཛႨႿࡼؓթԥఖྴֹᆶ်֥٠໙႘ഝ֞ؓթԥఖൌֹᆶ်֥٠໙bMMU ॥ᇅྴֹᆶॢ +ࡗ֥໴۱౵თđབྷ࡮і 27-9bֹᆶٓຶ V Addr1 ֞ V Addr4 ႨႿ٠໙ோຓ೺թđV AddrRAM ႨႿ٠໙ோຓ +RAMbᇿၩ V Addr4 ൞ V Addr0 ֥ሰࠢb + + і 27­9. ோຓթԥఖ֥ྴֹᆶ + +ֹᆶ նཬ ֮ шࢸֹᆶ ်ඔਈ + 0x3F40_0000 ۚ +V Addr0 4 MB 0x4000_0000 0x3F7F_FFFF 64 +V Addr1 4 MB 0x4040_0000 0x403F_FFFF 64* +V Addr2 4 MB 0x4080_0000 0x407F_FFFF 64 +V Addr3 4 MB 0x3F40_0000 0x40BF_FFFF 64 +V Addr4 1 MB 0x3F80_0000 0x3F4F_FFFF 16 +V AddrRAM 4 MB 0x3FBF_FFFF 128 + +* Վԩູਔіඍٚьࡼֹᆶٓຶཿቔ 0x4000_0000 ~ 0x403F_FFFF ᆃဢ၂۱ປᆜ֥ 4 MB ֹᆶॢࡗb֌ +ఃᇏ҆‫ֹٳ‬ᆶٓຶ໭‫م‬٠໙bֹᆶٓຶ 0x4000_0000 ~ 0x400C_1FFF ᆺ٠໙ோഈթԥఖbࠧ V Addr1 ֥ଖུ +஥ᇂཛ҂߶Ф൐Ⴈb + +ோຓ೺թ + +і 27-10 ‫ ބ‬27-11 བྷ༥૭ඍਔ஥ᇂཛ‫ݼ‬đྴ୅թԥఖٓຶ‫ ބ‬PID ֥ܱ༢bᆃਆ۱і۬ਙԛਔૄ۱թԥఖ౵თ‫ބ‬ +PID ቆ‫ކ‬෮ؓႋ֥ܵ৘႘ഝֻ֥၂۱ MMU ஥ᇂཛbі۬ᇏ֥ඔሳ൞ᆷܵ৘ֻ၂۱ֹᆶ်֥ MMU ஥ᇂཛĠoඔ +ਈp၂ਙіൕ်֥ඔਈđՎູؓႋ֥թԥఖֹᆶٓຶᅝႨ်֥ඔਈb + +ুᶈྐ༏॓࠯ 557 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + +ᆃਆ۱іЧᇉഈ൞ཌྷ๝֥đ౵љᄝႿ APP_CPU ֥஥ᇂཛ‫ݼ‬бؓႋ֥ PRO_CPU ஥ᇂཛ‫ݼ‬ն 2048bᇿၩđֹᆶ +ٓຶ V Addr0 ‫ ބ‬V Addr1 ᆺିႮ PID ູ 0 ࠇ 1 ֥ࣉӱ٠໙đV Addr4 ᆺିႮ PID ູ 2 ֞ 7 ֥ࣉӱ٠໙b + + і 27­10. PRO_CPU ֥ MMU ஥ᇂཛ‫ݼ‬ + +ֹᆶ ඔਈ PID ؓႋֻ֥၂۱ MMU ஥ᇂཛ + +V Addr0 64 0/1 2 3 4 5 6 7 +V Addr1 64 +V Addr2 64 0 - - - - - - +V Addr3 64 +V Addr4 16 64 - - - - - - + + 128 256 384 512 640 768 896 + + 192 320 448 576 704 832 960 + + - 1056 1072 1088 1104 1120 1136 + + і 27­11. APP_CPU ֥ MMU ஥ᇂཛ‫ݼ‬ + +ֹᆶ ඔਈ PID ؓႋֻ֥၂۱ MMU ஥ᇂཛ + +V Addr0 64 0/1 2 3 4 5 6 7 +V Addr1 64 2048 - - +V Addr2 64 2112 - - - - - - +V Addr3 64 2176 2304 2944 +V Addr4 16 2240 2368 - - - - 3008 + - 3104 3184 + 2432 2560 2688 2816 + + 2496 2624 2752 2880 + + 3120 3136 3152 3168 + +ೂၛഈі۬෮ൕđྴֹᆶ V Addr1 ᆺିႮ PID ູ 0 ࠇ 1 ֥ࣉӱ൐ႨbູՎህ૊Ⴕ၂ᇕଆൔ൐֤ PID ູ 2 ֞ 7 ֥ +ࣉӱି‫ܔ‬๙‫ֹݖ‬ᆶ V Addr1 ‫؀‬౼ோຓ೺թb֒࠷թఖ DPORT_PRO_CACHE_CTRL_REG ᇏ֥ DPORT_PRO_ +SINGLE_IRAM_ENA ໊ᇂ 1 ൈđMMU ࣉೆՎห൹ଆൔ൐֤ PRO_CPU ٠໙թԥఖb๝৘đ֒࠷թఖ +DPORT_APP_ CACHE_CTRL_REG ᇏ֥ DPORT_APP_SINGLE_IRAM_ENA ູ໊ 1 ൈđAPP_CPU ᄝՎᇕଆൔ +༯٠໙թԥఖbᄝᆃᇕଆൔ༯đMMU ֥ૄ۱஥ᇂཛ෮ᆦӻ֥ࣉӱ‫ֹྴބ‬ᆶ်҂๝bऎุҕॉі 27-12 ‫ބ‬і +27-13bೂᆃུі۬෮ൕđᄝՎห൹ଆൔ༯đ҂ି൐Ⴈ V Addr2 ‫ ބ‬V Addr3 ٠໙ோຓ೺թb + + і 27­12. PRO_CPU ֥ MMU ஥ᇂཛ‫ݼ‬čห൹ଆൔĎ + +ֹᆶ ඔਈ PID ؓႋֻ֥၂۱ MMU ஥ᇂཛ + +V Addr0 0/1 2 3 4 5 6 7 +V Addr1 +V Addr2 64 0 - - - - - - +V Addr3 +V Addr4 64 64 256 384 512 640 768 896 + + 64 - - - - - - - + + 64 - - - - - - - + + 16 - 1056 1072 1088 1104 1120 1136 + +ুᶈྐ༏॓࠯ 558 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + + і 27­13. APP_CPU ֥ MMU ஥ᇂཛ‫ݼ‬čห൹ଆൔĎ + +ֹᆶ ඔਈ PID ؓႋֻ֥၂۱ MMU ஥ᇂཛ + +V Addr0 64 0/1 2 3 4 5 6 7 +V Addr1 64 2048 - - +V Addr2 64 2112 2304 - - - - 2944 +V Addr3 64 - - - +V Addr4 16 - - 2432 2560 2688 2816 - + - 3104 3184 + - - - - + + - - - - + + 3120 3136 3152 3168 + +MMU ֥ૄ۱஥ᇂཛࡼ CPU ࣉӱ֥ྴֹᆶ်႘ഝ֞ൌֹᆶ်bૄ۱஥ᇂཛ໊ॺູ 32bఃᇏđ0 ֞ 7 ‫໊ݼ‬іൕႮ +ྴֹᆶ်႘ഝಀ֥ൌֹᆶ်bMMU ஥ᇂཛႵིൈсྶౢԢ 8 ‫໊ݼ‬b8 ‫໊ݼ‬ᇂ 1 ֥஥ᇂཛ҂߶ࡼ಩‫ޅ‬ൌֹᆶ႘ +ഝ֞ྴֹᆶb10 ‫ ໊֞ݼ‬32 ‫໊ݼ‬҂൐ႨđႋཿູਬbႮႿ MMU ཛᇏႵ 8 ۱ֹᆶ໊đோຓ೺թ်֥նཬູ 64 +KBđၹՎᆦӻ֥ቋնோຓ೺թ 256 * 64 KB = 16 MBb + +ൕ২ + +ൕ২ 1ğPID ູ 1 ֥ PRO_CPU ࣉӱླေ๙‫ֹྴݖ‬ᆶ 0x3F70_2375 ‫؀‬౼ோຓ೺թֹᆶ 0x07_2375bMMU ҂ԩ +Ⴟห൹ଆൔb + + • ۴ऌі 27-9đྴֹᆶ 0x3F70_2375 ໊Ⴟ V Addr0 ֥ 0x30 ‫ݼ‬်b + • ۴ऌі 27-10đPID ູ 0/1 ൈđؓႿ PRO_CPUđV Addr0 ֥ MMU ஥ᇂཛՖ 0 ष൓b + • Ф۷‫ ֥ڿ‬MMU ஥ᇂཛູ 0 + 0x30 = 0x30b + • ֹᆶ 0x07_2375 ໊Ⴟ 7 ‫ ݼ‬64 KB ်ഈb + • MMU ஥ᇂཛ 0x30 ླေഡᇂູ 7đѩ๙‫ ࡼݖ‬8 ‫໊ݼ‬ᇂູ 0 টѓ࠺ູႵིđၹՎđࡼ 0x007 ཿೆ MMU ஥ + + ᇂཛ 0x30b + +ൕ২ 2ğPID ູ 4 ֥ APP_CPU ࣉӱླေ๙‫ֹྴݖ‬ᆶ 0x4044_048C ‫؀‬౼ோຓ೺թֹᆶ 0x44_048CbMMU ҂ԩ +Ⴟห൹ଆൔb + + • ۴ऌі 27-9đྴֹᆶ 0x4044_048C ໊Ⴟ V Addr2 ֥ 0x4 ‫ݼ‬်b + • ۴ऌі 27-11đPID ູ 4 ൈđؓႿ APP_CPUđV Addr2 ֥ MMU ஥ᇂཛՖ 2560 ष൓b + • Ф۷‫ ֥ڿ‬MMU ஥ᇂཛ൞ 2560 + 0x4 = 2564b + • ֹᆶ 0x44_048C ໊Ⴟ 0x44 ‫ ݼ‬64 KB ်ഈb + • MMU ஥ᇂཛ 2564 ླေഡᇂູ 0x44 ѩ౏๙‫ ࡼݖ‬8 ‫໊ݼ‬ᇂູ 0 টѓ࠺ູႵིđၹՎđࡼ 0x044 ཿೆ MMU + + ஥ᇂཛ 2564b + +ோຓ RAM + +ᄝ PRO_CPU ‫ ބ‬APP_CPU ഈᄎྛ֥ࣉӱॖၛ๙‫ߏݖ‬թ‫؀‬ཿோຓ SRAMđ‫؀‬ཿֹᆶູྴֹᆶٓຶ V AddrRAM đ +ࠧ 0x3F80_0000 ~ 0x3FBF_FFFFbა೺թ MMU ၂ဢđֹᆶॢࡗ‫ބ‬໾৘թԥఖФ‫ٳ‬Ӯ်bؓႿோຓ RAM MMUđ +်նཬູ 32 KBđѩ౏ MMU ି‫ ࡼܔ‬256 ۱ൌֹᆶ်႘ഝ֞ྴֹᆶॢࡗđᄍྸ႘ഝ 32 KB * 256 = 8 MB ֥ோຓ +RAM ൌֹᆶb + +‫ֹھ‬ᆶٓຶ֥ྴֹᆶ်႘ഝ౼थႿ MMU ෮ԩ֥ଆൔğ֮-ۚଆൔđ୽-అଆൔࠇᆞӈଆൔbᄝ෮Ⴕ౦ঃ༯đ࠷թ +ఖ DPORT_PRO_CACHE_CTRL_REG ᇏ֥ DPORT_PRO_DRAM_HL ໊‫ ބ‬DPORT_PRO_DRAM_SPLIT ໊đ + +ুᶈྐ༏॓࠯ 559 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + +DPORT _APP_CACHE_CTRL_REG ᇏ֥ DPORT_APP_DRAM_HL ໊‫ ބ‬DPORT_APP_DRAM_SPLIT ໊‫܋‬๝थ‫ק‬ +ோຓ +SRAM ֥ྴֹᆶଆൔđऎุҕॉі 27-14bೂ‫ླݔ‬ေ PRO_CPU ‫ ބ‬APP_CPU ֥႘ഝ҂๝đᄵႋ࿊ᄴᆞӈଆൔđ +ၹູ෱൞ື၂ॖၛղ֞Վေ౰֥ଆൔbೂ‫ݔ‬ᄍྸ PRO_CPU ‫ ބ‬APP_CPU ‫܋‬ཚཌྷ๝֥႘ഝđ൐Ⴈۚ-֮ࠇ୽-అ +ଆൔॖၛᄝਆ۱ CPU ௔َ٠໙թԥఖൈิۚ෎؇b + +APP_CPU Cache ܱоൈđ0x4007_8000 ֞ 0x4007_FFFF ֥౵თႨቔᆞӈ֥ோഈ RAMđ۲ᇕ Cache ଆൔ֥ॖ +ႨྟႵ෮э߄bᆞӈଆൔ༯đॖၛᄝ PRO_CPU ٠໙ோຓ RAM ֥๝ൈЌӻ Cache ᆞӈᄎྛđ֌ APP_CPU ໭ +‫م‬٠໙ோຓ RAMbۚ-֮ଆൔ༯đਆ۱ CPU ‫׻‬ॖၛ൐Ⴈோຓ RAMđ֌ᆺି൐Ⴈ 0x3F80_0000 ֞ 0x3F9F_FFFF +֥ 2 MB թԥఖྴֹᆶb҂ࡹၰᄝ APP_CPU Cache ౵თܱо֥౦ঃ༯൐Ⴈఅ-୽ଆൔb + + і 27­14. ோຓ SRAM ֥ྴ୅ֹᆶଆൔ + +ଆൔ DPORT_PRO_DRAM_HL DPORT_PRO_DRAM_SPLIT + DPORT_APP_DRAM_HL DPORT_APP_DRAM_SPLIT +֮-ۚ 1 0 +୽-అ 0 1 +ᆞӈ 0 0 + +ᄝᆞӈଆൔ༯đਆ۱ CPU ֥ྴֹᆶ်֞ൌֹᆶ်֥႘ഝॖၛ൞҂๝֥b๙‫ ݖ‬LV AddrRAM ֥ MMU ஥ᇂཛഡ +ᇂ PRO_CPU ်֥႘ഝĠ๙‫ ݖ‬RV AddrRAM ֥ MMU ஥ᇂཛഡᇂ APP_CPU ်֥႘ഝbᄝᆃ၂ଆൔ༯đ +LV Addr and RV Addr ֥ 128 ်‫׻‬Ф൐ႨđՖ‫ܔିط‬႘ഝቋնູ 8 MB ֥ଽթbఃᇏ 4 MB ႘ഝ֞ PRO_CPU + +ֹᆶđ4 MB ႘ഝ֞ APP_CPU ֹᆶđೂі 27-15 ෮ൕb + + і 27­15. ோຓ SRAM ֥ྴֹᆶčᆞӈଆൔĎ + +ྴ୅ֹᆶ նཬ ֮ PRO_CPU ֹᆶ +LV AddrRAM 4 MB 0x3F80_0000 ۚ +ྴ୅ֹᆶ նཬ 0x3FBF_FFFF +RV AddrRAM 4 MB ֮ + 0x3F80_0000 APP_CPU ֹᆶ + ۚ + 0x3FBF_FFFF + +ᄝ֮-ۚଆൔ༯đPRO_CPU ၛࠣ APP_CPU ൐Ⴈཌྷ๝֥႘ഝ஥ᇂཛbᄝᆃᇕଆൔ༯đLV AddrRAM ႨႿྴֹᆶ +ॢࡗ֥֮ 2 MBđ‫ ط‬RV AddrRAM ႨႿྴֹᆶॢࡗ֥ۚ 2 MBbᆃ္ၩ໅ሢ LV AddrRAM ֥ۚ 64 ۱ MMU ஥ᇂ +ཛၛࠣ RV AddrRAM ֥֮ 64 ۱஥ᇂཛໃ൐Ⴈbі 27-16 བྷ༥૭ඍਔᆃֹུᆶٓຶb + + і 27­16. ோຓ SRAM ֥ྴֹᆶč֮­ۚଆൔĎ + +ྴ୅ֹᆶ նཬ ֮ PRO_CPU/APP_CPU ֹᆶ + 0x3F80_0000 ۚ +LV AddrRAM 2 MB 0x3FA0_0000 0x3F9F_FFFF +RV AddrRAM 2 MB 0x3FBF_FFFF + +ᄝ୽-అթԥఖᇏđVRAM Фҷ‫ ູٳ‬32 ሳࢫ֥ॶb୽ඔॶ๙‫ ݖ‬MMU ஥ᇂཛ‫ٳ‬೛֞ LV AddrRAM đఅඔॶ๙‫ݖ‬ +MMU ஥ᇂཛ‫ٳ‬೛֞ RV AddrRAM b၂ϮটඪđLV AddrRAM ‫ ބ‬RV AddrRAM ֥ MMU ஥ᇂཛࡼФഡᇂູཌྷ๝ +֥ᆴđၹՎྴֹᆶ်ॖၛ႘ഝ֞໾৘թԥఖ֥၂۱৵࿃౵თbі 27-17 བྷ༥ඪૼਔᆃᇕଆൔb + +ুᶈྐ༏॓࠯ 560 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + + і 27­17. ோຓ SRAM ֥ྴֹᆶč୽­అଆൔĎ + +ྴ୅ֹᆶ նཬ ֮ PRO_CPU/APP_CPU ֹᆶ + 0x3F80_0000 ۚ +LV AddrRAM 32 ሳࢫ 0x3F80_0020 0x3F80_001F +RV AddrRAM 32 ሳࢫ 0x3F80_0040 0x3F80_003F +LV AddrRAM 32 ሳࢫ 0x3F80_0060 0x3F80_005F +RV AddrRAM 32 ሳࢫ 0x3F80_007F + ... +LV AddrRAM 32 ሳࢫ 0x3FBF_FFC0 0x3FBF_FFDF +RV AddrRAM 32 ሳࢫ 0x3FBF_FFE0 0x3FBF_FFFF + +ோຓ RAM MMU ஥ᇂཛ໊֥஥ᇂა೺թཌྷ๝ğ஥ᇂཛູ 32 ໊࠷թఖđ൐Ⴈ֮ 9 ໊b0 ‫ ໊֞ݼ‬7 ‫໊ݼ‬Ї‫ݣ‬஥ᇂ +ཛླေ႘ഝఃؓႋྴֹᆶ်֥ൌֹᆶ်bೂ‫ݔ‬஥ᇂཛႵིđᄵ 8 ‫໊ݼ‬ФౢԢĠೂ‫ݔ‬஥ᇂཛ໭ིđᄵ 8 ‫໊ݼ‬ᇂ 1b +і 27-18 བྷ༥ඪૼ LV AddrRAM ‫ ބ‬RV AddrRAM ؓႋ෮Ⴕ PID ֻ֥၂۱ MMU ஥ᇂཛ‫ݼ‬b + + і 27­18. ோຓ RAM ֥ MMU ஥ᇂཛ‫ݼ‬ + +ֹᆶ ်ඔਈ PID ؓႋֻ֥၂۱ MMU ஥ᇂཛ + +LV AddrRAM 128 0/1 2 3 4 5 6 7 +RV AddrRAM 128 1152 1280 1920 + 3200 3328 1408 1536 1664 1792 3968 + + 3456 3584 3712 3840 + +ൕ২ + +ൕ২ 1ğPRO_CPU ഈᄎྛ֥ PID ູ 7 ֥ࣉӱླေ๙‫ֹྴݖ‬ᆶ 0x3FA7_2375 ‫؀‬౼ࠇཿೆோຓ RAM ֹᆶ +0x7F_A375bMMU ԩႿ֮-ۚଆൔb + + • ۴ऌі 27-9đྴֹᆶ 0x3FA7_2375 ໊Ⴟ V AddrRAM ֥ 0x4E ‫ ݼ‬32 KB ်ഈb + • ۴ऌі 27-16đྴֹᆶ 0x3FA7_2375 Ⴎ RV AddrRAM ܵ৘b + • ۴ऌі 27-18 ؓႿ PRO_CPU ഈᄎྛ֥ PID ູ 7 ֥ࣉӱđRV AddrRAM ؓႋ֥ MMU ஥ᇂཛ൓Ⴟ 3968b + • Фྩ‫ ֥ڿ‬MMU ஥ᇂཛູ 3968 + 0x4E = 4046b + • ֹᆶ 0x7F_A375 ໊Ⴟ 255 ‫ ݼ‬32 KB ်ഈb + • MMU ஥ᇂཛ 4046 ླေФᇂູ 255đѩ๙‫ݖ‬ౢԢ 8 ‫໊ݼ‬টѓ࠺ູႵིđၹՎđࡼ 0x0FF ཿೆ MMU ஥ᇂ + + ཛ 4046b + +ൕ২ 2ğAPP_CPU ഈᄎྛ֥ PID ູ 5 ֥ࣉӱླေՖྴֹᆶ 0x3F85_5805 ष൓‫؀‬౼ࠇཿೆோຓ RAM ֹᆶٓຶ +0x55_5805 ֞ 0x55_5823bMMU ԩႿఅ-୽ଆൔb + + • ۴ऌі 27-9đྴֹᆶ 0x3F85_5805 ໊Ⴟ V AddrRAM ֥ 0x0A ‫ ݼ‬32 KB ်ഈb + • ۴ऌі 27-17đေ‫؀‬౼ࠇཿೆֹ֥ᆶٓຶЇ‫ݣ‬ਔ RV AddrRAM ‫ ބ‬LV AddrRAM ᇏ֥۲ 32 ሳࢫ֥౵თb + • ۴ऌі 27-18đؓႿ PID 5đLV AddrRAM ֥ MMU ஥ᇂཛ൓Ⴟ 1664b + • ۴ऌі 27-18đؓႿ PID 5đRV AddrRAM ֥ MMU ஥ᇂཛ൓Ⴟ 3712b + • Фྩ‫ ֥ڿ‬MMU ஥ᇂཛູ 1664 + 0x0A = 1674 ‫ ބ‬3712 + 0x0A = 3722b + • ֹᆶٓຶ 0x55_5805 ֞ 0x55_5823 ໊Ⴟ 0xAA ‫ ݼ‬32 KB ်ഈb + +ুᶈྐ༏॓࠯ 561 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + + • MMU ஥ᇂཛ 1674 ‫ ބ‬3722 ླေФഡᇂູ 0xAAđѩ౏๙‫ ࡼݖ‬8 ‫໊ݼ‬ᇂູ 0 টѓ࠺ູႵིđၹՎđࡼ + 0x0AA ཿೆ MMU ஥ᇂཛ 1674 ‫ ބ‬3722b‫ھ‬႘ഝൡႨႿ PRO_CPU ၛࠣ APP_CPUb + +ൕ২ 3ğPRO_CPU ഈᄎྛ֥ PID ູ 1 ֥ࣉӱ‫ ބ‬APP_CPU ഈᄎྛ֥ PID ູ 1 ֥ࣉӱླေ൐Ⴈྴֹᆶ +0x3F80_0876 ‫؀‬౼ࠇཿೆோຓ RAMbPRO_CPU ླေ‫ֹྴھ‬ᆶট٠໙ൌֹᆶ 0x10_0876đ‫ ط‬APP_CPU ླေ๙ +‫ֹྴھݖ‬ᆶ٠໙ൌֹᆶ 0x20_0876bMMU ԩႿᆞӈଆൔb + + • ۴ऌі 27-9đྴ୅ֹᆶ 0x3F80_0876 ໊Ⴟ V AddrRAM ֥ 0 ‫ ݼ‬32 KB ်ഈb + • ۴ऌі 27-18, ؓႿ PRO_CPU ഈᄎྛ֥ PID ູ 1 ֥ࣉӱđMMU ஥ᇂཛ൓Ⴟ 1152b + • ۴ऌі 27-18, ؓႿ APP_CPU ഈᄎྛ֥ PID ູ 1 ֥ࣉӱđMMU ஥ᇂཛ൓Ⴟ 3200b + • ؓႿ PRO_CPUđФྩ‫ ֥ڿ‬MMU ஥ᇂཛູ 1152 + 0 = 1152đؓႿ APP_CPUđФྩ‫ ֥ڿ‬MMU ஥ᇂཛູ + + 3200 + 0 = 3200b + • ֹᆶ 0x10_0876 ໊Ⴟ 0x20 ‫ ݼ‬32 KB ်ഈb + • ֹᆶ 0x20_0876 ໊Ⴟ 0x40 ‫ ݼ‬32 KB ်ഈb + • ؓႿ PRO_CPU, MMU ஥ᇂཛ 1152 ླေФᇂູ 0x20 ѩ౏๙‫ݖ‬ౢԢ 8 ‫໊ݼ‬টѓ࠺Ⴕིđ෮ၛࡼ 0x020 ཿ + + ೆ MMU ஥ᇂཛ 1152b + • ؓႿ APP_CPUđMMU ஥ᇂཛ 3200 ླေФᇂູ 0x40 ѩ౏๙‫ݖ‬ౢԢ 8 ‫໊ݼ‬টѓ࠺Ⴕིđ෮ၛࡼ 0x040 ཿ + + ೆ MMU ஥ᇂཛ 3200b + • ᆃဢ PRO_CPU ‫ ބ‬APP_CPU ࣼॖၛ๙‫ݖ‬ཌྷ๝֥ྴֹᆶ٠໙҂๝֥໾৘ଽթ౵თb + +27.3.2.3 ຓഡ + +ຓഡ MPU ܵ৘ 39 ۱ຓഡଆॶb۴ऌૄ۱ຓഡଆॶđॖၛ๙‫ݖ‬஥ᇂ MMUđᄍྸᆺႵห‫ ק‬PID ֥ࣉӱ٠໙ຓഡb +஥ᇂ MMU ֥࠷թఖབྷ༥ྐ༏౨ҕॉі 27-19b + + і 27­19. ܵ৘ຓഡ֥ MPU + +ຓഡ PID = 0/1 ಃཋ + ٠໙ PID = 2 ~ 7 +DPort Register ٠໙ ࣌ᆸ +AES Accelerator ٠໙ ࣌ᆸ +RSA Accelerator ٠໙ ࣌ᆸ +SHA Accelerator ٠໙ ࣌ᆸ +Secure Boot ٠໙ ࣌ᆸ +Cache MMU Table ٠໙ ࣌ᆸ +PID Controller ٠໙ ࣌ᆸ +UART0 ٠໙ DPORT_AHBLITE_MPU_TABLE_UART_REG +SPI1 ٠໙ DPORT_AHBLITE_MPU_TABLE_SPI1_REG +SPI0 ٠໙ DPORT_AHBLITE_MPU_TABLE_SPI0_REG +GPIO ٠໙ DPORT_AHBLITE_MPU_TABLE_GPIO_REG +RTC ٠໙ DPORT_AHBLITE_MPU_TABLE_RTC_REG +IO MUX ٠໙ DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG +SDIO Slave ٠໙ DPORT_AHBLITE_MPU_TABLE_HINF_REG +UDMA1 ٠໙ DPORT_AHBLITE_MPU_TABLE_UHCI1_REG +I2S0 ٠໙ DPORT_AHBLITE_MPU_TABLE_I2S0_REG +UART1 DPORT_AHBLITE_MPU_TABLE_UART1_REG + +ুᶈྐ༏॓࠯ 562 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 27 թԥఖܵ৘‫ބ‬Ќ޹ֆჭ (MMU, MPU) + +ຓഡ PID = 0/1 ಃཋ + ٠໙ PID = 2 ~ 7 +I2C0 ٠໙ DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG +UDMA0 ٠໙ DPORT_AHBLITE_MPU_TABLE_UHCI0_REG +SDIO Slave ٠໙ DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG +RMT ٠໙ DPORT_AHBLITE_MPU_TABLE_RMT_REG +PCNT ٠໙ DPORT_AHBLITE_MPU_TABLE_PCNT_REG +SDIO Slave ٠໙ DPORT_AHBLITE_MPU_TABLE_SLC_REG +LED PWM ٠໙ DPORT_AHBLITE_MPU_TABLE_LEDC_REG +Efuse Controller ٠໙ DPORT_AHBLITE_MPU_TABLE_EFUSE_REG +Flash Encryption ٠໙ DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG +PWM0 ٠໙ DPORT_AHBLITE_MPU_TABLE_PWM0_REG +TIMG0 ٠໙ DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG +TIMG1 ٠໙ DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG +SPI2 ٠໙ DPORT_AHBLITE_MPU_TABLE_SPI2_REG +SPI3 ٠໙ DPORT_AHBLITE_MPU_TABLE_SPI3_REG +SYSCON ٠໙ DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG +I2C1 ٠໙ DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG +SDMMC ٠໙ DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG +EMAC ٠໙ DPORT_AHBLITE_MPU_TABLE_EMAC_REG +PWM1 ٠໙ DPORT_AHBLITE_MPU_TABLE_PWM1_REG +I2S1 ٠໙ DPORT_AHBLITE_MPU_TABLE_I2S1_REG +UART2 ٠໙ DPORT_AHBLITE_MPU_TABLE_UART2_REG +RNG DPORT_AHBLITE_MPU_TABLE_PWR_REG + +࠷թఖ DPORT_AHBLITE_MPU_TABLE_X_REG ֥ૄ۱໊थ‫ૄק‬۱ࣉӱ൞‫ڎ‬ॖၛ٠໙࠷թఖܵ৘֥ຓഡbབྷ༥ +ྐ༏౨ҕॉі 27-20b֒࠷թఖ DPORT_AHBLITE_MPU_TABLE_X_REG ֥ଖ۱໊ᇂ 1 ൈđᆃၩ໅ሢऎႵཌྷႋ +PID ֥ࣉӱॖၛ٠໙Վ࠷թఖ֥ཌྷႋຓഡb‫ڎ‬ᄵđࣉӱ໭‫م‬٠໙ཌྷႋ֥ຓഡb + + і 27­20. DPORT_AHBLITE_MPU_TABLE_X_REG + +PID 234567 +DPORT_AHBLITE_MPU_TABLE_X_REG ໊ 012345 + +෮Ⴕ֥ DPORT_AHBLITE_MPU_TABLE_X_REG ࠷թఖ໊Ⴟຓഡ DPort ࠷թఖᇏbᆺႵ PID ູ 0/1 ֥ࣉӱॖၛ +۷‫ڿ‬ᆃུ࠷թఖb + +ুᶈྐ༏॓࠯ 563 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 28 PID ॥ᇅఖ (PID) + +28 PID ॥ᇅఖ (PID) + +28.1 ‫ۀ‬ඍ + +ESP32 ච‫ނ‬ྉோॖၛ๝ൈԩ৘‫؟‬۱ཌӱbPID ॥ᇅఖᄝࣉӱ్ߐ֥‫ݖ‬ӱᇏđ‫ڣ‬ᇹປӮࣉӱ‫ ݼ‬PID ్֥ߐbՎຓđ +PID ॥ᇅఖߎॖၛ๙‫࠺ݖ‬੣ CPU ԩ৘ᇏ؎֥ሑ෿টܵ৘ళสᇏ؎bၹՎđPID ॥ᇅఖॖၛ൐֤Ⴈ޼ᄝႋႨᇏ۷ +Ⴕֹིܵ৘ࣉӱ్ߐ‫ބ‬ళสᇏ؎b + +28.2 ᇶေหྟ + +PID ॥ᇅఖႵၛ༯หྟğ + • ܵ৘ࣉӱႪ༵ࠩ + • ్ߐࣉӱ‫ ݼ‬PID + • ࠺੣ᇏ؎ྐ༏ + • ܵ৘ᇏ؎ళส + +28.3 ‫ିۿ‬૭ඍ + +CPU ऎႵ 8 ۱ࣉӱđࣉӱ‫ ݼ‬PID ‫ٳ‬љູ 0 ~ 7bᆃ 8 ۱ࣉӱᇏđPID ູ 0/1 ֥ࣉӱб PID ູ 2 ~ 7 ֥ࣉӱႚႵ۷ +‫֥؟‬ಃཋb +CPU ᄝਆᇕ౦ྙ༯߶ࣉྛࣉӱ్ߐb + + • ֒ᇏ؎‫ؿ‬ളđCPU Ֆᇏ؎ཟਈೆ१ֹᆶ౼ᆷ֥ൈީb໭ંᇏ؎‫ؿ‬ളᆭభᆞᄝᄎྛ֥൞ଧ۱ࣉӱđ༢๤Վ + ൈ‫ࡼ׻‬ᇏ؎౼ᆷ൪ູ PID ູ 0 ֥ࣉӱb + + • ֒భࣉӱᇶ‫ࣉߐ్׮‬ӱൈbି‫ܔ‬ᇶ‫ࣉྛࣉ׮‬ӱ్ߐ֥ࣉӱ၂‫ק‬൞ PID ູ 0/1 ֥ۚಃཋࣉӱb + +28.3.1 ᇏ؎്љ + +CPU ၂‫܋‬Ⴕ Level 1aLevel 2aLevel 3aLevel 4aLevel 5aLevel 6čDebugĎaNMI ௾۱Ⴊ༵֥ࠩᇏ؎bૄ၂ࠩ +ᇏ؎Ⴕ၂۱ᇏ؎ཟਈೆ१ֹᆶbPID ॥ᇅఖ്љ֞ CPU Ֆᇏ؎ཟਈೆ१ֹᆶ౼ᆷ֥ൈީሱ‫ ߐ్׮‬PID ᇀ 0bೂ +‫ ݔ‬CPU ᆺ൞ؓᇏ؎ཟਈೆ१ֹᆶቓඔऌ٠໙đପહ PID ॥ᇅఖ҂Ґ౼಩‫׮ޅ‬ቔb +PID ॥ᇅఖି‫്ܔ‬љ֥ᇏ؎Ⴊ༵ࠩ౼थႿ࠷թఖ PIDCTRL_INTERRUPT_ENABLE_REGb࠷թఖ +PIDCTRL_INTERRUPT_ENABLE_REG ᇏ֥ଖູ໊ 1 ൈđ֒ CPU ՖՎ໊ؓႋ֥ᇏ؎ཟਈೆ१ֹᆶ౼ᆷൈđPID +॥ᇅఖࡼ్ߐࣉӱĠ೏࠷թఖ PIDCTRL_INTERRUPT_ENABLE_REG ᇏ֥ଖູ໊ 0 ൈđᄵ PID ॥ᇅఖ҂Ґ౼಩ +‫׮ޅ‬ቔbᆃ௾ࠩᇏ؎۲ሱ֥ᇏ؎ཟਈೆ१ֹᆶႮ࠷թఖ PIDCTRL_INTERRUPT_ADDR_1_REG ~ +PIDCTRL_INTERRUPT_ADDR_7_REG थ‫ק‬đབྷ࡮і 28-1b + +ুᶈྐ༏॓࠯ 564 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 28 PID ॥ᇅఖ (PID) + + і 28­1. ᇏ؎ཟਈೆ१ֹᆶ + + ᇏ؎Ⴊ༵ࠩ ᇏ؎്љ൐ି໊ ᇏ؎ཟਈೆ१ֹᆶ + PIDCTRL_INTERRUPT_ENABLE_REG ໊ + Level 1 PIDCTRL_INTERRUPT_ADDR_1_REG + Level 2 1 PIDCTRL_INTERRUPT_ADDR_2_REG + Level 3 2 PIDCTRL_INTERRUPT_ADDR_3_REG + Level 4 3 PIDCTRL_INTERRUPT_ADDR_4_REG + Level 5 4 PIDCTRL_INTERRUPT_ADDR_5_REG +Level 6 ( Debug ) 5 PIDCTRL_INTERRUPT_ADDR_6_REG + 6 PIDCTRL_INTERRUPT_ADDR_7_REG + NMI 7 + +28.3.2 ྐ༏࠺੣ + +֒ PID ॥ᇅఖ്љ֞ᇏ؎ൈđԢਔሱ‫ ߐ్׮‬PID ູ 0đߎ߶࠺੣ 3 ่ྐ༏ğ + 1. ֒భᇏ؎֥Ⴊ༵ࠩ + 2. ༢๤֥ഈ၂Ցᇏ؎ሑ෿ + 3. CPU ᄎྛ֥ഈ၂۱ࣉӱ + +PID ॥ᇅఖ߶ࡼ֒భ‫ؿ‬ള֥ᇏ؎֥Ⴊ༵ࠩ࠺੣֞࠷թఖ PIDCTRL_LEVEL_REGđབྷ࡮і 28-2b + + і 28­2. PIDCTRL_LEVEL_REG + +࠷թఖᆴ ༢๤֒భᇏ؎ሑ෿ +0 ҂ԩႿᇏ؎ᇏ +1 ԩႿ Level 1 ᇏ؎ +2 ԩႿ Level 2 ᇏ؎ +3 ԩႿ Level 3 ᇏ؎ +4 ԩႿ Level 4 ᇏ؎ +5 ԩႿ Level 5 ᇏ؎ +6 ԩႿ Level 6 ᇏ؎ +7 ԩႿ NMI ᇏ؎ + +PID ॥ᇅఖߎࡼ֒భᇏ؎‫ؿ‬ളᆭభ֥ሑ෿࠺੣ࣉ࠷թఖ PIDCTRL_FROM_n_REGb࠷թఖ +PIDCTRL_FROM_n_REG ໊֥ॺູ 7bఃۚ 4 ໊іൕՎ࠷թఖؓႋᇏ؎‫ؿ‬ളᆭభ༢๤֥ᇏ؎ሑ෿b֮ 3 ໊іൕ +Վ࠷թఖؓႋᇏ؎‫ؿ‬ളᆭభ༢๤ԩႿଧ۱ࣉӱbབྷ࡮і 28-3b + +ুᶈྐ༏॓࠯ 565 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 28 PID ॥ᇅఖ (PID) + + і 28­3. PIDCTRL_FROM_n_REG + +[6:3] ֒భᇏ؎‫ؿ‬ളభ༢๤֥ᇏ؎ሑ෿ [2:0] ֒భᇏ؎‫ؿ‬ളభ༢๤ᄎྛ֥ࣉӱ +0 ҂ԩႿᇏ؎ 0 PID ູ 0 ֥ࣉӱ +1 ԩႿ Level 1 ᇏ؎ 1 PID ູ 1 ֥ࣉӱ +2 ԩႿ Level 2 ᇏ؎ 2 PID ູ 2 ֥ࣉӱ +3 ԩႿ Level 3 ᇏ؎ 3 PID ູ 3 ֥ࣉӱ +4 ԩႿ Level 4 ᇏ؎ 4 PID ູ 4 ֥ࣉӱ +5 ԩႿ Level 5 ᇏ؎ 5 PID ູ 5 ֥ࣉӱ +6 ԩႿ Level 6 ᇏ؎ 6 PID ູ 6 ֥ࣉӱ +7 ԩႿ Level 7 ᇏ؎ 7 PID ູ 7 ֥ࣉӱ + +PID ॥ᇅఖႚႵ࠷թఖ PIDCTRL_FROM_1_REG ~ PIDCTRL_FROM_7_REGđ෱ૌ‫ٳ‬љؓႋ Level 1aLevel 2a +Level 3aLevel 4aLevel 5aLevel 6čDebugĎaNMI ௾ࠩᇏ؎b༢๤๙‫ݖ‬ᆃུ࠷թఖԩ৘ᇏ؎ళสđೂ๭ 28-1 +෮ൕb + +ুᶈྐ༏॓࠯ 566 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 28 PID ॥ᇅఖ (PID) + + ๭ 28­1. ᇏ؎ళส + +ೂ‫ݔ‬ᇏ؎‫ؿ‬ളđ֌൞ႮႿ࠷թఖ PIDCTRL_INTERRUPT_ENABLE_REG ֥஥ᇂđ‫ط‬൐֤ PID ॥ᇅఖીႵ്љ֞ +෱đପહ PID ॥ᇅఖ҂߶ቓ಩‫࠺ޅ‬੣đ္҂߶۷‫࠷ڿ‬թఖ PIDCTRL_LEVEL_REGaPIDCTRL_FROM_n_REG ֥ +ᆴb + +28.3.3 ࣉӱᇶ‫ࣉߐ్׮‬ӱ + +ᆺႵ PID ູ 0/1 ֥ࣉӱॖၛᇶ‫ࣉߐ్׮‬ӱb్ߐᆭު֥ࣉӱॖၛ൞ PID ູ 0 ~ 7 ᇏ֥಩‫ޅ‬၂۱bࣉӱᇶ‫ߐ్׮‬ +ࣉӱ֥ܱ࡯ᄝႿđՖ֒భࣉӱ֥ቋު၂่ᆷ਷๋ሇ֞ྍࣉӱֻ֥၂่ᆷ਷֥ൈީđPID ေ‫ݺې‬Ֆ 0/1 эູྍࣉ +ӱ֥ PIDb + +ࣉӱᇶ‫ࣉߐ్׮‬ӱ֥ೈࡱੀӱູ + +ুᶈྐ༏॓࠯ 567 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 28 PID ॥ᇅఖ (PID) + + 1. ೈࡱ௠зԢ NMI ᇏ؎ᆭຓ֥෮Ⴕᇏ؎ + 2. ࡼ࠷թఖ PIDCTRL_NMI_MASK_ENABLE_REG ᇂ 1đളӮ CPU NMI ᇏ؎௠зྐ‫ݼ‬ + 3. ஥ᇂ࠷թఖ PIDCTRL_PID_DELAY_REGaPIDCTRL_NMI_DELAY_REG + 4. ஥ᇂ࠷թఖ PIDCTRL_PID_NEW_REG + 5. ஥ᇂ࠷թఖ PIDCTRL_LEVEL_REGaPIDCTRL_FROM_n_REG + 6. ࡼ࠷թఖ PIDCTRL_PID_CONFIRM_REGaPIDCTRL_NMI_MASK_DISABLE_REG ᇂ 1 + 7. Ӝཧؓ NMI ᇏ؎ᆭຓ֥ᇏ؎֥௠з + 8. ్ߐ֞ྍࣉӱ౼ᆷ +ෙಖ༢๤ॖၛԩ৘ᇏ؎ళส֥౦ঃđ֌ PID ູ 0/1 ֥ࣉӱ҂ႋᄝࣉӱ్ߐൈФྍ֥ᇏ؎յ؎đၹՎᄝ҄ᇧ 1a +҄ᇧ 2 ᇏ௠зਔ෮Ⴕᇏ؎b +҄ᇧ 3 ᇏ஥ᇂ֥࠷թఖ PIDCTRL_PID_DELAY_REGaPIDCTRL_NMI_DELAY_REG ֥ᆴࡼ߶ቔႨႿ҄ᇧ +6b +҄ᇧ 4 ᇏ஥ᇂ֥࠷թఖ PIDCTRL_PID_NEW_REG ֥ᆴࡼ߶ᄝ҄ᇧ 6 ᆭުӮູྍ֥ࣉӱ PIDb +ೂ‫֒ݔ‬భԩႿళสᇏ؎ᇏ౏ေ߫‫֞گ‬ഈ၂۱ᇏ؎đପહᄝ҄ᇧ 5 ᇏླေ۴ऌ࠷թఖ n ᇏ࠺੣֥ྐ༏߫‫࠷گ‬թఖ +PIDCTRL_LEVEL_REGb +҄ᇧ 6 ᇏđࡼ࠷թఖ PIDCTRL_PID_CONFIRM_REGaPIDCTRL_NMI_MASK_DISABLE_REG ᇂ 1 ުđPID ॥ᇅ +ఖѩ҂߶৫ࠧࡼ PID ్ߐູ PIDCTRL_PID_NEW_REG ᇏ֥ᆴđ္҂߶৫ܱࠧо CPU NMI ᇏ؎௠зྐ‫ݼ‬đ‫ط‬൞ +߶‫ٳ‬љ֩ր၂‫ק‬ඔਈ֥ൈᇒᇛ௹ඔުҌ߶ᆳྛᆃਆ۱಩ༀbᆃਆ‫֩؍‬րൈᇒᇛ௹ඔࠧ࠷թఖ +PIDCTRL_PID_DELAY_REGaPIDCTRL_NMI_DELAY_REG ᇏ֥ᆴb +ᄝ҄ᇧ 7 ᇏߎॖၛᆳྛః෰಩ༀđᆺླေᄝ҄ᇧ 3 ᇏ஥ᇂ࠷թఖ PIDCTRL_PID_DELAY_REGa +PIDCTRL_NMI_DELAY_REG ൈЇ‫ݣ‬ᆃུ಩ༀ֥ൈࡗषཧࠧॖb + +28.4 ࠷թఖਙі + +ুᶈྐ༏॓࠯ 568 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 28 PID ॥ᇅఖ (PID) + +଀ӫ ૭ඍ ֹᆶ ٠໙ +PIDCTRL_INTERRUPT_ENABLE_REG PID ᇏ؎്љ൐ି໊ 0x3FF1F000 ‫؀‬Ĕཿ +PIDCTRL_INTERRUPT_ADDR_1_REG Level 1 ᇏ؎ཟਈೆ१ֹᆶ 0x3FF1F004 ‫؀‬Ĕཿ +PIDCTRL_INTERRUPT_ADDR_2_REG Level 2 ᇏ؎ཟਈೆ१ֹᆶ 0x3FF1F008 ‫؀‬Ĕཿ +PIDCTRL_INTERRUPT_ADDR_3_REG Level 3 ᇏ؎ཟਈೆ१ֹᆶ 0x3FF1F00C ‫؀‬Ĕཿ +PIDCTRL_INTERRUPT_ADDR_4_REG Level 4 ᇏ؎ཟਈೆ१ֹᆶ 0x3FF1F010 ‫؀‬Ĕཿ +PIDCTRL_INTERRUPT_ADDR_5_REG Level 5 ᇏ؎ཟਈೆ१ֹᆶ 0x3FF1F014 ‫؀‬Ĕཿ +PIDCTRL_INTERRUPT_ADDR_6_REG Level 6 ᇏ؎ཟਈೆ१ֹᆶ 0x3FF1F018 ‫؀‬Ĕཿ +PIDCTRL_INTERRUPT_ADDR_7_REG NMI ᇏ؎ཟਈೆ१ֹᆶ 0x3FF1F01C ‫؀‬Ĕཿ +PIDCTRL_PID_DELAY_REG ྍ֥ PID ളིభ֥࿼Ӿ 0x3FF1F020 ‫؀‬Ĕཿ +PIDCTRL_NMI_DELAY_REG ܱо NMI ௠зྐ‫ݼ‬భ֥࿼Ӿ 0x3FF1F024 ‫؀‬Ĕཿ +PIDCTRL_LEVEL_REG ֒భᇏ؎Ⴊ༵ࠩ 0x3FF1F028 ‫؀‬Ĕཿ +PIDCTRL_FROM_1_REG Level 1 ᇏ؎‫ؿ‬ളభ֥༢๤ሑ෿ 0x3FF1F02C ‫؀‬Ĕཿ +PIDCTRL_FROM_2_REG Level 2 ᇏ؎‫ؿ‬ളభ֥༢๤ሑ෿ 0x3FF1F030 ‫؀‬Ĕཿ +PIDCTRL_FROM_3_REG Level 3 ᇏ؎‫ؿ‬ളభ֥༢๤ሑ෿ 0x3FF1F034 ‫؀‬Ĕཿ +PIDCTRL_FROM_4_REG Level 4 ᇏ؎‫ؿ‬ളభ֥༢๤ሑ෿ 0x3FF1F038 ‫؀‬Ĕཿ +PIDCTRL_FROM_5_REG Level 5 ᇏ؎‫ؿ‬ളభ֥༢๤ሑ෿ 0x3FF1F03C ‫؀‬Ĕཿ +PIDCTRL_FROM_6_REG Level 6 ᇏ؎‫ؿ‬ളభ֥༢๤ሑ෿ 0x3FF1F040 ‫؀‬Ĕཿ +PIDCTRL_FROM_7_REG NMI ᇏ؎‫ؿ‬ളభ֥༢๤ሑ෿ 0x3FF1F044 ‫؀‬Ĕཿ +PIDCTRL_PID_NEW_REG ஥ᇂྍ֥ PID 0x3FF1F048 ‫؀‬Ĕཿ +PIDCTRL_PID_CONFIRM_REG ಒಪྍ֥ PID 0x3FF1F04C ᆺཿ +PIDCTRL_NMI_MASK_ENABLE_REG NMI ᇏ؎௠з൐ି࠷թఖ 0x3FF1F054 ᆺཿ +PIDCTRL_NMI_MASK_DISABLE_REG NMI ᇏ؎௠зܱо࠷թఖ 0x3FF1F058 ᆺཿ + +ুᶈྐ༏॓࠯ 569 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 28 PID ॥ᇅఖ (PID) + +28.5 ࠷թఖ + + Register 28.1. PIDCTRL_INTERRUPT_ENABLE_REG (0x000) + + (reserved) PIDCTRL_INTERRUPT(_reEsNeArvBeLdE) + +31 87 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PIDCTRL_INTERRUPT_ENABLE ‫໊ھ‬ႨႿ൐ିᇏ؎്֥љ‫ބ‬ԩ৘bč‫؀‬ĔཿĎ + + Register 28.2. PIDCTRL_INTERRUPT_ADDR_1_REG (0x004) 0 + +31 Reset + + 0x040000340 + + PIDCTRL_INTERRUPT_ADDR_1_REG Level 1 ᇏ؎ཟਈೆ१ֹᆶbč‫؀‬ĔཿĎ + + Register 28.3. PIDCTRL_INTERRUPT_ADDR_2_REG (0x008) 0 + +31 Reset + + 0x040000180 + + PIDCTRL_INTERRUPT_ADDR_2_REG Level 2 ᇏ؎ཟਈೆ१ֹᆶbč‫؀‬ĔཿĎ + + Register 28.4. PIDCTRL_INTERRUPT_ADDR_3_REG (0x00C) 0 + +31 Reset + + 0x0400001C0 + + PIDCTRL_INTERRUPT_ADDR_3_REG Level 3 ᇏ؎ཟਈೆ१ֹᆶbč‫؀‬ĔཿĎ + + Register 28.5. PIDCTRL_INTERRUPT_ADDR_4_REG (0x010) 0 + +31 Reset + + 0x040000200 + + PIDCTRL_INTERRUPT_ADDR_4_REG Level 4 ᇏ؎ཟਈೆ१ֹᆶbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 570 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 28 PID ॥ᇅఖ (PID) 0 + + Register 28.6. PIDCTRL_INTERRUPT_ADDR_5_REG (0x014) Reset + + 31 + + 0x040000240 + + PIDCTRL_INTERRUPT_ADDR_5_REG Level 5 ᇏ؎ཟਈೆ१ֹᆶbč‫؀‬ĔཿĎ + + Register 28.7. PIDCTRL_INTERRUPT_ADDR_6_REG (0x018) 0 + +31 Reset + + 0x040000280 + + PIDCTRL_INTERRUPT_ADDR_6_REG Level 6 ᇏ؎ཟਈೆ१ֹᆶbč‫؀‬ĔཿĎ + + Register 28.8. PIDCTRL_INTERRUPT_ADDR_7_REG (0x01C) 0 + +31 Reset + + 0x0400002C0 + + PIDCTRL_INTERRUPT_ADDR_7_REG NMI ᇏ؎ཟਈೆ१ֹᆶbč‫؀‬ĔཿĎ + + Register 28.9. PIDCTRL_PID_DELAY_REG (0x020) + + (reserved) PIDCTRL_PID_DELAY + 20 +31 12 11 0 + +00000000000000000000 Reset + + PIDCTRL_PID_DELAY ྍ‫ٳ‬஥֥ PID ളིభ֥࿼Ӿbč‫؀‬ĔཿĎ + + Register 28.10. PIDCTRL_NMI_DELAY_REG (0x024) + + (reserved) PIDCTRL_NMI_DELAY + 16 +31 12 11 0 + +00000000000000000000 Reset + + PIDCTRL_NMI_DELAY ܱо CPU NMI ᇏ؎௠зྐ‫ݼ‬భ֥࿼Ӿbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 571 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 28 PID ॥ᇅఖ (PID) + + Register 28.11. PIDCTRL_LEVEL_REG (0x028) + + (reserved) PIDCTRL_CURRENT_STATUS + +31 43 0 + +0000000000000000000000000000 0 Reset + + PIDCTRL_CURRENT_STATUS ༢๤֒భሑ෿bč‫؀‬ĔཿĎ + + Register 28.12. PIDCTRL_FROM_n_REG (n: 1­7) (0x28+0x4*n) + + (reserved) PIDCTRL_PREVIOUS_STATUS_n + +31 76 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PIDCTRL_PREVIOUS_STATUS_n ಩၂ Level 1 ᇀ Level 6đࠇ NMI ᇏ؎‫ؿ‬ളభ֥༢๤ሑ෿bč‫؀‬Ĕ + ཿĎ + + Register 28.13. PIDCTRL_PID_NEW_REG (0x048) + + (reserved) PIDCTRL_PID_NEW + +31 32 0 + +00000000000000000000000000000 0 Reset + + PIDCTRL_PID_NEW ྍ֥ PIDbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 572 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 28 PID ॥ᇅఖ (PID) + + Register 28.14. PIDCTRL_PID_CONFIRM_REG (0x04C) + + (reserved) PIDCTRL_PID_CONFIRM + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PIDCTRL_PID_CONFIRM ‫໊ھ‬ႨႿ൐ྍ PID ളིbčᆺཿĎ + + Register 28.15. PIDCTRL_NMI_MASK_ENABLE_REG (0x054) + + (reserved) PIDCTRL_NMI_MASK_ENABLE + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PIDCTRL_NMI_MASK_ENABLE ൐ି CPU NMI ᇏ؎௠зྐ‫ݼ‬bčᆺཿĎ + + Register 28.16. PIDCTRL_NMI_MASK_DISABLE_REG (0x058) + + (reserved) PIDCTRL_NMI_MASK_DISABLE + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + PIDCTRL_NMI_MASK_DISABLE ܱо CPU NMI ᇏ؎௠зྐ‫ݼ‬bčᆺཿĎ + +ুᶈྐ༏॓࠯ 573 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + +29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + +29.1 ‫ۀ‬ඍ + +ູਔᆦӻ‫؟‬ᇕႋႨӆࣟđESP32 ᇶေҐႨਔ 2 ᇕো྘֥Ԯ‫ۋ‬ఖğ‫׈‬ಸൔԨଃԮ‫ۋ‬ఖ čቋۚᆦӻ 10 ਫ਼ൻೆĎ +‫ིغࠉބ‬ႋԮ‫ۋ‬ఖb +ESP32 ֥ଆ୅ྐ‫ݼ‬ԩ৘ᇶေႮ 2 ۱ᇯՑЯ࣍ଆ୅ඔሳሇߐఖ (Successive Approximation ADC, SAR ADC) ປӮb +༢๤ህ૊ଽᇂਔ 5 ۱ ADC ህႨ॥ᇅఖđॖᄝሇߐଆ୅ൻೆྐ‫ݼ‬ൈᆦӻۚྟିა֮‫ ݻۿ‬2 ᇕଆൔđԩ৘ఖ֥ष +ཧቋ֮b +ՎຓđESP32 ߎॖ൐Ⴈ 2 ۱‫׿‬৫ඔሳଆ୅ሇߐఖ (DAC)‫ ބ‬1 ۱Ⴥ༿ѯྙ‫ؿ‬ളఖളӮଆ୅ྐ‫ݼ‬b + +29.2 ‫׈‬ಸൔԨଃԮ‫ۋ‬ఖ + +29.2.1 ࡥࢺ + +ԨଃԮ‫ۋ‬ఖ༢๤ᇶေႮ 3 ۱҆‫ٳ‬ቆӮđՖຓ֞ଽ၇Ցູ௜૫Ќ޹Ҫa‫ࠞ׈‬აࠎோđ࡮๭ 29-1b֒Ⴈ޼ԨஷЌ޹ +ҪൈđԮ‫ۋ‬ఖ༢๤֥‫׈‬ಸਈ߶‫ؿ‬ള‫ڿ‬эđ࠿‫ط‬ളӮ 1 ۱ॖၛّ႘ЧՑԨஷ൞‫ڎ‬Ԩ‫ࣉؽ֥ؿ‬ᇅྐ‫ݼ‬b + + ๭ 29­1. ԨଃԮ‫ۋ‬ఖ + +29.2.2 ᇶေหྟ + + • ቋ‫؟‬ᆦӻ 10 ਫ਼‫׈‬ಸԨଃܵ࢖/๙Ⴈൻೆൻԛࢤ१ (General Purpose Input and Output, GPIO) + • Ԩଃܵ࢖ॖၛቆ‫ކ‬൐Ⴈđॖ‫ۂڭ‬۷նԨ‫ۋ‬౵თࠇ۷‫؟‬Ԩ‫ׄۋ‬ + • Ԩଃܵ࢖֥Ԯ‫ۋ‬ႮႵཋሑ෿ࠏ (FSM) ႗ࡱ॥ᇅđႮೈࡱࠇህႨ႗ࡱ࠹ൈఖ‫ؿ‬ఏ + • Ԩଃܵ࢖൞‫ڎ‬൳֞Ԩஷ֥ྐ༏ॖႮၛ༯ٚൔࠆ֤ğ + + – Ⴎೈࡱᆰࢤ࡟ҰԨଃԮ‫ۋ‬ఖ֥࠷թఖ + – ႮԨଃࡓҩଆॶ‫ؿ‬ఏ֥ᇏ؎ྐ‫ݼ‬஑؎ + – ႮԨଃࡓҩଆॶഈ֥ CPU ൞‫ڎ‬Ֆ Deep-sleep ᇏߒྜ஑؎ + • ᆦӻၛ༯ӆࣟ༯֥֮‫۽ݻۿ‬ቔğ + – CPU ԩႿ Deep-sleep ࢫିଆൔđࡼᄝ൳֞Ԩஷުᇯ҄ߒྜ + +ুᶈྐ༏॓࠯ 574 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + +– ԨଃࡓҩႮӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP coprocessor) ܵ৘ + ULP Ⴈ޼ӱ྽ॖ๙‫ݖ‬ཿೆა࡟Ұห‫࠷ק‬թఖđ஑؎൞‫ڎ‬ղ֞Ԩஷᚐᆴ + +29.2.3 ॖႨ๙Ⴈൻೆൻԛࢤ१ + +ಆ҆ 10 ۱ॖႨ๙Ⴈൻೆൻԛࢤ१֥ྐ༏đ౨࡮і 29-1b + + і 29­1. ESP32 ‫׈‬ಸൔԨଃԮ‫ۋ‬ఖ֥ܵ࢖ + +ԨଃԮ‫଀ݼྐۋ‬ ܵ࢖ +T0 GPIO4 +T1 GPIO0 +T2 GPIO2 +T3 MTDO +T4 MTCK +T5 MTDI +T6 MTMS +T7 GPIO27 +T8 32K_XN +T9 32K_XP + +29.2.4 ‫ିۿ‬૭ඍ + +ԨଃԮ‫ۋ‬ఖ֥ଽ҆ࢲ‫ܒ‬౨࡮๭ 29-2đ‫۽‬ቔੀӱ౨࡮๭ 29-3b + + ๭ 29­2. ԨଃԮ‫ۋ‬ఖ֥ଽ҆ࢲ‫ܒ‬ + +Ԩଃܵ࢖֥‫׈‬ಸ߶ࣉྛᇛ௹ྟԉ٢‫׈‬b” Ԩଃܵ࢖֥ଽ҆‫׈‬࿢” սіԉ/٢‫׈׈‬࿢ᄝҕॉۚᆴ (drefH) აҕॉ֮ᆴ +(drefL) ᆭࡗ֥э߄bᄝૄՑэ߄ᇏđԨଃԮ‫ۋ‬ఖࡼളӮ၂۱ൻԛઝԊ (OUT)bႮႿԨଃܵ࢖൳֞Ԩஷčۚ‫׈‬ಸĎ +აໃ൳֞Ԩஷč֮‫׈‬ಸĎൈ֥‫׈‬࿢э߄෎ੱ҂๝đ໡ૌॖၛ๙‫ݖ‬๤࠹๝၂ൈࡗࡗ‫ۯ‬ଽԛགྷ֥ൻԛઝԊඔਈđ஑ +؎Ԩଃܵ࢖൞‫ڎ‬൳֞Ԩஷbॖၛ๙‫ ݖ‬TIE_OPT ഡᇂष൓ԉ/٢‫֥׈‬Ԛ൓‫׈‬࿢‫׈‬௜b + +29.2.5 Ԩ‫ؿ‬Ԯ‫ۋ‬ఖ֥ሑ෿ࠏ + +Ⴕཋሑ෿ࠏ (Finite-State Machine, FSM) ࡼᆳྛ 29.2.4 ᅣࢫ૭ඍ֥྽ਙ࡟ҩbೈࡱॖ๙‫ݖ‬ህႨ࠷թఖҠቔ FSMb +FSM ֥ଽ҆ࢲ‫ܒ‬ॖ࡮๭ 29-4b + +FSM ֥‫ିۿ‬Їওğ + +ুᶈྐ༏॓࠯ 575 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + ๭ 29­3. ԨଃԮ‫ۋ‬ఖ֥‫۽‬ቔੀӱ + • ࢤ൬ೈࡱࠇ࠹ൈఖ‫ؿ‬ԛ֥ष൓ྐ‫ݼ‬ + + – ֒ SENS_SAR_TOUCH_START_FORCE = 1 ൈđॖ๙‫ݖ‬ഡᇂ SENS_SAR_TOUCH_START_EN ‫ؿ‬ఏ + ၂Ցྟ࡟ҩĠ + + – ֒ SENS_SAR_TOUCH_START_FORCE = 0 ൈđॖ০Ⴈ࠹ൈఖൌགྷᇛ௹ྟ࡟ҩb + ԨଃԮ‫ۋ‬ఖᄝඤ૤ଆൔ༯္ି‫۽‬ቔb۷‫ྐ؟‬༏đ౨࡮‫ܵݻۿ‬৘ᅣࢫbॖ๙‫࠷ݖ‬թఖ + SENS_SAR_TOUCH_SLEEP_CYCLES ഡ‫࡟ק‬ҩᇛ௹bԮ‫ۋ‬ఖႮ FAST_CLK ॥ᇅđӈ࡮ൈᇒ௔ੱູ 8 + MHzb۷‫ྐ؟‬༏đ౨࡮‫ބ໊گ‬ൈᇒᅣࢫb + • ۴ऌॖ‫ࢫט‬ൈ྽đളӮ XPD_TOUCH_BIAS / TOUCH_XPD / TOUCH_START + ᄝ࿊ᄴ൐ିԨଃܵ࢖ൈđTOUCH_XPD / TOUCH_START ᇏ֥ଽಸࡼФ 10 ໊࠷թఖ + SENS_SAR_TOUCH_PAD_WORKEN ᅻဃb + • ࠹ඔ TOUCH0_OUT ~ TOUCH9_OUT ഈ֥ઝԊඔਈ + ࠹ඔࢲ‫ݔ‬ॖ࡮ SENS_SAR_TOUCH_MEAS_OUTnbಆ҆ 10 ۱Ԩଃܵ࢖ॖᆦӻ๝ൈ‫۽‬ቔb + • ളӮߒྜᇏ؎ + ೂ‫ݔ‬၂۱ܵ࢖֥ઝԊ࠹ඔࢲ‫֮ݔ‬Ⴟᚐᆴđᄵ FSM ൪‫࢖ܵھ‬ФoԨஷpb10 ໊࠷թఖ + SENS_TOUCH_PAD_OUTEN1 & SENS_TOUCH_PAD_OUTEN2 ॖၛࡼ෮Ⴕܵ࢖‫ק‬ၬູ 2 ቆđࠧ SET1 & + SET2bଏಪሑ෿༯đೂ‫ ݔ‬SET1 ᇏ֥಩ၩܵ࢖ФoԨஷpđࠧॖളӮߒྜᇏ؎đ္ॖၛ஥ᇂູ SET1 ‫ބ‬ + SET2 ᇏनႵܵ࢖ФoԨஷpൈႵིb + +ুᶈྐ༏॓࠯ 576 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + ๭ 29­4. FSM ֥ଽ҆ࢲ‫ܒ‬ + +29.3 SAR ADC + +29.3.1 ࡥࢺ + +ESP32 ଽᇂਔ 2 ۱ 12 ໊֥ SAR ADCđႮ 5 ۱ህႨሇߐఖ॥ᇅఖܵ৘đॖҩਈটሱ 18 ۱ܵ࢖֥ଆ୅ྐ‫ݼ‬đߎ +ॖҩਈ vdd33 ֩ଽ҆ྐ‫ݼ‬b + + ๭ 29­5. SAR ADC ֥‫ۀ‬ঃ + +SAR ADC ൐Ⴈ֥ 5 ۱॥ᇅఖनູህႨ॥ᇅఖđఃᇏ 2 ۱ᆦӻۚྟି‫؟‬๙֡ೡ૭a2 ۱ࣜ‫ݖ‬Ⴊ߄ॖᆦӻ + +ুᶈྐ༏॓࠯ 577 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + +Deep-sleep ଆൔ༯֥֮‫ݻۿ‬ᄎྛđਸ਼ຓ 1 ۱ህ૊ႨႿ PWDET / PKDET č‫࡟ੱۿ‬ҩ‫ڂބ‬ᆴࡓҩĎbSAR ADC ֥ +ࠎЧ‫ۀ‬ঃ࡮๭ 29-5b + + ඪૼğ + PWDET/PKDET ॥ᇅఖࣇ‫ ܂‬Wi-Fi ଽ҆൐Ⴈbೂ‫ ݔ‬Wi-Fi ᆞᄝ൐Ⴈ SAR ADC2đᄵႨ޼໭‫م‬൐Ⴈ SAR ADC2 ҩਈܵ࢖ + ֥ଆ୅ྐ‫ݼ‬bWi-Fi ൤٢ SAR ADC2 ᆭުđႨ޼ॖᆞӈ൐Ⴈ SAR ADC2b + +29.3.2 ᇶေหྟ + + • ҐႨ 2 ۱ SAR ADCđॖᆦӻ๝ൈҐဢაሇߐ + • ҐႨ 5 ۱ህႨ ADC ॥ᇅఖđॖᆦӻ҂๝ႋႨӆࣟčбೂđۚྟିa֮‫ݻۿ‬đࠇ‫࡟ੱۿ‬ҩ‫ڂބ‬ᆴ࡟ҩĎ + • ᆦӻ 18 ۱ଆ୅ൻೆܵ࢖ + • 1 ۱ଽ҆‫׈‬࿢ vdd33 ๙֡a2 ۱ pa_pkdet ๙֡č҆‫ٳ‬॥ᇅఖᆦӻĎ + • ॖ஥ᇂ 12 ໊a11 ໊a10 ໊a9 ໊‫؟‬ᇕ‫ٳ‬яੱ + • ᆦӻ DMAč1 ۱॥ᇅఖᆦӻĎ + • ᆦӻ‫؟‬๙֡ೡ૭ଆൔč2 ۱॥ᇅఖᆦӻĎ + • ᆦӻ Deep-sleep ଆൔᄎྛč1 ۱॥ᇅఖᆦӻĎ + • ᆦӻ ULP ླྀԩ৘ఖ॥ᇅč2 ۱॥ᇅఖᆦӻĎ + +29.3.3 ‫ۀିۿ‬ঃ + +SAR ADC ֥ᇶေჭࡱა৵ࢤ౦ঃ࡮๭ 29-6b + + ๭ 29­6. SAR ADC ֥‫ۀିۿ‬ঃ + +ুᶈྐ༏॓࠯ 578 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + +෮Ⴕॖିა SAR ADCčЇও ADC1 ‫ ބ‬ADC2ĎႵܱ֥ܵ࢖ྐ༏đ౨࡮і 29-2b + + і 29­2. SAR ADC ֥ྐ‫ݼ‬ൻೆ + +ྐ‫଀ݼ‬ӫ ܵ࢖ # ADC ࿊ᄴ +VDET_2 7 SAR ADC1 +VDET_1 6 +32K_XN 5 SAR ADC2 +32K_XP 4 +SENSOR_VN 3 +SENSOR_CAPN 2 +SENSOR_CAPP 1 +SENSOR_VP 0 +Hall sensor n/a +GPIO26 9 +GPIO25 8 +GPIO27 7 +MTMS 6 +MTDI 5 +MTCK 4 +MTDO 3 +GPIO2 2 +GPIO0 1 +GPIO4 0 +pa_pkdet1 n/a +pa_pkdet2 n/a +vdd33 n/a + +ඪૼğ +SAR ADC2 ֥࡟ҩܵ࢖ᇏđЇও GPIO0aGPIO2 ‫ ބ‬GPIO15 ູྉோ Strapping ܵ࢖đႨ޼൐Ⴈൈླหљᇿၩb + +ESP32 ଽᇂਔ 5 ۱ህႨ ADC ॥ᇅఖğRTC ADC1 CTRLaRTC ADC2 CTRLaDIG ADC1 CTRLaDIG ADC2 +CTRLđࠣ PWDET CTRLb۲॥ᇅఖ֥ӆࣟᆦӻ౦ঃ࡮і 29-3b + + і 29­3. ESP32 ֥ SAR ADC ॥ᇅఖ + + RTC ADC1 RTC ADC2 DIG ADC1 DIG ADC2 PWDET + - - - - +DAC Y Y - - - + Y - - - +Deep-sleep Y Y - Y - + - - - Y +ULP ླྀԩ৘ఖ Y - - - - + - Y - - +vdd33 - + +PWDET/PKDET - + +ࠉ‫غ‬Ԯ‫ۋ‬ఖ Y + +DMA - + +ুᶈྐ༏॓࠯ 579 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + +29.3.4 RTC SAR ADC ॥ᇅఖ + +RTC ‫׈‬ჷთᇏ֥ SAR ADC ॥ᇅఖčRTC ADC1 CTRL ‫ ބ‬RTC ADC2 CTRLĎॖᄝ֮௔ሑ෿༯ิ‫܂‬ቋཬ‫ݻۿ‬ +ADC ҩਈb +۲॥ᇅఖ֥ऎุ‫ۀିۿ‬ঃ࡮๭ 29-7bؓႿૄ۱॥ᇅఖটඪđሇߐ൞Ⴎ࠷թఖ SENS_SAR_MEASn_START_SAR +Ԩ‫ؿ‬đҩਈࢲ‫ݔ‬ॖ࡮࠷թఖ SENS_SAR_MEASn_DATA_SARb + + ๭ 29­7. RTC SAR ADC ֥‫ۀିۿ‬ঃ + +ULP ླྀԩ৘ఖა॥ᇅఖᆭࡗ֥ܱ༢٤ӈࣅૡđၘࣜଽᇂਔᆷ਷ট൐Ⴈ ADCb‫؟ޓ‬౦ঃ༯đ॥ᇅఖनླေა ULP +ླྀԩ৘ఖླྀ๝‫۽‬ቔđбೂğ + + • ॖᄝ Deep-sleep ଆൔ༯ؓ๙֡ࣉྛᇛ௹ྟ࡟ҩbDeep-sleep ଆൔ༯đULP ླྀԩ৘ఖ൞ື၂֥Ԩ‫ؿ‬ఖb + • ॖο၂‫ק‬ඨ྽ؓ๙֡ࣉྛ৵࿃ྟೡ૭b࣐ܵ॥ᇅఖ໭‫م‬ᆦӻ৵࿃ྟೡ૭ࠇ DMAđ֌ ULP ླྀԩ৘ఖॖླྀᇹ + + ൌགྷᆃ҆‫ିۿٳ‬b + +29.3.5 DIG SAR ADC ॥ᇅఖ + +ა RTC SAR ADC ॥ᇅఖཌྷбđDIG SAR ADC ॥ᇅఖ֥ྟି‫ބ‬๽๳नൌགྷਔ၂‫ק‬Ⴊ߄đऎСၛ༯หׄğ + • ۚྟିbൈᇒ۷ॹđၹՎҐဢ෎ੱൌགྷਔն‫ิږ‬ശb + • ᆦӻ‫؟‬๙֡ೡ૭ଆൔbૄ۱ SAR ADC ֥ҩਈܿᄵॖ࡮ဢൔіbೡ૭ଆൔॖ஥ᇂູֆ๙֡ଆൔaච๙֡ଆ + ൔࠇࢌูଆൔb + • ೡ૭ॖႮೈࡱࠇ I2S ሹཌ‫ؿ‬ఏb + • ᆦӻ DMAbೡ૭ປӮࠧ‫ؿ‬ളᇏ؎b + + ඪૼğ + ႮႿ໭‫م‬๙‫ݖ‬ᆰࢤ٠໙‫ؿ‬ఏ၂Ցྟ SAR ADC ሇߐđၹՎ໡ૌࡼᄝЧᅣࢫᇏҐႨoष൓ೡ૭p֥ඪ‫م‬đսі໡ૌࡼ০Ⴈ + DIG SAR ADC ॥ᇅఖೡ૭၂༢ਙ๙֡b + +๭ 29-8 ᅚൕਔ DIG SAR ADC ॥ᇅఖ֥ჰ৘๭b + +ুᶈྐ༏॓࠯ 580 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + ๭ 29­8. DIG SAR ADC ॥ᇅఖ֥‫ۀ‬ঃ + +ဢൔіॖၛ૭ඍ DIG SAR ADC ॥ᇅఖླေ቎൯֥۲ཛҩਈܿᄵđૄ۱іཛႚႵ 16 ۱ཛđॖթԥ๙֡࿊ᄴa‫ٳ‬ +яੱ‫ބ‬කࡨྐ༏֩ଽಸb֒ೡ૭ष൓ൈđ॥ᇅఖࡼᇯ่‫؀‬౼ဢൔіᇏ֥ҩਈܿᄵbؓႿૄ۱॥ᇅఖ‫ط‬࿽đૄ۱ +ೡ૭྽ਙቋ‫؟‬ႚႵ 16 ่҂๝ܿᄵb + +ဢൔі࠷թఖ֥Ӊ؇ູ 8 ໊đ‫܋‬Їও 3 ۱ሳ‫؍‬đ‫ٳ‬љթԥਔ๙֡a‫ٳ‬яੱ‫ބ‬කࡨྐ༏֥ଽಸđऎุ࡮і +29-4b + + і 29­4. ဢൔі࠷թఖ֥ሳ‫ྐ؍‬༏ + +ch_sel[3:0] ဢൔі࠷թఖ [7:0] atten[1:0] +ೡ૭๙֡ bit_width[1:0] කࡨ + ‫ٳ‬яੱ + +ೡ૭ଆൔॖ஥ᇂູğֆ๙֡ଆൔaච๙֡ଆൔࠇࢌูଆൔb + • ֆ๙֡ଆൔğࣇ SAR ADC1 ࠇ SAR ADC2 ֥๙֡ࡼФೡ૭b + • ච๙֡ଆൔğSAR ADC1 ‫ ބ‬SAR ADC2 ֥๙֡๝ࡼФೡ૭b + • ࢌูଆൔğSAR ADC1 ‫ ބ‬SAR ADC2 ֥๙֡ࡼФࢌูೡ૭b + +ESP32 ቋۚᆦӻ 12 ໊֥ SAR ADC ‫ٳ‬яੱđቋᇔཟ DMA Ԯ‫ ֥־‬16 ໊ඔऌЇও ADC ሇߐࢲ‫ݔ‬đࠣ၂ུၹೡ૭ +ଆൔ҂๝‫ط‬Ⴕ෮ҵљ֥ཌྷܱྐ༏đऎุູğ + + • ֆ๙֡ଆൔğࣇᄹࡆ 4 ໊๙֡࿊ᄴྐ༏b + • ච๙֡ଆൔࠇࢌูଆൔğᄹࡆ 4 ໊๙֡࿊ᄴྐ༏đࠣ 1 ໊ SAR ADC ࿊ᄴྐ༏b + +ুᶈྐ༏॓࠯ 581 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + +ૄᇕೡ૭ଆൔनႵఃؓႋ֥ඔऌ۬ൔđࠧ I ྘‫ ބ‬II ྘bႵܱᆃਆᇕඔऌ۬ൔ֥ऎุ૭ඍđ౨࡮і 29-5 ‫ބ‬і +29-6b + + і 29­5. I ྘ DMA ඔऌ۬ൔ + +ch_sel[3:0] I ྘ DMA ඔऌ۬ൔ [15:0] +๙֡ data[11:0] + SAR ADC ྐ༏ + + і 29­6. II ྘ DMA ඔऌ۬ൔ + +sar_sel II ྘ DMA ඔऌ۬ൔ [15:0] SAR ADC data[10:0] +SAR ADCn ch_sel[3:0] SAR ADC ྐ༏ + ๙֡ + +I ྘ඔऌ۬ൔ֥ SAR ADC ‫ٳ‬яੱቋۚॖᆦӻ 12 ໊đII ྘ඔऌ۬ൔ֥ SAR ADC ‫ٳ‬яੱቋۚॖᆦӻ 11 ໊b + +DIG SAR ADC ॥ᇅఖᄍྸ๙‫ ݖ‬I2S ሹཌൌགྷᆰࢤଽթ٠໙bI2S ሹཌ֥ WS ྐ‫ݼ‬ॖႨቔҩਈԨ‫ݼྐؿ‬bॖ๙‫ݖ‬ +DATA ྐ‫֤ࠆݼ‬ҩਈࢲ‫ݔ‬൞‫ڎ‬ປӮ֥ྐ༏bॖ๙‫ݖ‬ೈࡱ஥ᇂ APB_SARADC_DATA_TO_I2Sđࡼ ADC ৵ࢤᇀ I2S +ሹཌb + +29.4 ࠉ‫غ‬Ԯ‫ۋ‬ఖ + +29.4.1 ࡥࢺ + +۴ऌࠉ‫ིغ‬ႋđ֒‫׈‬ੀԼᆰႿՈӆ๙‫ ݖ‬N ྘϶ุ֝ൈđ߶ᄝԼᆰႿ‫׈‬ੀ‫ބ‬Ոӆ֥ٚཟӁള‫׈ࡆڸ‬ӆđՖ‫ط‬ᄝ϶ +ุ֝ਆ؊ྙӮ‫׈‬൝ҵđऎุ֮ۚა‫׈‬Ոӆ఼֥؇‫׈ބ‬ੀնཬႵܱb֒‫׈קޚ‬ੀԬ‫ݖ‬Ոӆࠇ‫׈‬ੀթᄝႿ‫קޚ‬Ոӆ +ൈđࠉ‫ིغ‬ႋԮ‫ۋ‬ఖॖႨႿҩਈՈӆ఼؇bࠉ‫غ‬Ԯ‫ۋ‬ఖ֥ႋႨӆ‫ކ‬٤ӈܼٗđЇওࢤ࣍ฐҩa‫໊ק‬aҩ෎ა‫׈‬ +ੀ࡟ҩ֩b + +ESP32 ᇏ֥ࠉ‫غ‬Ԯ‫ۋ‬ఖࣜ‫ݖ‬ህ૊ഡ࠹đॖཟ SAR ADC ิ‫׈܂‬࿢ྐ‫ݼ‬đൌགྷՈӆԮ‫ିۿۋ‬bᄝླေ֮‫׈‬࿢֥‫۽‬ +ቔଆൔ༯đ‫ھ‬Ԯ‫ۋ‬ఖॖႮ ULP ླྀԩ৘ఖ॥ᇅbᄝՎো‫֥ିۿ‬ᆦӻ༯đESP32 ऎС֥ԩ৘ି৯‫ބ‬ਲࠃྟन൐ఃᄝ +໊ᇂԮ‫ۋ‬aࢤ࣍࡟ҩࠣҩ෎֩ႋႨӆࣟ༯Ӯູ၂ᇕࠞऎ་ႄ৯֥ࢳथٚσb + +29.4.2 ᇶေหྟ + + • ଽᇂࠉ‫غ‬ჭࡱ + + • ॖ஥‫ ކ‬ADC ‫۽‬ቔ + + • ॖᆦӻൻԛսіՈӆ఼؇֥ଆ୅‫׈‬࿢აඔሳྐ‫ݼ‬ + + • ‫఼ିۿ‬ն౏ၞႿൌགྷđҐႨਔଽᇂൔ ULP ླྀԩ৘ఖaGPIOaCPU ࠣ Wi-Fi ֩ଆॶ + +29.4.3 ‫ିۿ‬૭ඍ + +ࠉ‫غ‬Ԯ‫ۋ‬ఖॖࡼՈӆሇູ‫׈‬࿢đෂೆ٢նఖଽđ‫ުط‬๙‫ ࢖ܵݖ‬SENSOR_VP ‫ ࢖ܵބ‬SENSOR_VN ൻԛbESP32 +ଽᇂ ADC ॖࡼྐ‫ݼ‬ሇ߄ູඔሳᆴđࢌႮ CPU ᄝඔሳთଽປӮၛ༯Ҡቔb + +ࠉ‫غ‬Ԯ‫ۋ‬ఖ֥ࢲ‫࡮ܒ‬๭ 29-9b + +ুᶈྐ༏॓࠯ 582 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + ๭ 29­9. ࠉ‫غ‬Ԯ‫ۋ‬ఖ֥ࢲ‫ܒ‬ + +ॖ๙‫࠷ݖ‬թఖ SENS_SAR_TOUCH_CTRL1_REG ປӮࠉ‫غ‬Ԯ‫ۋ‬ఖ֥‫؀‬౼஥ᇂđRTCIO_HALL_SENS_REG ູԮ +‫ۋ‬ఖ‫׈܂‬bު࿃ҠቔॖࢌႮ SAR ADC1 ປӮbቋᇔࢲ‫ݔ‬ॖ๙‫ ݖ‬RTC ADC1 ॥ᇅఖࠆ֤b۷‫ྐ؟‬༏đ౨࡮ 29.3 +ᅣࢫb + +29.5 ඔሳଆ୅ሇߐఖ + +29.5.1 ࡥࢺ + +ඔሳଆ୅ሇߐఖ (DAC) ջႵ 2 ۱ 8 ໊๙֡đॖࡼඔሳᆴሇߐູቋۚ 2 ਫ਼ଆ୅ൻԛྐ‫ݼ‬đЇওࠢӮ‫׈‬ቅԱ‫ߏބ‬Ԋ +౵bᆃᇕච๙֡ DAC ᆦӻࡼ‫׈‬ჷ֒ቓൻೆ‫׈‬࿢ҕॉđ౏ᆦӻච๙֥֡‫׿‬৫/๝ൈሇߐb + +29.5.2 ᇶေหྟ + +DAC ֥ᇶေหྟЇওğ + • 2 ۱ 8 ໊ DAC ๙֡ + • ᆦӻච๙֥֡‫׿‬৫/๝ൈሇߐ + • ॖՖ VDD3P3_RTC ႄ࢖ࠆ֤‫׈‬࿢ҕॉ + • ‫ݣ‬ႵჅ༿ѯ྘‫ؿ‬ളఖ + • ᆦӻ DMA ‫ିۿ‬ + • ॖ๙‫ݖ‬ೈࡱࠇ SAR ADC FSM ष൓ሇߐb۷‫ྐ؟‬༏đ౨࡮ SAR ADC ᅣࢫb + • ॖႮ ULP ླྀԩ৘ఖ๙‫ݖ‬॥ᇅ࠷թఖটൌགྷປಆ॥ᇅb౨࡮ ULP ླྀԩ৘ఖᅣࢫb + +ֆ๙֡ DAC ֥‫ۀିۿ‬ঃ౨࡮๭ 29-10bऎุࢺകđ౨࡮Чᅣࢫ༯ٚଽಸb + +29.5.3 ࢲ‫ܒ‬ + +ච๙֡ DAC ֥ 2 ۱ 8 ໊๙֡ॖൌགྷ‫׿‬৫஥ᇂđૄ۱๙֥֡ൻԛଆ୅‫׈‬࿢࠹ෘٚൔ࡮༯ğ + + DACn_OUT = VDD3P3_RTC · PDACn_DAC/255 + • VDD3P3_RTC սі VDD3P3_RTC ႄ࢖֥‫׈‬࿢ (๙ӈູ 3.3V)b + +ুᶈྐ༏॓࠯ 583 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + ๭ 29­10. DAC ֥‫ۀିۿ‬ঃ + + • PDACn_DAC ႚႵ‫؟‬۱টჷğჅ༿ѯྙളӮఖa࠷թఖ RTCIO_PAD_DACn_REGđࠣ DMA b +ॖ๙‫࠷ݖ‬թఖ RTCIO_PAD_PDACn_XPD_DAC थ‫ק‬ሇߐ൞‫ڎ‬ष൓đೈࡱࠇ SAR ADC FSM ॥ᇅሇߐੀӱЧദđ +ऎุ౨࡮๭ 29-10b + +29.5.4 Ⴥ༿ѯྙളӮఖ + +Ⴥ༿ѯྙളӮఖॖႨႿളӮჅ༿ѯྙ/ᆞ༿ѯྙđऎุ‫۽‬ቔੀӱॖ࡮๭ 29-11b +Ⴥ༿ѯྙളӮఖ֥หׄЇওğ + + • ௔ੱॖ‫ࢫט‬ + Ⴥ༿ѯ֥௔ੱॖ๙‫࠷ݖ‬թఖ SENS_SAR_SW_FSTEP[15:0] ‫ࢫט‬ğ + + freq = dig_clk_rtc_freq · SENS_SAR_SW_FSTEP/65536 + + ๙ӈđdig_clk_rtc ֥௔ੱູ 8 MHzb + • ᆒ‫ږ‬ॖ‫ࢫט‬ + + ॖ๙‫࠷ݖ‬թఖ SENS_SAR_DAC_SCALEn[1:0] ഡᇂѯྙᆒ‫ږ‬đ‫ט‬ᆜູ 1a1/2a1/4 ࠇ 1/8 Пb + • ᆰੀொ၍ + + ࠷թఖ SENS_SAR_DAC_DCn[7:0] ॖିႄೆ၂ུᆰੀொ၍đ֝ᇁࢲ‫ݔ‬Ў‫ބ‬b + • ཌྷ໊၍‫׮‬ + + ॖ๙‫࠷ݖ‬թఖ SENS_SAR_DAC_INVn[1:0] ᄹࡆ 0/90/180/270° ཌྷ໊ொ၍b + +29.5.5 ᆦӻ DMA + +ච๙֡ DAC ֥ᆰࢤଽթթ౼ (DMA) ॥ᇅఖॖؓ 2 ۱ DAC ๙֥֡ൻԛࣉྛഡᇂb๙‫ݖ‬஥ᇂ +SENS_SAR_DAC_DIG_FORCE đI2S_clk ॖ৵ࢤᇀ DAC clkđI2S_DATA_OUT ॖ৵ࢤᇀ DAC_DATA ൌགྷᆰࢤଽ +թ٠໙b +۷‫ྐ؟‬༏đ౨࡮ DMA ᅣࢫb + +ুᶈྐ༏॓࠯ 584 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + ๭ 29­11. Ⴥ༿ѯྙളӮఖ֥‫۽‬ቔੀӱ + +29.6 ࠷թఖਙі + +ඪૼğ༯ٚ࠷թఖ֥‫ٳ‬োᇶေၛ‫ູିۿ‬ᇶđѩ҂ّ႘٠໙ଽթ֥ऎุඨ྽b + +29.6.1 Ԯ‫ۋ‬ఖ ૭ඍ ֹᆶ ٠໙ো྘ + + ଀ӫ Ԩଃϰ॥ᇅ 0x3FF48858 ‫؀‬/ཿ + Ԩଃܵ࢖ഡᇂა॥ᇅ࠷թఖ Ԩଃϰ॥ᇅაሑ෿ 0x3FF48884 ᆺ‫؀‬ + SENS_SAR_TOUCH_CTRL1_REG ߒྜᇏ؎॥ᇅა‫۽‬ቔ SET 0x3FF4888C ‫؀‬/ཿ + SENS_SAR_TOUCH_CTRL2_REG ܵ࢖ 0 ‫ ࢖ܵބ‬1 ֥ᚐᆴഡᇂ 0x3FF4885C ‫؀‬/ཿ + SENS_SAR_TOUCH_ENABLE_REG ܵ࢖ 2 ‫ ࢖ܵބ‬3 ֥ᚐᆴഡᇂ 0x3FF48860 ‫؀‬/ཿ + SENS_SAR_TOUCH_THRES1_REG ܵ࢖ 4 ‫ ࢖ܵބ‬5 ֥ᚐᆴഡᇂ 0x3FF48864 ‫؀‬/ཿ + SENS_SAR_TOUCH_THRES2_REG ܵ࢖ 6 ‫ ࢖ܵބ‬7 ֥ᚐᆴഡᇂ 0x3FF48868 ‫؀‬/ཿ + SENS_SAR_TOUCH_THRES3_REG ܵ࢖ 8 ‫ ࢖ܵބ‬9 ֥ᚐᆴഡᇂ 0x3FF4886C ‫؀‬/ཿ + SENS_SAR_TOUCH_THRES4_REG ܵ࢖ 0 ‫ ࢖ܵބ‬1 ֥࠹ඔఖ 0x3FF48870 ᆺ‫؀‬ + SENS_SAR_TOUCH_THRES5_REG ܵ࢖ 2 ‫ ࢖ܵބ‬3 ֥࠹ඔఖ 0x3FF48874 ᆺ‫؀‬ + SENS_SAR_TOUCH_OUT1_REG ܵ࢖ 4 ‫ ࢖ܵބ‬5 ֥࠹ඔఖ 0x3FF48878 ᆺ‫؀‬ + SENS_SAR_TOUCH_OUT2_REG ܵ࢖ 6 ‫ ࢖ܵބ‬7 ֥࠹ඔఖ 0x3FF4887C ᆺ‫؀‬ + SENS_SAR_TOUCH_OUT3_REG ܵ࢖ 8 ‫ ࢖ܵބ‬9 ֥࠹ඔఖ 0x3FF48880 ᆺ‫؀‬ + SENS_SAR_TOUCH_OUT4_REG + SENS_SAR_TOUCH_OUT5_REG SAR ADC1 ‫ ބ‬ADC2 ॥ᇅ 0x3FF4882C ‫؀‬/ཿ + SAR ADC ॥ᇅ࠷թఖ + SENS_SAR_START_FORCE_REG SAR ADC1 ඔऌაҐဢ॥ᇅ 0x3FF48800 ‫؀‬/ཿ + SAR ADC1 ٠໙॥ᇅఖ SAR ADC1 ሇߐ॥ᇅაሑ෿ 0x3FF48854 ᆺ‫؀‬ + SENS_SAR_READ_CTRL_REG + SENS_SAR_MEAS_START1_REG SAR ADC2 ඔऌაҐဢ॥ᇅ 0x3FF48890 ‫؀‬/ཿ + SAR ADC2 ॥ᇅ࠷թఖ SAR ADC2 ሇߐ॥ᇅაሑ෿ 0x3FF48894 ᆺ‫؀‬ + SENS_SAR_READ_CTRL2_REG + SENS_SAR_MEAS_START2_REG ULP ླྀԩ৘ఖ֥ඤ૤ᇛ௹ 0x3FF48818 ‫؀‬/ཿ + ULP ླྀԩ৘ఖ஥ᇂ࠷թఖ + SENS_ULP_CP_SLEEP_CYC0_REG + ܵ࢖කࡨ஥ᇂ࠷թఖ + +ুᶈྐ༏॓࠯ 585 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + +SENS_SAR_ATTEN1_REG ૄ۱ܵ࢖֥ 2 ໊කࡨ 0x3FF48834 ‫؀‬/ཿ +SENS_SAR_ATTEN2_REG ૄ۱ܵ࢖֥ 2 ໊කࡨ 0x3FF48838 ‫؀‬/ཿ +DAC ॥ᇅ࠷թఖ +SENS_SAR_DAC_CTRL1_REG DAC ॥ᇅ 0x3FF48898 ‫؀‬/ཿ +SENS_SAR_DAC_CTRL2_REG DAC ൻԛ॥ᇅ 0x3FF4889C ‫؀‬/ཿ + +29.6.2 ຓຶሹཌ + +଀ӫ ૭ඍ ֹᆶ ٠໙ٚൔ + +SAR ADC1 ‫ ބ‬ADC2 ๙Ⴈ஥ᇂ࠷թఖ + +APB_SARADC_CTRL_REG SAR ADC ๙Ⴈ஥ᇂ 0x60002610 ‫؀‬/ཿ + 0x60002614 ‫؀‬/ཿ +APB_SARADC_CTRL2_REG SAR ADC ๙Ⴈ஥ᇂ 0x60002618 ‫؀‬/ཿ + +APB_SARADC_FSM_REG SAR ADC FSM Ґဢᇛ௹஥ᇂ + +SAR ADC1 ဢൔі࠷թఖ + +APB_SARADC_SAR1_PATT_TAB1_REG ဢൔі 0 - 3 0x6000261C ‫؀‬/ཿ + 0x60002620 ‫؀‬/ཿ +APB_SARADC_SAR1_PATT_TAB2_REG ဢൔі 4 - 7 0x60002624 ‫؀‬/ཿ + 0x60002628 ‫؀‬/ཿ +APB_SARADC_SAR1_PATT_TAB3_REG ဢൔі 8 - 11 + +APB_SARADC_SAR1_PATT_TAB4_REG ဢൔі 12 - 15 + +SAR ADC2 ဢൔі࠷թఖ + +APB_SARADC_SAR2_PATT_TAB1_REG ဢൔі 0 - 3 0x6000262C ‫؀‬/ཿ + 0x60002630 ‫؀‬/ཿ +APB_SARADC_SAR2_PATT_TAB2_REG ဢൔі 4 - 7 0x60002634 ‫؀‬/ཿ + 0x60002638 ‫؀‬/ཿ +APB_SARADC_SAR2_PATT_TAB3_REG ဢൔі 8 - 11 + +APB_SARADC_SAR2_PATT_TAB4_REG ဢൔі 12 - 15 + +29.6.3 RTC I/O + +Ⴕܱ RTC I/O ֥ཌྷܱ࠷թఖਙіđ౨ҕ࡮ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔᅣࢫᇏ࠷թఖਙі֥ଽಸb + +ুᶈྐ༏॓࠯ 586 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + +29.7 ࠷թఖ + +29.7.1 Ԯ‫ۋ‬ఖ + +Чཬࢫও‫ݼ‬ᇏֹ֥ᆶनູཌྷؓႿ (RTC ࠎֹᆶ + 0x0800) ֹ֥ᆶொ၍ਈčཌྷֹؓᆶĎbRTC ࠎֹᆶ࡮ᅣࢫ 1 ༢๤ +‫ބ‬թԥఖ ᇏ֥і 1-6 ຓഡֹᆶ႘ഝb࠷թఖधֹؓᆶ࡮ᅣࢫ 29.6.1 Ԯ‫ۋ‬ఖb + + Register 29.1. SENS_SAR_READ_CTRL_REG (0x0000) + + (reserved) SENSS_SENARS1_S_DAART1A__DINIGV_FORCE (reserved) SENS_SAR1_SAMPLE_BIT SENS_SAR1_SAMPLE_CYCLE SENS_SAR1_CLK_DIV + +31 29 28 27 26 18 17 16 15 87 0 + +0 0 00 00 0 0 0 0 0 0 0 0 3 9 2 Reset + + SENS_SAR1_DATA_INV ّሇ SAR ADC1 ඔऌbč‫؀‬/ཿĎ + SENS_SAR1_DIG_FORCE 1ğSAR ADC1 Ⴎ DIG ADC1 CTR ॥ᇅĠ0ğSAR ADC1 Ⴎ RTC ADC1 + + CTRL ॥ᇅbč‫؀‬/ཿĎ + SENS_SAR1_SAMPLE_BIT SAR ADC1 ໊֥ॺđ00ğ9 ໊Ġ01ğ10 ໊Ġ10ğ11 ໊Ġ11ğ12 ໊bč‫؀‬/ཿĎ + SENS_SAR1_SAMPLE_CYCLE SAR ADC1 ֥Ґဢᇛ௹bč‫؀‬/ཿĎ + SENS_SAR1_CLK_DIV ൈᇒ‫ٳ‬௔ఖbč‫؀‬/ཿĎ + + Register 29.2. SENS_ULP_CP_SLEEP_CYC0_REG (0x0018) 0 + +31 Reset + + 200 + + SENS_ULP_CP_SLEEP_CYC0_REG ULP ླྀԩ৘ఖ࠹ൈఖ֥ඤ૤ᇛ௹bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 587 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.3. SENS_SAR_START_FORCE_REG (0x002c) + + (reserved) SENSS_SENARS1_S_SATRO2P_STOP SENS_PC_INIT (reservSeEdN) SS_UENLPS__CUPLP_SS_CTEANPR_STF_O_STRAORCPS2EE__PNSWTSA_DRSESATT_ER_TN2CO_SCEP_TNSA_TRES2SE_TBNIST__SWAIDRT1H_BIT_WIDTH + +31 24 23 22 21 11 10 9 8 7 543 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Reset + + SENS_SAR1_STOP ๔ᆸ SAR ADC1 ֥ሇߐbč‫؀‬/ཿĎ + SENS_SAR2_STOP ๔ᆸ SAR ADC2 ֥ሇߐbč‫؀‬/ཿĎ + SENS_PC_INIT ULP ླྀԩ৘ఖ֥Ԛ൓߄ PC bč‫؀‬/ཿĎ + SENS_ULP_CP_START_TOP 1ğఓ‫ ׮‬ULP ླྀԩ৘ఖđࣇᄝ reg_ulp_cp_force_start_top = 1 ൈႵ + + ིbč‫؀‬/ཿĎ + SENS_ULP_CP_FORCE_START_TOP 1ğULP ླྀԩ৘ఖႮೈࡱఓ‫׮‬Ġ0ğULP ླྀԩ৘ఖႮ࠹ൈఖఓ + + ‫׮‬bč‫؀‬/ཿĎ + SENS_SAR2_PWDET_CCT SAR2_PWDET_CCTđPA ‫ࡓੱۿ‬ҩఖ֥‫׈‬ಸ‫ཾט‬bč‫؀‬/ཿĎ + SENS_SAR2_EN_TEST SAR2_EN_TESTđࣇᄝ reg_sar2_dig_force = 0 ൈႵིbč‫؀‬/ཿĎ + SENS_SAR2_BIT_WIDTH SAR ADC2 ໊֥ॺđ00ğ9 ໊Ġ01ğ10 ໊Ġ10ğ11 ໊Ġ11ğ12 ໊bč‫؀‬/ཿĎ + SENS_SAR1_BIT_WIDTH SAR ADC1 ໊֥ॺđ00ğ9 ໊Ġ01ğ10 ໊Ġ10ğ11 ໊Ġ11ğ12 ໊bč‫؀‬/ཿĎ + + Register 29.4. SENS_SAR_ATTEN1_REG (0x0034) + +31 0 + + 0x0FFFFFFFF Reset + + SENS_SAR_ATTEN1_REG ૄ۱ܵ࢖֥කࡨđ11ğ1 dBĠ10ğ6 dBĠ01ğ3 dBĠ00ğ0 dBb[1:0] Ⴈ + Ⴟ૭ඍ ADC1_CH0a[3:2] ႨႿ૭ඍ ADC1_CH1đၛՎো๷bč‫؀‬/ཿĎ + + Register 29.5. SENS_SAR_ATTEN2_REG (0x0038) + +31 0 + + 0x0FFFFFFFF Reset + + SENS_SAR_ATTEN2_REG ૄ۱ܵ࢖֥කࡨđ11ğ1 dBĠ10ğ6 dBĠ01ğ3 dBĠ00ğ0 dBb[1:0] Ⴈ + Ⴟ૭ඍ ADC2_CH0a[3:2] ႨႿ૭ඍ ADC1_CH2đၛՎো๷bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 588 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.6. SENS_SAR_MEAS_START1_REG (0x0054) + + SENS_SAR1_EN_PAD_FORCE SENS_SAR1_EN_PAD SENSS_MENESAS_SME1N_ESSA_TSMA1R_ETSA_TSFA1OR_RTD_COSENAER_SAR SENS_MEAS1_DATA_SAR + +31 30 19 18 17 16 15 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SENS_SAR1_EN_PAD_FORCE 1ğSAR ADC1 ܵ࢖൐ି໊๭Ⴎೈࡱ॥ᇅĠ0ğႮ ULP ླྀԩ৘ఖ॥ + ᇅbč‫؀‬/ཿĎ + + SENS_SAR1_EN_PAD SAR ADC1 ܵ࢖൐ି໊๭đࣇ֒ reg_sar1_en_pad_force = 1 ൈႵིbč‫؀‬/ཿĎ + + SENS_MEAS1_START_FORCE 1ğSAR ADC1 ॥ᇅఖ (RTC) Ⴎೈࡱఓ‫׮‬Ġ0ğႮ ULP ླྀԩ৘ఖఓ + ‫׮‬bč‫؀‬/ཿĎ + + SENS_MEAS1_START_SAR SAR ADC1 ॥ᇅఖ (RTC) ष൓ሇߐđࣇ֒ reg_meas1_start_force = 1 + ൈႵིbč‫؀‬/ཿĎ + + SENS_MEAS1_DONE_SAR SAR ADC1 սіሇߐၘປӮbčᆺ‫؀‬Ď + + SENS_MEAS1_DATA_SAR SAR ADC1 ඔऌbčᆺ‫؀‬Ď + + Register 29.7. SENS_SAR_TOUCH_CTRL1_REG (0x0058) + + (reserved) SENSS_HENASLSL__XEPPNHDSSA__HTESONEA_LUSFL_CO_THFOR_OCUORECUCHTE__O1EUNT_SELSENS_TOUCH_XPD_WAIT SENS_TOUCH_MEAS_DELAY + 0x01000 +31 28 27 26 25 24 23 16 15 0 + +0 0 0 00 0 1 0 0x004 Reset + + SENS_HALL_PHASE_FORCE 1ğHALL PHASE Ⴎೈࡱ॥ᇅĠ0ğႮ ULP ླྀԩ৘ఖ֥ FSM ॥ + ᇅbč‫؀‬/ཿĎ + + SENS_XPD_HALL_FORCE 1ğXPD HALL Ⴎೈࡱ॥ᇅĠ0ğႮ ULP ླྀԩ৘ఖ֥ FSM ॥ᇅbč‫؀‬/ཿĎ + + SENS_TOUCH_OUT_1EN 1ğ֒ SET1 ᇏႵܵ࢖൳֞Ԩஷđߒྜᇏ؎ӁളĠ0ğ֒ SET1 & SET2 ᇏ + नႵܵ࢖൳֞Ԩஷđߒྜᇏ؎Ӂളbč‫؀‬/ཿĎ + + SENS_TOUCH_OUT_SEL 1ğ֒࠹ඔఖඔᆴնႿᚐᆴđᄵ൪‫࢖ܵھ‬൳֞ԨஷĠ0ğ֒࠹ඔఖඔᆴཬ + Ⴟᚐᆴđᄵ൪‫࢖ܵھ‬൳֞Ԩஷbč‫؀‬/ཿĎ + + SENS_TOUCH_XPD_WAIT (8 MHz ᇛ௹) TOUCH_START ‫ ބ‬TOUCH_XPD ᆭࡗ֥֩րൈࡗčb‫؀‬/ཿĎ + + SENS_TOUCH_MEAS_DELAY (8 MHz ᇛ௹) ҩਈӻ࿃ൈӉbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 589 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.8. SENS_SAR_TOUCH_THRES1_REG (0x005c) + + SENS_TOUCH_OUT_TH0 SENS_TOUCH_OUT_TH1 + +31 16 15 0 + + 0x00000 0x00000 Reset + + SENS_TOUCH_OUT_TH0 ܵ࢖ 0 ֥ᚐᆴbč‫؀‬/ཿĎ + SENS_TOUCH_OUT_TH1 ܵ࢖ 1 ֥ᚐᆴbč‫؀‬/ཿĎ + + Register 29.9. SENS_SAR_TOUCH_THRES2_REG (0x0060) + + SENS_TOUCH_OUT_TH2 SENS_TOUCH_OUT_TH3 + +31 16 15 0 + + 0x00000 0x00000 Reset + + SENS_TOUCH_OUT_TH2 ܵ࢖ 2 ֥ᚐᆴbč‫؀‬/ཿĎ + SENS_TOUCH_OUT_TH3 ܵ࢖ 3 ֥ᚐᆴbč‫؀‬/ཿĎ + + Register 29.10. SENS_SAR_TOUCH_THRES3_REG (0x0064) + + SENS_TOUCH_OUT_TH4 SENS_TOUCH_OUT_TH5 + +31 16 15 0 + + 0x00000 0x00000 Reset + + SENS_TOUCH_OUT_TH4 ܵ࢖ 4 ֥ᚐᆴbč‫؀‬/ཿĎ + SENS_TOUCH_OUT_TH5 ܵ࢖ 5 ֥ᚐᆴbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 590 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.11. SENS_SAR_TOUCH_THRES4_REG (0x0068) + + SENS_TOUCH_OUT_TH6 SENS_TOUCH_OUT_TH7 + +31 16 15 0 + + 0x00000 0x00000 Reset + + SENS_TOUCH_OUT_TH6 ܵ࢖ 6 ֥ᚐᆴbč‫؀‬/ཿĎ + SENS_TOUCH_OUT_TH7 ܵ࢖ 7 ֥ᚐᆴbč‫؀‬/ཿĎ + + Register 29.12. SENS_SAR_TOUCH_THRES5_REG (0x006c) + + SENS_TOUCH_OUT_TH8 SENS_TOUCH_OUT_TH9 + +31 16 15 0 + + 0x00000 0x00000 Reset + + SENS_TOUCH_OUT_TH8 ܵ࢖ 8 ֥ᚐᆴbč‫؀‬/ཿĎ + SENS_TOUCH_OUT_TH9 ܵ࢖ 9 ֥ᚐᆴbč‫؀‬/ཿĎ + + Register 29.13. SENS_SAR_TOUCH_OUT1_REG (0x0070) + + SENS_TOUCH_MEAS_OUT0 SENS_TOUCH_MEAS_OUT1 + +31 16 15 0 + + 0x00000 0x00000 Reset + + SENS_TOUCH_MEAS_OUT0 ܵ࢖ 0 ֥࠹ඔఖbčᆺ‫؀‬Ď + SENS_TOUCH_MEAS_OUT1 ܵ࢖ 1 ֥࠹ඔఖbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 591 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.14. SENS_SAR_TOUCH_OUT2_REG (0x0074) + + SENS_TOUCH_MEAS_OUT2 SENS_TOUCH_MEAS_OUT3 + +31 16 15 0 + + 0x00000 0x00000 Reset + + SENS_TOUCH_MEAS_OUT2 ܵ࢖ 2 ֥࠹ඔఖbčᆺ‫؀‬Ď + SENS_TOUCH_MEAS_OUT3 ܵ࢖ 3 ֥࠹ඔఖbčᆺ‫؀‬Ď + + Register 29.15. SENS_SAR_TOUCH_OUT3_REG (0x0078) + + SENS_TOUCH_MEAS_OUT4 SENS_TOUCH_MEAS_OUT5 + +31 16 15 0 + + 0x00000 0x00000 Reset + + SENS_TOUCH_MEAS_OUT4 ܵ࢖ 4 ֥࠹ඔఖbčᆺ‫؀‬Ď + SENS_TOUCH_MEAS_OUT5 ܵ࢖ 5 ֥࠹ඔఖbčᆺ‫؀‬Ď + + Register 29.16. SENS_SAR_TOUCH_OUT4_REG (0x007c) + + SENS_TOUCH_MEAS_OUT6 SENS_TOUCH_MEAS_OUT7 + +31 16 15 0 + + 0x00000 0x00000 Reset + + SENS_TOUCH_MEAS_OUT6 ܵ࢖ 6 ֥࠹ඔఖbčᆺ‫؀‬Ď + SENS_TOUCH_MEAS_OUT7 ܵ࢖ 7 ֥࠹ඔఖbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 592 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.17. SENS_SAR_TOUCH_OUT5_REG (0x0080) + + SENS_TOUCH_MEAS_OUT8 SENS_TOUCH_MEAS_OUT9 + +31 16 15 0 + + 0x00000 0x00000 Reset + + SENS_TOUCH_MEAS_OUT8 ܵ࢖ 8 ֥࠹ඔఖbčᆺ‫؀‬Ď + SENS_TOUCH_MEAS_OUT9 ܵ࢖ 9 ֥࠹ඔఖbčᆺ‫؀‬Ď + + Register 29.18. SENS_SAR_TOUCH_CTRL2_REG (0x0084) + + (reservSeEdN) S_TOUCH_MEAS_EN_CLR SENS_TOUCH_SLEEP_CYCLES SENSS_TEONUSS_CTEHON_USSS_CTTEAHONR_USTS_C_TTFAHOOR_URTSC_CTEAHENR_TM_EFASSM__DEONNE SENS_TOUCH_MEAS_EN + 0x00100 +31 30 29 14 13 12 11 10 9 0 + +00 0010 0x000 Reset + + SENS_TOUCH_MEAS_EN_CLR ౢਬ reg_touch_meas_en bčᆺཿĎ + SENS_TOUCH_SLEEP_CYCLES ࠹ൈఖ֥ඤ૤ᇛ௹bč‫؀‬/ཿĎ + SENS_TOUCH_START_FORCE 1ğԨଃ FSM Ⴎೈࡱఓ‫׮‬Ġ0ğႮ࠹ൈఖఓ‫׮‬bč‫؀‬/ཿĎ + SENS_TOUCH_START_EN 1ğఓ‫׮‬Ԩଃ FSMđ֒ reg_touch_start_force ഡᇂൈႵིbč‫؀‬/ཿĎ + SENS_TOUCH_START_FSM_EN 1ğTOUCH_START & TOUCH_XPD ႮԨଃ FSM ॥ᇅĠ0ğႮ࠷ + + թఖ॥ᇅbč‫؀‬/ཿĎ + SENS_TOUCH_MEAS_DONE Ⴎ FSM ഡᇂđսіԨଃҩਈၘປӮbčᆺ‫؀‬Ď + SENS_TOUCH_MEAS_EN 10 ໊࠷թఖđսіऎุ൳֞Ԩஷ֥ܵ࢖bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 593 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.19. SENS_SAR_TOUCH_ENABLE_REG (0x008c) + + (reserved) SENS_TOUCH_PAD_OUTEN1 SENS_TOUCH_PAD_OUTEN2 SENS_TOUCH_PAD_WORKEN + +31 30 29 20 19 10 9 0 + +00 0x3FF 0x3FF 0x3FF Reset + +SENS_TOUCH_PAD_OUTEN1 ‫ק‬ၬ SET1 ߒྜᇏ؎ളӮ໊֥๭đࣇ֒ SET1 ᇏᇀഒႵ 1 ۱ܵ࢖൳ + ֞ԨஷđҌ൪ SET1 ൳֞Ԩஷbč‫؀‬/ཿĎ + +SENS_TOUCH_PAD_OUTEN2 ‫ק‬ၬ SET2 ߒྜᇏ؎ളӮ໊֥๭đࣇ֒ SET2 ᇏᇀഒႵ 1 ۱ܵ࢖൳ + ֞ԨஷđҌ൪ SET2 ൳֞Ԩஷbč‫؀‬/ཿĎ + +SENS_TOUCH_PAD_WORKEN ‫ק‬ၬҩਈႵི SET ໊֥๭bč‫؀‬/ཿĎ + + Register 29.20. SENS_SAR_READ_CTRL2_REG (0x0090) + + (reservedS) ENSS_SENARS2_S_DAART2A__DINIGV_FORCE (reserved) SENS_SAR2_SAMPLE_BIT SENS_SAR2_SAMPLE_CYCLE SENS_SAR2_CLK_DIV + +31 30 29 28 27 18 17 16 15 87 0 + +0 00 00 0 0 0 0 0 0 0 0 0 3 9 2 Reset + +SENS_SAR2_DATA_INV ّሇ SAR ADC2 ඔऌbč‫؀‬/ཿĎ +SENS_SAR2_DIG_FORCE 1ğSAR ADC2 Ⴎ DIG ADC2 CTRL ࠇ PWDET CTRL ॥ᇅĠ0ğႮ RTC + + ADC2 CTRL ॥ᇅbč‫؀‬/ཿĎ +SENS_SAR2_SAMPLE_BIT SAR ADC2 ໊֥ॺ, 00ğ9 ໊Ġ01ğ10 ໊Ġ10ğ11 ໊Ġ11ğ12 ໊bč‫؀‬/ཿĎ +SENS_SAR2_SAMPLE_CYCLE SAR ADC2 ֥Ґဢᇛ௹bč‫؀‬/ཿĎ +SENS_SAR2_CLK_DIV ൈᇒ‫ٳ‬௔ఖbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 594 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.21. SENS_SAR_MEAS_START2_REG (0x0094) + + SENS_SAR2_EN_PAD_FORCE SENS_SAR2_EN_PAD SENSS_MENESAS_SME2N_ESSA_TSMA2R_ETSA_TSFA2OR_RTD_COSENAER_SAR SENS_MEAS2_DATA_SAR + +31 30 19 18 17 16 15 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SENS_SAR2_EN_PAD_FORCE 1ğSAR ADC2 ܵ࢖൐ି໊๭Ⴎೈࡱ॥ᇅĠ0ğႮ ULP ླྀԩ৘ఖ॥ + ᇅbč‫؀‬/ཿĎ + + SENS_SAR2_EN_PAD SAR ADC2 ܵ࢖൐ି໊๭đࣇ֒ reg_sar2_en_pad_force = 1 ൈႵིbč‫؀‬/ཿĎ + + SENS_MEAS2_START_FORCE 1: SAR ADC2 ॥ᇅఖ (RTC) Ⴎೈࡱఓ‫׮‬Ġ0ğႮ ULP ླྀ॥ᇅఖఓ + ‫׮‬bč‫؀‬/ཿĎ + + SENS_MEAS2_START_SAR SAR ADC2 ॥ᇅఖ (RTC) ष൓ሇߐđࣇ֒ reg_meas2_start_force = 1 + ൈႵིbč‫؀‬/ཿĎ + + SENS_MEAS2_DONE_SAR սі SAR ADC2 ሇߐၘປӮbčᆺ‫؀‬Ď + + SENS_MEAS2_DATA_SAR SAR ADC2 ඔऌbčᆺ‫؀‬Ď + + Register 29.22. SENS_SAR_DAC_CTRL1_REG (0x0098) + + (reserved) SENSS_DENASCS__DECNALSCKS___DEICNNALVSCK___DFCOALCRK_C_FDEOI_GRH_(CrIFGeEOsH_eRLrvCOeEWd) _TONE_EN _FSTEP + SENS_SW SENS_SW + +31 26 25 24 23 22 21 17 16 15 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SENS_DAC_CLK_INV 1ğّሇ PDAC_CLKĠ0Ġ҂ࣉྛّሇbč‫؀‬/ཿĎ + SENS_DAC_CLK_FORCE_HIGH PDAC_CLK ఼ᇅ౼ 1bč‫؀‬/ཿĎ + SENS_DAC_CLK_FORCE_LOW PDAC_CLK ఼ᇅ౼ 0bč‫؀‬/ཿĎ + SENS_DAC_DIG_FORCE 1ğDAC1 & DAC2 ൐Ⴈ DMAĠ0ğDAC1 & DAC2 ҂൐Ⴈ DMA bč‫؀‬/ཿĎ + SENS_SW_TONE_EN 1ğ൐ି CW ‫ؿ‬ളఖĠ0ğ࣌Ⴈ CW ‫ؿ‬ളఖbč‫؀‬/ཿĎ + SENS_SW_FSTEP CW ‫ؿ‬ളఖ֥௔ੱࢨᄁđॖႨႿ‫ࢫט‬ѯྙ௔ੱbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 595 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.23. SENS_SAR_DAC_CTRL2_REG (0x009c) + + (reserved) SENSS_DENASC__DCSAWEC_N_ESCN_W2D_AECNS_1EINNVS2_DACS_EINNVS1_DACS_ESNCSA_LDEA2C_SCALE1 SENS_DAC_DC2 SENS_DAC_DC1 + +31 26 25 24 23 22 21 20 19 18 17 16 15 87 0 + +0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SENS_DAC_CW_EN2 1ğ࿊ᄴ CW ‫ؿ‬ളఖູ PDAC2_DAC[7:0] ֥ඔऌটჷĠ0ğ࿊ᄴ࠷թఖ + reg_pdac2_dac[7:0] ູ PDAC2_DAC[7:0] ֥ඔऌটჷbč‫؀‬/ཿĎ + + SENS_DAC_CW_EN1 1ğ࿊ᄴ CW ‫ؿ‬ളఖູ PDAC1_DAC[7:0] ֥ඔऌটჷĠ0ğ࿊ᄴ࠷թఖ + reg_pdac1_dac[7:0] ູ PDAC1_DAC[7:0] ֥ඔऌটჷbč‫؀‬/ཿĎ + + SENS_DAC_INV2 DAC2đ00ğ҂ّሇ಩‫໊ޅ‬Ġ01ğّሇ෮Ⴕ໊ğ10ğّሇ MSBĠ11ğّሇԢ MSB + ຓ֥෮Ⴕ໊bč‫؀‬/ཿĎ + + SENS_DAC_INV1 DAC1đ00ğ҂ّሇ಩‫໊ޅ‬Ġ01ğّሇ෮Ⴕ໊ğ10ğّሇ MSBĠ11ğّሇԢ MSB + ຓ֥෮Ⴕ໊bč‫؀‬/ཿĎ + + SENS_DAC_SCALE2 DAC2đ00ğ1 ПĠ01ğ1/2 ПĠ10ğ1/4 ПĠ11ğ1/8 Пbč‫؀‬/ཿĎ + + SENS_DAC_SCALE1 DAC1đ00ğ1 ПĠ01ğ1/2 ПĠ10ğ1/4 ПĠ11ğ1/8 Пbč‫؀‬/ཿĎ + + SENS_DAC_DC2 DAC2 CW ‫ؿ‬ളఖ֥ᆰੀொ၍bč‫؀‬/ཿĎ + + SENS_DAC_DC1 DAC1 CW ‫ؿ‬ളఖ֥ᆰੀொ၍bč‫؀‬/ཿĎ + +29.7.2 ۚࠩຓຶሹཌ + +Чཬࢫও‫ݼ‬ᇏֹ֥ᆶनູཌྷؓႿ 0x6000_2600 ֹ֥ᆶொ၍ਈčࣜ AHB ሹཌ٠໙Ďb࠷թఖधֹؓᆶ࡮ᅣࢫ +29.6.2 ຓຶሹཌb + +ুᶈྐ༏॓࠯ 596 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.24. APB_SARADC_CTRL_REG (0x10) + + (reserved) APB_SAAPRBA_SADAPCRB_A_DSADAAPCTRBA_A__DSTDAOACTR_A_IA_S2SDSAACRAR2_P_S_SBPAEA_RSLT1TA__RPPAA_TDCTCL__EPSA_ACRRL2E_AAPRPATBT__SLAERNADC_SAR1_PATT_LEN APB_SARADC_SAR_CLKA_PDBIV_SAAPRBA_SDACAR_PASBDA_CRS__ACSARALPAKRBD___GSCSAEA_APWLTRBEOA_DSARDAPKCRB__MA_SSDAOACRDR2_EAS_DMTACUR_XTSTART_FORCE + +31 27 26 25 24 23 22 19 18 15 14 76 54 32 1 0 + +0 0 0 0 00 0 0 0 15 15 4 1 0 0 0 0 0 Reset + + APB_SARADC_DATA_TO_I2S 1ğI2S (DMA) ൻೆඔऌটሱ SAR ADCĠ0ğI2S ൻೆඔऌটሱ GPIO + इᆔbč‫؀‬/ཿĎ + + APB_SARADC_DATA_SAR_SEL 1ğsar_sel ࡼႮ 16 ໊ൻԛඔऌ֥ MSB щ઒đՎൈ‫ٳ‬яੱ҂ႋն + Ⴟ 11 ໊Ġ0ğՎൈ SAR ADC ‫ٳ‬яੱႋູ 12 ໊bč‫؀‬/ཿĎ + + APB_SARADC_SAR2_PATT_P_CLEAR DIG ADC2 CTRL ֥ဢൔіᆷᆌౢਬbč‫؀‬/ཿĎ + APB_SARADC_SAR1_PATT_P_CLEAR DIG ADC1 CTRL ֥ဢൔіᆷᆌౢਬbč‫؀‬/ཿĎ + APB_SARADC_SAR2_PATT_LEN SAR ADC2đ0 - 15 սіဢൔі֥ 1 - 16 ໊bč‫؀‬/ཿĎ + APB_SARADC_SAR1_PATT_LEN SAR ADC1đ0 - 15 սіဢൔі֥ 1 - 16 ໊bč‫؀‬/ཿĎ + APB_SARADC_SAR_CLK_DIV SAR ൈᇒ‫ٳ‬௔ఖbč‫؀‬/ཿĎ + APB_SARADC_SAR_CLK_GATED Ќ਽໊đ౨Ԛ൓߄ູ 0b1 bč‫؀‬/ཿĎ + APB_SARADC_SAR_SEL 0ğSAR1Ġ1ğSAR2đ‫ھ‬ഡᇂൡႨֆ๙֡ SAR ଆൔbč‫؀‬/ཿĎ + APB_SARADC_WORK_MODE 0ğֆ๙֡ଆൔĠ1ğච๙֡ଆൔĠ2ğࢌูଆൔbč‫؀‬/ཿĎ + APB_SARADC_SAR2_MUX 1ğSAR ADC2 Ⴎ DIG ADC2 CTRL ॥ᇅĠ0ğSAR ADC2 Ⴎ PWDET + + CTRL ॥ᇅbč‫؀‬/ཿĎ + APB_SARADC_START Ќ਽໊đ౨Ԛ൓߄ູ 0 bč‫؀‬/ཿĎ + APB_SARADC_START_FORCE Ќ਽໊đ౨Ԛ൓߄ູ 0 bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 597 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.25. APB_SARADC_CTRL2_REG (0x14) + + (reserved) APB_SAAPRBA_SDACR_ASDACR2_S_IANRV1_INVAPB_SARADC_MAX_MEAASP_BN_USMARADC_MEAS_NUM_LIMIT + +31 11 10 9 8 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 255 0 Reset + + APB_SARADC_SAR2_INV 1ğൻೆ DIG ADC2 CTRL ֥ඔऌФّሇĠ0ğൻೆ DIG ADC2 CTRL ֥ + ඔऌໃФّሇbč‫؀‬/ཿĎ + + APB_SARADC_SAR1_INV 1ğൻೆ DIG ADC1 CTRL ֥ඔऌФّሇĠ0ğൻೆ DIG ADC1 CTRL ֥ + ඔऌໃФّሇbč‫؀‬/ཿĎ + + APB_SARADC_MAX_MEAS_NUM ቋնሇߐඔਈbč‫؀‬/ཿĎ + + APB_SARADC_MEAS_NUM_LIMIT Ќ਽໊đ౨Ԛ൓߄ູ 0b1 bč‫؀‬/ཿĎ + + Register 29.26. APB_SARADC_FSM_REG (0x18) + + APB_SARADC_SAMPLE_CYCLE (reserved) + +31 24 47 24 + + 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + APB_SARADC_SAMPLE_CYCLE Ґဢᇛ௹bč‫؀‬/ཿĎ + + Register 29.27. APB_SARADC_SAR1_PATT_TAB1_REG (0x1C) + +31 0 + + 0x00F0F0F0F Reset + + APB_SARADC_SAR1_PATT_TAB1_REG սі SAR ADC1 ֥ဢൔі 0 - 3đૄཛᅝႨ 1 ሳࢫğ + [31:28] pattern0_channela[27:26] pattern0_bit_widtha[25:24] pattern0_attenuationa[23:20] pat- + tern1_channelđ֩bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 598 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.28. APB_SARADC_SAR1_PATT_TAB2_REG (0x20) + +31 0 + + 0x00F0F0F0F Reset + +APB_SARADC_SAR1_PATT_TAB2_REG սі SAR ADC1 ֥ဢൔі 4 - 7đૄཛᅝႨ 1 ሳࢫğ + [31:28] pattern4_channela[27:26] pattern4_bit_widtha[25:24]bpattern4_attenuationa[23:20] pat- + tern5_channelđ֩bč‫؀‬/ཿĎ + + Register 29.29. APB_SARADC_SAR1_PATT_TAB3_REG (0x24) + +31 0 + + 0x00F0F0F0F Reset + +APB_SARADC_SAR1_PATT_TAB3_REG սі SAR ADC1 ֥ဢൔі 8 - 11đૄཛᅝႨ 1 ሳࢫğ + [31:28] pattern8_channela[27:26] pattern8_bit_widtha[25:24] pattern8_attenuationa[23:20] pat- + tern9_channelđ֩bč‫؀‬/ཿĎ + + Register 29.30. APB_SARADC_SAR1_PATT_TAB4_REG (0x28) + +31 0 + + 0x00F0F0F0F Reset + +APB_SARADC_SAR1_PATT_TAB4_REG սі SAR ADC1 ֥ဢൔі 12 - 15đૄཛᅝႨ 1 ሳࢫğ + [31:28] pattern12_channela[27:26] pattern12_bit_widtha[25:24] pattern12_attenuationa[23:20] + pattern13_channelđ֩bč‫؀‬/ཿĎ + + Register 29.31. APB_SARADC_SAR2_PATT_TAB1_REG (0x2C) + +31 0 + + 0x00F0F0F0F Reset + +APB_SARADC_SAR2_PATT_TAB1_REG սі SAR ADC2 ֥ဢൔі 0 - 3đૄཛᅝႨ 1 ሳࢫğ + [31:28] pattern0_channela[27:26] pattern0_bit_widtha[25:24] pattern0_attenuationa[23:20] pat- + tern1_channelđ֩bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 599 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ + + Register 29.32. APB_SARADC_SAR2_PATT_TAB2_REG (0x30) + +31 0 + + 0x00F0F0F0F Reset + +APB_SARADC_SAR2_PATT_TAB2_REG սі SAR ADC2 ֥ဢൔі 4 - 7đૄཛᅝႨ 1 ሳࢫğ + [31:28] pattern4_channela[27:26] pattern4_bit_widtha[25:24] pattern4_attenuationa[23:20] pat- + tern5_channelđ֩bč‫؀‬/ཿĎ + + Register 29.33. APB_SARADC_SAR2_PATT_TAB3_REG (0x34) + +31 0 + + 0x00F0F0F0F Reset + +APB_SARADC_SAR2_PATT_TAB3_REG սі SAR ADC2 ֥ဢൔі 8 - 11đૄཛᅝႨ 1 ሳࢫğ + [31:28] pattern8_channela[27:26] pattern8_bit_widtha[25:24] pattern8_attenuationa[23:20] pat- + tern9_channelđ֩bč‫؀‬/ཿĎ + + Register 29.34. APB_SARADC_SAR2_PATT_TAB4_REG (0x38) + +31 0 + + 0x00F0F0F0F Reset + +APB_SARADC_SAR2_PATT_TAB4_REG սі SAR ADC2 ֥ဢൔі 12 - 15đૄཛᅝႨ 1 ሳࢫğ + [31:28] pattern12_channela[27:26] pattern12_bit_widtha[25:24] pattern12_attenuationa[23:20] + pattern13_channelđ֩bč‫؀‬/ཿĎ + +29.7.3 RTC I/O + +Ⴕܱ RTC I/O ֥ཌྷܱ࠷թఖđ౨ҕ࡮ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔᅣࢫᇏ࠷թఖ֥ଽಸb + +ুᶈྐ༏॓࠯ 600 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +30.1 ‫ۀ‬ඍ + +ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP Coprocessor) ൞၂ᇕ‫ླྀ֥֮ࠞݻۿ‬ԩ৘ఖഡСđॖᄝᇶ༢๤ࠩྉோ (SoC) ༢๤ࣉೆ +Deep-sleep ሑ෿ൈЌӻഈ‫׈‬đᄍྸष‫ؿ‬ᆀ๙‫ݖ‬թԥᄝ RTC ᇏ֥ህႨӱ྽đ٠໙ຓຶഡСaଽ҆Ԯ‫ۋ‬ఖࠣ RTC +࠷թఖbULP ླྀԩ৘ఖ֥ᇶေႋႨӆࣟЇও၂ུླေᄝЌᆣቋ֮‫֥ݻۿ‬౦ঃ༯đ๙‫ݖ‬ຓ҆ࠃ‫࠹ࠇ׮‬ൈఖčࠇਆ +ᆀ࡙ႵĎߒྜ CPU ֥ႋႨb + +30.2 ᇶေหྟ + + • ॖ٠໙ቋ‫ ؟‬8 KB SRAM RTC ત෎ଽթđԥթᆷ਷‫ބ‬ඔऌ + • ҐႨ 8 MHz RTC_FAST_CLK ൈᇒ௔ੱ + • ᆦӻᆞӈଆൔ‫ ބ‬Deep-sleep ଆൔ + • ॖߒྜ CPU ࠇཟ CPU ‫ؿ‬ෂᇏ؎ + • ॖ٠໙ຓຶഡСaଽ҆Ԯ‫ۋ‬ఖࠣ RTC ࠷թఖ + • ҐႨ 4 ۱ 16 ໊๙Ⴈ࠷թఖ (R0 - R3)đࣉྛඔऌҠቔ‫ބ‬ଽթ٠໙ + • ҐႨ 1 ۱ 8 ໊ࢨ‫࠹؍‬ඔఖ࠷թఖ Stage_cntđॖ๙‫ ݖ‬ALU ᆷ਷ࣉྛҠቔѩႨႿ JUMP ᆷ਷ + + APB Bus + + bridge + + RTC Memory Arbiter RTC CNTL REG + I2C CTRL RTC IO REG + SARADC REG + TSENS CTRL RTC I2C REG + SAR CTRL + ULP RTC Timer + Coprocessor + ESP32 RTC + + ๭ 30­1. ULP ླྀԩ৘ఖࠎЧࡏ‫ܒ‬ + +ুᶈྐ༏॓࠯ 601 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +30.3 ‫ିۿ‬૭ඍ + +ULP ླྀԩ৘ఖ൞၂ᇕॖщӱႵཋሑ෿ࠏ (FSM)đॖᄝ CPU ࣉೆ Deep-sleep ሑ෿ൈ‫۽‬ቔbླྀԩ৘ఖᆦӻ҆‫ٳ‬๙ +Ⴈ CPU ᆷ਷đॖླྀᇹࣉྛ၂ུ‫گ‬ᄖઆࠠᄎෘbՎຓđߎᆦӻ၂ུห൹֥ RTC ॥ᇅაຓຶഡС॥ᇅᆷ਷bა +CPU ၂ဢđULP ླྀԩ৘ఖ္ॖ٠໙ 8 KB SRAM RTC ત෎ଽթb္ᆞၹೂՎđᆃॶଽթࣜӈФႨႿթԥ၂ུླྀ +ԩ৘ఖ‫ ބ‬CPU ֥๙Ⴈᆷ਷b + +ULP ླྀԩ৘ఖॖႮೈࡱӱ྽ࠇ႗ࡱ‫ק‬ൈఖᇛ௹ྟఓ‫׮‬đѩ๙‫ݖ‬ᆳྛ HALT ᆷ਷๔ᆸbླྀԩ৘ఖ֥‫ିۿ‬٤ӈ఼նđ +ॖၛ๙‫ݖ‬ଽᇂᆷ਷‫ ބ‬RTC ࠷թఖđ٠໙ RTC თᇏ֥ࠫެ෮ႵଆॶbULP ླྀԩ৘ఖॖᄝ‫؟ޓ‬ႋႨӆࣟᇏӮູ +CPU ֥Ⴕ৯Ҁԉđമᇀ౼ս CPUđหљ൞ᄝ၂ུؓ‫֥ۋૹޓݻۿ‬ႋႨᇏbULP ླྀԩ৘ఖ֥ࠎЧࡏ‫ܒ‬ॖ࡮๭ +30-1b + +30.4 ᆷ਷ࠢ + +ULP ླྀԩ৘ఖॖᆦӻ༯ਙᆷ਷ğ + +• ෘඔაઆࠠ - ALU + +• ࡆᄛაඔऌթԥ - LDaSTaREG_RD ࠣ REG_WR + +• ๋ሇᇀଖֹᆶ - JUMP + +• ܵ৘ӱ྽ᆳྛ - WAIT ‫ ބ‬HALT + +• ॥ᇅླྀԩ৘ఖ֥ඤ૤ᇛ௹ - SLEEP + +• ߒྜ CPU ࠣა SoC ๙ྐ - WAKE + +• ҩਈ - ADC + +• I²C ሹཌ๙ྐ - I2C_RD ‫ ބ‬I2C_WR + +ULP ླྀԩ৘ఖᆷ਷֥۬ൔॖ࡮๭ 30-2b + +31 28 27 0 + +OpCode Operands + + ๭ 30­2. ULP ླྀԩ৘ఖ֥ᆷ਷۬ൔ + +۴ऌ Operands ֥ഡᇂ҂๝đ๝၂۱ OpCode ॖؓႋ‫؟‬ᇕ҂๝ҠቔbбೂđALU ି‫ܔ‬ᆳྛ 10 ᇕ҂๝֥ෘඔ‫ބ‬આ +ࠠᄎෘđJUMP ္ॖᆳྛႵ่ࡱ๋ሇa໭่ࡱ๋ሇaध๋ؓሇࠣཌྷ๋ؓሇ֩‫؟‬ᇕྙൔ๋֥ሇb + +ULP ླྀԩ৘ఖ֥෮Ⴕᆷ਷न‫ ູקܥ‬32 ໊b๙‫ݖ‬ᆃ၂༢ਙᆷ਷đླྀԩ৘ఖӱ྽ࠧॖ֤֞ᆳྛbӱ྽ଽ֥҆ᆳྛ +नҐႨ 32 ໊࿙ᆶb‫ھ‬ӱ྽ऎุթԥᄝ 1 ॶህႨ֥ત෎ଽթ౵ (RTC_SLOW_MEM)đֹᆶٓຶູ 0x5000_0000 +֞ 0x5000_1FFF (8 KB)đؓᇶ CPU ॖ࡮b + +Ч໓ᇏ OpCode ֥۬ൔູ 4’dxđఃᇏ 4 սі 4 ໊ॺđ’d սі൅ࣉᇅđx սі OpCode ֥ᆴ (x: 0 ~ 15)b + +30.4.1 ALU ­ ෘඔაઆࠠᄎෘ + +ෘඔઆࠠֆჭ (ALU) ॖၛࣉྛෘඔ‫ބ‬આࠠᄎෘđؓའູླྀԩ৘ఖ࠷թఖᇏթԥ֥ඔᆴࠇᆷ਷ᇏթԥ֥৫ࠧ +ᆴb +ऎุॖၛᆦӻ֥ᄎෘো྘ೂ༯ğ + + • ෘඔ - ࡆ (ADD) ‫( ࡨބ‬SUB) + +ুᶈྐ༏॓࠯ 602 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + • આࠠ - ο໊ა (AND) ‫ބ‬ο໊ࠇ (OR) + • ၍໊ - ቐ၍ (LSH) ‫ބ‬Ⴗ၍ (RSH) + • ࠷թఖ‫ڮ‬ᆴ - ၍‫( ׮‬MOVE) + • ࠹ඔఖ࠷թఖҠቔ - STAGE_RSTaSTAGE_INC ‫ ބ‬STAGE_DEC +࣐ܵ OpCode ཌྷ๝, ֌ॖ๙‫ݖ‬ഡᇂླྀԩ৘ఖᆷ਷ [27:21] ໊đ࿊ᄴห‫֥ק‬ෘඔ‫ބ‬આࠠᄎෘb + +30.4.1.1 ؓ࠷թఖඔᆴ֥ᄎෘ + +31 28 27 25 24 21 543210 + + 4’d7 3’b0 ALU_sel Rsrc2Rsrc1 Rdst + + ๭ 30­3. ᆷ਷ো྘ ­ ؓ࠷թఖඔᆴ֥ ALU ᄎෘ + +ೂ๭ 30-3 ෮ൕđ֒ླྀԩ৘ఖᆷ਷ [27:25] ໊ഡᇂູ 3’b0 ൈđALU ࡼؓླྀԩ৘ఖ࠷թఖ R[0-3] ᇏթԥ֥ଽಸࣉ +ྛᄎෘđᄎෘো྘ᄵ౼थႿᆷ਷֥ ALU_sel [24:21] ໊đऎุഡᇂٚൔ࡮༯і 30-1b + +Operand ૭ඍ - ࡮๭ 30-3 +ALU_sel ALU ᄎෘো྘ +Rdst ࠷թఖ R[0-3]đଢѓֹᆶ࠷թఖ +Rsrc1 ࠷թఖ R[0-3]đჷֹᆶ࠷թఖ +Rsrc2 ࠷թఖ R[0-3]đჷֹᆶ࠷թఖ + + ALU_sel ᆷ਷ ᄎෘো྘ ૭ඍ + 0 ADD ࡆ + 1 SUB Rdst = Rsrc1 + Rsrc2 ࡨ + 2 AND Rdst = Rsrc1 - Rsrc2 ο໊ა + 3 OR Rdst = Rsrc1 & Rsrc2 ο໊ࠇ + 4 MOVE Rdst = Rsrc1 | Rsrc2 ࠷թఖ‫ڮ‬ᆴ + 5 LSH Rdst = Rsrc1 ቐ၍ + 6 RSH Rdst = Rsrc1 « Rsrc2 Ⴗ၍ + Rdst = Rsrc1 » Rsrc2 + + і 30­1. ؓ࠷թఖඔᆴ֥ ALU ᄎෘ + +ᇿၩğ + • ADD ‫ ބ‬SUB ᄎෘॖႨႿഡᇂࠇౢԢ ALU ၮԛѓᆽ໊b + • ෮Ⴕ ALU ᄎෘनॖႨႿഡᇂࠇౢԢ ALU ਬѓᆽ໊b + +30.4.1.2 ؓᆷ਷৫ࠧᆴ֥ᄎෘ + +31 28 27 25 24 21 19 43210 + + 4’d7 3’b1 ALU_sel Imm Rsrc1 Rdst + + ๭ 30­4. ᆷ਷ো྘ ­ ؓᆷ਷৫ࠧᆴ֥ ALU ᄎෘ + +ুᶈྐ༏॓࠯ 603 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +ೂ๭ 30-4 ෮ൕđ֒ླྀԩ৘ఖᆷ਷ [27:25] ໊ഡᇂູ 3’b1 ൈđALU ࡼؓླྀԩ৘ఖ࠷թఖ R[0-3] ‫ބ‬ᆷ਷ [19:4] ໊ +թԥ֥৫ࠧᆴࣉྛᄎෘđᄎෘো྘౼थႿᆷ਷֥ ALU_sel [24:21] ໊đऎุഡᇂٚൔ࡮༯і 30-2b + +Operand ૭ඍ - ࡮๭ 30-4 +ALU_sel ALU ᄎෘো྘ +Rdst ࠷թఖ R[0-3]đଢѓֹᆶ࠷թఖ +Rsrc1 ࠷թఖ R[0-3]đჷֹᆶ࠷թఖ +Imm ᆷ਷৫ࠧᆴđ16 ໊Ⴕ‫ݼژ‬ඔ + + ALU_sel ᆷ਷ ᄎෘ ૭ඍ + 0 ADD ࡆ + 1 SUB Rdst = Rsrc1 + Imm ࡨ + 2 AND Rdst = Rsrc1 - Imm ο໊ა + 3 OR Rdst = Rsrc1 & Imm ο໊ࠇ + 4 MOVE Rdst = Rsrc1 | Imm ࠷թఖ‫ڮ‬ᆴ + 5 LSH Rdst = Imm ቐ၍ + 6 RSH Rdst = Rsrc1 « Imm Ⴗ၍ + Rdst = Rsrc1 » Imm + + і 30­2. ؓᆷ਷৫ࠧᆴ֥ ALU ᄎෘ + +ᇿၩğ + • ADD ‫ ބ‬SUB ᄎෘॖႨႿഡᇂࠇౢԢ ALU ၮԛѓᆽ໊b + • ෮Ⴕ ALU ᄎෘनॖႨႿഡᇂࠇౢԢ ALU ਬѓᆽ໊b + +30.4.1.3 ؓࢨ‫࠹؍‬ඔఖ࠷թఖඔᆴ֥ᄎෘ + +31 28 27 25 24 21 11 4 + + 4’d7 3’d2 ALU_sel Imm + + ๭ 30­5. ᆷ਷ো྘ ­ ؓࢨ‫࠹؍‬ඔఖ࠷թఖ֥ ALU ᄎෘ + +ೂ๭ 30-5 ෮ൕđ֒ླྀԩ৘ఖᆷ਷ [27:25] ໊ഡᇂູ 3’b2 ൈđALU ࡼؓ 8 ໊࠷թఖ Stage_cnt ࣉྛ‫־‬ᄹa‫ࡨ־‬ +ࠇᇗᇂҠቔđᄎෘো྘౼थႿᆷ਷֥ ALU_sel [24:21] ໊đऎุഡᇂٚൔ࡮༯і 30-5b + +Operand ૭ඍ - ࡮๭ 30-5 +ALU_sel ALU ᄎෘো྘ +Stage_cnt ህႨ 8 ໊ࢨ‫࠹؍‬ඔఖ࠷թఖđॖթԥ࿖ߌ༯ѓ֩эਈ +Imm ᆷ਷৫ࠧᆴđ8 ໊ඔ + + ALU_sel ᆷ਷ ᄎෘ ૭ඍ + 0 STAGE_INC Stage_cnt = Stage_cnt + Imm ࢨ‫࠹؍‬ඔఖ࠷թఖ‫־‬ᄹ + 1 STAGE_DEC Stage_cnt = Stage_cnt - Imm ࢨ‫࠹؍‬ඔఖ࠷թఖ‫ࡨ־‬ + 2 STAGE_RST Stage_cnt = 0 ࢨ‫࠹؍‬ඔఖ࠷թఖ‫໊گ‬ + + і 30­3. ؓࢨ‫࠹؍‬ඔఖ࠷թఖ֥ ALU ᄎෘ + +ুᶈྐ༏॓࠯ 604 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +30.4.2 ST ⚶թԥඔऌᇀଽթ + + 31 28 27 25 20 10 3210 + + 4’d6 3’b100 4’b0 Offset 6’b0 Rdst Rsrc + + ๭ 30­6. ᆷ਷ো྘ ­ ST + +Operand ૭ඍ - ࡮๭ 30-6 +Offset 10 ໊Ⴕ‫ݼژ‬ඔđֆູ໊ 32 ໊ሳ +Rsrc ࠷թఖ R[0-3]đЌ਽ླթԥ֥ 16 ໊ඔ +Rdst ࠷թఖ R[0-3]đଢѓ࠷թఖֹᆶđֆູ໊ 32 ໊ሳ + +૭ඍ + +‫ھ‬ᆷ਷ॖࡼ Rsrc ᇏЌ਽֥ 16 ໊ඔթԥᇀଽթֹᆶູ Rdst + Offset ֥֮϶ሳᇏb‫ھ‬ଽթᇏ֥ۚ϶ሳູӱ྽࠹ඔ +ఖ (PC) ᇏ֥ଽಸčၛሳູֆ໊Ďቐ၍ 5 ໊đઆࠠࠇ Rdst (0..3)ğ + + Mem [ Rdst + Offset ]{31:0} = {PC[10:0], 3’b0, Rdst, Rsrc[15:0]} + +ႋႨӱ྽ॖ๙‫϶ۚݖ‬ሳ஑؎ ULP ӱ྽ᇏ֥ଧ่ᆷ਷ऎุཟଽթཿೆਔ൉હଽಸb +ᇿၩğ + + • ‫ھ‬ᆷ਷ࣇିၛ 32 ໊ሳູֆ໊ࣉྛ٠໙b + + • ಩‫ޅ‬౦ঃ༯đRsrc ᇏЌ਽֥ 16 ໊ඔႥჹࣇିթԥᇀଽթ֥֮϶ሳᇏđࠧႥჹ҂ॖିࡼ Rsrc թԥᇀଽթ + ֥ۚ϶ሳᇏb + + • Mem ཿೆ֥൞ RTC_SLOW_MEM ત෎ଽթđULP ླྀԩ৘ఖֹ֥ᆶ 0 ࠧཌྷ֒Ⴟᇶ CPU ֹ֥ᆶ + 0x50000000b + +30.4.3 LD ⚶Ֆଽթࡆᄛඔऌ + + 31 28 20 10 3210 + + 4’d13 Offset Rsrc Rdst + + ๭ 30­7. ᆷ਷ো྘ ­ LD + +Operand ૭ඍ - ࡮๭ 30-7 +Offset 10 ໊Ⴕ‫ݼژ‬ඔđֆູ໊ 32 ໊ሳ +Rsrc ࠷թఖ R[0-3]đЌ਽ଢѓ࠷թఖֹ֥ᆶđֆູ໊ 32 ໊ሳ +Rdst ࠷թఖ R[0-3]đଢѓ࠷թఖ + +૭ඍ + +‫ھ‬ᆷ਷ॖࡼଽթֹᆶ Rsrc + offset ᇏ֥֮϶ሳࡆᄛᇀଢѓ࠷թఖ Rdstğ + + Rdst[15:0] = Mem[ Rsrc + Offset ][15:0] + +ᇿၩğ + • ‫ھ‬ᆷ਷ࣇିၛ 32 ໊ሳູֆ໊ࣉྛ٠໙b + • ಩‫ޅ‬౦ঃ༯đRsrt ࣇॖࡆᄛଽթ֥֮϶ሳđࠧႥჹ҂ॖିࡼଽթ֥ۚ϶ሳࡆᄛᇀ Rsrt ᇏb + +ুᶈྐ༏॓࠯ 605 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +• ࡆᄛ֥ Mem ࡼթԥᇀ RTC_SLOW_MEM ત෎ଽթᇏđULP ླྀԩ৘ఖֹ֥ᆶ 0 ࠧཌྷ֒Ⴟᇶ CPU ֹ֥ᆶ + 0x50000000b + +30.4.4 JUMP ⚶๋ሇᇀधֹؓᆶ + +31 28 27 25 24 22 21 12 210 + + 4’d8 3’b0 Type Sel ImmAddr Rdst + + Cond๭ 30­8. ᆷ਷ো྘ ­ JUMP + +Operand ૭ඍ - ࡮๭ 30-8 +Rdst ࠷թఖ R[0-3]đԥթླ๋ሇᇀ֥ଢѓֹᆶ +ImmAddr 11 ֹ໊ᆶđֆູ໊ 32 ໊ሳ +Sel ๋ሇଢѓֹᆶটჷğ + 0 - ImmAddr թԥֹ֥ᆶ +Type 1 - Rdst թԥֹ֥ᆶ + ๋ሇো྘ğ + 0 - ໭่ࡱ๋ሇ + 1 - Ⴕ่ࡱ๋ሇđࣇ֒ቋު၂Ց ALU ᄎෘഡᇂਔਬѓᆽ໊ൈ๋ሇ + 2 - Ⴕ่ࡱ๋ሇđࣇ֒ቋު၂Ց ALU ᄎෘഡᇂਔၮԛѓᆽ໊ൈ๋ሇ + +ᇿၩğ +෮Ⴕ๋ሇֹᆶनၛ 32 ໊ሳູֆ໊b + +૭ඍ +‫ھ‬ᆷ਷ॖၛಞླྀԩ৘ఖ๋ሇᇀห‫ֹק‬ᆶđ๋ሇॖၛູ໭่ࡱ๋ሇࠇႵ่ࡱ๋ሇb + +30.4.5 JUMPR ⚶๋ሇᇀཌྷֹؓᆶčࠎႿ R0 ࠷թఖ஑؎Ď + +31 28 27 25 24 17 16 15 0 + + 4’d8 3’b1 Step Threshold + + ๭ 30­9. ᆷ਷ো྘ ­ JUMPR + +Operand ૭ඍ - ࡮๭ 30-9 +Step ཌྷؓ၍໊ਈđֆູ໊ 32 ໊ሳğ + ೂ‫ ݔ‬Step[7] = 0đᄵ PC = PC + Step[6:0] +Threshold ೂ‫ ݔ‬Step[7] = 1đᄵ PC = PC - Step[6:0] +Cond ๋ሇ่ࡱᚐᆴč࡮༯ٚ Cond Ď + ๋ሇ่ࡱğ + 0 - ೂ‫ ݔ‬R0 < Thresholdđ๋ࠧሇ + 1 - ೂ‫ ݔ‬R0 >= Thresholdđ๋ࠧሇ + +ᇿၩğ +෮Ⴕ๋ሇֹᆶनၛ 32 ໊ሳູֆ໊b + +૭ඍ +ೂ‫๋ݔ‬ሇ่ࡱčࠧбࢠ R0 ࠷թఖ֥ᆴა Threshold ᚐᆴĎູᆇđ‫ھ‬ᆷ਷ॖၛಞླྀԩ৘ఖ๋ሇᇀ 1 ۱ཌྷֹؓ +ᆶb + +ুᶈྐ༏॓࠯ 606 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +30.4.6 JUMPS ⚶๋ሇᇀཌྷֹؓᆶčࠎႿࢨ‫࠹؍‬ඔఖ࠷թఖ஑؎Ď + + 31 28 27 25 24 17 16 15 7 0 + + 4’d8 3’d2 Step Cond Threshold + + ๭ 30­10. ᆷ਷ো྘ ­ JUMPS + +Operand ૭ඍ - ࡮๭ 30-10 +Step ཌྷ໊ؓ၍ਈđֆູ໊ 32 ໊ሳğ + ೂ‫ ݔ‬Step[7] = 0đᄵ PC = PC + Step[6:0] +Threshold ೂ‫ ݔ‬Step[7] = 1đᄵ PC = PC - Step[6:0] +Cond ๋ሇ่ࡱᚐᆴč࡮༯ٚ Cond Ď + ๋ሇ่ࡱğ + 1X - ೂ‫ ݔ‬Stage_cnt <= Thresholdđ๋ࠧሇ + 00 - ೂ‫ ݔ‬Stage_cnt < Thresholdđ๋ࠧሇ + 01 - ೂ‫ ݔ‬Stage_cnt >= Thresholdđ๋ࠧሇ + +ᇿၩğ + +• Ⴕܱࢨ‫࠹؍‬ඔఖ֥ཌྷܱഡᇂđ౨࡮ 30.4.1.3 ALU ࢨ‫࠹؍‬ඔఖᅣࢫb + + • ෮Ⴕ๋ሇֹᆶनၛ 32 ໊ሳູֆ໊b + +૭ඍ +ೂ‫๋ݔ‬ሇ่ࡱčࠧбࢠ Stage_cnt ࢨ‫࠹؍‬ඔఖ࠷թఖ֥ᆴა Threshold ᚐᆴĎູᆇđ‫ھ‬ᆷ਷ॖၛಞླྀԩ৘ఖ๋ሇ +ᇀ 1 ۱ཌྷֹؓᆶb + +30.4.7 HALT ⚶ࢲඏӱ྽ + + 31 28 0 + + 4’d11 + + ๭ 30­11. ᆷ਷ো྘ ­ HALT + +૭ඍ +‫ھ‬ᆷ਷ॖၛಞླྀԩ৘ఖࣉೆ؎‫׈‬ଆൔb + +ᇿၩğ +ᆳྛ‫ھ‬ᆷ਷ުđULP ླྀԩ৘ఖ֥႗ࡱ࠹ൈఖࡼष൓࠹ൈb + +30.4.8 WAKE ⚶ߒྜྉோ + + 31 28 27 25 0 + + 4’d9 3’b0 1’b1 + + ๭ 30­12. ᆷ਷ো྘ ­ WAKE + +૭ඍ +‫ھ‬ᆷ਷ॖၛಞ ULP ླྀԩ৘ఖཟ RTC ॥ᇅఖ‫ؿ‬ෂᇏ؎b + + • ֒ SoC ԩႿ Deep-sleep ଆൔൈđ‫ھ‬ᆷ਷ॖߒྜ SoCb + + • ֒ SoC ԩႿ Deep-sleep ᆭຓ֥ଆൔൈđೂ‫ ݔ‬RTC_CNTL_INT_ENA_REG ࠷թఖഡᇂਔ + RTC_CNTL_ULP_CP_INT_ENA ᇏ؎໊đ‫ھ‬ᆷ਷ࠧԨ‫ ؿ‬RTC ᇏ؎b + +ুᶈྐ༏॓࠯ 607 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +30.4.9 SLEEP ⚶ഡᇂ႗ࡱ࠹ൈఖ֥ߒྜᇛ௹ + +31 28 27 25 3 0 + + 4’d9 3’b1 sleep_reg + + ๭ 30­13. ᆷ਷ো྘ ­ SLEEP + + Operand ૭ඍ - ࡮๭ 30-13 + sleep_reg ᄝ 5 ۱թԥਔ҂๝ߒྜᇛ௹֥ SENS_ULP_CP_SLEEP_CYCn_REG (n: 0-4) ࠷թఖᇏࣉྛ࿊ᄴb + +૭ඍ +‫ھ‬ᆷ਷ॖ࿊ᄴ ULP ླྀԩ৘ఖ࠹ൈఖ֥ߒྜᇛ௹টჷđࠧ SENS_ULP_CP_SLEEP_CYCn_REG (n: 0-4) ࠷թఖᇏ +֥ 1 ۱bଏಪ౦ঃ༯đULP ླྀԩ৘ఖࡼҐႨ SENS_ULP_CP_SLEEP_CYC0_REG ᇏ֥ᆴູߒྜᇛ௹b + +30.4.10 WAIT ⚶֩ր೏‫ۄ‬۱ᇛ௹ + +31 28 15 0 + + 4’d4 Cycles + + ๭ 30­14. ᆷ਷ো྘ ­ WAIT + + Operand ૭ඍ - ࡮๭ 30-14 + Cycles ਆՑඤ૤ᆭࡗ֥֩րᇛ௹ඔ + +૭ඍ +‫ھ‬ᆷ਷ॖၛഡ‫ླྀק‬ԩ৘ఖਆՑඤ૤ᆭࡗ֥֩րᇛ௹b + +30.4.11 ADC ⚶ؓ ADC ࣉྛҩਈ + +31 28 65 210 + + 4’d5 Sel Sar Mux Rdst + + ๭ 30­15. ᆷ਷ো྘ ­ ADC + +Operand ૭ඍ - ࡮๭ 30-15 +Rdst ଢѓֹᆶ࠷թఖ R[0-3]đࡼթԥҩਈࢲ‫ݔ‬ +Sel ࿊ᄴ ADCğ0 սі࿊ᄴ SAR ADC1Ġ1 սі࿊ᄴ SAR ADC2đऎุॖ࡮і 30-4b +Sar Mux ൐ି SARADC ܵ࢖ [Sar_Mux - 1]đ࡮і 30-4b + + і 30­4. ADC ᆷ਷֥ൻೆྐ‫ݼ‬ + +ܵ࢖଀ / ྐ‫ ଀ݼ‬/ GPIO Sar_Mux ADC ࿊ᄴčSelĎ +SENSOR_VP (GPIO36) 1 Sel = 0đ࿊ᄴ SAR ADC1 +SENSOR_CAPP (GPIO37) 2 +SENSOR_CAPN (GPIO38) 3 +SENSOR_VN (GPIO39) 4 +32K_XP (GPIO33) 5 +32K_XN (GPIO32) 6 +VDET_1 (GPIO34) 7 +VDET_2 (GPIO35) 8 +Hall phase 1 9 +Hall phase 0 10 + +ুᶈྐ༏॓࠯ 608 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +ܵ࢖଀ / ྐ‫ ଀ݼ‬/ GPIO Sar_Mux ADC ࿊ᄴčSelĎ +GPIO4 1 Sel = 1đ࿊ᄴ SAR ADC2 +GPIO0 2 +GPIO2 3 +MTDO (GPIO15) 4 +MTCK (GPIO13) 5 +MTDI (GPIO12) 6 +MTMS (GPIO14) 7 +GPIO27 8 +GPIO25 9 +GPIO26 10 + +૭ඍ +‫ھ‬ᆷ਷ॖؓ ADC ֥ྐ‫ྛࣉݼ‬ҩਈbADC ᆷ਷ҩਈ֥ܵ࢖აྐ‫࡮ݼ‬і 30-4b + +30.4.12 I2C_RD / I2C_WR ⚶‫ ؀‬/ ཿ I²C + +31 28 27 25 22 21 19 18 16 15 87 0 + + 4’d3 R/W I2C Sel High Low Data Sub-addr + + ๭ 30­16. ᆷ਷ো྘ ­ I²C + +Operand ૭ඍ - ࡮๭ 30-16 +Sub-addr Ֆࠏ֥࠷թఖֹᆶ +Data I2C_WR ᄎෘᇏླཿೆ֥ඔऌč֌҂߶ႨႿ I2C_RD ᄎෘĎ +Low ໊ဃ઒໊֥ۚ +High ໊ဃ઒໊֥֮ +I2C Sel ᄝ 8 ۱թԥ I²C Ֆࠏֹᆶ֥࠷թఖ SENS_I2C_SLAVE_ADDRn (n: 0-7) ᇏࣉྛ࿊ᄴ +R/W I²C ๙ྐো྘ğ + 1 - I²C ཿ + 0 - I²C ‫؀‬ + +૭ඍ +‫ھ‬ᆷ਷ॖၛᆦӻაຓ҆ I²C Ֆࠏࣉྛ๙ྐč‫؀‬/ཿĎđႵܱ RTC I²C ຓຶഡС֥൐Ⴈđॖ࡮ 30.6b + +ᇿၩğ +ᄝᇶࠏଆൔ༯đRTC_I2C ॖᄝ SCL ൈᇒ֥༯ࢆခؓ SDA ൻೆྐ‫ྛࣉݼ‬Ґဢb + +30.4.13 REG_RD ⚶Ֆຓຶ࠷թఖ‫؀‬౼ + +31 28 27 23 22 18 9 0 + + 4’d2 High Low Addr + + ๭ 30­17. ᆷ਷ো྘ ­ REG_RD + +Operand ૭ඍ - ࡮๭ 30-17 +Addr ຓຶഡС࠷թఖֹᆶđֆູ໊ 32 ໊ሳ +High ࠷թఖࢲඏ໊ +Low ࠷թఖष൓໊ + +ুᶈྐ༏॓࠯ 609 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +૭ඍ +‫ھ‬ᆷ਷ॖၛՖຓຶՖࠏ࠷թఖᇏ‫؀‬౼ቋۚ 16 ໊֥ଽಸđѩթೆ๙Ⴈ࠷թఖ R0b + + R0 = REG[Addr][High:Low] + +ೂླ‫؀‬౼֥ଽಸӑ‫ ݖ‬16 ໊đࠧ High - Low + 1 > 16đᄵ‫ھ‬ᆷ਷ࡼْ߭ [Low+15:Low] ֥ଽಸb +ᇿၩğ + + • ‫ھ‬ᆷ਷ॖ٠໙ RTC_CNTLaRTC_IOaSENS ࠣ RTC_I2C ຓຶഡСᇏ֥࠷թఖbULP ླྀԩ৘ఖॖ๙‫ݖ‬ཌྷ๝ + ࠷թఖᄝ DPORT ሹཌഈֹ֥ᆶđ࠹ෘຓຶ࠷թఖֹ֥ᆶđऎุٚൔ࡮༯ğ + addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE) / 4 + +• addr_ulp ၛ 32 ໊ሳč‫ط‬٤ሳࢫĎູֆ໊đ0 ॖ๧ഝᇀ DR_REG_RTCCNTL_BASEčՖᇶ CPU ֥࢘؇Ďb + ၹՎđ10 ໊ ULP ླྀԩ৘ఖֹ֥ᆶॖ‫ۂڭ‬ຓຶ࠷թఖॢࡗ֥ 4096 ሳࢫđЇও DR_REG_RTCCNTL_BASEa + DR_REG_RTCIO_BASEaDR_REG_SENS_BASE ࠣ DR_REG_RTC_I2C_BASE ౵თb + +30.4.14 REG_WR ⚶ཿೆຓຶ࠷թఖ + + 31 28 27 23 22 18 17 10 9 0 + + 4’d1 High Low Data Addr + + ๭ 30­18. ᆷ਷ো྘ ­ REG_WR + +Operand ૭ඍ - ࡮๭ 30-18 +Addr ଢѓ࠷թఖֹᆶđֆູ໊ 32 ໊ሳ +High ࠷թఖࢲඏ໊ +Low ࠷թఖष൓໊ +Data ླཿೆ֥ᆴđ8 ໊ඔ + +૭ඍ + +‫ھ‬ᆷ਷ॖၛཟຓഡ࠷թఖཿೆ၂۱ 8 ໊৫ࠧᆴ (Data)b + + REG[Addr][High:Low] = Data + +ೂླཿೆ֥ଽಸӑ‫ ݖ‬8 ໊đࠧ High - Low + 1 > 8đᄵ‫ھ‬ᆷ਷߶۳ 8 ໊ၛഈ֥ଽಸแԉ 0b +ᇿၩğ +Ⴕܱ addr_ulp ֥ଽಸđ౨࡮ 30.4.13b + +30.5 ULP ླྀԩ৘ఖӱ྽֥ᆳྛ + +ULP ླྀԩ৘ఖࣜ‫ݖ‬ህ૊ഡ࠹đॖ‫׿‬৫Ⴟᇶ CPU ᄎྛđ໭ંުᆀ൞‫ڎ‬ԩႿ Deep-sleep ଆൔb + +ᄝ‫྘ׅ‬ӆࣟᇏđູਔࢆ֮‫ݻۿ‬đ༢๤ॖ൐ᇶ CPU ࣉೆ Deep-sleep ሑ෿đ‫ط‬০Ⴈ ULP ླྀԩ৘ఖࣉྛсေҠቔb +ູਔࣉ၂҄ࢆ֮‫ݻۿ‬đULP ླྀԩ৘ఖሱദ္ॖၛࣉೆඤ૤ଆൔbᄝᆃᇕ౦ঃ༯đႮႿ໭‫م‬ᄎྛ಩‫ޅ‬ೈࡱӱ྽đ +ၹՎ༢๤஥Сਔ 1 ۱ห൹֥႗ࡱ࠹ൈఖđॖႨႿߒྜ ULP ླྀԩ৘ఖb‫ھ‬႗ࡱ࠹ൈఖсྶิభࣉྛ஥ᇂđѩᄝ 5 +۱թԥਔ҂๝ߒྜᇛ௹֥ SENS_ULP_CP_SLEEP_CYCn_REG ࠷թఖᇏࣉྛ࿊ᄴbᇶ CPU ‫ ބ‬ULP ླྀԩ৘ఖӱ + +ুᶈྐ༏॓࠯ 610 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +྽नॖ๙‫ ݖ‬REG_WR ‫ ބ‬SLEEP ᆷ਷ࣉྛཌྷܱഡᇂbࢤሢđ༢๤ॖ๙‫ݖ‬ഡᇂ RTC_CNTL_STATE0_REG ࠷թఖ +ᇏ֥ RTC_CNTL_ULP_CP_SLP_TIMER_EN ໊đఓ‫ ׮‬ULP ླྀԩ৘ఖ࠹ൈఖb +ULP ླྀԩ৘ఖॖ๙‫ݖ‬ᆳྛ HALT ᆷ਷ࣉೆඤ૤ሑ෿đᆃ္ࡼ๝ൈԨ‫ ؿ‬ULP ླྀԩ৘ఖ֥႗ࡱ࠹ൈఖ +RTC_SLOW_CLK ष൓๤࠹ൈᇒඔčଏಪሑ෿༯đটሱଽ֥҆ 150 kHz RC ᆒ֕ఖĎb࠹ൈఖ၂֊֞௹đULP ླྀ +ԩ৘ఖࡼഈ‫׈‬ѩ๙‫ݖ‬թԥᄝ SENS_PC_INIT ᇏ֥ PC ఓ‫׮‬bഈඍྐ‫ݼ‬ა࠷թఖᆭࡗ֥ܱ༢ॖ࡮๭ 30-19b + + ๭ 30­19. ULP ླྀԩ৘ఖӱ྽ॿ๭ + +‫ބ໊گ‬ഈ‫׈‬ටࡗđULP ླྀԩ৘ఖӱ྽ࣇ߶ᄝ ULP ࠹ൈఖ֥ଏಪᇛ௹ SENS_ULP_CP_SLEEP_CYC0_REG ‫ݖ‬௹ +ުఓ‫׮‬b +ULP ླྀԩ৘ఖӱ྽֥ᄎྛඨ྽ൕ২ॖ࡮๭ 30-20đఃᇏऎุ҄ᇧЇওğ + + 1. ೈࡱ๙‫ ݖ‬RTC_CNTL_ULP_CP_SLP_TIMER_EN ໊ఓ‫ ׮‬ULP ࠹ൈఖb + 2. ULP ࠹ൈఖ‫ݖ‬௹đULP ླྀԩ৘ఖष൓Ֆ PC = SENS_PC_INIT ԩᄎྛӱ྽b + 3. ᆳྛ HALT ᆷ਷đULP ӱ྽๔ᆸᄎྛđULP ࠹ൈఖᄜՑఓ‫׮‬b + 4. ᆳྛ SLEEP ᆷ਷đྩ‫ڿ‬ඤ૤࠹ൈఖᇛ௹࠷թఖb + 5. ULP ླྀԩ৘ఖӱ྽ࠇೈࡱ๙‫ ݖ‬RTC_CNTL_ULP_CP_SLP_TIMER_EN ໊đܱо ULP ླྀԩ৘ఖ࠹ൈఖb + +ুᶈྐ༏॓࠯ 611 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + ๭ 30­20. ULP ླྀԩ৘ఖӱ྽ੀ॥๭ + +ULP ླྀԩ৘ఖߒྜaᆳྛӱ྽‫ބ‬ඤ૤֥ऎุൈ྽Ⴎ ULP FSM ॥ᇅđऎุູğ + + 1. ULP ࠹ൈఖ‫ݖ‬௹ൈđFSM ߒྜ ULP ླྀԩ৘ఖđᆃ۱‫ݖ‬ӱӻ࿃ਆ۱ൈᇒᇛ௹b + + 2. ULP ླྀԩ৘ఖӱ྽ᆳྛᆭభđFSM ֩ր RTC_CNTL_TIMER2_REG ࠷թఖᇏ + RTC_CNTL_ULPCP_TOUCH_START_WAIT ഡᇂ֥೏‫ۄ‬۱ൈᇒᇛ௹đᆃ۱‫ݖ‬ӱ൞ູਔ֩ր 8 MHz ൈᇒሑ + ෿໗‫ק‬b + + 3. ULP ླྀԩ৘ఖӱ྽ᆳྛb + + 4. ‫ט‬Ⴈ HALT ᆷ਷ުđULP ླྀԩ৘ఖӱ྽ᆳྛ๔ᆸbFSM ߎླေਆ۱ൈᇒᇛ௹ট൐ ULP ླྀԩ৘ఖࣉೆඤ૤ + ሑ෿b + +30.6 RTC_I2C ॥ᇅఖ + +ULP ླྀԩ৘ఖॖ൐Ⴈ 1 ॻ໊Ⴟ RTC თ֥‫׿‬৫ I²C ॥ᇅఖđაຓ҆ I²C Ֆࠏࣉྛ๙ྐbა I2C0 / I2C1 ຓຶഡС +ཌྷбđRTC_I2C ֥‫ࠢିۿ‬ཌྷؓႵཋb + +30.6.1 ஥ᇂ RTC_I2C + +ULP ླྀԩ৘ఖᄝᆞӈ൐Ⴈ I²C ᆷ਷ᆭభсྶ஥ᇂ RTC_I2C ᇏ֥ห‫ק‬ҕඔđॖ๙‫ݖ‬ଖᇶ CPU ࠇ ULP ླྀԩ৘ఖЧ +ദᄎྛӱ྽ປӮđऎุࠧཟ RTC_I2C ࠷թఖཿೆห‫࠹ק‬ൈҕඔb + + 1. ๙‫ ݖ‬RTC_I2C_SCL_LOW_PERIOD_REG ‫ ބ‬RTC_I2C_SCL_HIGH_PERIOD_REG ഡᇂ RTC_FAST_CLK + ᇛ௹ᇏ SCL ൈᇒ֥֮ۚ‫׈‬௜ॺ؇‫ބ‬ᇛ௹č২đ௔ੱູ 100 kHz ൈđഡᇂ RTC_I2C_SCL_LOW_PERIOD = + 40aRTC_I2C_SCL_HIGH_PERIOD = 40Ďb + + 2. ๙‫ ݖ‬RTC_FAST_CLK ᇏ֥ RTC_I2C_SDA_DUTY_REG ഡᇂ SDA ్ߐభ֩ր֥ᇛ௹ඔč২đ + RTC_I2C_SDA_DUTY=16Ďb + + 3. ๙‫ ݖ‬RTC_I2C_SCL_START_PERIOD_REG ഡᇂఓ‫֥֩ުݼྐ׮‬րൈࡗč২đ + RTC_I2C_SCL_START_PERIOD = 30Ďb + + 4. ๙‫ ݖ‬RTC_I2C_SCL_STOP_PERIOD_REG ഡᇂ๔ᆸྐ‫ݼ‬భ֥֩րൈࡗč২đ + RTC_I2C_SCL_STOP_PERIOD = 44Ďb + + 5. ๙‫ ݖ‬RTC_I2C_TIMEOUT_REG ഡᇂ๙ྐӑൈҕඔč২đRTC_I2C_TIMEOUT = 200Ďb + +ুᶈྐ༏॓࠯ 612 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + 6. ๙‫ ݖ‬RTC_I2C_CTRL_REG ᇏ֥ RTC_I2C_MS_MODE ໊ఓ‫׮‬ᇶࠏଆൔb + + 7. ࡼຓ҆Ֆࠏֹ֥ᆶཿೆ SENS_I2C_SLAVE_ADDRn (n: 0-7)đቋ‫؟‬ॖ๙‫ݖ‬ᆃᇕٚൔყщӱ 8 ۱Ֆࠏֹᆶb + ՎުđॖູૄՑ๙ྐ࿊ᄴ 1 ۱ഈඍֹᆶđ‫܋‬๝ቆӮླྀԩ৘ఖ I2C ᆷ਷b + + ປӮഈඍ RTC_I2C ஥ᇂުđࠧॖ൐Ⴈ I2C_RD / I2C_WR ⚶‫؀‬/ཿ I²C ᆷ਷b + + 30.6.2 ൐Ⴈ RTC_I2C + + ULP ླྀԩ৘ఖ֥ 2 ۱ᆷ਷ࠢčҐႨ๝ 1 ۱ OpCodeĎनॖ൐Ⴈ RTC_I2C ॥ᇅఖğI2C_RD č‫؀‬Ď‫ ބ‬I2C_WR +čཿĎđབྷ࡮ I2C_RD / I2C_WR ⚶‫؀‬/ཿ I²C ᅣࢫb + +30.6.2.1 I2C_RD ­ ‫؀‬౼ֆ۱ሳࢫ + +I2C_RD ᆷ਷֥ᆳྛ҄ᇧೂ༯đ࡮๭ 30-21ğ + 1. ᇶࠏ‫ؿ‬ෂఓ‫ݼྐ׮‬b + 2. ᇶࠏ‫ؿ‬ෂଁ਷ሳࢫđЇওՖࠏֹᆶ‫؀ބ‬/ཿ॥ᇅ໊čՎൈđ‫؀‬/ཿ॥ᇅ໊ᇂູ 0đսіoཿpĎbՖࠏֹᆶॖ + Ֆ SENS_I2C_SLAVE_ADDRn ᇏࠆ౼đఃᇏ࠷թఖ֥ऎุ࿊ᄴॖ๙‫ ݖ‬I2C_RD ഡᇂb + 3. Ֆࠏ‫ؿ‬ෂႋճྐ‫ݼ‬b + 4. ᇶࠏ‫ؿ‬ෂՖࠏ࠷թఖֹᆶđఃᇏ࠷թఖ֥ऎุ࿊ᄴॖ๙‫ ݖ‬I2C_RD ഡᇂb + 5. Ֆࠏ‫ؿ‬ෂႋճྐ‫ݼ‬b + 6. ᇶࠏ‫ؿ‬ෂᇗ‫گ‬ఓ‫ݼྐ׮‬b + 7. ᇶࠏ‫ؿ‬ෂՖࠏֹᆶđఃᇏ‫؀‬/ཿ॥ᇅ໊ᇂູ 1đսіo‫؀‬pb + 8. Ֆࠏ‫ؿ‬ෂ 1 ۱ሳࢫ֥ඔऌb + 9. ᇶࠏ‫ؿ‬ෂ٤ႋճྐ‫ݼ‬b + + 10. ᇶࠏ‫ؿ‬ෂ๔ᆸྐ‫ݼ‬đࢲඏ‫؀‬౼b + + 1 2 3 4 56 7 8 9 10 + Data + START + ACK + ACK + + RSTRT + NACK + STOP +Master Slave Address W Reg Address Slave Address R + Slave + + ๭ 30­21. I2C ‫؀‬Ҡቔ + +ᇿၩğ +RTC_I2C ॥ᇅఖຓຶഡС߶ؓ SCL ൈᇒ༯ࢆခഈ֥ SDA ྐ‫ྛࣉݼ‬Ґဢbೂ‫ݔ‬Ֆࠏ֥ SDA ྐ‫ݼ‬ᄝჿ 0.38 ms +ଽ‫ؿ‬ള‫ڿ‬эđᇶࠏᄵࡼࢤ൬֞҂ᆞಒ֥ඔऌb +Ֆࠏࢤ൬֥֞ሳࢫࡼթԥᄝ R0 ࠷թఖᇏb + +30.6.2.2 I2C_WR ­ ཿೆֆ۱ሳࢫ + +I2C_WR ᆷ਷֥ᆳྛ҄ᇧೂ༯đ࡮๭ 30-22ğ + 1. ᇶࠏ‫ؿ‬ෂष൓ྐ‫ݼ‬b + +ুᶈྐ༏॓࠯ 613 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + 2. ᇶࠏ‫ؿ‬ෂଁ਷ሳࢫđЇওՖࠏֹᆶ‫؀ބ‬/ཿ॥ᇅ໊čՎൈđ‫؀‬/ཿ॥ᇅ໊ᇂູ 0đսіoཿpĎbՖࠏֹᆶॖ + Ֆ SENS_I2C_SLAVE_ADDRn ᇏࠆ౼đఃᇏ࠷թఖ֥ऎุ࿊ᄴॖ๙‫ ݖ‬I2C_WR ഡᇂb + + 3. Ֆࠏ‫ؿ‬ෂႋճྐ‫ݼ‬b + 4. ᇶࠏ‫ؿ‬ෂՖࠏ࠷թఖֹᆶđఃᇏ࠷թఖ֥ऎุ࿊ᄴॖ๙‫ ݖ‬I2C_WR ഡᇂb + 5. Ֆࠏ‫ؿ‬ෂႋճྐ‫ݼ‬b + 6. ᇶࠏ‫ؿ‬ෂᇗ‫گ‬ఓ‫ݼྐ׮‬b + 7. ᇶࠏ‫ؿ‬ෂՖࠏֹᆶđఃᇏ‫؀‬/ཿ໊ᇂູ 0đսіoཿpb + 8. ᇶࠏ‫ؿ‬ෂ 1 ۱ሳࢫ֥ඔऌb + 9. Ֆࠏ‫ؿ‬ෂႋճྐ‫ݼ‬b +10. ᇶࠏ‫ؿ‬ෂ๔ᆸྐ‫ݼ‬đࢲඏཿೆb + + 1 2 3 4 56 7 8 9 10 + Data + START + ACK + ACK + + RSTRT + ACK + + STOP +Master Slave Address W Reg Address Slave Address W + Slave + + ๭ 30­22. I²C ཿҠቔ + +30.6.2.3 ࡟ҩհ༂่ࡱ + +ULP ླྀԩ৘ఖᆷ਷ I2C_RD ‫ ބ‬I2C_WR ҂߶๙‫࠷ݖ‬թఖБۡՖࠏ NACK ֩հ༂่ࡱbཌྷّđႋႨӱ྽ॖၛ๙‫ݖ‬ +Ұ࿘ RTC_I2C_INT_ST_REG ࠷թఖᇏ֥ห‫໊ק‬đ஑؎ᆷ਷൞‫ڎ‬Ӯ‫ۿ‬ᆳྛbູਔ࡟Ұห‫֥ק‬๙ྐࠃ‫׮‬đ +RTC_I2C_INT_EN_REG ࠷թఖᇏ֥ཌྷႋ໊ႋࣉྛഡᇂbᇿၩđ༢๤໊๭ࡼ၍ 1bೂ‫࡟ݔ‬ҩ֞ห‫ק‬๙ྐࠃ‫׮‬đ౏ +ഡᇂਔ RTC_I2C_INT_ST_REG ࠷թఖđᄵॖ๙‫ ݖ‬RTC_I2C_INT_CLR_REG ࠷թఖౢਬb + +30.6.2.4 ৵ࢤ I²C ྐ‫ݼ‬ + +SDA ‫ ބ‬SCL ൈᇒྐ‫ݼ‬ॖ๙‫ݖ‬஥ᇂ RTCIO_SAR_I2C_IO_REG ࠷թఖđ৵ࢤᇀ 2 ۱ GPIO ܵ࢖č‫ ܋‬4 ۱Ďđབྷ༥ +‫ק‬ၬ౨࡮ᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔᇏ֥і RTC_MUX ܵ࢖ౢֆb + +30.7 ࠷թఖਙі ૭ඍ ֹᆶ ٠໙ো྘ + +30.7.1 SENS_ULP ֹᆶॢࡗ ࠹ൈఖᇛ௹ഡᇂ 0 0x3FF48818 ‫؀‬/ཿ + ࠹ൈఖᇛ௹ഡᇂ 1 0x3FF4881C ‫؀‬/ཿ + ଀ӫ ࠹ൈఖᇛ௹ഡᇂ 2 0x3FF48820 ‫؀‬/ཿ + ULP ࠹ൈఖᇛ௹࿊ᄴ ࠹ൈఖᇛ௹ഡᇂ 3 0x3FF48824 ‫؀‬/ཿ + SENS_ULP_CP_SLEEP_CYC0_REG ࠹ൈఖᇛ௹ഡᇂ 4 0x3FF48828 ‫؀‬/ཿ + SENS_ULP_CP_SLEEP_CYC1_REG + SENS_ULP_CP_SLEEP_CYC2_REG I²C ֹᆶ 0 ‫ ބ‬1 0x3FF4883C ‫؀‬/ཿ + SENS_ULP_CP_SLEEP_CYC3_REG I²C ֹᆶ 2 ‫ ބ‬3 0x3FF48840 ‫؀‬/ཿ + SENS_ULP_CP_SLEEP_CYC4_REG + RTC I²C ՖഡСֹᆶ࿊ᄴ + SENS_SAR_SLAVE_ADDR1_REG + SENS_SAR_SLAVE_ADDR2_REG + +ুᶈྐ༏॓࠯ 614 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +SENS_SAR_SLAVE_ADDR3_REG I²C ֹᆶ 4 ‫ ބ‬5 0x3FF48844 ‫؀‬/ཿ +SENS_SAR_SLAVE_ADDR4_REG I²C ֹᆶ 6 ‫ ބ‬7đI²C ॥ᇅ 0x3FF48848 ‫؀‬/ཿ +RTC I²C ॥ᇅ +SENS_SAR_I2C_CTRL_REG I²C ॥ᇅ࠷թఖ 0x3FF48850 ‫؀‬/ཿ + +30.7.2 RTC_I2C ֹᆶॢࡗ ૭ඍ ֹᆶ ٠໙ো྘ + + ଀ӫ Ԯൻഡᇂ 0x3FF48C04 ‫؀‬/ཿ + RTC I²C ॥ᇅ࠷թఖ ‫ט‬൫ሑ෿ 0x3FF48C08 ‫؀‬/ཿ + RTC_I2C_CTRL_REG ӑൈഡᇂ 0x3FF48C0C ‫؀‬/ཿ + RTC_I2C_DEBUG_STATUS_REG ЧֹՖഡСֹᆶഡᇂ 0x3FF48C10 ‫؀‬/ཿ + RTC_I2C_TIMEOUT_REG + RTC_I2C_SLAVE_ADDR_REG ஥ᇂ SCL ༯ࢆခު֥ SDA Ќӻൈࡗ 0x3FF48C30 ‫؀‬/ཿ + RTC I²C ྐ‫ݼ‬ഡᇂ࠷թఖ ஥ᇂ SCL ൈᇒ֥֮‫׈‬௜ॺ؇ 0x3FF48C00 ‫؀‬/ཿ + RTC_I2C_SDA_DUTY_REG ஥ᇂ SCL ൈᇒ֥ۚ‫׈‬௜ॺ؇ 0x3FF48C38 ‫؀‬/ཿ + RTC_I2C_SCL_LOW_PERIOD_REG ஥ᇂष൓่ࡱ༯đSDA ა SCL ༯ࢆ + RTC_I2C_SCL_HIGH_PERIOD_REG ခᆭࡗ֥࿼Ӿ 0x3FF48C40 ‫؀‬/ཿ + ஥ᇂ๔ᆸ่ࡱ༯đSDA ა SCL ༯ࢆ + RTC_I2C_SCL_START_PERIOD_REG ခᆭࡗ֥࿼Ӿ 0x3FF48C44 ‫؀‬/ཿ + + RTC_I2C_SCL_STOP_PERIOD_REG ౢԢ I²C ๙ྐࠃ‫׮‬ሑ෿ 0x3FF48C24 ‫؀‬/ཿ + ष൓ѽሚ I²C ๙ྐሑ෿ࠃ‫׮‬ 0x3FF48C28 ‫؀‬/ཿ + RTC I²C ᇏ؎࠷թఖ ­ ࣇႨႿ‫ט‬൫ଢ֥ ѽሚ I²C ๙ྐࠃ‫֥׮‬ሑ෿ 0x3FF48C2C ᆺ‫؀‬ + RTC_I2C_INT_CLR_REG + RTC_I2C_INT_EN_REG + RTC_I2C_INT_ST_REG + +ᇿၩğ +টሱ RTC_I2C ॥ᇅఖ֥ᇏ؎ᄠൈഉໃ৵ࢤđၛഈᇏ؎࠷թఖࣇႨႿ‫ט‬൫ଢ֥b + +30.8 ࠷թఖ + +30.8.1 SENS_ULP ֹᆶॢࡗ + +Чཬࢫও‫ݼ‬ᇏֹ֥ᆶनູཌྷؓႿ (RTC ࠎֹᆶ + 0x0800) ֹ֥ᆶொ၍ਈčཌྷֹؓᆶĎbRTC ࠎֹᆶ࡮ᅣࢫ 1 ༢๤ +‫ބ‬թԥఖ ᇏ֥і 1-6 ຓഡֹᆶ႘ഝb࠷թఖधֹؓᆶ࡮ᅣࢫ 30.7.1 SENS_ULP ֹᆶॢࡗb + + Register 30.1. SENS_ULP_CP_SLEEP_CYCn_REG (n: 0­4) (0x18+0x4*n) + +31 0 + + 20 Reset + +SENS_ULP_CP_SLEEP_CYCn_REG ULP ࠹ൈఖᇛ௹ഡᇂ nđULP ླྀԩ৘ఖॖ๙‫ݖ‬ᆷ਷ SLEEP ᄝ + ഈඍ࠷թఖᇏࣉྛ࿊ᄴbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 615 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + Register 30.2. SENS_SAR_START_FORCE_REG (0x002c) + + (reserved) SENS_PC_INIT (reservSeEdN) SS_UENLPS__CUPLP_S_CTAPR_TFO_TROCPE_(SreTsAeRrvTe_dT)OP + +31 22 21 11 10 9 8 7 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SENS_PC_INIT ULP PC ೆ१ֹᆶbč‫؀‬/ཿĎ + + SENS_ULP_CP_START_TOP ఓ‫ ׮‬ULP ླྀԩ৘ఖđࣇ֒ SENS_ULP_CP_FORCE_START_TOP = 1 + ൈႵིbč‫؀‬/ཿĎ + + SENS_ULP_CP_FORCE_START_TOP 1ğULP ླྀԩ৘ఖႮ SENS_ULP_CP_START_TOP ఓ‫׮‬Ġ0ğ + ULP ླྀԩ৘ఖႮ႗ࡱ࠹ൈఖఓ‫׮‬bč‫؀‬/ཿĎ + + Register 30.3. SENS_SAR_SLAVE_ADDR1_REG (0x003c) + + (reserved) SENS_I2C_SLAVE_ADDR0 SENS_I2C_SLAVE_ADDR1 + +31 22 21 11 10 0 + +0000000000 0x000 0x000 Reset + + SENS_I2C_SLAVE_ADDR0 I²C Ֆࠏֹᆶ 0bč‫؀‬/ཿĎ + SENS_I2C_SLAVE_ADDR1 I²C Ֆࠏֹᆶ 1bč‫؀‬/ཿĎ + + Register 30.4. SENS_SAR_SLAVE_ADDR2_REG (0x0040) + + (reserved) SENS_I2C_SLAVE_ADDR2 SENS_I2C_SLAVE_ADDR3 + +31 22 21 11 10 0 + +0000000000 0x000 0x000 Reset + + SENS_I2C_SLAVE_ADDR2 I²C Ֆࠏֹᆶ 2bč‫؀‬/ཿĎ + SENS_I2C_SLAVE_ADDR3 I²C Ֆࠏֹᆶ 3bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 616 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + Register 30.5. SENS_SAR_SLAVE_ADDR3_REG (0x0044) + + (reserved) SENS_I2C_SLAVE_ADDR4 SENS_I2C_SLAVE_ADDR5 + +31 22 21 11 10 0 + +0000000000 0x000 0x000 Reset + + SENS_I2C_SLAVE_ADDR4 I²C Ֆࠏֹᆶ 4bč‫؀‬/ཿĎ + SENS_I2C_SLAVE_ADDR5 I²C Ֆࠏֹᆶ 5bč‫؀‬/ཿĎ + + Register 30.6. SENS_SAR_SLAVE_ADDR4_REG (0x0048) + + (reservSeEdN) S_I2C_DONE SENS_I2C_RDATA SENS_I2C_SLAVE_ADDR6 SENS_I2C_SLAVE_ADDR7 + +31 30 29 22 21 11 10 0 + +00 0x000 0x000 0x000 Reset + + SENS_I2C_DONE ൕၩ I²C ၘປӮbčᆺ‫؀‬Ď + SENS_I2C_RDATA I²C ‫؀‬౼ඔऌbčᆺ‫؀‬Ď + SENS_I2C_SLAVE_ADDR6 I²C Ֆࠏֹᆶ 6bč‫؀‬/ཿĎ + SENS_I2C_SLAVE_ADDR7 I²C Ֆࠏֹᆶ 7bč‫؀‬/ཿĎ + + Register 30.7. SENS_SAR_I2C_CTRL_REG (0x0050) + + (reservedS) ENSS_SENARS__IS2ACR__SIT2ACR_TS_TFAORRTCE SENS_SAR_I2C_CTRL + +31 30 29 28 27 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + SENS_SAR_I2C_START_FORCE 1ğI²C Ⴎೈࡱఓ‫׮‬Ġ0ğI²C Ⴎ FSM ఓ‫׮‬bč‫؀‬/ཿĎ + SENS_SAR_I2C_START ఓ‫ ׮‬I²Cđࣇ֒ SENS_SAR_I2C_START_FORCE = 1 ൈႵིbč‫؀‬/ཿĎ + SENS_SAR_I2C_CTRL I²C ॥ᇅඔऌđࣇ֒ SENS_SAR_I2C_START_FORCE = 1 ൈႵིbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 617 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + +30.8.2 RTC_I2C ֹᆶॢࡗ + +Чཬࢫও‫ݼ‬ᇏֹ֥ᆶनູཌྷؓႿ (RTC ࠎֹᆶ + 0x0C00) ֹ֥ᆶொ၍ਈčཌྷֹؓᆶĎbRTC ࠎֹᆶ࡮ᅣࢫ 1 ༢๤ +‫ބ‬թԥఖ ᇏ֥і 1-6 ຓഡֹᆶ႘ഝb࠷թఖधֹؓᆶ࡮ᅣࢫ 30.7.2 RTC_I2C ֹᆶॢࡗb + + Register 30.8. RTC_I2C_SCL_LOW_PERIOD_REG (0x000) + + (reserved) RTC_I2C_SCL_LOW_PERIOD + +31 19 18 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_SCL_LOW_PERIOD SCL ൈᇒྐ‫ݼ‬ԩႿ֮‫׈‬௜ൈ֥ᇛ௹ඔbč‫؀‬/ཿĎ + + Register 30.9. RTC_I2C_CTRL_REG (0x004) + + (reserved) RTC_RI2TCC__RRIX2TC_CL_S_TRIBX2T__CLFC_SI_RTBIRS2_ACTF(Nr_IeRMSsS_eSTSr_vTMeAdORR) DTTCE_RI2TCC__SIC2CL__FSODRAC_FEO_ORCUET_OUT + +31 87 6 5 43 21 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_RX_LSB_FIRST Ⴊ༵ࢤ൬ LSBbč‫؀‬/ཿĎ + RTC_I2C_TX_LSB_FIRST Ⴊ༵‫ؿ‬ෂ LSBbč‫؀‬/ཿĎ + RTC_I2C_TRANS_START ఼ᇅӁളष൓่ࡱbč‫؀‬/ཿĎ + RTC_I2C_MS_MODE ࿊ᄴଆൔğ1 սіᇶࠏଆൔĠ0 սіՖࠏଆൔbč‫؀‬/ཿĎ + RTC_I2C_SCL_FORCE_OUT SCL ൻԛଆൔğ1 սі๷ຝൻԛĠ0 սіष੐ൻԛbč‫؀‬/ཿĎ + RTC_I2C_SDA_FORCE_OUT SDA ൻԛଆൔğ1 սі๷ຝൻԛĠ0 սіष੐ൻԛbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 618 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + Register 30.10. RTC_I2C_DEBUG_STATUS_REG (0x008) + +(reserved) RTC_I2C_SCL_SRTATTCE_I2C_MAIN_STATE (reserved) RTC_RI2TCC__BRIY2TCTCE___SRITL2RTACCAV_EN_BRI_SU2ATCSDC__D_ABRIRR2UTC_BSCM__Y_TLARIIO2TMTCCSEC_THD_SI_L2OACUV_ETA_CRKW_VAL + +31 30 28 27 25 24 76 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_SCL_STATE SCL ሑ෿ࠏ֥ሑ෿bč‫؀‬/ཿĎ + RTC_I2C_MAIN_STATE ᇶሑ෿ࠏ֥ሑ෿bč‫؀‬/ཿĎ + RTC_I2C_BYTE_TRANS ൕၩ 8 ໊ԮൻၘປӮbč‫؀‬/ཿĎ + RTC_I2C_SLAVE_ADDR_MATCH Ֆࠏଆൔ༯đ஑؎ֹᆶ൞‫ڎ‬ཌྷ‫ژ‬bč‫؀‬/ཿĎ + RTC_I2C_BUS_BUSY ൕၩᄎෘᆞᄝࣉྛᇏbč‫؀‬/ཿĎ + RTC_I2C_ARB_LOST ᇶࠏଆൔ༯đാಀ I²C ሹཌ॥ᇅbč‫؀‬/ཿĎ + RTC_I2C_TIMED_OUT I²C ๙ྐၘӑൈbč‫؀‬/ཿĎ + RTC_I2C_SLAVE_RW Ֆࠏଆൔ༯đࢤ൬֥֞‫؀‬/ཿ໊֥ᆴbč‫؀‬/ཿĎ + RTC_I2C_ACK_VAL ሹཌഈႋճྐ‫֥ݼ‬ᆴbč‫؀‬/ཿĎ + + Register 30.11. RTC_I2C_TIMEOUT_REG (0x00c) + + (reserved) RTC_I2C_TIMEOUT + +31 20 19 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_TIMEOUT Ԯൻॖၛࢤ൬֥ RTC_FAST_CLK ቋնᇛ௹ඔbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 619 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + Register 30.12. RTC_I2C_SLAVE_ADDR_REG (0x010) + + RTC_I2C_SLAVE_ADDR_10BIT (reserved) RTC_I2C_SLAVE_ADDR + +31 30 15 14 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_SLAVE_ADDR_10BIT ֒ЧֹՖࠏֹᆶູ 10 ໊ൈഡᇂbč‫؀‬/ཿĎ + RTC_I2C_SLAVE_ADDR ЧֹՖࠏֹᆶbč‫؀‬/ཿĎ + + Register 30.13. RTC_I2C_INT_CLR_REG (0x024) + + (reserved) RTC_RI2TCC__TRII2MTCEC___TORIR2UTACCTN___MSIRIN2_ATCTCSC__OTC_AEMILR2RPRCB_L_ITTESRRTLAAEANT_(VrIISeNOEs__TNeCT_r_ORvCLeAMLOdNRPS) SLT_E_CITNOET_M_INCPTLL_RECTLER_INT_CLR + +31 98 7 6 5 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_TIME_OUT_INT_CLR ౢԢӑൈᇏ؎bč‫؀‬/ཿĎ + RTC_I2C_TRANS_COMPLETE_INT_CLR ౢԢ๔ᆸଆൔࡓҩᇏ؎bč‫؀‬/ཿĎ + RTC_I2C_MASTER_TRANS_COMPLETE_INT_CLR ᇶࠏଆൔ༯đౢԢ‫׮‬ቔປӮᇏ؎bč‫؀‬/ཿĎ + RTC_I2C_ARBITRATION_LOST_INT_CLR ᇶࠏଆൔ༯đౢԢാಀሹཌ॥ᇅᇏ؎bč‫؀‬/ཿĎ + RTC_I2C_SLAVE_TRANS_COMPLETE_INT_CLR Ֆࠏଆൔ༯đౢԢ‫׮‬ቔປӮᇏ؎bč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 620 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + Register 30.14. RTC_I2C_INT_EN_REG (0x028) + + (reserved) RTC_RI2TCC__TRII2MTCEC___TORIR2UTACCTN___MSIIN2_ACTCS__OTEAEMNRRPAB_LITTERRT(rAAeENsT_eII_NOrCvTNeO__dMEL)NOPA_SITN_TIN_ETN_EANA + +31 98 7 6 54 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_TIME_OUT_INT_ENA षఓӑൈᇏ؎bč‫؀‬/ཿĎ + RTC_I2C_TRANS_COMPLETE_INT_ENA षఓ๔ᆸଆൔࡓҩᇏ؎bč‫؀‬/ཿĎ + RTC_I2C_MASTER_TRAN_COMP_INT_ENA ᇶࠏଆൔ༯đषఓ‫׮‬ቔປӮᇏ؎bč‫؀‬/ཿĎ + RTC_I2C_ARBITRATION_LOST_INT_ENA ᇶࠏଆൔ༯đषఓാಀሹཌ॥ᇅᇏ؎bč‫؀‬/ཿĎ + + Register 30.15. RTC_I2C_INT_ST_REG (0x02c) + + (reserved) RTC_RI2TCC__TRII2MTCEC___TORIR2UTACCTN___MSIIN2_ACTCS__OTSAEMTRRPB_(LrITTeERsRTeAAErNT_veII_NOdCTN)O__MSLTOP_SITN_TIN_STT_ST + +31 87 6 5 43 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_TIME_OUT_INT_ST ࡓҩ֥֞ӑൈbčᆺ‫؀‬Ď + RTC_I2C_TRANS_COMPLETE_INT_ST ࡓҩ֥֞ I²C ሹཌ๔ᆸଆൔbčᆺ‫؀‬Ď + RTC_I2C_MASTER_TRAN_COMP_INT_ST ᇶࠏଆൔ༯đປӮ‫׮‬ቔbčᆺ‫؀‬Ď + RTC_I2C_ARBITRATION_LOST_INT_ST ᇶࠏଆൔ༯đሹཌാಀ॥ᇅbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 621 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + Register 30.16. RTC_I2C_SDA_DUTY_REG (0x030) + + (reserved) RTC_I2C_SDA_DUTY + +31 20 19 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_SDA_DUTY SCL ༯ࢆခა SDA ్ߐᆭࡗ֥ RTC_FAST_CLK ᇛ௹ඔbč‫؀‬/ཿĎ + + Register 30.17. RTC_I2C_SCL_HIGH_PERIOD_REG (0x038) + + (reserved) RTC_I2C_SCL_HIGH_PERIOD + +31 20 19 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_SCL_HIGH_PERIOD SCL ູ֥ۚ RTC_FAST_CLK ᇛ௹ඔbč‫؀‬/ཿĎ + + Register 30.18. RTC_I2C_SCL_START_PERIOD_REG (0x040) + + (reserved) RTC_I2C_SCL_START_PERIOD + +31 20 19 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_SCL_START_PERIOD Ӂളष൓่ࡱభđླေ֩ր֥ RTC_FAST_CLK ᇛ௹ඔbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 622 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 30 ӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP) + + Register 30.19. RTC_I2C_SCL_STOP_PERIOD_REG (0x044) + + (reserved) RTC_I2C_SCL_STOP_PERIOD + +31 20 19 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_I2C_SCL_STOP_PERIOD Ӂള๔ᆸ่ࡱభđླေ֩ր֥ RTC_FAST_CLK ᇛ௹ඔbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 623 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + +31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + +31.1 ‫ۀ‬ඍ + +ESP32 ҐႨਔིۚaਲࠃ֥‫ܵݻۿ‬৘࠯ඌđॖၛᄝ‫ݻۿ‬॥ᇅaߒྜ࿼Ӿ‫ބ‬҂๝ߒྜჷᆭࡗൌགྷቋࡄ௜‫ޙ‬bྉோ +֥ᇶԩ৘ఖᆦӻ 5 ᇕ‫ݻۿ‬ଆൔđॖၛડቀႨ޼֥҂๝ӆࣟླ౰bՎຓđESP32 ߎᆦӻӑ֮‫ླྀݻۿ‬ԩ৘ఖ (ULP +Co-processor) ॥ᇅđᄍྸᇶԩ৘ఖࣉೆ Deep-sleep ଆൔđՖ‫ط‬ቋնӱ؇ࢆ֮‫ݻۿ‬đᆦӻႨ޼֥֮‫ݻۿ‬ႋ +Ⴈb + +31.2 ᇶေหྟ + + • ᆦӻ 5 ᇕყഡ‫ݻۿ‬ଆൔđൡႨႿ‫؟‬ᇕႋႨӆࣟ + • ᆦӻۚղ 16 KB Ќ਽ଽթ (Retention Memory) + • 8 x 32-bit Ќ਽࠷թఖ (Retention Register) + • ෮Ⴕ֮‫ݻۿ‬ଆൔनᆦӻ ULP ླྀԩ৘ఖ॥ᇅ + • ᆦӻ RTC boot ‫ିۿ‬đॖ෪؋ߒྜ࿼Ӿ + + ๭ 31­1. ESP32 ‫ݻۿ‬॥ᇅൕၩ๭ + +31.3 ‫ିۿ‬૭ඍ 624 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ +ুᶈྐ༏॓࠯ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + +31.3.1 ࡥࢺ + +ESP32 ֥֮‫ܵݻۿ‬৘ֆჭЇও‫ט‬࿢ఖa‫ݻۿ‬॥ᇅఖa‫׈‬ჷषܱֆჭa‫׈‬ჷთ‫ۯ‬৖ֆჭ (Isolation Cell) ֩҆‫ٳ‬đऎ +ุࢲ‫ܒ‬ൕၩ๭ॖ࡮ഈٚ๭ 31-1b + +31.3.2 ඔሳଽ‫טނ‬࿢ఖ + +ESP32 ֥ଽᇂඔሳଽ‫טނ‬࿢ఖॖၛࡼຓ҆‫׈‬ჷ‫׈‬࿢č๙ӈູ 3.3VĎሇߐູ 1.1Vđᆦӻඔሳଽ‫֥ނ‬ᆞӈ‫۽‬ቔb +‫טھ‬࿢ఖॖၛࢤ൳֥ຓ҆ൻೆ‫׈‬࿢ٓຶູ 1.8V ֞ 3.6Vđൻԛ‫׈‬࿢ٓຶູ 0.90V ֞ 1.25Vbऎุࢲ‫ܒ‬ൕၩ๭ॖ +࡮༯ٚ๭ 31-2b + + 1. ֒ XPD_DIG_REG == 1 ൈđ‫טھ‬࿢ఖ֥ൻԛ‫׈‬࿢ູ 1.1Vđඔሳଽ‫ނ‬ॖၛᆞӈ‫۽‬ቔĠ֒ XPD_DIG_REG == + 0 ൈđ‫ט‬࿢ఖ‫ބ‬ඔሳଽ‫ނ‬न໭‫۽م‬ቔb + + 2. DIG_REG_DBIAS[2:0] ॖၛ‫ࢫט‬ඔሳଽ‫׈׈܂֥ނ‬࿢ğ + + VDD_DIG = 0.90 + DBIAS · 0.05V + + 3. ੀೆඔሳଽ‫׈֥ނ‬ੀটሱܵ࢖ VDD3P3_CPU ‫ ބ‬VDD3P3_RTCb + + 90 + + ๭ 31­2. ඔሳଽ‫טނ‬࿢ఖ + +31.3.3 ֮‫טݻۿ‬࿢ఖ + +ESP32 ֥ଽᇂ֮‫טݻۿ‬࿢ఖॖၛࡼຓ҆‫׈‬ჷ‫׈‬࿢č๙ӈູ 3.3VĎሇߐູ 1.1Vđᆦӻଽ҆ RTC ඔሳଽ‫֥ނ‬ᆞӈ +‫۽‬ቔbູਔࢆ֮‫ݻۿ‬đ‫טھ‬࿢ఖॖၛࢤ൳֥ຓ҆ൻೆ‫׈‬࿢ٓຶູ 1.8V ֞ 3.6Vđൻԛ‫׈‬࿢ٓຶॖ‫ט‬ğᆞӈ‫۽‬ቔ +ଆൔ༯֥‫׈‬࿢ൻԛٓຶູ 0.90V ֞ 1.25VĠDeep-sleep ‫ބ‬ඤ૤ଆൔ༯֥‫׈‬࿢ൻԛ‫ ູקܥ‬0.75VĠྨ૤ଆൔ༯֥ +‫׈‬࿢ൻԛ۷֮bऎุࢲ‫ܒ‬ൕၩ๭ॖ࡮༯ٚ๭ 31-3b + + 1. ֒ܵ࢖ CHIP_PU ູۚ‫׈‬௜ൈđ֮‫טݻۿ‬࿢ఖ໭‫ܱم‬оđࣇିᄝᆞӈ‫ ބ‬Deep-sleep ଆൔᆭࡗࣉྛ్ߐb + + 2. ᄝᆞӈଆൔ༯đRTC_DBIAS[2:0] ॖၛ‫ࢫט‬ൻԛ‫׈‬࿢ğ + +ুᶈྐ༏॓࠯ 625 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + VDD_RTC = 0.90 + DBIAS · 0.05V + 3. ᄝ Deep-sleep ଆൔ༯đ‫ט‬࿢ఖ֥ൻԛ‫׈‬࿢‫ ູקܥ‬0.75Vb + 4. ੀཟ RTC ඔሳଽ‫׈֥ނ‬ੀটሱܵ࢖ VDD3P3_RTCb + + 90 + + ๭ 31­3. ֮‫טݻۿ‬࿢ఖ + +31.3.4 Flash ‫ט‬࿢ఖ + +ESP32 ֥ଽᇂ flash ‫ט‬࿢ఖॖၛཟ༢๤ᇏ֥ః෰ഡСൻԛ 3.3V ࠇ 1.8V ‫׈‬࿢đбೂ flashb‫טھ‬࿢ఖ֥ቋն‫׈‬ੀ +ൻԛູ 40 mAbऎุࢲ‫ܒ‬ൕၩ๭ॖ࡮༯ٚ๭ 31-4b + + 1. ֒ XPD_SDIO_VREG == 1 ൈđ‫ט‬࿢ఖ֥ൻԛ‫׈‬࿢ູ 3.3V ࠇ 1.8VĠ֒ XPD_SDIO_VREG == 0 ൈđ‫ט‬࿢ఖ + ֥ൻԛ‫׈‬࿢ູۚቅॆđ‫׈‬࿢Ⴎຓ҆‫׈‬ჷ‫܂‬ႋb + + 2. ֒ SDIO_TIEH == 1 ൈđ‫ט‬࿢ఖࡼܵ࢖ VDD_SDIO ‫ ࢖ܵބ‬VDD3P3_RTC ؋ਫ਼đ‫׈‬࿢ൻԛູ 3.3Vđࠧܵ࢖ + VDD3P3_RTC ֥‫׈‬࿢Ġ֒ SDIO_TIEH == 0 ൈđ‫ט‬࿢ఖ֥‫׈‬࿢ൻԛູҕॉ‫׈‬࿢ VREFđ๙ӈູ 1.8Vb + + 3. ۷‫ ڿ‬DREFH_SDIOaDREFM_SDIO ‫ ބ‬DREFL_SDIO ॖၛཬ‫ࢫטږ‬ҕॉ‫׈‬࿢ VREFđ֌ᆃᇕҠቔॖି߶႕ + ཙ༢๤ଽߌ֥໗‫ྟק‬đၹՎ҂๷ࡩࣉྛ۷‫ڿ‬b + + 4. ֒‫ט‬࿢ఖൻԛູ 3.3V ࠇ 1.8V ൈđൻԛ‫׈‬ੀটሱܵ࢖ VDD3P3_RTCb + +ুᶈྐ༏॓࠯ 626 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + ๭ 31­4. Flash ‫ט‬࿢ఖ + +31.3.5 ఴ࿢࡟ҩఖ + +ESP32 ֥ఴ࿢࡟ҩఖॖၛ࡟Ұܵ࢖ VDD3P3_RTC ֥‫׈‬࿢b֒‫׈‬࿢ॹ෎༯ઋᇀ၂‫ק‬ඣ௜đఴ࿢࡟ҩఖࡼ‫ؿ‬ԛԨ +‫ݼྐؿ‬đܱо҆‫׈ݻٳ‬ଆॶčбೂ LNA ‫ ބ‬PA ֩ĎđՖ‫ູط‬ඔሳଆॶᆚ౼۷‫؟‬ൈࡗđႨၛЌթaሇ၍ᇗေඔऌb +ఴ࿢࡟ҩఖ֥‫ݻۿ‬٤ӈ֮đࡼᄝྉோषఓൈႥჹЌӻषఓđऎุ֥ྐ‫ݼ‬Ԩ‫ؿ‬ᚐᆴॖၛ‫ࢫט‬đ๙ӈູ 2.5Vbऎุ +ࢲ‫ܒ‬ൕၩ๭ॖ࡮༯ٚ๭ 31-5b + + 1. RTC_CNTL_BROWN_OUT_DET ູఴ࿢࡟ҩఖ֥ൻԛ‫׈‬௜đࡼᄝܵ࢖ VDD3P3_RTC ‫׈‬࿢֮Ⴟᚐᆴൈ๋ᇀ + ۚ‫׈‬௜b + + 2. RTC_CNTL_DBROWN_OUT_THRES[2:0] ॖႨႿ‫ࢫט‬ఴ࿢࡟ҩఖ֥ྐ‫ݼ‬Ԩ‫ؿ‬ᚐᆴđ๙ӈູ 2.5Vb + + ๭ 31­5. ఴ࿢࡟ҩఖ + +31.3.6 RTC ଆॶ + +ESP32 ֥ RTC ଆॶࣜ‫ݖ‬ህ૊ഡ࠹đॖႨႿܵ৘֮‫ݻۿ‬ଆൔ֥ࣉೆ‫ބ‬๼ԛđ॥ᇅൈᇒჷaPLLa‫׈‬ჷषܱ‫ۯބ‬৖ +ֆჭၛӁള‫׈‬ჷ૊॥aൈᇒ૊॥‫ݼྐ໊گބ‬bRTC ଆॶ֥ࢲ‫ܒ‬๭ॖ࡮๭ 31-6đᇶေ҆‫ٳ‬Їওğ + + • RTC ᇶሑ෿ࠏ⚶⚶࠺੣‫׈‬ჷሑ෿b + + • ඔሳ & ଆ୅‫׈‬ჷ॥ᇅఖ⚶⚶ॖႨႿູ RTC ֥ඔሳଆॶ‫ބ‬ଆ୅ଆॶളӮ‫׈‬ჷ૊॥Ĕൈᇒ૊॥ྐ‫ݼ‬b + + • ඤ૤ & ߒྜ॥ᇅఖ⚶⚶ॖԩ৘֮‫ݻۿ‬ଆൔ֥ࣉೆ‫ބ‬๼ԛb + + • ࠹ൈఖ⚶⚶Їও RTC ᇶ࠹ൈఖaULP ླྀԩ৘ఖ࠹ൈఖ‫ބ‬Ԩଃ࠹ൈఖb + +ুᶈྐ༏॓࠯ 627 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + • ֮‫ݻۿ‬ԩ৘ఖ‫ބ‬Ԯ‫ۋ‬ఖ॥ᇅఖ⚶⚶ULP ླྀԩ৘ఖaԨଃ॥ᇅఖaSAR ADC ॥ᇅఖ֩b + • Ќ਽ଽթ + + – RTC ત෎ଽթ⚶⚶ᆦӻ 8 KB SRAMđधն҆‫ٳ‬ႨቔЌ਽ଽթࠇթԥ ULP ླྀԩ৘ఖ֥ᆷ਷ & ඔऌଽթb + CPU ॖ๙‫ ݖ‬APB ሹཌ٠໙ત෎ଽթđఏ൓ֹᆶູ 0x50000000b + + – RTC ॹ෎ଽթ⚶⚶ᆦӻ 8 KB SRAMđधն҆‫ٳ‬ႨቔЌ਽ଽթbCPU ॖ๙‫ ݖ‬IRAM0/DRAM0 ٠໙ॹ෎ + ଽթbRTC ॹ෎ଽթ֥෎؇ჿູ RTC ત෎ଽթ֥ 10 Пb + + • Ќ਽࠷թఖ⚶⚶8 x 32 ໊b‫࠷ھ‬թఖႥჹषఓđॖႨႿඔऌթԥb + • RTC IO ܵ࢖⚶⚶18 ۱oalways-onpܵ࢖đ๙ӈቔູߒྜჷb + + ๭ 31­6. RTC ࢲ‫ܒ‬๭ + +31.3.7 ֮‫ݻۿ‬ൈᇒ + +ᄝ֮‫ݻۿ‬ଆൔ༯đESP32 ֥ 40 MHz ࣖᆒ‫ ބ‬PLL ๙ӈࡼ؎‫׈‬ၛࢆ֮‫ݻۿ‬đ֌ൈᇒಯࡼषఓđၛಒЌྉோᄝ֮‫ۿ‬ +‫ݻ‬ଆൔ༯֥ᆞӈ‫۽‬ቔb + +RTC ଽ‫ނ‬ॖၛ൐Ⴈ 5 ۱ൈᇒჷğ + +ুᶈྐ༏॓࠯ 628 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + • ຓ֮҆෎ࣖᆒൈᇒ CK_XTAL_32K (32.768 kHz) + • ຓ҆ۚ෎ࣖᆒൈᇒ CK_40M_DIG (2 MHz ~ 40 MHz) + • ଽ҆ RC ᆒ֕ఖ SLOW_CKč௔ੱॖ‫ט‬đ๙ӈູ 150 kHzĎ + • ଽ҆ 8 MHz ᆒ֕ఖ CK8M_OUT + • ଽ҆ 31.25 kHz ൈᇒ CK8M_D256_OUTčটሱଽ҆ 8 MHz ᆒ֕ఖđ256 ‫ٳ‬௔Ď +ᆃུൈᇒॖၛӁള fast_rtc_clk ‫ ބ‬slow_rtc_clk bଏಪ౦ঃ༯đfast_rtc_clk ࿊ᄴ CK8M_OUTđslow_rtc_clk ࿊ᄴ +SLOW_CKđऎุॖ࡮๭ 31-7b + + ๭ 31­7. RTC ֮‫ݻۿ‬ൈᇒ +ؓႿඔሳଽ‫ނ‬đlow_power_clk ॖᄝ 4 ۱ൈᇒჷᆭࡗ్ߐđऎุॖ࡮๭ 31-8b + + ๭ 31­8. ඔሳ֮‫ݻۿ‬ൈᇒ + +ুᶈྐ༏॓࠯ 629 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + +31.3.8 ‫׈‬ჷ૊॥֥ൌགྷ + + ๭ 31­9. RTC ሑ෿ + +‫׈‬ჷ૊॥ሇ߄๭ऎุॖ࡮๭ 31-9bൌ࠽‫׈‬ჷ॥ᇅྐ‫ݼ‬ॖ๙‫ݖ‬ೈࡱഡᇂ఼ູᇅषఓ (FPU) ࠇ఼ᇅܱо (FPD)b‫׈‬ +ჷთᆦӻ‫׿‬৫‫׈‬ჷ૊॥đॖᆌؓ‫؟‬ᇕ҂๝ႋႨӆࣟࣉྛऎุቆ‫ކ‬bі 31-1 ᅚൕਔ ESP32 ‫׈‬ჷთ֥॥ᇅٚ +ൔb + + і 31­1. RTC ‫׈‬ჷთ + + ‫׈‬ჷთ RTC ᇶေሑ෿ ೈࡱ࿊ཛ ᇿၩ * + + ඔሳଽ‫ނ‬ DIG ࠃᄁ RTC ࠃᄁ RTC ඤ૤ յष ܱо 1 + RTC ຓຶ ON 2 + RTC ત෎ଽթ ON ON ON N N 3 + RTC ॹ෎ଽթ ON 4 +RTC ඔሳଽ‫ނ‬ ON ON OFF Y Y 5 +ඔሳ Wi-Fi ON 6 +ଆ୅ ROM ON OFF OFF Y Y - + ଽ҆ SRAM ON 7 + 40 MHz ࣖᆒ ON OFF OFF Y Y - + PLL ON - + 8 MHz ᆒ֕ఖ ON OFF OFF Y Y - + ഝ௔ ON - + - OFF OFF Y Y + + OFF OFF Y Y + + OFF OFF Y Y + + OFF OFF Y Y + + OFF OFF Y Y + + OFF OFF Y Y + + - - Y Y + +ুᶈྐ༏॓࠯ 630 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + +ᇿၩ *ğ +1. ‫׈‬ჷთ RTC ඔሳଽ‫ູނ‬oalways-onp‫׈‬ჷთđFPU/FPD ࿊ཛ҂ॖႨb +2. ‫׈‬ჷთ RTC ຓഡଽ‫ ݣ‬RTC თ֥ն‫؟‬ඔॹ෎આࠠଆॶđЇও ULP ླྀԩ৘ఖaԮ‫ۋ‬ఖ॥ᇅఖ֩b +3. ‫׈‬ჷთ RTC ત෎ଽթᄝႨቔЌ਽ଽթࠇᄝ ULP ླྀԩ৘ఖ‫۽‬ቔൈđႋ఼ᇅषఓb +4. ‫׈‬ჷთ RTC ॹ෎ଽթᄝႨቔЌ਽ଽթൈđႋ఼ᇅषఓb +5. ֒‫׈‬ჷთඔሳଽ‫ܱނ‬оൈđ‫׈‬ჷთᇏ֥෮Ⴕଆॶनܱоb +6. ‫׈‬ჷთ Wi-Fi Їও Wi-Fi MAC ‫ ބ‬BBb +7. ૄ۱ଽ҆ SRAM नᆦӻ‫׿‬৫‫׈‬ჷ૊॥b + +31.3.9 ყഡ‫ݻۿ‬ଆൔ + +ESP32 ᆦӻ 5 ᇕყഡ‫ݻۿ‬ଆൔđॖၛ‫ۂڭ‬धն‫؟‬ඔႋႨӆࣟbၹՎđႨ޼ᄝሱྛ‫ט‬ᆜ۲۱‫׈‬ჷ॥ᇅྐ‫ݼ‬భđႋ +൮༵Ӈ൫ᆃ 5 ᇕ‫ݻۿ‬ଆൔି‫ڎ‬ડቀေ౰đऎุЇওğ + + • Active ଆൔ + – CPU ֥‫۽‬ቔൈᇒູ XTAL_DIV_N (40 MHz/26 MHz) ࠇ PLL (80 MHz/160 MHz/240 MHz)b + – ྉோॖၛࢤ൬a‫ؿ‬ഝࠇࡓ๐ྐ‫ݼ‬b + + • Modem-sleep ଆൔ + – CPU ॖၛ‫۽‬ቔđൈᇒॖၛ஥ᇂb + – Wi-Fi Ĕড࿩ࠎջ൳ൈᇒ૊ཋ॥ᇅࠇܱоđഝ௔ଆॶܱоb + – PLL ູ 80 MHz ൈđ‫׈‬ੀཨ‫ݻ‬ğ∼30 mAb + – XTAL ູ 2 MHz ൈđ‫׈‬ੀཨ‫ݻ‬ğ∼3 mAb + – ࠧख़ߒྜb + + • Light-sleep ଆൔ + – ଽ҆ 8 MHz ᆒ֕ఖa40 MHz ۚ෎ࣖᆒaPLL ࠣഝ௔ଆॶन࣌Ⴈb + – ඔሳଽ‫ނ‬ൈᇒ൳૊ཋཋᇅđCPU ᄠ๔‫۽‬ቔb + – ULP ླྀԩ৘ఖ‫ބ‬Ԩଃ॥ᇅఖॖၛᇛ௹ྟԨ‫ؿ‬đؓԮ‫ۋ‬ఖࣉྛࡓҩb + – ‫׈‬ੀཨ‫ݻ‬ğ∼ 800 µAb + – ߒྜ࿼Ӿğ֮Ⴟ 1 msb + + • Deep-sleep ଆൔ + – ଽ҆ 8 MHz ᆒ֕ఖa40 MHz ۚ෎ࣖᆒaPLL ࠣഝ௔ଆॶन࣌Ⴈb + – ඔሳଽ‫׈؎ނ‬đCPU ଽಸ‫ש‬ാb + – RTC ଽ‫׈׈܂֥ނ‬࿢ࢆᇀ 0.7Vb + – 8 x 32 ໊ඔऌЌթᄝ๙ႨЌ਽࠷թఖᇏb + +ুᶈྐ༏॓࠯ 631 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + – RTC ଽթ‫ॹބ‬෎ RTC ଽթॖၛЌӻb + – ‫׈‬ੀཨ‫ݻ‬ğ∼ 6.5 µAb + – ߒྜ࿼Ӿğ֮Ⴟ 1 msb + – ๷ࡩႨႿ၂ུ٤௔َ৵ࢤ Wi-Fi Ĕড࿩֥ӑ֮‫ݻۿ‬ႋႨӆࣟb + • ྨ૤ଆൔ + – ଽ҆ 8 MHz ᆒ֕ఖa40 MHz ۚ෎ࣖᆒaPLL ࠣഝ௔ଆॶन࣌Ⴈb + – ඔሳଽ‫׈؎ނ‬đCPU ଽಸ‫ש‬ാb + – RTC ຓഡთ؎‫׈‬b + – RTC ଽ‫׈׈܂֥ނ‬࿢ࢆᇀ 0.7Vb + – 8 x 32 ໊ඔऌЌթᄝ๙ႨЌ਽࠷թఖᇏb + – RTC ଽթ‫ॹބ‬෎ RTC ଽթ؎‫׈‬b + – ‫׈‬ੀཨ‫ݻ‬ğ∼ 4.5 µAb + – ߒྜჷğࣇᆦӻ RTC ࠹ൈఖb + – ߒྜ࿼Ӿğ֮Ⴟ 1 msb + – ๷ࡩႨႿ၂ུ٤௔َ৵ࢤ Wi-Fi Ĕড࿩֥ӑ֮‫ݻۿ‬ႋႨӆࣟb + + ๭ 31­10. ‫ݻۿ‬ଆൔ + +ଏಪ౦ঃ༯đESP32 ༢๤‫ࣉࡼު໊گ‬ೆ Active ଆൔb֒ CPU ҂ླေ၂ᆰ‫۽‬ቔൈđбೂ֒֩րຓ҆ࠃ‫ྜߒ׮‬ൈđ +༢๤ॖၛࣉೆ‫؟‬ᇕ֮‫ݻۿ‬ଆൔbႨ޼ॖ۴ऌऎุ‫ݻۿ‬aߒྜ࿼Ӿ‫ބ‬ॖႨߒྜჷླ౰đᄝ۲ᇕ‫ݻۿ‬ଆൔᇏࣉྛ࿊ +ᄴbབྷ࡮๭ 31-10b + +ুᶈྐ༏॓࠯ 632 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + +ᆴ֤၂ิ֥൞đESP32 ֥ყഡ‫ݻۿ‬ଆൔॖᆦӻࣉ၂҄Ⴊ߄đၛൡႋ҂๝֥ႋႨӆࣟb + +31.3.10 ߒྜჷ + +ESP32 ॖᆦӻ‫؟‬ᇕߒྜჷđॖࡼ CPU Ֆ҂๝ඤ૤ଆൔᇏߒྜbߒྜჷ֥࿊ᄴႮ RTC_CNTL_WAKEUP_ENA थ +‫ק‬đ࡮і 31-2b + + і 31­2. ߒྜჷ + + WAKEUP_ENA ߒྜჷ Light-sleep Deep-sleep ྨ૤ ᇿၩ * + 0x1 EXT0 Y Y - 1 + 0x2 EXT1 Y Y Y 2 + 0x4 GPIO Y Y - 3 + 0x8 RTC ࠹ൈఖ Y Y Y - + 0x10 SDIO Y - - 4 + 0x20 Wi-Fi Y - - 5 + 0x40 UART0 Y - - 6 + 0x80 UART1 Y - - 6 + 0x100 TOUCH Y Y - - + 0x200 ULP ླྀԩ৘ఖ Y Y - - + 0x400 BT Y - - 5 + +ᇿၩ *ğ + +1. EXT0 ࣇॖࡼྉோՖ Light-sleep/Deep-sleep ଆൔᇏߒྜb֒ RTC_CNTL_EXT_WAKEUP0_LV ູ 1 ൈࡼԨ‫ؿ‬ +ܵ࢖ۚ‫׈‬௜đ‫ڎ‬ᄵࡼԨ‫׈֮࢖ܵؿ‬௜bႨ޼ॖ๙‫ݖ‬ഡᇂ RTCIO_EXT_WAKEUP0_SEL[4:0]đ࿊ᄴࡼቔູߒྜჷ +֥ RTC ܵ࢖b + +2. EXT1 ࣜ‫ݖ‬ህ૊ഡ࠹đॖࡼྉோՖ಩‫ޅ‬ඤ૤ଆൔᇏߒྜđ‫ߎ౏ط‬ᆦӻ‫؟‬۱ܵ࢖֥ቆ‫ކ‬b൮༵đႋοᅶ࿊‫ק‬ቔ +ູߒྜჷ֥ܵ࢖໊๭đ஥ᇂ RTC_CNTL_EXT_WAKEUP1_SEL[17:0]bࢤሢđ֒ RTC_CNTL_EXT_WAKEUP1_LV +ູ 1 ൈđᆺေႵ಩‫ޅ‬࿊ᄴ֥ܵ࢖ູۚ‫׈‬࿢đᄵࡼԨ‫ྜߒݼྐؿ‬ྉோĠ֒ RTC_CNTL_EXT_WAKEUP1_LV ູ 0 +ൈđᄵсྶಆ҆࿊ᄴ֥ܵ࢖नູ֮‫׈‬࿢Ҍ߶Ԩ‫ݼྐؿ‬b + +3. ᄝ Deep-sleep ଆൔ༯đࣇႵ RTC GPIO ॖၛቔູߒྜჷđ‫ط‬٤ඔሳ GPIOb + +4. ಩‫ࢤޅ‬൬֥֞ SDIO ଁ਷नࡼԨ‫׮ྜߒؿ‬ቔb + +5. ູਔ๙‫ ݖ‬Wi-Fi ࠇ BT ჷߒྜྉோđྉோࡼᄝ ActiveaModem-sleep ‫ ބ‬Light-sleep ᆭࡗࣉྛ్ߐđCPUa +Wi-FiaBluetooth ‫ބ‬ഝ௔ଆॶनࡼᄝყഡࡗ‫ۯ‬ᇏߒྜđЌᆣ Wi-Fi/ড࿩֥ᆞӈ৵ࢤb + +6. ֒ൻೆ RxD ခэ߄֥ՑඔնႿ֩Ⴟ (UART_ACTIVE_THRESHOLD+2) ൈđࠧԨ‫ྜߒؿ‬bᇿၩğRxD ҂ି๙‫ݖ‬ +GPIO ࢌߐइᆔൻೆđᆺି๙‫ ݖ‬IO_MUX ൻೆb + +31.3.11 RTC ࠹ൈఖ + +RTC ࠹ൈఖູ၂۱ॖ‫ ؀‬48-bit ࠹ඔఖđൈᇒູ RTC_SLOW_CLKbԢഈ‫໊گ׈‬ຓఃჅ಩‫໊گޅ‬Ĕඤ૤न҂߶൐ +RTC ࠹ൈఖ๔ᆸࠇ‫໊گ‬b + +RTC ࠹ൈఖॖၛᄝᆷ‫ק‬ൈࡗߒྜ CPUđѩᇛ௹ྟߒྜԨଃ॥ᇅఖ‫ ބ‬ULP ླྀԩ৘ఖb + +31.3.12 RTC Boot + +ႮႿ CPU ֥ ROM ‫ ބ‬RAM ଽթनࡼᄝ Deep-sleep ‫ྨބ‬૤ଆൔ༯؎‫׈‬đ‫ ط‬ROM ࢳЇა SPI ఓ‫׮‬čՖ flash ᇏ +‫گ‬ᇅඔऌĎनླေൈࡗđၹՎᆃਆᇕଆൔ༯֥ߒྜ‫ݖ‬ӱनб Light-sleep ‫ ބ‬Modem-sleep ଆൔӉ֥‫؟‬bRTC თ + +ুᶈྐ༏॓࠯ 633 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + +ᇏႵ 2 ᇕ SRAM ଽթđ‫ٳ‬љູ RTC ત෎ଽթ‫ ބ‬RTC ॹ෎ଽթbᆃ 2 ᇕ SRAM ଽթनࡼᄝ Deep-sleep ଆൔ༯ +Ќӻषఓb၂ུս઒ܿଆ҂ն֥ႋႨčཬႿ 8 KBĎॖ๙‫ݖ‬ਆᇕٚ‫م‬đх૧ ROM ࢳЇࠇ SPI ఓ‫׮‬đՖ‫ࡆط‬෎ྉ +ோߒྜ‫ݖ‬ӱb +ֻ၂ᇕٚ‫م‬ğ൐Ⴈ RTC ત෎ଽթ + + 1. ഡᇂ PRO_CPU ࠷թఖ RTC_CNTL_PROCPU_STAT_VECTOR_SELčࠇഡᇂ APP_CPU + ࠷թఖ RTC_CNTL_APPCPU_STAT_VECTOR_SELĎູ 0b + + 2. ྉோࣉೆඤ૤ଆൔb + 3. ֒ CPU षఓൈđ‫໊گ‬ཟਈࡼՖֹᆶ 0x50000000đ‫ط‬٤ 0x40000400 ष൓‫໊گ‬đᆜ۱‫ݖ‬ӱѩ҂ླေࣉྛ + + ROM ࢳЇ‫ ބ‬SPI bootbRTC ଽթᇏ֥ս઒ࣇླᄝ C ე࿽ߌ࣢ᇏࣉྛ҆‫ٳ‬Ԛ൓߄Ҡቔࠧॖb +ֻ‫ؽ‬ᇕٚ‫م‬ğ൐Ⴈ RTC ॹ෎ଽթ + + 1. ഡᇂ PRO_CPU ࠷թఖ RTC_CNTL_PROCPU_STAT_VECTOR_SELčࠇഡᇂ APP_CPU + ࠷թఖ RTC_CNTL_APPCPU_STAT_VECTOR_SELĎູ 1b + + 2. ࠹ෘ RTC ॹ෎ଽթ֥ CRC ઒đѩࡼࢲ‫ݔ‬Ќթᄝ࠷թఖ RTC_CNTL_RTC_STORE6_REG[31:0] ᇏb + 3. ࡼ RTC ॹ෎ଽթ֥ೆ१ֹᆶൻೆ࠷թఖ RTC_CNTL_RTC_STORE7_REG[31:0]b + 4. ྉோࣉೆඤ૤ଆൔb + 5. CPU षఓđᄝປӮ ROM ࢳЇࠣ҆‫ٳ‬Ԛ൓߄‫۽‬ቔުđᄜՑ࠹ෘ CRC ઒bೂ‫࠹ݔ‬ෘࢲ‫ݔ‬ა࠷թఖ + + RTC_CNTL_RTC_STORE6_REG[31:0] ၂ᇁđᄵ CPU ࡼ๋ሇᇀೆ१ֹᆶb +ESP32 ֥ఓ‫׮‬ੀӱ๭ູ๭ 31-11b + +ুᶈྐ༏॓࠯ ๭ 31­11. ESP32 ఓ‫׮‬ੀӱ๭ ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + + 634 + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + +31.4 ࠷թఖਙі + +ඪૼğ + +• ၛ༯࠷թఖၘοᅶऎุ‫ٳྛࣉିۿ‬ቆđ֌ਙіᇏ֥ඨ྽ѩ҂ّ႘࠷թఖᄝଽթᇏ֥ᆇൌඨ྽b + +• ೂ‫ݔ‬Ֆ AHB ሹཌࣉྛ٠໙đᄵ࠷թఖ֥ࠎᆶູ 0x60008000Ġೂ‫ݔ‬Ֆ DPORT ሹཌࣉྛ٠໙đᄵ࠷թఖ֥ + ࠎᆶູ 0x3FF48000b + +଀ӫ ૭ඍ ֹᆶ ٠໙ٚൔ + +RTC ࿊ཛ࠷թఖ 0x3FF48000 ‫؀‬Ĕཿ + +RTC_CNTL_OPTIONS0_REG ஥ᇂ RTC ࿊ཛ 0x3FF48004 ‫؀‬Ĕཿ + 0x3FF48008 ‫؀‬Ĕཿ +RTC ࠹ൈఖ࠷թఖ֥॥ᇅა஥ᇂ 0x3FF4800C ᆺ‫؀‬ + 0x3FF48010 ᆺ‫؀‬ +RTC_CNTL_SLP_TIMER0_REG RTC ඤ૤࠹ൈఖ 0x3FF48014 ᆺ‫؀‬ + 0x3FF48018 ‫؀‬Ĕཿ +RTC_CNTL_SLP_TIMER1_REG RTC ඤ૤࠹ൈఖaࣞБ‫ބ‬॥ᇅ 0x3FF4801C ‫؀‬Ĕཿ + 0x3FF48020 ‫؀‬Ĕཿ +RTC_CNTL_TIME_UPDATE_REG RTC ࠹ൈఖ֥۷ྍ॥ᇅ 0x3FF4802C ‫؀‬Ĕཿ + +RTC_CNTL_TIME0_REG RTC ࠹ൈఖ֮ 32 ໊ 0x3FF48034 ᆺ‫؀‬ + 0x3FF48038 ᆺ‫؀‬ +RTC_CNTL_TIME1_REG RTC ࠹ൈఖۚ 16 ໊ 0x3FF48060 ‫؀‬Ĕཿ + +RTC_CNTL_STATE0_REG RTC ඤ૤aSDIO ‫ ބ‬ULP ॥ᇅ 0x3FF480CC ‫؀‬/ཿ + +RTC_CNTL_TIMER1_REG CPU ֩ր൐ି 0x3FF480D0 ᆺ‫؀‬ + +RTC_CNTL_TIMER2_REG ત෎ൈᇒ‫ބ‬Ԩଃ॥ᇅఖ஥ᇂ 0x3FF4803C ‫؀‬Ĕཿ + 0x3FF48040 ᆺ‫؀‬ +RTC_CNTL_TIMER5_REG ત෎ൈᇒ༯֥ቋཬඤ૤ᇛ௹ 0x3FF48044 ᆺ‫؀‬ + 0x3FF48048 ᆺཿ +‫໊گ‬ሑ෿აߒྜ॥ᇅ࠷թఖ + 0x3FF4804C ‫؀‬Ĕཿ +RTC_CNTL_RESET_STATE_REG CPU ‫໊گ‬ሑ෿॥ᇅაჰၹ 0x3FF48050 ‫؀‬Ĕཿ + 0x3FF48054 ‫؀‬Ĕཿ +RTC_CNTL_WAKEUP_STATE_REG ߒྜ‫ݖ‬ੲఖa൐ିაჰၹ 0x3FF48058 ‫؀‬Ĕཿ + 0x3FF480B0 ‫؀‬Ĕཿ +RTC_CNTL_EXT_WAKEUP_CONF_REG ֮/ۚ‫׈‬௜ߒྜ஥ᇂ 0x3FF480B4 ‫؀‬Ĕཿ + 0x3FF480B8 ‫؀‬Ĕཿ +RTC_CNTL_EXT_WAKEUP1_REG ຓ҆ߒྜ໊აߒྜౢԢ໊֥ܵ࢖ 0x3FF480BC ‫؀‬Ĕཿ + ࿊ᄴ + 0x3FF48030 ‫؀‬Ĕཿ +RTC_CNTL_EXT_WAKEUP1_STATUS_REG ຓ҆ߒྜሑ෿ 0x3FF4807C ‫؀‬Ĕཿ + 0x3FF48080 ‫؀‬Ĕཿ +RTC ᇏ؎॥ᇅაሑ෿࠷թఖ + +RTC_CNTL_INT_ENA_REG ᇏ؎൐ି໊ + +RTC_CNTL_INT_RAW_REG ჰ൓ᇏ؎ሑ෿ + +RTC_CNTL_INT_ST_REG ௠зᇏ؎ሑ෿ + +RTC_CNTL_INT_CLR_REG ᇏ؎ౢԢ໊ + +RTC ๙ႨЌ਽࠷թఖ + +RTC_CNTL_STORE0_REG ๙ႨЌ਽࠷թఖ 0 + +RTC_CNTL_STORE1_REG ๙ႨЌ਽࠷թఖ 1 + +RTC_CNTL_STORE2_REG ๙ႨЌ਽࠷թఖ 2 + +RTC_CNTL_STORE3_REG ๙ႨЌ਽࠷թఖ 3 + +RTC_CNTL_STORE4_REG ๙ႨЌ਽࠷թఖ 4 + +RTC_CNTL_STORE5_REG ๙ႨЌ਽࠷թఖ 5 + +RTC_CNTL_STORE6_REG ๙ႨЌ਽࠷թఖ 6 + +RTC_CNTL_STORE7_REG ๙ႨЌ਽࠷թఖ 7 + +ଽ҆‫ܵݻۿ‬৘࠷թఖ + +RTC_CNTL_ANA_CONF_REG ഈ‫׈‬Ĕ؎‫׈‬஥ᇂ + +RTC_CNTL_VREG_REG ଽ҆‫ٳݻۿ‬஥ა॥ᇅ + +RTC_CNTL_PWC_REG RTC თ‫ܵݻۿ‬৘ + +ুᶈྐ༏॓࠯ 635 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + +଀ӫ ૭ඍ ֹᆶ ٠໙ٚൔ +RTC_CNTL_DIG_PWC_REG ඔሳთ‫ܵݻۿ‬৘ 0x3FF48084 ‫؀‬Ĕཿ +RTC_CNTL_DIG_ISO_REG ඔሳთ‫ۯ‬৖॥ᇅ 0x3FF48088 ᆺ‫؀‬ +RTC ु૊‫ܐ‬஥ᇂთ॥ᇅ࠷թఖ +RTC_CNTL_WDTCONFIG0_REG WDT ஥ᇂ࠷թఖ 0 0x3FF4808C ‫؀‬Ĕཿ +RTC_CNTL_WDTCONFIG1_REG WDT ஥ᇂ࠷թఖ 1 0x3FF48090 ‫؀‬Ĕཿ +RTC_CNTL_WDTCONFIG2_REG WDT ஥ᇂ࠷թఖ 2 0x3FF48094 ‫؀‬Ĕཿ +RTC_CNTL_WDTCONFIG3_REG WDT ஥ᇂ࠷թఖ 3 0x3FF48098 ‫؀‬Ĕཿ +RTC_CNTL_WDTCONFIG4_REG WDT ஥ᇂ࠷թఖ 4 0x3FF4809C ‫؀‬Ĕཿ +RTC_CNTL_WDTFEED_REG ່‫࠷ܐ‬թఖ 0x3FF480A0 ᆺཿ +RTC_CNTL_WDTWPROTECT_REG ु૊‫ܐ‬ཿЌ޹࠷թఖ 0x3FF480A4 ‫؀‬Ĕཿ +ః෰ RTC ஥ᇂ࠷թఖ +RTC_CNTL_EXT_XTL_CONF_REG ຓ҆ܵ࢖ XTAL ॥ᇅ 0x3FF4805C ‫؀‬Ĕཿ +RTC_CNTL_SLP_REJECT_CONF_REG ऋधჰၹ‫ބ‬൐ି॥ᇅ 0x3FF48064 ‫؀‬Ĕཿ +RTC_CNTL_CPU_PERIOD_CONF_REG CPU ᇛ௹࿊ᄴ 0x3FF48068 ‫؀‬Ĕཿ +RTC_CNTL_CLK_CONF_REG RTC ൈᇒ஥ᇂ 0x3FF48070 ‫؀‬Ĕཿ +RTC_CNTL_SDIO_CONF_REG SDIO ஥ᇂ 0x3FF48074 ‫؀‬Ĕཿ +RTC_CNTL_SW_CPU_STALL_REG CPU ๔ࠏ 0x3FF480AC ‫؀‬Ĕཿ +RTC_CNTL_HOLD_FORCE_REG RTC ܵ࢖Ќ਽࠷թఖ 0x3FF480C8 ‫؀‬Ĕཿ +RTC_CNTL_BROWN_OUT_REG ఴ࿢ܵ৘ 0x3FF480D4 ‫؀‬Ĕཿ + +ুᶈྐ༏॓࠯ 636 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + +31.5 ࠷թఖ + + Register 31.1. RTC_CNTL_OPTIONS0_REG (0x3FF48000) + +RTC_RCTNCT_LRC_STNWCT_L_C_SDNYGTSL__W_RDSRGTA_PW_FR(rOAeRsPe_CrFvEOe_dRN)COER_SRTST RTC_RCTNCT_LRC_BTNCITA_LSRC__BTNCCITAO_LSRRC__EBTNC_CITAOF_LSORRC__REBTNC_CCITAOFE_LSOR_RC__RPEBTNI2_UCCITAFCE_LSO__RC__FLPBTNIOW2DCITACR__LS_C8RC__FMEBTNIO2_CITACRP_LS_UCRC__FEBTNFO_CIOTALP_LRSWDRC__CB_TNFE8CIOTA_M_LRSNRC__COXTNSESTCTL_LL_ELS_ERC_ELFEXTNPEOPTC_TERLF_LP_CORC_FEBTLNO_WCBTRPP_L_UCRC_L8EBLTNM__CBTPFP_LODRC_LRBLTN_CCBTFEP_LORC__LRPBLTN_UCCBTIE2P_LRCC__LPBLTN__DCFBTIO2__LIRCC_R2BTN_CCCFBTE_O__FL_ICO_RP2SNUCCRWRTE_CTFL__ECO_PP_S_DRRPWCUCON_ECAT_PLPPUR_PDS_TCRWCPS__UTCS_NTRATSLLTL_S_PWR_OSCTAPLUL__CA0PPCPU_C0 + +31 30 29 28 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 21 0 + +0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +RTC_CNTL_SW_SYS_RST ೈࡱ༢๤‫໊گ‬bčᆺཿĎ +RTC_CNTL_DG_WRAP_FORCE_NORST Deep-sleep ଆൔ༯đඔሳଽ‫఼ނ‬ᇅ҂‫໊گ‬bč‫؀‬ĔཿĎ +RTC_CNTL_DG_WRAP_FORCE_RST Deep-sleep ଆൔ༯đඔሳଽ‫఼ނ‬ᇅ‫໊گ‬bč‫؀‬ĔཿĎ +RTC_CNTL_BIAS_CORE_FORCE_PU BIAS_CORE ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_BIAS_CORE_FORCE_PD BIAS_CORE ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_BIAS_CORE_FOLW_8M BIAS_CORE ෛ CK8M э߄bč‫؀‬ĔཿĎ +RTC_CNTL_BIAS_I2C_FORCE_PU BIAS_I2C ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_BIAS_I2C_FORCE_PD BIAS_I2C ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_BIAS_I2C_FOLW_8M BIAS_I2C ෛ CK8M э߄bč‫؀‬ĔཿĎ +RTC_CNTL_BIAS_FORCE_NOSLEEP BIAS_SLEEP ఼ᇅ҂ඤ૤bč‫؀‬ĔཿĎ +RTC_CNTL_BIAS_FORCE_SLEEP BIAS_SLEEP ఼ᇅඤ૤bč‫؀‬ĔཿĎ +RTC_CNTL_BIAS_SLEEP_FOLW_8M BIAS_SLEEP ෛ CK8M э߄bč‫؀‬ĔཿĎ +RTC_CNTL_XTL_FORCE_PU Crystal ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_XTL_FORCE_PD Crystal ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_BBPLL_FORCE_PU BB_PLL ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_BBPLL_FORCE_PD BB_PLL ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_BBPLL_I2C_FORCE_PU BB_PLL_I2C ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_BBPLL_I2C_FORCE_PD BB_PLL _I2C ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_BB_I2C_FORCE_PU BB_I2C ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_BB_I2C_FORCE_PD BB_I2C ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_SW_PROCPU_RST PRO_CPU ೈࡱ‫໊گ‬bčᆺཿĎ +࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 637 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.1. RTC_CNTL_OPTIONS0_REG (0x3FF48000) + + ࠿ഈ၂်࠷թఖ૭ඍb + RTC_CNTL_SW_APPCPU_RST APP_CPU ೈࡱ‫໊گ‬bčᆺཿĎ + RTC_CNTL_SW_STALL_PROCPU_C0 ҕ࡮ RTC_CNTL_SW_CPU_STALL_REGbč‫؀‬ĔཿĎ + RTC_CNTL_SW_STALL_APPCPU_C0 ҕ࡮ RTC_CNTL_SW_CPU_STALL_REGbč‫؀‬ĔཿĎ + + Register 31.2. RTC_CNTL_SLP_TIMER0_REG (0x3FF48004) 0 + +31 Reset + + 0x000000000 + + RTC_CNTL_SLP_TIMER0_REG RTC ඤ૤࠹ൈఖ֮ 32 ໊bč‫؀‬ĔཿĎ + + Register 31.3. RTC_CNTL_SLP_TIMER1_REG (0x3FF48008) + + (reserved) RTC_CNTL_MAIN_TIMER_ALARM_EN RTC_CNTL_SLP_VAL_HI + +31 17 16 15 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0x00000 Reset + + RTC_CNTL_MAIN_TIMER_ALARM_EN ࠹ൈఖࣞБ൐ି໊bč‫؀‬ĔཿĎ + RTC_CNTL_SLP_VAL_HI RTC ඤ૤࠹ൈఖۚ 16 ໊bč‫؀‬ĔཿĎ + + Register 31.4. RTC_CNTL_TIME_UPDATE_REG (0x3FF4800C) + +RTC_RCTNCT_LC_TNIMTLE__TUIMPDE_AVTAELID (reserved) + +31 30 29 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_TIME_UPDATE ᇂ 1ğ൐Ⴈ RTC ࠹ൈఖ۷ྍ࠷թఖbčᆺཿĎ + RTC_CNTL_TIME_VALID іൕ࠷թఖၘ۷ྍbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 638 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) 0 + + Register 31.5. RTC_CNTL_TIME0_REG (0x3FF48010) Reset + + 31 + + 0x000000000 + + RTC_CNTL_TIME0_REG RTC ࠹ൈఖ֮ 32 ໊bčᆺ‫؀‬Ď + + Register 31.6. RTC_CNTL_TIME1_REG (0x3FF48014) + + (reserved) RTC_CNTL_TIME_HI + 0x00000 +31 16 15 0 + +0000000000000000 Reset + + RTC_CNTL_TIME_HI RTC ࠹ൈఖۚ 16 ໊bčᆺ‫؀‬Ď + + Register 31.7. RTC_CNTL_STATE0_REG (0x3FF48018) + +RTC_RCTNCT_LRC_STNLCTE_LERC_PSTN_LCTEP_LN_C_RSNELTJPLE_(_rCWeSsTDAeIKrOvEe_UAdP)CTRIVTEC__IRCNTNDCT_LC_UNLTPL__CTOP_USCLHP__STLIMPE_TRI_MEENR_EN (reserved) + +31 30 29 28 27 25 24 23 22 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_SLEEP_EN ඤ૤൐ି໊bč‫؀‬ĔཿĎ + RTC_CNTL_SLP_REJECT ඤ૤ऋध໊bč‫؀‬ĔཿĎ + RTC_CNTL_SLP_WAKEUP ඤ૤ߒྜ໊bč‫؀‬ĔཿĎ + RTC_CNTL_SDIO_ACTIVE_IND іൕ SDIO ࠗࠃbčᆺ‫؀‬Ď + RTC_CNTL_ULP_CP_SLP_TIMER_EN ULP ླྀԩ৘ఖ࠹ൈఖ൐ି໊bč‫؀‬ĔཿĎ + RTC_CNTL_TOUCH_SLP_TIMER_EN ԨଃԮ‫ۋ‬ఖ൐ି໊bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 639 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.8. RTC_CNTL_TIMER1_REG (0x3FF4801C) + + (reserved) RTC_CNTL_CPU_STALL_EN + +31 10 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset + + RTC_CNTL_CPU_STALL_EN CPU ᄠ๔൐ି໊bč‫؀‬ĔཿĎ + + Register 31.9. RTC_CNTL_TIMER2_REG (0x3FF48020) + + RTC_CNTL_MIN_TIME_CK8M_OFF RTC_CNTL_ULPCP_TOUCH_START_WAIT (reserved) + +31 24 23 15 14 0 + + 0x001 0x010 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_MIN_TIME_CK8M_OFF ܱо่ࡱ༯đCK8M slow_clk_rtc ֥ቋཬᇛ௹ඔbč‫؀‬ĔཿĎ + + RTC_CNTL_ULPCP_TOUCH_START_WAIT ULP ླྀԩ৘ఖĔԨଃԮ‫ۋ‬ఖष൓‫۽‬ቔభđslow_clk_rtc + ֥֩րᇛ௹ඔbč‫؀‬ĔཿĎ + + Register 31.10. RTC_CNTL_TIMER5_REG (0x3FF4802C) + + (reserved) RTC_CNTL_MIN_SLP_VAL (reserved) + +31 16 15 87 0 + +0000000000000000 0x080 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_MIN_SLP_VAL slow_clk_rtc ቋཬඤ૤ᇛ௹ඔbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 640 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.11. RTC_CNTL_ANA_CONF_REG (0x3FF48030) + +RTC_RCTNCT_L(C_rePNsLTeLLr_vR_Ie2CTdCCK)_G_PRCEUTNNCT__LI2RC_CRTN_CFTPR_LU(CX_reT_NsPXTeRBLrvFUR_e_PSTdI2VC_)CPT_MURC_PTNOUCTN_L_C_PPNULTLLA__PFLOLRA_CFEO_RPUCE_PD (reserved) + +31 30 29 28 27 26 25 24 23 22 0 + +0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_PLL_I2C_PU 1ğPLL_I2C յषĠ0ğܱоbč‫؀‬ĔཿĎ + RTC_CNTL_CKGEN_I2C_PU 1ğCKGEN_I2C յषĠ0ğܱоbč‫؀‬ĔཿĎ + RTC_CNTL_RFRX_PBUS_PU 1ğRFRX_PBUS յषĠ0ğܱоbč‫؀‬ĔཿĎ + RTC_CNTL_TXRF_I2C_PU 1ğTXRF_I2C յषĠ0ğܱоbč‫؀‬ĔཿĎ + RTC_CNTL_PVTMON_PU 1ğPVTMON յषĠ0ğܱоbč‫؀‬ĔཿĎ + RTC_CNTL_PLLA_FORCE_PU PLLA ఼ᇅյषbč‫؀‬ĔཿĎ + RTC_CNTL_PLLA_FORCE_PD PLLA ఼ᇅܱоbč‫؀‬ĔཿĎ + + Register 31.12. RTC_CNTL_RESET_STATE_REG (0x3FF48034) + + (reserved) RTC_RCTNCT_LC_PNRTOL_CAPPUP_CSPTRUATT_C_SV_TECACTN_TTVOLE_RCR_TESOSERELT_S_CELAUSE_APPRCTPCU_CNTL_RESET_CAUSE_PROCPU + +31 14 13 12 11 65 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x x x x x x x x x x x x Reset + + RTC_CNTL_PROCPU_STAT_VECTOR_SEL PRO_CPU ሑ෿ཟਈ࿊ᄴbč‫؀‬ĔཿĎ + RTC_CNTL_APPCPU_STAT_VECTOR_SEL APP_CPU ሑ෿ཟਈ࿊ᄴbč‫؀‬ĔཿĎ + RTC_CNTL_RESET_CAUSE_APPCPU APP_CPU ‫໊گ‬ჰၹbčᆺ‫؀‬Ď + RTC_CNTL_RESET_CAUSE_PROCPU PRO_CPU ‫໊گ‬ჰၹbčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 641 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.13. RTC_CNTL_WAKEUP_STATE_REG (0x3FF48038) + + (reserved) RTC_CNTL_GPIO_WAKEUP_FILTRERTC_CNTL_WAKEUP_ENA RTC_CNTL_WAKEUP_CAUSE + +31 23 22 21 11 10 0 + +0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 1 1 0 0 0x000 Reset + + RTC_CNTL_GPIO_WAKEUP_FILTER GPIO ߒྜ൙ࡱ൐ି‫ݖ‬ੲఖbč‫؀‬ĔཿĎ + RTC_CNTL_WAKEUP_ENA ߒྜ൐ି໊๭bč‫؀‬ĔཿĎ + RTC_CNTL_WAKEUP_CAUSE ߒྜჰၹbčᆺ‫؀‬Ď + + Register 31.14. RTC_CNTL_INT_ENA_REG (0x3FF4803C) + + (reserved) RTC_RCTNCT_LRC_MTNCAT_LINRC__BTNTCRTIMO_LRC_EWTTNRNOCT__U_LINORC_CTUUTNH_CLTTE_P__LINNI_RC_NACTTTNT_IPCMT_E__ELNEIRC_NN_AWTNATVC_ATDE_LLTRCN_I_DSTNAIN_DCTITNI_LO_CT_E_S_NINEDLTANPLLE_A_R_SIELNJPTE__CWETNA_AKINETU_PE_NINAT_ENA + +31 98 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_MAIN_TIMER_INT_ENA RTC_CNTL_MAIN_TIMER_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬ĔཿĎ + RTC_CNTL_BROWN_OUT_INT_ENA RTC_CNTL_BROWN_OUT_INT ᇏ؎֥ᇏ؎൐ି໊čb‫؀‬ĔཿĎ + RTC_CNTL_TOUCH_INT_ENA RTC_CNTL_TOUCH_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬ĔཿĎ + RTC_CNTL_ULP_CP_INT_ENA RTC_CNTL_ULP_CP_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬ĔཿĎ + RTC_CNTL_TIME_VALID_INT_ENA RTC_CNTL_TIME_VALID_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬ĔཿĎ + RTC_CNTL_WDT_INT_ENA RTC_CNTL_WDT_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬ĔཿĎ + RTC_CNTL_SDIO_IDLE_INT_ENA RTC_CNTL_SDIO_IDLE_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬ĔཿĎ + RTC_CNTL_SLP_REJECT_INT_ENA RTC_CNTL_SLP_REJECT_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬ĔཿĎ + RTC_CNTL_SLP_WAKEUP_INT_ENA RTC_CNTL_SLP_WAKEUP_INT ᇏ؎֥ᇏ؎൐ି໊bč‫؀‬Ĕ + + ཿĎ + +ুᶈྐ༏॓࠯ 642 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.15. RTC_CNTL_INT_RAW_REG (0x3FF48040) + + (reserved) RTC_RCTNCT_LRC_MTNCAT_LINRC__BTNTCRTIMO_LRC_EWTTNRNOCT__U_LINORC_CTUUTNH_CLTTR_P__LIANI_RC_NWCTTTNT_IPCMT_R__RLEAIRC_NA_WWTNWTVC_ATDR_LLTRC_AI_DSTNWIN_DCTITNI_LO_CT_R_S_NIARDLTWPALLE_W_R_SIELNJPTE__CWRTAA_WKINETU_PR_AINWT_RAW + +31 98 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_MAIN_TIMER_INT_RAW RTC_CNTL_MAIN_TIMER_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ + ‫؀‬Ď + + RTC_CNTL_BROWN_OUT_INT_RAW RTC_CNTL_BROWN_OUT_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ + ‫؀‬Ď + + RTC_CNTL_TOUCH_INT_RAW RTC_CNTL_TOUCH_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_ULP_CP_INT_RAW RTC_CNTL_ULP_CP_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_TIME_VALID_INT_RAW RTC_CNTL_TIME_VALID_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_WDT_INT_RAW RTC_CNTL_WDT_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_SDIO_IDLE_INT_RAW RTC_CNTL_SDIO_IDLE_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_SLP_REJECT_INT_RAW RTC_CNTL_SLP_REJECT_INT ᇏ؎֥ჰ൓ᇏ؎ሑ෿໊bčᆺ + + ‫؀‬Ď + + RTC_CNTL_SLP_WAKEUP_INT_RAW RTC_CNTL_SLP_WAKEUP_INT ᇏ ؎ ֥ ჰ ൓ ᇏ ؎ ሑ ෿ + ໊bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 643 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.16. RTC_CNTL_INT_ST_REG (0x3FF48044) + + (reserved) RTC_RCTNCT_LRC_MTNCAT_LINRC__BTNTCRTIMO_LRC_EWTTNRNOCT__U_LINORC_CTSUTNH_ACTTS_R__LITNIRC__NTITTNNT_ICMT_TS_SL_ETRC_ST_WTNTVCATD_LLTRC_I_DSTNIN_DCTITNI_LO_CT_S_S_NITSDLTTPLLE__R_SIELNJPTE__CWSTTA_KINETU_PS_TINT_ST + +31 98 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_MAIN_TIMER_INT_ST RTC_CNTL_MAIN_TIMER_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_BROWN_OUT_INT_ST RTC_CNTL_BROWN_OUT_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ + + ‫؀‬Ď + RTC_CNTL_TOUCH_INT_ST RTC_CNTL_TOUCH_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_SAR_INT_ST RTC_CNTL_SAR_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_TIME_VALID_INT_ST RTC_CNTL_TIME_VALID_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_WDT_INT_ST RTC_CNTL_WDT_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_SDIO_IDLE_INT_ST RTC_CNTL_SDIO_IDLE_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_SLP_REJECT_INT_ST RTC_CNTL_SLP_REJECT_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ‫؀‬Ď + RTC_CNTL_SLP_WAKEUP_INT_ST RTC_CNTL_SLP_WAKEUP_INT ᇏ؎֥௠зᇏ؎ሑ෿໊bčᆺ + + ‫؀‬Ď + +ুᶈྐ༏॓࠯ 644 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.17. RTC_CNTL_INT_CLR_REG (0x3FF48048) + + (reserved) RTC_RCTNCT_LRC_MTNCAT_LINRC__BTNTCRTIMO_LRC_EWTTNRNOCT__U_LINORC_CTSUTNH_ACTTC_R__LILNIRC__NRTITTNNT_ICMT_TC_CL_ELRC_CL_RWTNRLVCRATD_LLTRC_I_DSTNIN_DCTITNI_LO_CT_C_S_NILCDLTRPLLLRE__R_SIELNJPTE__CWCTLA_RKINETU_PC_LINRT_CLR + +31 98 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_MAIN_TIMER_INT_CLR Վ໊ᇂ 1 ౢԢ RTC_CNTL_MAIN_TIMER_INT ᇏ؎bčᆺཿĎ + RTC_CNTL_BROWN_OUT_INT_CLR Վ໊ᇂ 1 ౢԢ RTC_CNTL_BROWN_OUT_INT ᇏ؎bčᆺཿĎ + RTC_CNTL_TOUCH_INT_CLR Վ໊ᇂ 1 ౢԢ RTC_CNTL_TOUCH_INT ᇏ؎bčᆺཿĎ + RTC_CNTL_SAR_INT_CLR Վ໊ᇂ 1 ౢԢ RTC_CNTL_SAR_INT ᇏ؎bčᆺཿĎ + RTC_CNTL_TIME_VALID_INT_CLR Վ໊ᇂ 1 ౢԢ RTC_CNTL_TIME_VALID_INT ᇏ؎bčᆺཿĎ + RTC_CNTL_WDT_INT_CLR Վ໊ᇂ 1 ౢԢ RTC_CNTL_WDT_INT ᇏ؎bčᆺཿĎ + RTC_CNTL_SDIO_IDLE_INT_CLR Վ໊ᇂ 1 ౢԢ RTC_CNTL_SDIO_IDLE_INT ᇏ؎bčᆺཿĎ + RTC_CNTL_SLP_REJECT_INT_CLR Վ໊ᇂ 1 ౢԢ RTC_CNTL_SLP_REJECT_INT ᇏ؎bčᆺཿĎ + RTC_CNTL_SLP_WAKEUP_INT_CLR Վ໊ᇂ 1 ౢԢ RTC_CNTL_SLP_WAKEUP_INT ᇏ؎bčᆺཿĎ + + Register 31.18. RTC_CNTL_STOREn_REG (n: 0­3) (0x3FF4804C+4*n) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + RTC_CNTL_STOREn_REG 32-bit ๙ႨЌ਽࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 645 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.19. RTC_CNTL_LOW_POWER_ST_REG (0x3FF480C0) + + (reserved) RTC_CNTL_RTC_RDY_FOR_WAKEUP (reserved) + +31 20 19 18 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_RTC_RDY_FOR_WAKEUP սі RTC ၘሙСࢤ൳಩‫ྜߒޅ‬ჷ֥Ԩ‫ؿ‬bčᆺ‫؀‬Ď + + Register 31.20. RTC_CNTL_EXT_XTL_CONF_REG (0x3FF4805C) + +RTC_RCTNCT_LC_XNTTLL__EXXTTL__CETXRT__ECNTR_LV (reserved) + +31 30 29 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_XTL_EXT_CTR_EN ຓ҆ܵ࢖൐ି XTAL ॥ᇅbč‫؀‬ĔཿĎ + RTC_CNTL_XTL_EXT_CTR_LV 0ğۚ‫׈‬௜ൈđXTAL ܱоĠ1ğ֮‫׈‬௜ൈđXTAL ܱоbč‫؀‬ĔཿĎ + + Register 31.21. RTC_CNTL_EXT_WAKEUP_CONF_REG (0x3FF48060) + +RTC_RCTNCT_LC_ENXTTL__WEXATK_EWUAPK1E_LUVP0_LV (reserved) + +31 30 29 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_EXT_WAKEUP1_LV 0ğ֮‫׈‬௜ൈđຓ҆ߒྜĠ1ğۚ‫׈‬௜ൈđຓ҆ߒྜbč‫؀‬ĔཿĎ + RTC_CNTL_EXT_WAKEUP0_LV 0ğ֮‫׈‬௜ൈđຓ҆ߒྜĠ1ğۚ‫׈‬௜ൈđຓ҆ߒྜbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 646 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.22. RTC_CNTL_SLP_REJECT_CONF_REG (0x3FF48064) + + RTC_CNTL_RREJTECC_TRC_TNCCTA_LURC_DSTNCEETE_LRCP_L_TNISCGTL_LHPC_T_SN_RDSTEILLOJ_PE_G_RCRPETEIOJ_JEE_ECNRCTET_J_EEENCNT_EN (reserved) + +31 28 27 26 25 24 23 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_REJECT_CAUSE ඤ૤ऋधჰၹbčᆺ‫؀‬Ď + RTC_CNTL_DEEP_SLP_REJECT_EN ൐ିऋध Deep-sleepbč‫؀‬ĔཿĎ + RTC_CNTL_LIGHT_SLP_REJECT_EN ൐ିऋध Light-sleepbč‫؀‬ĔཿĎ + RTC_CNTL_SDIO_REJECT_EN ൐ି SDIO ऋधbč‫؀‬ĔཿĎ + RTC_CNTL_GPIO_REJECT_EN ൐ି GPIO ऋधbč‫؀‬ĔཿĎ + + Register 31.23. RTC_CNTL_CPU_PERIOD_CONF_REG (0x3FF48068) + + RTC_CNRTTLC_R_CTCN_TCLP_CUPPUESREIOLD_C_SOENLF (reserved) + +31 30 29 28 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_RTC_CPUPERIOD_SEL CPU ᇛ௹࿊ᄴbč‫؀‬ĔཿĎ + RTC_CNTL_CPUSEL_CONF CPU ࿊ᄴ࿊ཛbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 647 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.24. RTC_CNTL_CLK_CONF_REG (0x3FF48070) + +RTC_CNRTTLC_A_NCANR_TCTLC_LFK_AC_SRNTRTT_CTLCC__LSS_KEORC_LTNCRCT_T_CLCC_L_CNKSK_TES8LLM_ECL_KFO8MR_CFEO_RPUCRET_CP_DCNTL_CK8M_DFREQ (reserved) RTC_CNTL(_reCsKe8rvRMeT_dCD) _IVRC_TNSCTE_LLRC_DTNCITG_L_RC_CDTNLCITGK_L8_RC_CMDTNL_CITGKE_L8_NC_XMENT_NRATDBTLL2C_3_5EC2_6NKCK__BN8EEM_TNNCL__KDC8IVKM8(Mre_sDerIVved) + +31 30 29 28 27 26 25 24 17 16 15 14 12 11 10 9 8 7 6 5 43 0 + +0 0 0 00 0 00 2 0 0 1 0 0 0 0 1 0 0 0 0 Reset + +RTC_CNTL_ANA_CLK_RTC_SEL ࿊ᄴ slow_clk_rtcb0ğSLOW_CKĠ1ğCK_XTAL_32KĠ + 2ğCK8M_D256_OUTbč‫؀‬ĔཿĎ + +RTC_CNTL_FAST_CLK_RTC_SEL ࿊ᄴ fast_clk_rtcb0ğXTAL div 4Ġ1ğCK8M bč‫؀‬ĔཿĎ +RTC_CNTL_SOC_CLK_SEL ࿊ᄴ SOC ൈᇒb0ğXTALĠ1ğPLLĠ2ğCK8MĠ3: APLLbč‫؀‬ĔཿĎ +RTC_CNTL_CK8M_FORCE_PU CK8M ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_CK8M_FORCE_PD CK8M ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_CK8M_DFREQ CK8M_DFREQbč‫؀‬ĔཿĎ +RTC_CNTL_CK8M_DIV_SEL Divider = reg_rtc_cntl_ck8m_div_sel + 1bč‫؀‬ĔཿĎ +RTC_CNTL_DIG_CLK8M_EN ඔሳଽ‫ނ‬൐ି CK8Mčᇿၩğა RTC ଽ‫ނ‬໭ܱĎbč‫؀‬ĔཿĎ +RTC_CNTL_DIG_CLK8M_D256_EN ඔሳଽ‫ނ‬൐ି CK8M_D256_OUTčᇿၩğა RTC ଽ‫ނ‬໭ + + ܱĎbč‫؀‬ĔཿĎ +RTC_CNTL_DIG_XTAL32K_EN ඔሳଽ‫ނ‬൐ି CK_XTAL_32Kčᇿၩğა RTC ଽ‫ނ‬໭ܱĎbč‫؀‬ĔཿĎ +RTC_CNTL_ENB_CK8M_DIV 1ğCK8M_D256_OUT ൌ࠽ູ CK8MĠ0ğCK8M_D256_OUT ູ CK8M + + ֥ 256 ‫ٳ‬௔bč‫؀‬ĔཿĎ +RTC_CNTL_ENB_CK8M ࣌Ⴈ CK8M ‫ ބ‬CK8M_D256_OUTbč‫؀‬ĔཿĎ +RTC_CNTL_CK8M_DIV CK8M_D256_OUT ‫ٳ‬௔ఖb00ğ128 ‫ٳ‬௔Ġ01ğ256 ‫ٳ‬௔Ġ10ğ512 ‫ٳ‬௔Ġ + + 11ğ1024 ‫ٳ‬௔bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 648 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.25. RTC_CNTL_SDIO_CONF_REG (0x3FF48074) + +RTC_CNRTTLC_X_PCDN_TSLDR_DITOCR_E_VCFRHNE_TGSLRD_DTIOCRE_CFMNRT_TSLC_DD_IORCRTNECFTL_L_RC_SRTNDCETIG_LORC_1STPNDC8TI__LORC__SENTDATIEDILOH_Y_SFDOIOR_CVEREG_PD_EN (reserved) + +31 30 29 28 27 26 25 24 23 22 21 20 0 + +0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +RTC_CNTL_XPD_SDIO_VREG XPD_SDIO_VREG ೈࡱ࿊ཛđࣇᄝ reg_rtc_cntl_sdio_force == 1 ൈ + ࠗࠃbč‫؀‬ĔཿĎ + +RTC_CNTL_DREFH_SDIO DREFH_SDIO ೈࡱ࿊ཛđࣇᄝ reg_rtc_cntl_sdio_force == 1 ൈࠗࠃbč‫؀‬ + ĔཿĎ + +RTC_CNTL_DREFM_SDIO DREFM_SDIO ೈࡱ࿊ཛđࣇᄝ reg_rtc_cntl_sdio_force == 1 ൈࠗࠃbč‫؀‬ + ĔཿĎ + +RTC_CNTL_DREFL_SDIO DREFL_SDIO ೈࡱ࿊ཛđࣇᄝ reg_rtc_cntl_sdio_force == 1 ൈࠗࠃbč‫؀‬ + ĔཿĎ + +RTC_CNTL_REG1P8_READY REG1P8_READY ᆺ‫࠷؀‬թఖbčᆺ‫؀‬Ď + +RTC_CNTL_SDIO_TIEH SDIO_TIEH ೈࡱ࿊ཛđࣇᄝ reg_rtc_cntl_sdio_force == 1 ൈࠗࠃbč‫؀‬Ĕ + ཿĎ + +RTC_CNTL_SDIO_FORCE 1ğ൐Ⴈೈࡱ࿊ཛ॥ᇅ SDIO_VREGĠ0ğ൐Ⴈሑ෿ࠏ॥ᇅ SDIO_VREGčb‫؀‬ + ĔཿĎ + +RTC_CNTL_SDIO_VREG_PD_EN ඤ૤ሑ෿༯đSDIO_VREG ܱоđࣇᄝ reg_rtc_cntl_sdio_force == + 0 ൈࠗࠃbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 649 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.26. RTC_CNTL_VREG_REG (0x3FF4807C) + +RTC_RCTNCT_LRC_PTNRCTE_LRCG_PTN_RCFTOE_LCG_RDN_CBFTEOOL_R_RPODTUCSCBETO___CPFONODSTRTL_C_FEDO_BRPIAUCRSET__CWP_DACKNTL_DBIAS_SLP RTC_CNTL_SCK_DCAP RTC_CNTL_DIG_RVTRCE_GC_NDTBLI_ADSI_GW_VARKEG_DBIAS(_reSsLePrved) + +31 30 29 28 27 25 24 22 21 14 13 11 10 87 0 + +1010 4 4 0 4 4 0 0 0 0 0 0 0 0 Reset + +RTC_CNTL_VREG_FORCE_PU RTC ‫ט‬࿢ఖ - ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_VREG_FORCE_PD RTC ‫ט‬࿢ఖ - ఼ᇅܱоčᄝᆃᇕ౦ঃ༯đoܱоpᆷ‫׈‬࿢༯ࢆᇀ 0.8V + + ࠇ۷֮Ďbč‫؀‬ĔཿĎ +RTC_CNTL_DBOOST_FORCE_PU RTC_DBOOST ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_DBOOST_FORCE_PD RTC_DBOOST ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_DBIAS_WAK ߒྜࢨ‫ ֥؍‬RTC_DBIASbč‫؀‬ĔཿĎ +RTC_CNTL_DBIAS_SLP ඤ૤ࢨ‫ ֥؍‬RTC_DBIASbč‫؀‬ĔཿĎ +RTC_CNTL_SCK_DCAP ‫ ࢫט‬RTC ત෎ൈᇒ௔ੱbč‫؀‬ĔཿĎ +RTC_CNTL_DIG_VREG_DBIAS_WAK ߒྜࢨ‫֥؍‬ඔሳ‫ט‬࿢ఖ DBIASbč‫؀‬ĔཿĎ +RTC_CNTL_DIG_VREG_DBIAS_SLP ඤ૤ࢨ‫֥؍‬ඔሳ‫ט‬࿢ఖ DBIASbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 650 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.27. RTC_CNTL_PWC_REG (0x3FF48080) + + (reserved) RTC_RCTNCT_LRC_PTNDCT__LERC_NFTNOCTR_LRC_CFTNEOC_TRP_LRC_UCSTNELC_TOP_LRCW_DSTNMLCTOE_LMRCW_STN_MLCPTOED_LMRCW__FTEN_MACNFTSEO_LTMRC_RMFTN_CACEFTESOM_L_TRC_RP_MFTNPUCACEDTESM_L__TRC_EP_MSTNNFDLCEOTOM_LRRCW__CSTNFMELCOT_OE_LRPMRCW_UCSTN_MELCFT_OEO_LPMRCW_RDFTN_CMACFTESEO_L_TMRC_RLMFTNP_CACEFUTESOM_L_TRC_LL_MFWTNPFACEODT_SM_LCRTRC__CPMFTNFUEOCEOT_RM_LRLRC_CP_CFTNFEUEOCO_T_RN_LLLRC_CWOPSTNEDI_SLC_TCOOI_LSPRCW_OUSTNMLCTOE_LMCW_FN_MAFTSEOLTM_RMF_CAEFESOM_TRI_SMFCOEOEMR_N_CFOEO_ISRISOCOE_NOISO + +31 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 Reset + + RTC_CNTL_PD_EN ඤ૤ሑ෿༯đ൐ିܱо rtc_peribč‫؀‬ĔཿĎ + RTC_CNTL_FORCE_PU rtc_peri ఼ᇅյषbč‫؀‬ĔཿĎ + RTC_CNTL_FORCE_PD rtc_peri ఼ᇅܱоbč‫؀‬ĔཿĎ + RTC_CNTL_SLOWMEM_PD_EN ඤ૤ሑ෿༯đ൐ିܱо RTC ଽթbč‫؀‬ĔཿĎ + RTC_CNTL_SLOWMEM_FORCE_PU RTC ଽթ఼ᇅյषbč‫؀‬ĔཿĎ + RTC_CNTL_SLOWMEM_FORCE_PD RTC ଽթ఼ᇅܱоbč‫؀‬ĔཿĎ + RTC_CNTL_FASTMEM_PD_EN ඤ૤ሑ෿༯đ൐ିܱоॹ෎ RTC ଽթbč‫؀‬ĔཿĎ + RTC_CNTL_FASTMEM_FORCE_PU ॹ෎ RTC ଽթ఼ᇅյषbč‫؀‬ĔཿĎ + RTC_CNTL_FASTMEM_FORCE_PD ॹ෎ RTC ଽթ఼ᇅܱоbč‫؀‬ĔཿĎ + RTC_CNTL_SLOWMEM_FORCE_LPU RTC ଽթ఼ᇅյष֮‫ݻۿ‬ଆൔbč‫؀‬ĔཿĎ + RTC_CNTL_SLOWMEM_FORCE_LPD RTC ଽթ఼ᇅܱо֮‫ݻۿ‬ଆൔbč‫؀‬ĔཿĎ + RTC_CNTL_SLOWMEM_FOLW_CPU 1ğRTC ଽթ֮‫ݻۿ‬ଆൔ఼ᇅܱоđෛ CPU э߄Ġ0ğRTC + + ଽթ֮‫ݻۿ‬ଆൔ఼ᇅܱо PDđෛ RTC ሑ෿ࠏэ߄bč‫؀‬ĔཿĎ + RTC_CNTL_FASTMEM_FORCE_LPU ॹ෎ RTC ଽթ఼ᇅյष֮‫ݻۿ‬ଆൔbč‫؀‬ĔཿĎ + RTC_CNTL_FASTMEM_FORCE_LPD ॹ෎ RTC ଽթ఼ᇅܱо֮‫ݻۿ‬ଆൔbč‫؀‬ĔཿĎ + RTC_CNTL_FASTMEM_FOLW_CPU 1ğॹ෎ RTC ଽթܱо֮‫ݻۿ‬ଆൔđෛ CPU э߄Ġ0ğॹ෎ + + RTC ଽթܱо֮‫ݻۿ‬ଆൔđෛ RTC ሑ෿ࠏэ߄bč‫؀‬ĔཿĎ + RTC_CNTL_FORCE_NOISO rtc_peri ఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ + RTC_CNTL_FORCE_ISO rtc_peri ఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ + RTC_CNTL_SLOWMEM_FORCE_ISO RTC ଽթ఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ + RTC_CNTL_SLOWMEM_FORCE_NOISO RTC ଽթ఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ + RTC_CNTL_FASTMEM_FORCE_ISO ॹ෎ RTC ଽթ఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ + RTC_CNTL_FASTMEM_FORCE_NOISO ॹ෎ RTC ଽթ఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 651 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.28. RTC_CNTL_DIG_PWC_REG (0x3FF48084) + +RTC_RCTNCT_LRC_DTNCGT_L_RCW_WTNRCTIAF_LIPRC___PITNNPDCTTD__LE_ERC_RENITNN_NCRTT_LAERC_RMITNN_4CRTT__LAEPRC_RMDITNN__3CRTTE__LAENPC_RMDINN__2RTTE_LAENP(_RrMDeR__s1OREe_MArNPvMD0ed__0P)E_DNPR_DTE_CNE_NRCTNCT_LRC_DTNCGT_L_RCW_DTNRCGTA_L_PRCW__WTNFRCTIOAF_LIRPRC___CFWTNFOECTIOF_R_LIRPRC_C_UCFITNENOEC_TT_RP_LEPRCUC_RDITNEN_C_RTTP_LAERCD_RMITNN_4CRTT__LAEFRC_ROMITNN_R4CRTT_C_LAEFERC_ROM_ITNN_RP3CRTT_UC_LAEFERC_ROM_ITNN_RP3CRTT_DC_LAEFERC_ROM_ITNN_RP2CRTT_UC_LAEFERC_ROM_ITNN_RP2CRTT_DC_LAEFERC_ROM_ITNN_RP1CRTT_UC_LAEFERC_ROM_ITNN_RP1CRTT_DC_LAEFERC_ROM_RTN_RP0CORT_UC_LMAFERC_OM0_RTN_RP0COTF_DC_LOMFEC_OR0_LN_CRPSTFUCELLO_PE(_rRP__eLUCMPsSeDELEr_PvMPe__dDMF)EOMR_CFEO_RPUCE_PD + +31 30 29 28 27 26 25 24 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 + +x x x x x x x x 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 Reset + +RTC_CNTL_DG_WRAP_PD_EN ඤ૤ଆൔ༯đ൐ିܱоඔሳଽ‫ނ‬bč‫؀‬ĔཿĎ +RTC_CNTL_WIFI_PD_EN ඤ૤ଆൔ༯đ൐ିܱо Wi-Fi ଆॶbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM4_PD_EN ඤ૤ଆൔ༯đ൐ିܱоଽ҆ SRAM 4bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM3_PD_EN ඤ૤ଆൔ༯đ൐ିܱоଽ҆ SRAM 3bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM2_PD_EN ඤ૤ଆൔ༯đ൐ିܱоଽ҆ SRAM 2bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM1_PD_EN ඤ૤ଆൔ༯đ൐ିܱоଽ҆ SRAM 1bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM0_PD_EN ඤ૤ଆൔ༯đ൐ିܱоଽ҆ SRAM 0bč‫؀‬ĔཿĎ +RTC_CNTL_ROM0_PD_EN ඤ૤ଆൔ༯đ൐ିܱо ROMbč‫؀‬ĔཿĎ +RTC_CNTL_DG_WRAP_FORCE_PU ඔሳଽ‫఼ނ‬ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_DG_WRAP_FORCE_PD ඔሳଽ‫఼ނ‬ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_WIFI_FORCE_PU Wi-Fi ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_WIFI_FORCE_PD Wi-Fi ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM4_FORCE_PU ଽ҆ SRAM 4 ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM4_FORCE_PD ଽ҆ SRAM 4 ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM3_FORCE_PU ଽ҆ SRAM 3 ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM3_FORCE_PD ଽ҆ SRAM 3 ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM2_FORCE_PU ଽ҆ SRAM 2 ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM2_FORCE_PD ଽ҆ SRAM 2 ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM1_FORCE_PU ଽ҆ SRAM 1 ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM1_FORCE_PD ଽ҆ SRAM 1 ఼ᇅܱоbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM0_FORCE_PU ଽ҆ SRAM 0 ఼ᇅյषbč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM0_FORCE_PD ଽ҆ SRAM 0 ఼ᇅܱоbč‫؀‬ĔཿĎ +࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 652 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.28. RTC_CNTL_DIG_PWC_REG (0x3FF48084) + + ࠿ഈ၂်࠷թఖ૭ඍb + RTC_CNTL_ROM0_FORCE_PU ROM ఼ᇅյषbč‫؀‬ĔཿĎ + RTC_CNTL_ROM0_FORCE_PD ROM ఼ᇅܱоbč‫؀‬ĔཿĎ + RTC_CNTL_LSLP_MEM_FORCE_PU ඤ૤ଆൔ༯đඔሳଽ‫ނ‬ଽթ఼ᇅյषbč‫؀‬ĔཿĎ + RTC_CNTL_LSLP_MEM_FORCE_PD ඤ૤ଆൔ༯đඔሳଽ‫ނ‬ଽթ఼ᇅܱоbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 653 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.29. RTC_CNTL_DIG_ISO_REG (0x3FF48088) + +RTC_RCTNCT_LRC_DTNCGT_L_RCW_DTNRCGTA_L_PRCW__WTNFRCTIOAF_LIRPRC___CFWTNFOECTIOF_R_LIRNRC_C_CFOITNENOECI_TTS_RN_LEOIRCC_SORITNOENI_SC_RTTOI_LAESRC_RMOITNN_4CRTT__LAEFRC_ROMITNN_R4CRTT_C_LAEFERC_ROM_ITNN_RN3CRTT_CO_LAEFERCI_ROMS_ITNN_ORI3CSRTT_CO_LAEFERC_ROM_ITNN_RN2CRTT_CO_LAEFERCI_ROMS_ITNN_ORI2CSRTT_CO_LAEFERC_ROM_ITNN_RN1CRTT_CO_LAEFERCI_ROMS_ITNN_ORI1CSRTT_CO_LAEFERC_ROM_RTN_RN0CORT_CO_LMAFERCI_OMS0_RTNO_RI0COSTF_CO_LOMFERC_OR0_DTN_CRNCGTFCEO_LO__ERCIP_SRN_DATNOCIOCSDGTEIO__LS__RCFP_OISODATNOCDGRT__CL_RCFP_EODATN_CDGRHT__CL_ORCFP_ELORATN_DCEDRUTG__CLNCF__EHOCRN_OLRTITSLRCCLOD___ERDC_EGNNG_OTP_LISRA_ODDTCG_A__CUPATNODT(_LHreA_OsDUeLGTrDvO_ePHdA)ODL_DA_UETNOHOLD + +31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0 + +1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +RTC_CNTL_DG_WRAP_FORCE_NOISO ඔሳଽ‫఼ނ‬ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_DG_WRAP_FORCE_ISO ඔሳଽ‫఼ނ‬ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_WIFI_FORCE_NOISO Wi-Fi ଆॶ఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_WIFI_FORCE_ISO Wi-Fi ଆॶ఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM4_FORCE_NOISO ଽ҆ SRAM 4 ఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM4_FORCE_ISO ଽ҆ SRAM 4 ఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM3_FORCE_NOISO ଽ҆ SRAM 3 ఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM3_FORCE_ISO ଽ҆ SRAM 3 ఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM2_FORCE_NOISO ଽ҆ SRAM 2 ఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM2_FORCE_ISO ଽ҆ SRAM 2 ఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM1_FORCE_NOISO ଽ҆ SRAM 1 ఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM1_FORCE_ISO ଽ҆ SRAM 1 ఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM0_FORCE_NOISO ଽ҆ SRAM 0 ఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_INTER_RAM0_FORCE_ISO ଽ҆ SRAM 0 ఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_ROM0_FORCE_NOISO ROM ఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_ROM0_FORCE_ISO ROM ఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_DG_PAD_FORCE_HOLD ඔሳܵ࢖఼ᇅЌӻbč‫؀‬ĔཿĎ +RTC_CNTL_DG_PAD_FORCE_UNHOLD ඔሳܵ࢖఼ᇅࢳԢЌӻbč‫؀‬ĔཿĎ +RTC_CNTL_DG_PAD_FORCE_ISO ඔሳܵ࢖఼ᇅ‫ۯ‬৖bč‫؀‬ĔཿĎ +RTC_CNTL_DG_PAD_FORCE_NOISO ඔሳܵ࢖఼ᇅ҂‫ۯ‬৖bč‫؀‬ĔཿĎ +࠷թఖ૭ඍ༯၂်࠿࿃b + +ুᶈྐ༏॓࠯ 654 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.29. RTC_CNTL_DIG_ISO_REG (0x3FF48088) + + ࠿ഈ၂်࠷թఖ૭ඍb + RTC_CNTL_REG_RTC_CNTL_DG_PAD_AUTOHOLD_EN ඔሳܵ࢖൐ିሱ‫׮‬Ќӻbč‫؀‬ĔཿĎ + RTC_CNTL_CLR_REG_RTC_CNTL_DG_PAD_AUTOHOLD ᆺ ཿ ࠷ թ ఖđ ౢ Ԣ ඔ ሳ ܵ ࢖ ሱ ‫ ׮‬Ќ + + ӻbčᆺཿĎ + RTC_CNTL_DG_PAD_AUTOHOLD ᆺ‫࠷؀‬թఖđіൕඔሳܵ࢖֥ሱ‫׮‬Ќӻሑ෿bčᆺ‫؀‬Ď + + Register 31.30. RTC_CNTL_WDTCONFIG0_REG (0x3FF4808C) + +RTC_CNTLR_WTCD_TC_NENTL_WDTR_TSCT_GC0NTL_WDTR_TSCT_GC1NTL_WDTR_TSCT_GC2NTLr_eWseDrvTre_edSseTrGve3d RTC_CNTL_WDTR_TCCP_UC_NRTELSR_EWTTCD__LTRCE_TNNSCGTY_LSTRC__HWTNRCETD_LSTRC_E_WTNTFCL_TDLA_LTECS__NWHNPGBTRDLTOOT_H_OCWAPTPD_UPTM_C_ROPPEDAUSU__ErESeRTNsEE_e_ESrIvNNEeT_d_SELNP + +31 30 28 27 25 24 22 21 19 18 17 16 14 13 11 10 9 8 7 6 0 + +0 0 0 0 0 00 1 1 1001 0 Reset + + RTC_CNTL_WDT_PAUSE_IN_SLP ᇂ 1 ഡᇂoඤ૤ᇏ RTC WDT ᄠ๔൐Ⴈpbč‫؀‬/ཿĎ + + RTC_CNTL_WDT_APPCPU_RESET_EN ᇂ 1 ᄍྸ RTC WDT ‫ ໊گ‬APP_CPUbč‫؀‬/ཿĎ + + RTC_CNTL_WDT_PROCPU_RESET_EN ᇂ 1 ᄍྸ RTC WDT ‫ ໊گ‬PRO_CPUbč‫؀‬/ཿĎ + + RTC_CNTL_WDT_FLASHBOOT_MOD_EN ᇂ 1 ᄝྉோՖ flash ఓ‫׮‬ൈ൐ି RTC WDTbč‫؀‬/ཿĎ + + RTC_CNTL_WDT_SYS_RESET_LENGTH ഡᇂ༢๤‫࠹໊گ‬ඔఖ֥ൈӉđֆ໊ğRTC_SLOW_CLKđ + ౼ᆴٓຶğ0 ~ 7bč‫؀‬/ཿĎ + + RTC_CNTL_WDT_CPU_RESET_LENGTH ഡᇂ CPU ‫࠹໊گ‬ඔఖ֥ൈӉֆ໊ğRTC_SLOW_CLKđ + ౼ᆴٓຶğ0 ~ 7bč‫؀‬/ཿĎ + + RTC_CNTL_WDT_STG3 1ğᄝᇏ؎ࢨ‫؍‬൐ିĠ2ğᄝ CPU ‫؍ࢨ໊گ‬൐ିĠ3ğᄝ༢๤‫؍ࢨ໊گ‬൐ିĠ + 4ğᄝ RTC ‫؍ࢨ໊گ‬൐ିbč‫؀‬/ཿĎ + + RTC_CNTL_WDT_STG2 1ğᄝᇏ؎ࢨ‫؍‬൐ିĠ2ğᄝ CPU ‫؍ࢨ໊گ‬൐ିĠ3ğᄝ༢๤‫؍ࢨ໊گ‬൐ିĠ + 4ğᄝ RTC ‫؍ࢨ໊گ‬൐ିbč‫؀‬/ཿĎ + + RTC_CNTL_WDT_STG1 1ğᄝᇏ؎ࢨ‫؍‬൐ିĠ2ğᄝ CPU ‫؍ࢨ໊گ‬൐ିĠ3ğᄝ༢๤‫؍ࢨ໊گ‬൐ିĠ + 4ğᄝ RTC ‫؍ࢨ໊گ‬൐ିbč‫؀‬/ཿĎ + + RTC_CNTL_WDT_STG0 1ğᄝᇏ؎ࢨ‫؍‬൐ିĠ2ğᄝ CPU ‫؍ࢨ໊گ‬൐ିĠ3ğᄝ༢๤‫؍ࢨ໊گ‬൐ିĠ + 4ğᄝ RTC ‫؍ࢨ໊گ‬൐ିbč‫؀‬/ཿĎ + + RTC_CNTL_WDT_EN ൐ି RTC WDTbč‫؀‬/ཿĎ + +ুᶈྐ༏॓࠯ 655 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.31. RTC_CNTL_WDTCONFIGn_REG (n: 1­4) (0x3FF4808C+4*n) 0 + +31 Reset + + 0x000000FFF + + RTC_CNTL_WDTCONFIGn_REG ु૊‫קܐ‬ൈఖࢨ‫ ؍‬n ֥Ќӻᇛ௹bč‫؀‬ĔཿĎ + + Register 31.32. RTC_CNTL_WDTFEED_REG (0x3FF480A0) + +RTC_CNTL_WDT_FEED (reserved) + +31 30 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +RTC_CNTL_WDT_FEED ೈࡱ່‫ܐ‬bčᆺཿĎ + + Register 31.33. RTC_CNTL_WDTWPROTECT_REG (0x3FF480A4) + +31 0 + + 0x050D83AA1 Reset + +RTC_CNTL_WDTWPROTECT_REG ֒ RTC_CNTL_WDTWPROTECT ҂ູ 0x50d83aa1 ൈđRTC + ु૊‫࠹ܐ‬ൈఖࣉೆཿЌ޹ଆൔđՎൈ RTC_CNTL_WDTCONFIGn_REG ໭‫ڿྩم‬bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 656 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.34. RTC_CNTL_SW_CPU_STALL_REG (0x3FF480AC) + + RTC_CNTL_SW_STALL_PROCPUR_TCC1_CNTL_SW_STALL_APPCPU_C1 (reserved) + +31 26 25 20 19 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_SW_STALL_PROCPU_C1 reg_rtc_cntl_sw_stall_procpu_c1[5:0]đ + ֒ reg_rtc_cntl_sw_stall_procpu_c0[1:0] == 0x86 (100001 10) ൈđPRO_CPU ࡼᄠ๔‫۽‬ቔđ౨ҕ + ࡮ RTC_CNTL_OPTIONS0_REGbč‫؀‬ĔཿĎ + + RTC_CNTL_SW_STALL_APPCPU_C1 reg_rtc_cntl_sw_stall_appcpu_c1[5:0]đ + ֒ reg_rtc_cntl_sw_stall_appcpu_c0[1:0] == 0x86 (100001 10) ൈđAPP_CPU ࡼᄠ๔‫۽‬ቔđ౨ҕ + ࡮ RTC_CNTL_OPTIONS0_REGbč‫؀‬ĔཿĎ + + Register 31.35. RTC_CNTL_STOREn_REG (n: 4­7) (0x3FF480B0+4*n) + +31 0 + +x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset + + RTC_CNTL_STOREn_REG 32 ໊๙ႨЌ਽࠷թఖbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 657 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.36. RTC_CNTL_HOLD_FORCE_REG (0x3FF480C8) + + (reserved) RTC_RCTNCT_LRC_XTN3CT2_LNRC__XTNH3CT2O_LPRCL__TDTNHOC_TOFU_LOLRC_CDTRTNHO_CCT_FU_LEPORC_CARTTNDHOCCT7_UE_L_PRC_HCATTNDOHOCT6_LU_L_PDRC_HCA_TTNDOHFOCOT5_LU_L_PDRRC_HCA_CTTNDOHFEOCOT4_LU_L_PDRRC_HCA_CTTNDOHFEOCOT3_LU_L_PDRRC_HCA_CTTNDOHFEOCOT2_LU_L_PDRRC_HCA_CSTNDOHFEECOT1_LN_LP_DRRCS_HA_CSTENDOFEEC4OT0LN__L_DRHRCS_H_CSOTENOFEEC3LOTLN_D_LDRHRCS___CSOFTENFEOEC2LOTN_D_RLRHRCS__CCPOFTENEEODC1LT_AD_RLHRC_C_CPOFTN2EODC_LTHAD_RLC_CO_CAFN1LEOD_DTHCRL__OF2CAO_LEDHDRCO_CF1LEO_DHR_OFCOLEDR_CFEORCE + +31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + + RTC_CNTL_X32N_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_X32P_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_TOUCH_PAD7_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_TOUCH_PAD6_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_TOUCH_PAD5_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_TOUCH_PAD4_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_TOUCH_PAD3_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_TOUCH_PAD2_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_TOUCH_PAD1_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_TOUCH_PAD0_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_SENSE4_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_SENSE3_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_SENSE2_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_SENSE1_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_PDAC2_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_PDAC1_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_ADC2_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + RTC_CNTL_ADC1_HOLD_FORCE ྨ૤ሑ෿༯đՎ໊ᇂ 1 Ќӻܵ࢖ሑ෿bč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 658 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.37. RTC_CNTL_EXT_WAKEUP1_REG (0x3FF480CC) + + (reserved) RTC_CNTL_EXT_WAKEUP1_STATUS_CLR RTC_CNTL_EXT_WAKEUP1_SEL + 0 +31 19 18 17 0 + +0 0 0 0 0 0 0 0 0 0 0 0 00 Reset + + RTC_CNTL_EXT_WAKEUP1_STATUS_CLR ౢԢຓ҆ߒྜჷ 1 ֥ሑ෿bčᆺཿĎ + RTC_CNTL_EXT_WAKEUP1_SEL ູຓ҆ߒྜჷ࿊ᄴ RTC ܵ࢖໊֥๭bč‫؀‬ĔཿĎ + + Register 31.38. RTC_CNTL_EXT_WAKEUP1_STATUS_REG (0x3FF480D0) + + (reserved) RTC_CNTL_EXT_WAKEUP1_STATUS + 0 +31 18 17 0 + +00000000000000 Reset + + RTC_CNTL_EXT_WAKEUP1_STATUS ຓ҆ߒྜჷ 1 ֥ሑ෿bčᆺ‫؀‬Ď + +ুᶈྐ༏॓࠯ 659 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + 31 ֮‫ܵݻۿ‬৘ (RTC_CNTL) + + Register 31.39. RTC_CNTL_BROWN_OUT_REG (0x3FF480D4) + +RTC_RCTNCT_LC_BNRTOLR_WBTNCR_O_OCWUNNTT__LODR_DEUTCTBT_R_ECONNWATNL__BORUOT_WTNH_ROEUST_RSRT_TECN_ACNTL_BROWN_OUT_RSRT_TWC_ARCITTNCT_LC_BNRTOL_WBNR_OOWUNT__OPDU_TR_CF_LEONSAE_FLASH(re_sEeNrvAed) + +31 30 29 27 26 25 16 15 14 13 0 + +00 0x2 0 0x3FF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset + +RTC_CNTL_BROWN_OUT_DET ఴ࿢࡟ҩbčᆺ‫؀‬Ď + +RTC_CNTL_BROWN_OUT_ENA ൐ିఴ࿢࡟ҩbč‫؀‬ĔཿĎ + +RTC_CNTL_DBROWN_OUT_THRES ఴ࿢ᚐᆴb֒‫׈‬ჷ‫׈‬࿢֮ႿՎఴ࿢ᚐᆴൈđఴ࿢࡟ҩఖࡼ‫گ‬ + ໊ྉோb౨ᇿၩđૄ۱ ESP32 ྉோᆭࡗॖିթᄝఴ࿢ᚐᆴ֥ҵၳb0ğ2.43 V ± 0.05Ġ1ğ2.48 + V ± 0.05Ġ2ğ2.58 V ± 0.05Ġ3ğ2.62 V ± 0.05Ġ4ğ2.67 V ± 0.05Ġ5ğ2.70 V ± 0.05Ġ6ğ2.77 + V ± 0.05Ġ7ğ2.80 V ± 0.05bč‫؀‬ĔཿĎ + +RTC_CNTL_BROWN_OUT_RST_ENA ൐ିఴ࿢‫໊گ‬bč‫؀‬ĔཿĎ + +RTC_CNTL_BROWN_OUT_RST_WAIT ఴ࿢‫໊֩گ‬րᇛ௹bč‫؀‬ĔཿĎ + +RTC_CNTL_BROWN_OUT_PD_RF_ENA ֒ԛགྷఴ࿢ൈđ൐ିܱо RFbč‫؀‬ĔཿĎ + +RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA ֒ԛགྷఴ࿢ൈđ൐ିܱо flashčཟ flash ‫ؿ‬ෂ sus- + pend ᆷ਷Ďbč‫؀‬ĔཿĎ + +ুᶈྐ༏॓࠯ 660 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + Ս߸ਙі + +Ս߸ਙі + +ຓഡཌྷܱՍ߸ AES ࡆ෎ఖ + ۚࠩۚྟିሹཌ (Advanced High-performance Bus)b۷‫ྐ؟‬༏࡮ AHB ܿٓb + AES ۚࠩຓຶሹཌ (Advanced Peripheral Bus)b۷‫ྐ؟‬༏࡮ APB ܿٓb + AHB DMA ॥ᇅఖ + APB ඔऌ؊१ (Data Port) ֥෪ཿđಆӫູ XLMI ؊१ (Xtensa Local Memory Interface)b + DMA eFuse ॥ᇅఖ + DPORT ၛ෾ຩ MAC + eFuse I2C ॥ᇅఖ + EMAC I2S ॥ᇅఖ + I2C LED ॥ᇅ PWM + I2S ‫ࠏ׈‬॥ᇅ PWM + LEDC թԥఖܵ৘ֆჭ + MCPWM թԥఖЌ޹ֆჭ + MMU ઝԊ࠹ඔఖ॥ᇅఖ + MPU ຓഡ + PCNT ‫׈‬ჷܵ৘ֆჭ + PERI ࣉӱ‫ݼ‬ + PMU ‫ޣ‬ຓဪ॥ + PID ෛࠏඔളӮఖ + RMT RSA ࡆ෎ఖ + RNG ൌൈ॥ᇅఖbSOC ᇏ֥၂ቆ‫׈‬ਫ਼đᄝ಩‫ޅ‬ྉோଆൔ༯‫ି׻‬ෛൈЌӻ‫۽‬ቔ + RSA SD/MMC ᇶࠏ॥ᇅఖ + RTC SHA ࡆ෎ఖ + SDHOST SPI ॥ᇅఖ + SHA ‫ק‬ൈఖቆ + SPI චཌచӚࢤ१ + TIMG UART ॥ᇅఖ + TWAI ӑ֮‫ླྀݻۿ‬ԩ৘ఖ + UART USB On-The-Go + ULP ླྀԩ৘ఖ ु૊‫קܐ‬ൈఖ + USB OTG + WDT + +࠷թఖཌྷܱՍ߸ ‫ۯ‬৖b֒ଆॶ؎‫׈‬ൈđఃൻԛ֥ႄ࢖ࡼԩႿໃᆩሑ෿čଖུᇏࡗ‫׈‬࿢ĎboISOp + ࠷թఖࡼ൐ఃൻԛႄ࢖‫ۯ‬৖ᄝ၂۱ಒ‫׈֥ק‬࿢đՖ‫ط‬҂߶႕ཙః෰ໃ‫۽֥׈ו‬ + ISO ቔଆॶ֥ሑ෿b + ҂ॖ௠зᇏ؎b + NMI ࠷թఖb + REG ‫؀‬/ཿđೈࡱॖ‫؀‬ཿᆃ໊ུb + R/W ᆺ‫؀‬đೈࡱᆺି‫؀‬ᆃ໊ུb + RO ᆺཿđೈࡱᆺିཿᆃ໊ུb + WO + +ুᶈྐ༏॓࠯ 661 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + ྩ‫ר‬৥ൎ + +ྩ‫ר‬৥ൎ + +ರ௹ ϱЧ ‫҃ؿ‬ඪૼ + +2022.08 v4.7 • ۷ྍᅣࢫ 1 ༢๤‫ބ‬թԥఖ ᇏ֥і 1-6 + • ۷ྍᅣࢫ 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX)ğ +2021.11 v4.6 + – ྩᆞ࠷թఖਙіᇏ֥၂ԩг༂ + – ۷ྍֻ 4.2.2 ཬࢫᇏ֥૭ඍ + – ۷ྍؓ GPIO_PINn_INT_ENA ‫ ބ‬IO_MUX_PIN_CTRL ֥૭ඍ + • ᄝᅣࢫ 6 DMA ॥ᇅఖ (DMA) ᇏ֥ 6.4 ཬࢫྍᄹ၂่ܱႿࢤ൬৽і૭ඍ‫ژ‬ + ֥ඪૼ + • ۷ ྍ ᅣ ࢫ 7 SPI ॥ ᇅ ఖ (SPI) ᇏ ؓ SPI_TRANS_DONEa + SPI_SLV_WR_STA_DONEaSPI_SLV_RD_STA_DONEa + SPI_SLV_WR_BUF_DONEaSPI_SLV_RD_BUF_DONE ֥૭ඍ + • ۷ྍൈᇒ଀ӫğ + – RTC8M_CLK ۷ྍູ RC_FAST_CLK + – RTC8M_D256_CLK ۷ྍູ RC_FAST_DIV_CLK + – RTC_CLK ۷ྍູ RC_SLOW_CLK + – SLOW_CLK ۷ྍູ RTC_SLOW_CLK + – FAST_CLK ۷ྍູ RTC_FAST_CLK + • ྩᆞᅣࢫ 12 I2S ॥ᇅఖ (I2S) ᇏ࠷թఖਙіᇏ֥၂ԩг༂ + • ۷ྍᅣࢫ 18 ‫ק‬ൈఖቆ (TIMG) ᇏ֥࠷թఖਙі + • ᄝᅣࢫ 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ ᇏྍᄹਆ่ඪૼ + + ۷ྍᅣࢫ 1 ༢๤‫ބ‬թԥఖ ᇏ֥і 1-6 + ۷ྍᅣࢫ 2 ᇏ؎इᆔ (INTERRUPT) ᇏ֥і 2-1 + ۷ྍᅣࢫ 3 ‫ބ໊گ‬ൈᇒ ᇏ֥๭ 3-1 + ۷ྍᅣࢫ 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) ᇏ֥і 4-2 ‫ؓބ‬ + IO_MUX_PIN_CTRL ֥૭ඍ + ಆ૫۷ྍᅣࢫ 5 DPort ࠷թఖ + ᄝᅣࢫ 12 I2S ॥ᇅఖ (I2S) ֥і 12-1 ༯ٚྍᄹ၂่ඪૼ + ۷ྍᅣࢫ 8 SDIO Ֆࠏ॥ᇅఖ ᇏ֥ 8.3.6 ཬࢫ‫࠷ބ‬թఖ SLCHOST_CONF_REG + ۷ྍᅣࢫ 26 ோຓթԥఖࡆૡაࢳૡ (FLASH) ֥૭ඍ + ۷ྍᅣࢫ 29 ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ ᇏ֥ 29.5.3 ཬࢫ + ᄝᅣࢫ 4aᅣࢫ 7aᅣࢫ 12aᅣࢫ 15aᅣࢫ 29 ‫ބ‬ᅣࢫ 30 ᇏᄹࡆؓ࠷թఖֹᆶ + ֥ඪૼ + ‫ي‬ၲ‫؟‬۱ᅣࢫᇏ֥࠷թఖਙі + ۷ྍՍ߸ਙі + ྩᆞг༂ + + ࡮༯် + +ুᶈྐ༏॓࠯ 662 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + ྩ‫ר‬৥ൎ ϱЧ ࿃ഈ် + ರ௹ v4.5 + 2021.07 ‫҃ؿ‬ඪૼ + V4.4 ᄹࡆᅣࢫ 10.6.4 + 2021.03 V4.3 ᄝі 4-4 ༯ٚᄹࡆ၂่ඪૼ + 2020.09 ᄝᅣࢫ 14 LED PWM ॥ᇅఖ (LEDC) ۷ྍі 14-1 + ۷ྍᅣࢫ 3.2.7 ֥૭ඍ + ࡼᅣࢫ 10.9 ᇏ֥ Ethernet MAC ࠎֹᆶ۷ྍູ 0x3FF6_9000 + ᄝ ᅣ ࢫ 13 UART ॥ ᇅ ఖ (UART) ۷ ྍ UART_SW_RTSa + UART_RX_FLOW_THRHD ሳ‫֥؍‬૭ඍ + ᄝᅣࢫ 21 චཌచӚࢤ१ (TWAI) ۷ྍหྟ૭ඍ + ۷ྍᅣࢫ 25 ෛࠏඔ‫ؿ‬ളఖ (RNG) + ۷ྍᅣࢫ 30.4.2 ֥૭ඍ + ᄝᅣࢫ 5 DPort ࠷թఖ ‫ބ‬ᅣࢫ 2 ᇏ؎इᆔ (INTERRUPT) ᇏเࡆᇏ؎इᆔ࠷թఖ + ֥ࠎֹᆶྐ༏ + ۷ྍᅣࢫ 4 IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) ᇏܵ࢖‫ିۿ‬щ‫ݼ‬đщ‫ݼ‬ + Ֆ Function0 ष൓ + ೷Ԣᅣࢫ 13.3.4 ᇏᇗ‫֥گ‬ଽಸ + ྩᆞі 2-1 ‫ބ‬ᅣࢫ 6.4 ᇏ֥г༂ + ۷ྍᅣࢫ 16ğ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (PWM) ᇏ࠷թఖ PWM_TIMER0_SYNC_REG + ~ PWM_TIMER2_SYNC_REG ֥૭ඍ + ۷ྍᅣࢫ 18ğ‫ק‬ൈఖቆ (TIMG) ᇏ TIMGn_RTCCALICFG_REG ࠷թఖ‫ބ‬ + TIMGn_RTCCALICFG1_REG ࠷թఖ֥૭ඍ + ۷ྍᅣࢫ 31ğ֮‫ܵݻۿ‬৘ (RTC_CNTL) ᇏ RTC_CNTL_WDTCONFIG0_REG ࠷ + թఖ֥૭ඍ + ۷ྍᅣࢫ 10ğၛ෾ຩ (MAC) ᇏؓ EMACMIIADDR_REG ֥૭ඍ + ۷ྍᅣࢫ 4ğIO_MUX ‫ ބ‬GPIO ࢌߐइᆔ (GPIO, IO_MUX) ᇏؓ IO_MUX_x_REG + (x: GPIO0-GPIO39) ‫ ބ‬IO_MUX_x_REG (x: GPIO0-GPIO39) ֥૭ඍ + ۷ྍᅣࢫ 21ğචཌచӚࢤ१ (TWAI) ᇏ෮Ⴈ֥അѓ‫ݼژ‬ + ۷ྍᅣࢫ 31ğ֮‫ܵݻۿ‬৘ (RTC_CNTL) ᇏ RTC_CNTL_ULP_CP_TIMER_REG ࠷ + թఖ֥૭ඍ + ࡼ໓֖ཿቔܿٓᅣࢫᇗଁ଀ູՍ߸ਙіđѩ၍ᇀ໓֖ࢲແ + ۷ྍі 4-3ğIO_MUX Pad ਙі༯֥ٚඪૼ + ྍᄹᅣࢫ 21 චཌచӚࢤ१ (TWAI) + ᄝᅣࢫ eFuse ॥ᇅఖ ᇏྍᄹ uart_download_dis ༢๤ҕඔ֥ཌྷܱྐ༏b + ᄝᅣࢫ 25 ෛࠏඔ‫ؿ‬ളఖ (RNG) ᇏྍᄹ 25.4 щӱᆷଲ ཬࢫđѩ۷ྍ҆‫ٳ‬૭ඍb + ۷ྍؓ࠷թఖ SPI_ADDR_REG ‫ ބ‬SPI_SLV_WR_STATUS_REG ֥૭ඍ + + ࡮༯် + +ুᶈྐ༏॓࠯ 663 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + ྩ‫ר‬৥ൎ ϱЧ ࿃ഈ် + ರ௹ V4.2 ‫҃ؿ‬ඪૼ + ྍᄹ໓֖ཿቔܿٓᅣࢫ + 2020.06 ۷ྍᅣࢫ༢๤‫ބ‬թԥఖğ + + • ᄝі 1-6 ༯ٚเࡆܱႿ DPORT ‫ ބ‬AHB ֹᆶॢࡗ֥ඪૼ + ۷ྍᅣࢫ‫ބ໊گ‬ൈᇒğ + + • ۷ྍі 3-3ğᄹࡆ PLL_CLK ௔ੱູ 480 MHzđCPU_CLK ௔ੱູ 240 MHz + ֥૭ඍ + + • ۷ྍі 3-5ğࡼ CPU_CLK ჷູ PLL_CLK ൈ APB_CLK ֥௔ੱ‫ ູڿ‬80 + MHz + + ۷ྍᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔğ + • ྩᆞᅣࢫ 4.4.2 ᇏ֥၂ԩг༂ğؓႿൻೆྐ‫ݼ‬đсྶౢਬ SIG_IN_SEL ࠷ + թఖđᆰࢤࡼൻೆྐ‫ݼ‬ൻԛ֞ຓഡb + • ྩ‫ڿ‬і 4-3 ᇏ MTCKaMTMSaGPIO27 ֥ reset ሑ෿ + • ۷ྍ࠷թఖ FUN_DRV ֥૭ඍ + + ۷ྍᅣࢫ I²S: + • ۷ྍᅣࢫ 12.4.1.1 + + ۷ྍᅣࢫ UART ॥ᇅఖğ + • ۷ྍᅣࢫ 13.3.3 + • ۷ྍ࠷թఖ UART_FIFO_REG ‫ ބ‬UART_RX_TOUT_THRHD ֥૭ඍ + + ۷ྍᅣࢫ LED_PWMğ + • ᄹࡆі 14-1 + + ۷ྍᅣࢫ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖ (MCPWM)ğ + • ྩᆞᄝ‫־‬ᄹ࠹ඔଆൔa‫࠹ࡨ־‬ඔଆൔa‫־‬ᄹ-‫ࡨ־‬࿖ߌଆൔ༯ PWM ֥ᇛ + ௹ᆴ + + ۷ྍᅣࢫ PULSE_CNTğ + • ᄹࡆ࠷թఖ PCNT_Un_STATUS_REG ֥૭ඍ + + ۷ྍᅣࢫ eFuse ॥ᇅఖğ + • ࡼਆ۱༢๤ҕඔo32padp‫ބ‬ochip_versionp‫ކ‬ѩӮ၂۱ğpkg_version + • ۷ྍ࠷թఖ EFUSE_RD_CHIP_VER_PKG ‫ ބ‬EFUSE_CHIP_VER_PKG ֥ + ૭ඍ + + ۷ྍᅣࢫோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ğ + • ྩᆞࠫԩг༂ + + ۷ྍᅣࢫӑ֮‫ླྀݻۿ‬ԩ৘ఖğ + • ۷ྍᅣࢫ 30.4.13 ‫ ބ‬30.4.14 ᇏ֥૭ඍ + • ྩᆞࠫԩг༂ + + ۷ྍᅣࢫ֮‫ܵݻۿ‬৘ğ + • ᄹࡆ࠷թఖ RTC_CNTL_WDTCONFIG0_REG ֥૭ඍ + • ྩ‫࠷ڿ‬թఖ RTC_CNTL_WDTCONFIGn_REG ֥૭ඍ + + ࡮༯် + +ুᶈྐ༏॓࠯ 664 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + ྩ‫ר‬৥ൎ ࿃ഈ် + ರ௹ + ϱЧ ‫҃ؿ‬ඪૼ + 2019.11 V4.1 + ۷ྍᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔğ + • ۷ྍі 4-4Ġ + + • ᄝ ࠷ թ ఖ RTCIO_TOUCH_PADn_REG ૭ ඍ ᇏ ᄹ ࡆ RT- + + CIO_TOUCH_PADn_FUN_SEL ࠣఃඪૼĠ + + ۷ྍᅣࢫ SPIğ + • ྩᆞі 7.7 ᇏ SPI2aSPI3 ֥հ༂ֹᆶĠ + + ۷ྍᅣࢫ I²C ॥ᇅఖğ + + • ೷Ԣ I2C_SLAVE_TRAN_COMP_INT ᇏ؎Ġ + + ۷ྍᅣࢫ I²Sğ + + • ᄝі 12-1 ༯ᄹࡆ၂่ඪૼĠ + + ۷ྍᅣࢫ UART ॥ᇅఖğ + • ྩᆞ UART_FORCE_XOFF ‫ ބ‬UART_FORCE_XON ֥࠷թఖ૭ඍĠ + + • ྩᆞ ART_SWFC_CONF_REG ֥࠷թఖ૭ඍĠ + ۷ྍᅣࢫ‫ޣ‬ຓဪ॥ğ + + • ۷ྍ๭ 15-1Ġ + + ۷ྍᅣࢫ PULSE_CNTğ + • ۷ྍ๭ 17-1Ġ + + • ྩᆞ࠷թఖ PCNT_Un_CONF0_REG ૭ඍ৚֥г༂Ġ + ۷ྍᅣࢫ eFuse ॥ᇅఖğ + + • ྍᄹѩྩ‫ ڿ‬8 ۱༢๤ҕඔĠ۷ྍཌྷႋ࠷թఖĠ + + • ۷ྍі 20-4 ᇏ֥࠷թఖ஥ᇂᆴĠ + + • ࡼ༢๤ҕඔ flash_crypt_cnt ໊֥ॺ‫ ູڿ‬7 ໊Ġ + + ۷ྍᅣࢫ PID/MPU/MMUğ + + • ᄝі۬ 27-8 ༯ٚᄹࡆ၂่ඪૼĠ + ۷ྍᅣࢫோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘ğ + + • ྩᆞ SENS_SAR2_BIT_WIDTH ‫ ބ‬SENS_SAR1_BIT_WIDTH ֥࠷թఖ૭ + + ඍĠ + + ۷ྍᅣࢫӑ֮‫ླྀݻۿ‬ԩ৘ఖğ + + • ೷Ԣ TSENS ᆷ਷Ġ + + • ྩᆞ REG_WR ֥ OpCodeĠ + + • ۷ྍᅣࢫ 30.6.2.4Ġ + + • ྩᆞ RTC_I2C_RX_LSB_FIRST ‫ ބ‬RTC_I2C_TX_LSB_FIRST ֥࠷թఖ૭ + + ඍĠ + + •೷ Ԣ RTC_I2C_SLAVE_TRAN_COMP_INT_ENA ‫ބ‬ + + RTC_I2C_SLAVE_TRAN_COMP_INT_ST ֥࠷թఖ૭ඍĠ + + ۷ྍᅣࢫ֮‫ܵݻۿ‬৘ğ + + • ྩᆞ࠷թఖ RTC_CNTL_DBROWN_OUT_THRES ֥ଏಪᆴ‫ބ‬૭ඍĠ + + • ྩᆞ࠷թఖ RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA ֥૭ඍĠ + + ᄹࡆ໓ّ֖ঌ৽ࢤb + + ࡮༯် + +ুᶈྐ༏॓࠯ 665 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + ྩ‫ר‬৥ൎ + +ರ௹ ϱЧ ࿃ഈ် + ‫҃ؿ‬ඪૼ +2018.12 V4.0 ۷ྍᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ ᇏࠫԩ࠷թఖ଀ӫđၛ۵๨໓ࡱЌӻ၂ᇁĠ + ۷ྍᅣࢫ 7 SPIğ +2018.10 V3.9 + • ۷ྍᅣࢫ 7.3Ġ +2018.09 V3.8 • ۷ྍᅣࢫ 7.5.1Ġ + • ۷ྍᅣࢫ 7.8Ġ +2018.08 V3.7 ۷ྍᅣࢫ 13 UART ॥ᇅఖğ + • ࡼ UART ᆦӻ֥๔ᆸ໊ྩᆞູ 1/1.5/2/3 ۱Ġ +2018.08 V3.6 • ᄝᅣࢫ 13.3.2 ଌ‫؍‬ᄹࡆ၂ᄵඪૼĠ + • ۷ྍ࠷թఖ UART_DL0_EN ֥૭ඍĠ +2018.07 V3.5 ᄝ֮‫ܵݻۿ‬৘၂ᅣᇏߒྜჷ֥ଌ‫؍‬ᄹࡆ၂ᄵඪૼb + ۷ྍᅣࢫ 11ğI2C ॥ᇅఖᇏ๭ 11-3ğI2C ൈ྽๭b +2018.06 V3.4 ۷ྍ࠷թఖ TIMGn_Tx_ALARM_EN ֥૭ඍĠ + ᄝᅣࢫ 30.5 ᇏᄹࡆܱႿ ULP ླྀԩ৘ఖߒྜൈࡗ֥૭ඍb +2018.05 V3.3 ۷ྍ࠷թఖ UART_RX_GAP_TOUT ֥૭ඍb + ۷ྍᅣࢫ 30.4.6 ᇏ๋ሇ่ࡱĠ +2018.04 V3.2 ۷ྍ࠷թఖ UART_ACTIVE_THRESHOLD ֥૭ඍb + ۷ྍᅣࢫ 15 RMTğ + • ۷ྍᅣࢫ 15.2.2ğRMT RAM ᇏ RAM ֥ఏ൓ֹᆶĠ + • ྩᆞࠫԩ RMT ࠷թఖֹᆶհ༂Ġ + • ۷ྍ࠷թఖ RMT_APB_CONF_REG ֥૭ඍb + ۷ ྍ ࠷ թ ఖ UART_RX_TOUT_THRHDaUART_RXFIFO_FULL_INT_CLRa + UART_RXFIFO_FULL_INT_CLR ֥૭ඍb + ۷ྍᅣࢫ 4.8 ESP32 I/O Pad ‫׈܂‬ᇏ֥๭Ġ + ۷ྍᅣࢫ 11.3.3 I2C ሹཌൈ྽Ġ + ᄝᅣࢫ 14.2.3 LEDC ๙֡ᇏᄹࡆඪૼĠ + ۷ྍᅣࢫ 17.2.3 PULSE_CNT ܴҳׄᇏ֥oቋն࠹ඔᆴpĠ + ೷ԢႵܱ໑؇Ԯ‫ۋ‬ఖ‫ބ‬ӑ֮ᄮലభᇂଆ୅٢նఖཌྷܱ֥ଽಸb + ۷ྍ ֮‫ܵݻۿ‬৘ ᅣᇏ ࠷թఖਙі ࢫ‫࠷ ބ‬թఖ ࢫᇏ֥࠷թఖֹᆶb + ۷ྍ๭ 8-3 CMD53 ଽಸb + ᄝᅣࢫ Ethernet MAC ᇏᄹࡆၛ༯ 6 ۱࠷թఖğ + • DMAOPERATION_MODE_REG; + • DMAIN_EN_REG, + • DMAMISSEDFR_REG, + • PMT_RWUFFR_REG, + • PMT_CSR_REG, + • EMACLPI_CSR_REG, and + • EMACLPITIMERSCONTROL_REG. + +2018.04 V3.1 ۷ྍ๭ 15-1 RMT ࡏ‫ܒ‬Ġ + ᄝᅣࢫ 4.7 ᇏᄹࡆඪૼĠ + ᄝᅣࢫ 4.46 ᇏᄹࡆؓ࠷թఖ໊֥૭ඍĠ + ۷ྍᅣࢫ 30.4.2 ᇏ ST ᆷ਷֥‫ק‬ၬ๭Ġ + +2018.03 V3.0 ࡮༯် + +ুᶈྐ༏॓࠯ 666 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + ྩ‫ר‬৥ൎ ϱЧ ࿃ഈ် + ರ௹ ‫҃ؿ‬ඪૼ + V2.9 ᄝ ᅣ ࢫ 10.9 ‫ ބ‬10.10 ᇏ ᄹ ࡆ ࠷ թ ఖ EMACADDR2HIGH_REG ֞ + 2018.02 V2.8 EMACADDR7LOW_REG ඪૼb + 2018.01 V2.7 ۷ྍᅣࢫ 4.2.2a4.2.3a4.3.2Ġ + 2017.12 ᄝᅣࢫ I2S ࠷թఖ ᇏᄹࡆ I2S_FIFO_WR_REG ‫ ބ‬I2S_FIFO_RD_REG ࠷թఖb + V2.6 ᄹࡆᅣࢫၛ෾ຩ MACb + 2017.11 ᄝᅣࢫ eFuse ॥ᇅఖ ᇏᄹࡆ༢๤ҕඔ BLK3_part_reserve ֥૭ඍb + V2.5 ᄝᅣࢫ ༢๤‫ބ‬թԥఖ ᇏᄹࡆཬࢫ CacheĠ + 2017.11 ۷ྍᅣࢫ ‫ٳ‬௔ఖ ࠣ LED_PWM ᇏ‫؟‬۱࠷թఖ଀ӫĠ + V2.4 ۷ྍᅣࢫ eFuse ॥ᇅఖ ᇏ࠷թఖ console_debug_disable ֥૭ඍb + 2017.09 V2.3 ۷ྍᅣࢫ‫ޣ‬ຓဪ॥ğ + 2017.08 V2.2 + 2017.07 V2.1 • ۷ྍ๭ 15-1 RMT ࡏ‫ܒ‬Ġ + 2017.07 V2.0 • ۷ྍᅣࢫ RMT RAMĠ + 2017.07 V1.9 • ۷ྍᅣࢫ ‫ؿ‬ഝఖĠ + 2017.06 V1.8 • ۷ྍᇏ؎ RMT_CHn_TX_THR_EVENT_INT ֥૭ඍb + 2017.06 ᄝᅣࢫ UART RAM ‫࠷ބ‬թఖ UART_CONF0_REG ᇏᄹࡆඪૼb + V1.7 ۷ྍᅣࢫ SPI ࠷թఖਙіᇏ࠷թఖ SPI_CTRL_REG ֹ֥ᆶ૭ඍĠ + 2017.05 ᄝ ᅣ ࢫ SD/MMC ᇶ ࠏ ॥ ᇅ ఖ ᇏ ᄹ ࡆൈ ᇒ ཌྷ ໊ ࿊ ᄴđ ᄹ ࡆ ࠷ թ ఖ + V1.6 CLK_EDGE_SEL ֥ඪૼĠ + 2017.03 ܱႿ I2C ॥ᇅఖᅣࢫ֥ᇗնྩ‫ר‬b + ᄝᅣࢫ SDIO Ֆࠏ ᇏᄹࡆ࠷թఖ SLC0HOST_TOKEN_RDATA ֥૭ඍĠ + ᄝᅣࢫ I2S ଆॶൈᇒᇏᄹࡆᇿၩ൙ཛĠ + ᄝᅣࢫ GP-SPI ᇶࠏଆൔᇏᄹࡆඪૼĠ + ᄹࡆᅣࢫ DPort ࠷թఖĠ + ᄹࡆᅣࢫ DMA ॥ᇅఖb + ᄹࡆᅣࢫ Flash ࡆૡაࢳૡb + ᄹࡆᅣࢫ ֮‫ܵݻۿ‬৘b + ۷ྍᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔᇏ GPIO ஥ᇂ/ඔऌ࠷թఖ‫ ބ‬GPIO RTC ‫ۿ‬ + ି஥ᇂ࠷թఖֹ֥ᆶĠ + ᄹࡆᅣࢫ PID ॥ᇅఖb + ᄹࡆᅣࢫ SDIO Ֆࠏb + ۷ྍᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔĠ + ᄹࡆᅣࢫ ‫ࠏ׈‬॥ᇅઝॺ‫ט‬ᇅఖčMCPWMĎb + ᄝᅣࢫ I2S ᇏᄹࡆ࠷թఖ I2S_STATE_REG ֥૭ඍĠ + ۷ྍᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔĠ + ᄹࡆᅣࢫ ӑ֮‫ླྀݻۿ‬ԩ৘ఖb + ᄹࡆᅣࢫ ோഈԮ‫ۋ‬ఖაଆ୅ྐ‫ݼ‬ԩ৘Ġ + ᄹࡆᅣࢫ ၻ௔ PLLĠ + ۷ྍᅣࢫ eFuse ॥ᇅఖ࠷թఖਙіĠ + ۷ྍᅣࢫ I2S PDM ଆൔ‫ ބ‬LCD ଆൔĠ + ۷ྍᅣࢫğGP-SPI Ֆࠏᆦӻ֥๙ྐ۬ൔb + ᄹࡆᅣࢫ SD/MMC ᇶࠏ॥ᇅఖĠ + ᄝᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔᇏᄹࡆ࠷թఖ IO_MUX_PIN_CTRL ֥૭ඍb + + ࡮༯် + +ুᶈྐ༏॓࠯ 667 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + ྩ‫ר‬৥ൎ ϱЧ ࿃ഈ် + V1.5 ‫҃ؿ‬ඪૼ + ರ௹ V1.4 ᄹࡆᅣࢫ I2Sb + 2017.03 ᄹࡆᅣࢫ SPIĠ + 2017.01 V1.3 ᄹࡆᅣࢫ UART ॥ᇅఖb + ᄹࡆᅣࢫ eFuse ॥ᇅఖĠ + 2016.12 V1.2 ᄹࡆᅣࢫ RSA ࡆ෎ఖĠ + V1.1 ᄹࡆᅣࢫ ෛࠏඔ‫ؿ‬ളఖĠ + 2016.11 V1.0 ۷ྍᅣࢫ I2C ॥ᇅఖᇏ؎ ‫ ބ‬I2C ॥ᇅఖ࠷թఖb + 2016.09 ᄹࡆᅣࢫ PID/MPU/MMUĠ + 2016.08 ۷ྍᅣࢫ IO_MUX ‫ ބ‬GPIO ࢌߐइᆔ࠷թఖਙіĠ + ۷ྍᅣࢫ LED_PWM ࠷թఖਙіb + ᄹࡆᅣࢫ I2C ॥ᇅఖb + ൮Ց‫҃ؿ‬b + +ুᶈྐ༏॓࠯ 668 ESP32 ࠯ඌҕॉ൭Ҩ (ϱЧ 4.7) + ّঌ໓֖ၩ࡮ + www.espressif.com ૧ᄳലૼ‫ބ‬ϱಃ‫ۡ܄‬ + + Ч໓֖ᇏ֥ྐ༏đЇও‫܂‬ҕॉ֥ URL ֹᆶđೂႵэ۷đඖ҂ਸ਼ྛ๙ᆩb + Ч໓֖ॖିႄႨਔֻ೘֥ٚྐ༏đ෮ႵႄႨ֥ྐ༏नູoοགྷሑpิ‫܂‬đুᶈ҂ؓྐ + ༏֥ሙಒྟaᆇൌྟቓ಩‫ޅ‬Ќᆣb + ুᶈ҂ؓЧ໓֖֥ଽಸቓ಩‫ޅ‬ЌᆣđЇওଽಸ֥ൡཧྟa൞‫ڎ‬ൡႨႿห‫ק‬Ⴈ๯đ္҂ + ิ‫܂‬಩‫ޅ‬ః෰ুᶈิσaܿ۬඀ࠇဢ௖ᄝ෰ԩิ֥֞಩‫ޅ‬Ќᆣb + ুᶈ҂ؓЧ໓֖൞‫ֻٕ౓ڎ‬೘ٚಃ০ቓ಩‫ޅ‬Ќᆣđ္҂ؓ൐ႨЧ໓֖ଽྐ༏֝ᇁ֥಩ + ‫ٕ౓ޅ‬ᆩ്Ӂಃ֥ྛູ‫ڵ‬ᄳbЧ໓֖ᄝՎໃၛ࣌ᆸّ࿽ࠇః෰ٚൔ൱Ⴭ಩‫ޅ‬ᆩ്Ӂಃ + ྸॖđ҂ܵ൞ૼൕྸॖߎ൞πൕྸॖb + Wi-Fi ৳ૐӮჴѓᆽ݂ Wi-Fi ৳ૐ෮Ⴕbড࿩ѓᆽ൞ Bluetooth SIG ֥ᇿҨഅѓb + ໓֖ᇏิ֥֞෮Ⴕഅѓ଀ӫaഅѓ‫ބ‬ᇿҨഅѓनඋః۲ሱ෮Ⴕᆀ֥ҍӁđหՎലૼb + ϱಃ݂ © 2022 ুᶈྐ༏॓࠯čഈ‫ݚ‬Ď‫ٺܢ‬Ⴕཋ‫܄‬ඳbЌ਽෮Ⴕಃ০b + diff --git a/4.Software/TestGeekTrackSDK/.vs/TestGeekTrack/v16/.suo b/4.Software/TestGeekTrackSDK/.vs/TestGeekTrack/v16/.suo index c1ddf5d..bd80c8b 100644 Binary files a/4.Software/TestGeekTrackSDK/.vs/TestGeekTrack/v16/.suo and b/4.Software/TestGeekTrackSDK/.vs/TestGeekTrack/v16/.suo differ